5 4 3 2 1

ZQT/ZQS/ZQW CRV SYSTEM BLOCK DIAGRAM

m
D
DIS._eDP D

co
eDP Con. INT._eDP eDP
eDP
P23 IVY Bridge VRAM
N13P-GL/GS/GT P13, 14
rPGA 989
PEG /N13M-GS

a.
Dual Channel DDR III P3, 4, 5, 6 TX/RX
DDRIII-SODIMM1 DIS._HDMI
1066/1333/1600 MHZ IMC Display
DDRIII-SODIMM2 GFX
P13, 14
DIS._CRT
P23 DIS._LVDS
FDI DMI Int. MIC

si
DMI(x4) USB-8 LVDS/CCD/MIC
Con. P23
FDI DMI
INT_LVDS

CLK
INT_CRT

ne
CRT Con. P23
SATA 0 Display
SATA - HDD
C C
P26
SATA INT_HDMI
HDMI Con. P24
SATA - ODD SATA 5

do
P26 USB3-3/USB2-2
Cougar Point USB3.0/2.0 USB Charger
USB3 Port
Panther Point P31
MB side P31
G-Sensor SMBUS
P26 PCIE-1
PCI-E x1 MINI-SSD

In
PCH USB-3
USB2-1& 9 P25
P7, 8, 9, 10, 11, 12
PCI-E x1 PCIE-8

USB-10
MINI CARD
USB2-4 WLAN
Small Board Bluetooth Con. USB2.0 X'TAL P25

i-
32.768KHz
CONNECTOR P31
RJ45
PCIE-3
RTL8411 P29
X'TAL 25MHz 10/100/1G
P31
Cardreader Cardreader
P8 BATTERY RTC
is SPI SPI ROM
P29
CONN. P30
B P8 B
Azalia IHDA
CLK
LPC
kn

EC
Int. MIC ALC271X-VB6 X'TAL
AUDIO CODEC P28 WPCE885 32.768KHz bq24707A TPS51216 Discharger
P34 Batery Charger P35 +1.5V_SUS P39 Thermal Protection
P43
Te

RT8223P RT8241A
3V/5V 36 VCCSA P40
MIC JACK
P28
TPS51650 TPS51728
Speaker CPU core/VAXG P37 VGPU Core P41
w.

P28
EM-6781-T3 Touch Pad Fan Driver
HP K/B Con. HALL SENSOR Board Con. (PWM Type)
TPS51219 MP2139DD
P28 P33 P23 P26 P33 +1.05V_PCH / +1.05V_VTT +1.5V_GFX/1.05V_GFX/3V_GFX
P38 P42
ww

A A

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
Block Diagram
Date: Wednesday, February 08, 2012 Sheet 1 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

VGA power up sequence

+3V
EC

m
MOSFET +3V_GFX
A A
dGPU_RWR_EN

co
VIN
+VGACORE

a.
+1.05V
PWM
dGPU_VRON VGA_PG DGPU_PWROK
MOSFET +1.05V_GFX
MOSFET +1.5V_GFX

si
+1.5VSUS
VGA_VID

VGA_PG

ne
MOSFET +1.8V_GFX
B B
+1.8V

do
Power States
CONTROL

In
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
VIN +10V~+19V MAIN POWER ALWAYS ALWAYS

+3V_RTC +3V~+3.3V RTC POWER ALWAYS ALWAYS

i-
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Thermal Follow Chart
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

NTC
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5
is Thermal
C +5V_S5 +5V USB POWER S5_ON S0-S5 C
Protection
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

kn

+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0 H/W Throttling

+VGFX_AXG variation Internal GPU POWER VRON S0

Te

+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0

SML1ALERT#
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
PCH FAN Driver FAN
+1.05V +1.05V PCH CORE POWER/IVY/SNB bridge VCCIO MAINON S0
w.

+VCCSA +0.9V CPU POWER HWPG_VTT S0

SM-Bus
+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

EC
ww

MAINON S0 CPUFAN#
D D

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
PWR Status & GPU PWR CRL & THRM
Date: Wednesday, February 08, 2012 Sheet 2 of 46
1 2 3 4 5 6 7 8
 5 4 3 2 1

03
For Sandy Bridge processor only implementation:
PROC_SELECT can be left NC. IVY Bridge Processor (CLK,MISC,JTAG) iGPU wo eDP and dGPU
IVY Bridge Processor (DMI,PEG,FDI) For IVY/Sandy processor compatibility:
Needs a pull-up resistor to PCH VccDFTERM rail (1.8V) through a 2.2 K±5% pull-up resistor.
Connect DPLL_REF_SSCLK on Processor to GND through 1K ± 5% resistor.
U15A Connect to the DF_TVS of PCH though a 1K±5% series resistor. U15B Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K ± 5% resistor
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
7 DMI_TXN0 B27
DMI_RX#[0] PEG_RCOMPO
H22 PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
A28 CLK_CPU_BCLKP_R

m
7 DMI_TXN1 B25 PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils. 3 4 CLK_CPU_BCLKP 9
DMI_RX#[1] BCLK

MISC

CLOCKS
D D
A25 8 H_SNB_IVB# R398 *SHORT_4 PROC_SELECT# C26 A27 CLK_CPU_BCLKN_R 1 2 CLK_CPU_BCLKN 9
7 DMI_TXN2 DMI_RX#[2] PROC_SELECT# BCLK#
B24 K33 PEG_RX#0 16 R401 0_4P2R
7 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1 16
PEG_RX#[1] SKTOCC#
7 DMI_TXP0 B28
DMI_RX[0] PEG_RX#[2]
L34 PEG_RX#2 16 TP16 AN34
SKTOCC# Ra
B26 J35 A16 CLK_DPLL_SSCLKP_R 3 4

co
7 DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_RX#3 16 DPLL_REF_CLK CLK_DPLL_SSCLKP 9

DMI
7 DMI_TXP2 A24 DMI_RX[2] PEG_RX#[4] J32 PEG_RX#4 16 DPLL_REF_CLK# A15 CLK_DPLL_SSCLKN_R 1 2 CLK_DPLL_SSCLKN 9
B23 H34 PEG_RX#5 16 R412 IOP@0_4P2R
7 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
H31 PEG_RX#6 16 Rb
PEG_RX#[6] TP_CATERR# R414 EV@1K_4
7 DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33 PEG_RX#7 16 TP15 AL33 CATERR# +1.05V
7 DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30 PEG_RX#8 16 Rc
F21 F35 PEG_RX#9 16 R410 EV@1K_4
7 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]

THERMAL
7 DMI_RXN3 D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_RX#10 16 EV UMA/OPT.
E32 AN33 R8 CPU_DRAMRST#
PEG_RX#[11] PEG_RX#11 16 34 EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# 15
7 DMI_RXP0 G22 D33 PEG_RX#12 16 Ra NA 0 ohm

DDR3
MISC
DMI_TX[0] PEG_RX#[12]
7 DMI_RXP1 D22 D31 PEG_RX#13 16
DMI_TX[1] PEG_RX#[13]

a.
F20 B33 PEG_RX#14 16 Rb 1K NA

PCI EXPRESS* - GRAPHICS

7 DMI_RXP2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_RX#15 16 34,37 H_PROCHOT# H_PROCHOT# R101 56_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R460 140/F_4
7 DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP_1 R437 25.5./F_4 Rc 1K NA
SM_RCOMP[1] SM_RCOMP_2 R438 200/F_4
J33 PEG_RX0 16 A4
PEG_RX[0] SM_RCOMP[2]
L35 PEG_RX1 16
PEG_RX[1] PM_THRMTRIP#
PEG_RX[2] K34 PEG_RX2 16 10 PM_THRMTRIP# AN32 THERMTRIP# CRB 1.0 : SM_RCOMP[2..0] W:20mils, S:15mils, L 500mils
7 FDI_TXN0 A21 H35 PEG_RX3 16
FDI0_TX#[0] PEG_RX[3]
7 FDI_TXN1 H19 H32 PEG_RX4 16
FDI0_TX#[1] PEG_RX[4]
E19 G34
7 FDI_TXN2
F18
FDI0_TX#[2] PEG_RX[5]
G31
PEG_RX5 16 DIS.VGA-->EV@ + EOP@
Intel(R) FDI

7 FDI_TXN3 FDI0_TX#[3] PEG_RX[6] PEG_RX6 16

Intel recommended UNCOREPWRGOOD XDP_PRDY#

si
B21 F33 AP29
7
7
FDI_TXN4
FDI_TXN5 C20
FDI1_TX#[0] PEG_RX[7]
F30
PEG_RX7 16
PEG_RX8 16
Optimize-->IOP@ + EOP@ PRDY#
AP27 XDP_PREQ#
TP25
TP27
D18
FDI1_TX#[1] PEG_RX[8]
E35 routing on one layer PREQ#
7
7
FDI_TXN6
FDI_TXN7 E17
FDI1_TX#[2]
FDI1_TX#[3]
PEG_RX[9]
PEG_RX[10] E33
PEG_RX9 16
PEG_RX10 16
UMA-->IV@ + IOP@ TCK AR26 XDP_TCLK
TP29

PWR MANAGEMENT
F32 AR27 PCH_JTAG_TMS

JTAG & BPM

PEG_RX[11]
PEG_RX[12]
D34
PEG_RX11 16
PEG_RX12 16
Special-->SP@ 7 PM_SYNC R81 *SHORT_4 PM_SYNC_R AM34
PM_SYNC
TMS
TRST#
AP30 XDP_TRST#
TP28
TP20
7 FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31 PEG_RX13 16
G19 C33 apply C5205 for nosie C155 0.1u/10V_4 AR28 PCH_JTAG_TDI
7 FDI_TXP1 FDI0_TX[1] PEG_RX[14] PEG_RX14 16 TDI TP26
E20 B32 PEG_RX15 16 AP26 PCH_JTAG_TDO
7 FDI_TXP2 FDI0_TX[2] PEG_RX[15] TDO
G18 10 H_PWRGOOD R102 *SHORT_4 H_PWRGOOD_R AP33
7 FDI_TXP3 FDI0_TX[3] UNCOREPWRGOOD
B20 M29 R_PEG_TX#0 C411 [email protected]/10V_4 PEG_TX#0 16

ne
7 FDI_TXP4 FDI1_TX[0] PEG_TX#[0]
C19 M32 R_PEG_TX#1 C414 [email protected]/10V_4 PEG_TX#1 16 R107 10K_4
7 FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 R_PEG_TX#2 C416 [email protected]/10V_4 AL35
C 7 FDI_TXP6 FDI1_TX[2] PEG_TX#[2] PEG_TX#2 16 DBR# XDP_DBRST# 7 C
F17 L32 R_PEG_TX#3 C419 [email protected]/10V_4 PEG_TX#3 16 15 PM_DRAM_PWRGD_R V8
7 FDI_TXP7 FDI1_TX[3] PEG_TX#[3] R_PEG_TX#4 SM_DRAMPWROK
L29 C421 [email protected]/10V_4 PEG_TX#4 16
PEG_TX#[4] R_PEG_TX#5 C425 [email protected]/10V_4 XDP_BPM0
7 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 PEG_TX#5 16 BPM#[0] AT28 TP102
J17 K28 R_PEG_TX#6 C426 [email protected]/10V_4 +1.05V AR29 XDP_BPM1
7 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] PEG_TX#6 16 BPM#[1] TP101
J30 R_PEG_TX#7 C430 [email protected]/10V_4 AR30 XDP_BPM2
PEG_TX#[7] PEG_TX#7 16 BPM#[2] TP97
H20 J28 R_PEG_TX#8 C435 [email protected]/10V_4 R103 75_4 R105 43_4 CPU_PLTRST#_R AR33 AT30 XDP_BPM3
7 FDI_INT FDI_INT PEG_TX#[8]
PEG_TX#[9] H29 R_PEG_TX#9
R_PEG_TX#10
C438 [email protected]/10V_4
PEG_TX#8 16
PEG_TX#9 16
RESET# BPM#[3]
BPM#[4] AP32 XDP_BPM4
XDP_BPM5
TP99
TP19
For XDP
J19 G27 C440 [email protected]/10V_4 PEG_TX#10 16 AR31
7 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] BPM#[5] TP22

do
H17 E29 R_PEG_TX#11 C444 [email protected]/10V_4 PEG_TX#11 16 AT31 XDP_BPM6
7 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6] TP96
F27 R_PEG_TX#12 C446 [email protected]/10V_4 CPU_PLTRST# AR32 XDP_BPM7
PEG_TX#[12] PEG_TX#12 16 BPM#[7] TP95
D28 R_PEG_TX#13 C448 [email protected]/10V_4 PEG_TX#13 16 R106
PEG_TX#[13] R_PEG_TX#14 C451 [email protected]/10V_4
F26 PEG_TX#14 16
PEG_TX#[14] R_PEG_TX#15 C452 [email protected]/10V_4 *750/F_4
PEG_TX#[15] E25 PEG_TX#15 16
A18
eDP_COMP eDP_COMPIO R_PEG_TX0 C412 [email protected]/10V_4 Ivy Bridge_rPGA_2DPC_Rev0p61
A17 M28 PEG_TX0 16
eDP_ICOMPO PEG_TX[0] R_PEG_TX1 C415 [email protected]/10V_4
23 INT_eDP_HPD_Q B16 M33 PEG_TX1 16
eDP_HPD PEG_TX[1] R_PEG_TX2 C418 [email protected]/10V_4
M30 PEG_TX2 16
PEG_TX[2] R_PEG_TX3 C420 [email protected]/10V_4
L31 PEG_TX3 16
PEG_TX[3] R_PEG_TX4 C422 [email protected]/10V_4
C15 L28

In
23 EDP-AUX+ eDP_AUX PEG_TX[4] PEG_TX4 16
D15 K30 R_PEG_TX5 C424 [email protected]/10V_4
23 EDP-AUX- eDP_AUX# PEG_TX[5] PEG_TX5 16
eDP

K27 R_PEG_TX6 C428 [email protected]/10V_4 PEG_TX6 16

PEG_TX[6] R_PEG_TX7 C432 [email protected]/10V_4 R104 *1.5K/F_4
PEG_TX[7] J29 PEG_TX7 16 9 PCI_PLTRST#
C17 J27 R_PEG_TX8 C433 [email protected]/10V_4
23 EDP-ML0+ eDP_TX[0] PEG_TX[8] PEG_TX8 16
F16 H28 R_PEG_TX9 C436 [email protected]/10V_4 PEG_TX9 16 +3V
TP107 eDP_TX[1] PEG_TX[9]
C16 G28 R_PEG_TX10 C441 [email protected]/10V_4
TP104 eDP_TX[2] PEG_TX[10] PEG_TX10 16
G15 E28 R_PEG_TX11 C442 [email protected]/10V_4 PEG_TX11 16
TP109 eDP_TX[3] PEG_TX[11] R_PEG_TX12
PEG_TX[12]
F28 C447 [email protected]/10V_4 PEG_TX12 16 C156 CRB 1.0 : change to +3V(S0)
C18 D27 R_PEG_TX13 C449 [email protected]/10V_4 U4 0.1u/10V_4
23 EDP-ML0- eDP_TX#[0] PEG_TX[13] PEG_TX13 16
E16 E26 R_PEG_TX14 C450 [email protected]/10V_4 PEG_TX14 16 1 5
TP106 eDP_TX#[1] PEG_TX[14] NC VCC

i-
D16 D25 R_PEG_TX15 C455 [email protected]/10V_4
TP105 eDP_TX#[2] PEG_TX[15] PEG_TX15 16
TP108 F15 2
eDP_TX#[3] IN
3 4 CPU_PLTRST#
Ivy Bridge_rPGA_2DPC_Rev0p61 GND OUT
74LVC1G07GW
HPD disable DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
B This signal can be left as no PCIe Gen3 on future platforms. B

connect if entire eDP interface For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
is disabled.
N13P-GS--->Gen2
is
kn

FDI Disabling (Discrete Only)

Te

+1.05V

3
C29 Reserve FDI Disabling (Discrete Only), add
R665,R666,R667,R668,R669. 1/13 Processor pull-up(CPU)
1/13 add DP & PEG Compensation +1.05V 7,37 IMVP_PWRGD 2 Q8 5,7,8,9,11,23,34,37,38,42,43,46 +1.05V
7,8,9,10,11,13,14,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
FDV301N

+1.05V
Routed within 500 mils

1
FDI_INT +1.05V
w.

H_PROCHOT# R98 62_4

R665 EV@0_4 FDI_FSYNC0 R93
R668 EV@0_4 FDI_FSYNC1 PCH_JTAG_TDO R118 51_4 1K_4

A
R669 EV@0_4 FDI_LSYNC0
FDI_LSYNC1
Routed within 25 mils R409 24.9/F_4 PEG_COMP PCH_JTAG_TMS
PCH_JTAG_TDI
R119
R115
51_4
51_4 A
PEG_ICOMPI and RCOMPO signals should XDP_PREQ# R114 *51_4

2
FDI_FSYNC can gang R411 24.9/F_4 eDP_COMP be routed within 500 mils XDP_TCLK R121 51_4
R667 all these 4 XDP_TRST# R111 51_4 Q7
R666 eDP_COMPIO and ICOMPO signals should typical impedance = 43 mohms PM_THRMTRIP# 1 3 MMBT3904
signals together SYS_SHDN# 19,36,43
EV@1K/F_4 EV@1K/F_4 be shorted near balls and routed with
ww

and tie them with PEG_ICOMPO signals should

only one 1K typical impedance <25 mohms
be routed within 500 mils
resistor to GND typical impedance = 14.5 mohms
(DG V0.5 Ch2.2.9).
Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
IVY Bridge 1/4 3C

Date: Wednesday, February 08, 2012 Sheet 3 of 46

5 4 3 2 1
 5 4 3 2 1

IVY Bridge Processor (DDR3) 04

U15C U15D

AB6 AE2

m
13 M_A_DQ[63:0] SA_CLK[0] M_A_CLK0 13 14 M_B_DQ[63:0] SB_CLK[0] M_B_CLK0 14
SA_CLK#[0] AA6 M_A_CLK0# 13 SB_CLK#[0] AD2 M_B_CLK0# 14
D M_A_DQ0 M_B_DQ0 D
C5 SA_DQ[0] SA_CKE[0] V9 M_A_CKE0 13 C9 SB_DQ[0] SB_CKE[0] R9 M_B_CKE0 14
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]

co
M_A_DQ3 D2 M_B_DQ3 C8
M_A_DQ4 SA_DQ[3] M_B_DQ4 SB_DQ[3]
D6 AA5 M_A_CLK1 13 A9 AE1 M_B_CLK1 14
M_A_DQ5 SA_DQ[4] SA_CLK[1] M_B_DQ5 SB_DQ[4] SB_CLK[1]
C6 SA_DQ[5] SA_CLK#[1] AB5 M_A_CLK1# 13 A8 SB_DQ[5] SB_CLK#[1] AD1 M_B_CLK1# 14
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
SA_DQ[6] SA_CKE[1] M_A_CKE1 13 SB_DQ[6] SB_CKE[1] M_B_CKE1 14
M_A_DQ7 C3 M_B_DQ7 D8
M_A_DQ8 SA_DQ[7] M_B_DQ8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
M_A_DQ9 F8 M_B_DQ9 F4
M_A_DQ10 SA_DQ[9] M_B_DQ10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
M_A_DQ11 M_B_DQ11

a.
G9 AA4 G1 AA2
M_A_DQ12 SA_DQ[11] SA_CLK#[2] M_B_DQ12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
M_A_DQ13 F7 M_B_DQ13 F5
M_A_DQ14 SA_DQ[13] M_B_DQ14 SB_DQ[13]
G8 F2
M_A_DQ15 SA_DQ[14] M_B_DQ15 SB_DQ[14]
G7 G2
M_A_DQ16 SA_DQ[15] M_B_DQ16 SB_DQ[15]
K4 SA_DQ[16] SA_CLK[3] AB3 J7 SB_DQ[16] SB_CLK[3] AA1
M_A_DQ17 K5 AA3 M_B_DQ17 J8 AB1
M_A_DQ18 SA_DQ[17] SA_CLK#[3] M_B_DQ18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W10 K10 SB_DQ[18] SB_CKE[3] T10
M_A_DQ19 J1 M_B_DQ19 K9

si
M_A_DQ20 SA_DQ[19] M_B_DQ20 SB_DQ[19]
J5 J9
M_A_DQ21 SA_DQ[20] M_B_DQ21 SB_DQ[20]
J4 J10
M_A_DQ22 SA_DQ[21] M_B_DQ22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 M_A_CS#0 13 K8 SB_DQ[22] SB_CS#[0] AD3 M_B_CS#0 14
M_A_DQ23 K2 AL3 M_B_DQ23 K7 AE3
SA_DQ[23] SA_CS#[1] M_A_CS#1 13 SB_DQ[23] SB_CS#[1] M_B_CS#1 14
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ[24] SA_CS#[2] M_B_DQ25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
M_A_DQ26 N8 M_B_DQ26 N2
M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26]
N7 N1
SA_DQ[27] SB_DQ[27]

ne
M_A_DQ28 M10 M_B_DQ28 M4
M_A_DQ29 SA_DQ[28] M_B_DQ29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_A_ODT0 13 N5 SB_DQ[29] SB_ODT[0] AE4 M_B_ODT0 14

DDR SYSTEM MEMORY B

M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A

SA_DQ[30] SA_ODT[1] M_A_ODT1 13 SB_DQ[30] SB_ODT[1] M_B_ODT1 14

M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
C M_A_DQ32 SA_DQ[31] SA_ODT[2] M_B_DQ32 SB_DQ[31] SB_ODT[2] C
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
M_A_DQ34 SA_DQ[33] M_B_DQ34 SB_DQ[33]
AK6 AR3
M_A_DQ35 SA_DQ[34] M_B_DQ35 SB_DQ[34]
AK5 SA_DQ[35] AP3 SB_DQ[35]
M_A_DQ36 AH5 M_B_DQ36 AN3

do
M_A_DQ37 SA_DQ[36] M_A_DQS#0 M_B_DQ37 SB_DQ[36] M_B_DQS#0
AH6 C4 AN2 D7
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQS#1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQS#1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQS#2 M_B_DQ39 AP2 K6 M_B_DQS#2
M_A_DQ40 SA_DQ[39] SA_DQS#[2] M_A_DQS#3 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQS#3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ41 AK8 AL6 M_A_DQS#4 M_B_DQ41 AN9 AN5 M_B_DQS#4
M_A_DQ42 SA_DQ[41] SA_DQS#[4] M_A_DQS#5 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQS#5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
M_A_DQ43 AK9 AR12 M_A_DQS#6 M_B_DQ43 AT6 AK12 M_B_DQS#6
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQS#7 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQS#7
AH8 SA_DQ[44] SA_DQS#[7] AM15 M_A_DQS#[7:0] 13 AP6 SB_DQ[44] SB_DQS#[7] AP15 M_B_DQS#[7:0] 14

In
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ[45] M_B_DQ46 SB_DQ[45]
AL9 AR6
M_A_DQ47 SA_DQ[46] M_B_DQ47 SB_DQ[46]
AL8 AR5
M_A_DQ48 SA_DQ[47] M_B_DQ48 SB_DQ[47]
AP11 AR9
M_A_DQ49 SA_DQ[48] M_A_DQS0 M_B_DQ49 SB_DQ[48] M_B_DQS0
AN11 D4 AJ11 C7
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQS1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQS1
AL12 F6 AT8 G3
M_A_DQ51 SA_DQ[50] SA_DQS[1] M_A_DQS2 M_B_DQ51 SB_DQ[50] SB_DQS[1] M_B_DQS2
AM12 SA_DQ[51] SA_DQS[2] K3 AT9 SB_DQ[51] SB_DQS[2] J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
M_A_DQ53 SA_DQ[52] SA_DQS[3] M_A_DQS4 M_B_DQ53 SB_DQ[52] SB_DQS[3] M_B_DQS4

i-
AL11 AL5 AR8 AN6
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQS5 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQS5
AP12 AM9 AJ12 AP8
M_A_DQ55 SA_DQ[54] SA_DQS[5] M_A_DQS6 M_B_DQ55 SB_DQ[54] SB_DQS[5] M_B_DQS6
AN12 AR11 AH12 AK11
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQS7 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQS7
AJ14 AM14 M_A_DQS[7:0] 13 AT11 AP14 M_B_DQS[7:0] 14
M_A_DQ57 SA_DQ[56] SA_DQS[7] M_B_DQ57 SB_DQ[56] SB_DQS[7]
AH14 AN14
M_A_DQ58 SA_DQ[57] M_B_DQ58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ[59] M_B_DQ60 SB_DQ[59]
AL14 AT12
M_A_DQ61 SA_DQ[60] M_A_A0 M_B_DQ61 SB_DQ[60] M_B_A0
AK14 AD10 AN15 AA8
M_A_DQ62
M_A_DQ63
AJ15
AH15
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_MA[0]
SA_MA[1]
SA_MA[2]
W1
W2
M_A_A1
M_A_A2
is M_B_DQ62
M_B_DQ63
AR15
AT15
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_MA[0]
SB_MA[1]
SB_MA[2]
T7
R7
M_B_A1
M_B_A2
B M_A_A3 M_B_A3 B
SA_MA[3] W7 SB_MA[3] T6
V3 M_A_A4 T2 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
V2 T4
SA_MA[5] M_A_A6 SB_MA[5] M_B_A6
SA_MA[6] W3 SB_MA[6] T3
13 M_A_BS#0 AE10 W6 M_A_A7 14 M_B_BS#0 AA9 R2 M_B_A7
SA_BS[0] SA_MA[7] M_A_A8 SB_BS[0] SB_MA[7] M_B_A8
13 M_A_BS#1 AF10 V1 14 M_B_BS#1 AA7 T5
SA_BS[1] SA_MA[8] SB_BS[1] SB_MA[8]
kn

V6 W5 M_A_A9 R6 R3 M_B_A9
13 M_A_BS#2 SA_BS[2] SA_MA[9] 14 M_B_BS#2 SB_BS[2] SB_MA[9]
AD8 M_A_A10 AB7 M_B_A10
SA_MA[10] M_A_A11 SB_MA[10] M_B_A11
V4 R1
SA_MA[11] M_A_A12 SB_MA[11] M_B_A12
SA_MA[12] W4 SB_MA[12] T1
AE8 AF8 M_A_A13 AA10 AB10 M_B_A13
13 M_A_CAS# SA_CAS# SA_MA[13] 14 M_B_CAS# SB_CAS# SB_MA[13]
AD9 V5 M_A_A14 AB8 R5 M_B_A14
13 M_A_RAS# SA_RAS# SA_MA[14] 14 M_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 M_A_A15 AB9 R4 M_B_A15
13 M_A_WE# SA_WE# SA_MA[15] M_A_A[15:0] 13 14 M_B_WE# SB_WE# SB_MA[15] M_B_A[15:0] 14
Te

Ivy Bridge_rPGA_2DPC_Rev0p61 Ivy Bridge_rPGA_2DPC_Rev0p61

w.
ww

A A

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
IVY Bridge 2/4 3C

Date: Wednesday, February 08, 2012 Sheet 4 of 46

5 4 3 2 1
 5 4 3 2 1

05
3,7,8,9,11,23,34,37,38,42,43,46 +1.05V
37,45,46 +VCC_CORE
8,11,43,46 +1.8V CPU VTT
37,45 +VCC_GFX
IVY 45W:8.5A
CPU VGT IVY SPEC IVY Bridge Processor (GRAPHIC POWER)
15 +1.5V_CPU IVY Processor (POWER) Cose down IVY 45W:TDC 38A Cose down 22uF_8 x2 Socket TOP cavity
15 +VDDR_REF_CPU SNB : Spec 330uF x1 330uF x1 22uF_8 x2 Socket BOT cavity
Spec
40 +VCCSA 330uF/6mohm x 2
22uF x 12
22uF x 2 470uF/4mohm x 2 22uF x 4
22uF_8 x4 Socket TOP edge
22uF_8 x4 Socket BOT edge
U15G
POWER
470uF_7343 x2
+1.05V
10uF x 10 22uF x 12 10uF x 10
22uF x 7 (Non-stuff) reserved x 4 R369 100/F_4
CPU Core Power +VCC_GFX
POWER

SENSE
LINES
AT24 AK35 VCC_AXG_SENSE 37
U15F VAXG1 VAXG_SENSE
IVY 45W:TDC 52A +VCC_GFX AT23
VAXG2 VSSAXG_SENSE
AK34 VSS_AXG_SENSE 37
AT21 R370 100/F_4
+VCC_CORE VAXG3
D IVY SPEC + C503 + C235 + C534
AT20
VAXG4 D

m
AT18
22uF_8 x8 Socket TOP cavity + C539 + C204 VAXG5
AT17 VAXG6
22uF_8 x10 Socket BOT cavity AG35 330u/2V_7343 330u/2V_7343 IOP@330u/2V_7343 *IOP@330u/2V_7343 AR24
VCC1 IOP@330u/2V_7343 VAXG7
AG34 AH13 AR23 For M3 solution
22uF_8 x8 Socket TOP edge VCC2 VCCIO1 VAXG8
AG33
VCC3 VCCIO2
AH10 AR21
VAXG9 10 mil need Rb4, Rd1
470uF_7343 x4 AG32 AG10 AR20

co
VCC4 VCCIO3 VAXG10 +VDDR_REF_CPU
AG31 VCC5 VCCIO4 AC10 AR18 VAXG11 SM_VREF AL1 +VDDR_REF_CPU W/O M3 then NC
total : 10uF x 10 , RSVD x 1 AG30 Y10 AR17
VCC6 VCCIO5 VAXG12

VREF
total : 22uF x 16 , RSVD x 3 AG29 U10 AP24 ball B4 and D1
VCC7 VCCIO6 VAXG13
AG28 VCC8 VCCIO7 P10 AP23 VAXG14
tatal : 470u x 4, RSVD x2 AG27 L10 C526 C191 C190 C529 C206 C530 C187 C216 C208 C207 AP21 Rb4 R466 *1K_4
VCC9 VCCIO8 IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG15
AG26 J14 AP20 B4 SMDDR_VREF_DQ0_M3 13
VCC10 VCCIO9 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG16 SA_DIMM_VREFDQ
AF35 VCC11 VCCIO10 J13 AP18 VAXG17 SB_DIMM_VREFDQ D1 SMDDR_VREF_DQ1_M3 14
AF34 J12 AP17 R469 *1K_4
VCC12 VCCIO11 VAXG18
SNB : Spec Cose down AF33 VCC13 VCCIO12 J11 AN24 VAXG19 Rd1
AF32 H14 AN23
VCC14 VCCIO13 VAXG20

a.
470uF/4mohm x 4 330uF x2 AF31
VCC15 VCCIO14
H12 AN21
VAXG21
AF30
VCC16 VCCIO15
H11 AN20
VAXG22 IVY SPEC

DDR3 -1.5V RAILS

22uF x 16 22uF x 4 AF29
VCC17 VCCIO16
G14 AN18
VAXG23 330uF x1, 10uF_8 x6 Socket BOT edge. +1.5V_CPU
AF28 G13 C528 C527 C209 C522 C532 C525 AN17
VCC18 VCCIO17 VAXG24

GRAPHICS
PEG AND DDR
10uF x 10 10uF x 20 AF27
VCC19 VCCIO18
G12 AM24
VAXG25 VDDQ1
AF7
AF26 F14 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 C183 C217 C186 C193 AM23 AF4
reserved x 5 VCC20 VCCIO19 *IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG26 VDDQ2
AD35 F13 AM21 AF1
VCC21 VCCIO20 *IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG27 VDDQ3
AD34 F12 AM20 AC7
VCC22 VCCIO21 VAXG28 VDDQ4
AD33 VCC23 VCCIO22 F11 AM18 VAXG29 VDDQ5 AC4
AD32 E14 AM17 AC1 C546 C547 C544 C543 C234
C172 C513 C515 C510 C179 C164 C168 VCC24 VCCIO23 VAXG30 VDDQ6 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8

si
AD31 E12 AL24 Y7
VCC25 VCCIO24 VAXG31 VDDQ7
AD30 VCC26 AL23 VAXG32 VDDQ8 Y4
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 AD29 E11 C205 C536 C535 C521 C520 C523 AL21 Y1
*22u/6.3V_8 VCC27 VCCIO25 VAXG33 VDDQ9
AD28 VCC28 VCCIO26 D14 AL20 VAXG34 VDDQ10 U7
AD27 D13 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 AL18 U4
VCC29 VCCIO27 C184 C185 C201 C200 VAXG35 VDDQ11
AD26 D12 AL17 U1
VCC30 VCCIO28 *IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG36 VDDQ12
AC35 VCC31 VCCIO29 D11 AK24 VAXG37 VDDQ13 P7
AC34 C14 *IOP@22u/6.3V_8 IOP@22u/6.3V_8 AK23 P4 C558
C188 C189 C506 C178 C504 C180 C505 VCC32 VCCIO30 VAXG38 VDDQ14 C245 C240 C230 +
AC33
VCC33 VCCIO31
C13 IVY SPEC AK21
VAXG39 VDDQ15
P1
C AC32 C12 22uF_8 x7 Socket TOP cavity AK20 10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 C
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VCC34 VCCIO32 VAXG40 330u/2V_7343
AC31 C11 AK18

ne
*22u/6.3V_8 *22u/6.3V_8 VCC35 VCCIO33 22uF_8 x5 Socket BOT cavity VAXG41
AC30 B14 AK17
VCC36 VCCIO34 22uF_8 x2 Socket TOP cavity (no stuff) VAXG42
AC29 VCC37 VCCIO35 B12 AJ24 VAXG43
AC28 A14 22uF_8 x5 Socket BOT cavity (no stuff) AJ23
VCC38 VCCIO36 C507 C516 C501 C512 VAXG44
AC27 A13 330uF_7343 x2 AJ21
VCC39 VCCIO37 IOP@22u/6.3V_8 IOP@22u/6.3V_8 VAXG45
AC26 VCC40 VCCIO38 A12 AJ20 VAXG46
AA35 A11 IOP@22u/6.3V_8 IOP@22u/6.3V_8 AJ18
VCC41 VCCIO39 VAXG47
AA34 AJ17 M27

SA RAIL
VCC42 +1.05V_VTT_40 R407 *SHORT_4 VAXG48 VCCSA1
AA33 VCC43 VCCIO40 J23 +1.05V AH24 VAXG49 VCCSA2 M26 +VCCSA
C514 C176 C181 C511 C517 AA32 AH23 L26
VCC44 VAXG50 VCCSA3
AA31 AH21 J26
VCC45 VAXG51 VCCSA4

do
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 AA30 AH20 J25 C182 C169 C502 + C445
AA29
VCC46 DIS.VGA-->EV@ + EOP@ AH18
VAXG52 VCCSA5
J24 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 330u/2V_7343
AA28
VCC47 R129 Ra EV@0/J_4 AH17
VAXG53 VCCSA6
H26
AA27
VCC48
VCC49
Optimus-->IOP@ + EOP@ VAXG54 VCCSA7
VCCSA8
H25
AA26 VCC50 UMA-->IV@ + IOP@
CORE SUPPLY

Y35
C195 C498 C499 C500 C177 Y34
VCC51 DIS. VGA UMA/ Optimus
Y33
VCC52
VCC53
Ssecial-->SP@ Ra 0 ohm NA

1.8V RAIL
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 Y32
*10u/6.3V_8 VCC54
Y31 H23 VCCSA_SENSE 40
VCC55 VCCSA_SENSE
Y30

In
VCC56 R470 *SHORT_8
Y29 +1.8V
VCC57
Y28 VCC58 B6 VCCPLL1

MISC
Y27 R471 *SHORT_8 CPU_VCCPLL A6 C22
VCC59 VCCPLL2 VCCSA_VID[0] VCCSA_VID0 40
10uF (Reserved) Y26
VCC60
A2
VCCPLL3 VCCSA_VID[1]
C24 VCCSA_VID1 40
V35
VCC61 CPU VCCPL
SVID

V34 AJ29 H_CPU_SVIDALRT#

C167 C197 C146 C194 C196 VCC62 VIDALERT# H_CPU_SVIDCLK C551 C555 C556 + C550
V33 AJ30
VCC63 VIDSCLK H_CPU_SVIDDAT 10u/6.3V_8 1u/6.3V_4 1u/6.3V_4 *330u/2V_7343 VCCIO_SEL_NC
V32
VCC64 VIDSOUT
AJ28 IVY 45W:1.5A VCCIO_SEL
A19 TP103
22u/6.3V_8 22u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 V31
VCC65
V30
VCC66 Spec Real

i-
V29 Ivy Bridge_rPGA_2DPC_Rev0p61
VCC67
V28
VCC68 330uF/7mohm x 1 10uF x 1
V27
VCC69
Voltage selection for VCCIO:
B V26
VCC70 10uF x 1 1uF x 2 this pin must be pulled high B
U35 VCC71 on the motherboard
C175 C174 C457 C454 U34 1uF x 2
+ + + + U33
VCC72 Layout note: need routing
VCC73 SVID CLK On CRB
330u/2V_7343 330u/2V_7343 *470u/2V_7343 *470u/2V_7343
U32
U31
VCC74
IVY SPEC
together and ALERT need H_SNB_IVB#_PWRCTRL = low, 1.0V
VCC75
U30
VCC76 330uF x1, 10uF_8 x1, 1uF_4 x2 between CLK and DATA Remove PU resistor 54.9/F, H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
U29
U28
U27
VCC77
VCC78
VCC79
is Socket BOT edge. stuff at IMVP7 page

U26 VCC80
R35
VCC81
R34
VCC82
R33 VCC83 IVY SPEC
R32 H_CPU_SVIDCLK R354 *SHORT_4
R31
VCC84 VR_SVID_CLK 37 330uF x1, 10uF_8 x1 Socket BOT edge, CPU MCH
VCC85 10uF_8 x2 Socket BOT cavity.
R30
VCC86 IVY 45W: 5A
R29
kn
VCC87
SENSE LINES

R28 R360 100/F_4

R27
VCC88
AJ35 R367 *SHORT_4
+VCC_CORE Place PU resistor close to CPU CPU SA Spec
R26
VCC89 VCC_SENSE
AJ34 R368 *SHORT_4
VCC_SENSE 37 SVID DATA IVY 45W: 6A 330uF/6mohm x 1
VCC90 VSS_SENSE VSS_SENSE 37 +1.05V
P35 R361 100/F_4
VCC91
P34 VCC92 Remove PU resistor 130/F, Spec Real 10uF x 6
P33 stuff at IMVP7 page
VCC93 VTT_VCCP_SENSE
P32
VCC94 VCCIO_SENSE
B10
VTT_VSSP_SENSE
VTT_VCCP_SENSE 38 330uF/7mohm x 1 10uF x 3 Real
P31 A10 VTT_VSSP_SENSE 38
VCC95 VSS_SENSE_VCCIO R365
P30 VCC96 10uF x 3 10uF x 8
P29 130/F_4
VCC97
Te

P28
VCC98 R421 10/F_4 H_CPU_SVIDDAT R353 *SHORT_4
P27 +1.05V VR_SVID_DATA 37
VCC99
P26 VCC100 R425 10/F_4

Trace Route to Power IC area. Place PU resistor close to CPU SVID ALERT
Ivy Bridge_rPGA_2DPC_Rev0p61
A +1.05V A
w.

R366
75_4

H_CPU_SVIDALRT# R359 43_4 R355 *SHORT_4 VR_SVID_ALERT# 37

Quanta Computer Inc.
PROJECT : ZQS 45W
ww

Size Document Number Rev

IVY Bridge 3/4 3C

Date: Wednesday, February 08, 2012 Sheet 5 of 46

5 4 3 2 1
 5 4 3 2 1

IVY Bridge Processor (GND)

AT35
AT32
AT29
U15H

VSS1
VSS2
VSS3
VSS81
VSS82
VSS83
AJ22
AJ19
AJ16 T35
U15I

VSS161 VSS234 F22

IVY Bridge Processor (RESERVED, CFG)
U15E 06
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 AJ10 T33 E30 AH27 VCC_DIE_SENSE
VSS5 VSS85 VSS163 VSS236 XDP_CFG0 VCC_DIE_SENSE VSS_DIE_SENSE TP17
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27 TP21 AK28 CFG[0] VSS_DIE_SENSE AH26 TP24
AT19 AJ4 T31 E24 CFG1 AK29
VSS7 VSS87 VSS165 VSS238 TP18 CFG[1]
AT16 AJ3 T30 E21 CFG2 AL26
VSS8 VSS88 VSS166 VSS239 CFG3 CFG[2] R112
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 TP23 AL27 CFG[3] Rs
AT10 AJ1 T28 E15 CFG4 AK26 L7 *0_4 For Sandy For IVY

m
D VSS10 VSS90 VSS168 VSS241 CFG5 CFG[4] RSVD28 D
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AL29 CFG[5] RSVD29 AG7
AT4 AH34 T26 E10 CFG6 AL30 AE7 Rs Stuff NC
VSS12 VSS92 VSS170 VSS243 CFG7 CFG[6] RSVD30
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM31 CFG[7] RSVD31 AK2
AR25 AH30 P8 E8 AM32

co CFG
VSS14 VSS94 VSS172 VSS245 CFG[8]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM30 CFG[9] RSVD32 W8
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AM28 CFG[10]
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5 AM26 CFG[11]
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4 AN28 CFG[12] RSVD33 AT26
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3 AN31 CFG[13] RSVD34 AM33
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2 AN26 CFG[14] RSVD35 AJ27
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1 AM27 CFG[15]
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35 AK31 CFG[16]

a.
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32 AN29 CFG[17]
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20 RSVD37 T8
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17 RSVD38 J16
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34 TP98 AJ31 VAXG_VAL_SENSE RSVD39 H16
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31 TP11 AH31 VSSAXG_VAL_SENSE RSVD40 G16
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28 AJ33 VCC_VAL_SENSE

si
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27 AH33 VSS_VAL_SENSE
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10 AJ26 RSVD5 RSVD41 AR35

RESERVED
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1 RSVD42 AT34
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22 RSVD43 AT33
AN25 AE28 L4 B19 AP35
AN22
AN19
VSS37
VSS38 VSS VSS118
VSS119 AE27
AE26
L3
L2
VSS195
VSS196 VSS VSS268
VSS269 B17
B15
RSVD44
RSVD45 AR34

ne
VSS39 VSS120 VSS197 VSS270
C AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13 C
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11 F25 RSVD8
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9 F24 RSVD9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8 F23 RSVD10
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD46 B34
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD47 A33
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3 G24 RSVD13 RSVD48 A34
AM22 AC2 H33 B2 E23 B35

do
VSS47 VSS128 VSS205 VSS278 RSVD14 RSVD49
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35 D23 RSVD15 RSVD50 C35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32 C30 RSVD16
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29 A31 RSVD17
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26 B30 RSVD18
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23 B29 RSVD19
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD51 AJ32 TP100
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD52 AK32 TP12
AM2 VSS55 VSS136 AB28 H10 VSS213 A30 RSVD22

In
AM1 VSS56 VSS137 AB27 H9 VSS214 C29 RSVD23
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216 BCLK_ITP AN35 TP14
AL28 VSS59 VSS140 Y8 H6 VSS217 J20 RSVD24 BCLK_ITP# AM35 TP13
AL25 VSS60 VSS141 Y6 H5 VSS218 B18 RSVD25
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221

i-
AL13 VSS64 VSS145 W 35 H1 VSS222 J15 RSVD27 RSVD56 AT2
AL10 VSS65 VSS146 W 34 G35 VSS223 RSVD57 AT1
AL7 VSS66 VSS147 W 33 G32 VSS224 RSVD58 AR1
AL4 VSS67 VSS148 W 32 G29 VSS225
AL2 VSS68 VSS149 W 31 G26 VSS226
B
AK33 VSS69 VSS150 W 30 G23 VSS227 B
AK30 VSS70 VSS151 W 29 G20 VSS228 KEY B1
AK27 VSS71 VSS152 W 28 G17 VSS229
AK25 W 27 G11
AK22
AK19
VSS72
VSS73
VSS153
VSS154 W 26
U9
F34
F31
VSS230
VSS231
is
VSS74 VSS155 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 U6 Ivy Bridge_rPGA_2DPC_Rev0p61
VSS76 VSS157
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80
kn

Ivy Bridge_rPGA_2DPC_Rev0p61 Ivy Bridge_rPGA_2DPC_Rev0p61

Te

The CFG signals have a default value of '1' if not terminated on the board.
Processor Strapping CFG[6:5] (PCIE Port Bifurcation Straps)
CFG2 R120 1K/F_4
1 0 CFG5 R110 *1K/F_4 11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG6 R108 *1K/F_4
w.

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

CFG2 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
A
(PEG Static Lane Reversal) Normal Operation Lane Reversed CFG4 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
A
R113 1K/F_4
eDP_EN# 23

CFG4
(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
CFG7 R109 *1K/F_4
Quanta Computer Inc.
ww

CFG7 PEG train immediately following PEG wait for BIOS training
(PEG Defer Training) xxRESETB de assertion PROJECT : ZQS 45W
Size Document Number Rev
IVY Bridge 4/4 3C

Date: Wednesday, February 08, 2012 Sheet 6 of 46

5 4 3 2 1
 5 4 3 2 1

3,5,8,9,11,23,34,37,38,42,43,46
23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46
8,9,10,11,15,16,29,31,33,36,37,38,43,44
+1.05V
+3V
+3V_S5
34 DPWROK_EC DPWROK_EC
CPT/PPT (LVDS,DDI)
U21D
07
CPT/PPT (DMI,FDI,PM) Pin K47 --->LVDS Enable 23 INT_LVDS_BLON J47
M45
L_BKLTEN SDVO_TVCLKINN
AP43
AP45
23 INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
U21C --->2.2K pull-up 3.3V
23 INT_LVDS_BRIGHT P45 AM42
Disable ---> No connect L_BKLTCTL SDVO_STALLN
AM40 Pin M39 ---> Enable
SDVO_STALLP
3 DMI_RXN0 BC24 DMI0RXN FDI_RXN0 BJ14 FDI_TXN0 3 23 INT_LVDS_EDIDCLK T40 L_DDC_CLK
D 3 DMI_RXN1 BE20
DMI1RXN FDI_RXN1
AY14 FDI_TXN1 3 23 INT_LVDS_EDIDDATA K47
L_DDC_DATA SDVO_INTN
AP39 --->2.2K pull-up 3.3V D

m
3 DMI_RXN2 BG18 BE14 FDI_TXN2 3 AP40
DMI2RXN FDI_RXN2 R176 2.2K_4 SDVO_INTP
3 DMI_RXN3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_TXN3 3 +3V T45 L_CTRL_CLK
BC12 R168 2.2K_4 P39
FDI_RXN4 FDI_TXN4 3 L_CTRL_DATA
3 DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 3
3 DMI_RXP1 BC20 BG10 R190 2.37K/F_4 AF37 P38

co
DMI1RXP FDI_RXN6 FDI_TXN6 3 LVD_IBG SDVO_CTRLCLK HDMI_DDCCLK_SW 24
3 DMI_RXP2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_TXN7 3 TP126 AF36 LVD_VBG SDVO_CTRLDATA M39 HDMI_DDCDATA_SW 24
3 DMI_RXP3 BJ20 DMI3RXP
FDI_RXP0 BG14 FDI_TXP0 3 AE48 LVD_VREFH

INT. HDMI
3 DMI_TXN0 AW24 BB14 FDI_TXP1 3 AE47 AT49
DMI0TXN FDI_RXP1 LVD_VREFL DDPB_AUXN
3 DMI_TXN1 AW20 DMI1TXN FDI_RXP2 BF14 FDI_TXP2 3 DDPB_AUXP AT47
3 DMI_TXN2 BB18 DMI2TXN FDI_RXP3 BG13 FDI_TXP3 3 DDPB_HPD AT40 HDMI_HP 24
3 DMI_TXN3 AV18 BE12 23 INT_TXLCLKOUT- AK39

DMI
FDI

LVDS
DMI3TXN FDI_RXP4 FDI_TXP4 3 LVDSA_CLK#
BG12 FDI_TXP5 3 23 INT_TXLCLKOUT+ AK40 AV42 INT_HDMITX2N 24
FDI_RXP5 LVDSA_CLK DDPB_0N
3 DMI_TXP0 AY24 BJ10 FDI_TXP6 3 AV40 INT_HDMITX2P 24
DMI0TXP FDI_RXP6 DDPB_0P
AY20 BH9 AN48 AV45

a.
3 DMI_TXP1 DMI1TXP FDI_RXP7 FDI_TXP7 3 23 INT_TXLOUT0- LVDSA_DATA#0 DDPB_1N INT_HDMITX1N 24
3 DMI_TXP2 AY18 23 INT_TXLOUT1- AM47 AV46 INT_HDMITX1P 24

Digital Display Interface

DMI2TXP LVDSA_DATA#1 DDPB_1P
3 DMI_TXP3 AU18 DMI3TXP 23 INT_TXLOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 INT_HDMITX0N 24
FDI_INT AW16 FDI_INT 3 AJ48 LVDSA_DATA#3 DDPB_2P AU47 INT_HDMITX0P 24
DDPB_3N AV47 INT_HDMICLK- 24
BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 3 23 INT_TXLOUT0+ AN47 LVDSA_DATA0 DDPB_3P AV49 INT_HDMICLK+ 24
23 INT_TXLOUT1+ AM49 LVDSA_DATA1
+1.05V R495 49.9/F_4 DMI_COMP BG25 BC10 23 INT_TXLOUT2+ AK49
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 3 LVDSA_DATA2
R499 750/F_4 BH21 AV14
AJ47
LVDSA_DATA3 DDPC_CTRLCLK
P46
P42 DDPC_HPD_PU
Pin P42 ---> Enable
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 3 DDPC_CTRLDATA

si
--->2.2K pull-up 3.3V
BB10 FDI_LSYNC1 3 AF40
FDI_LSYNC1 LVDSB_CLK#
AF39 AP47
LVDSB_CLK DDPC_AUXN
AP49
DDPC_AUXP +3V
AH45 AT38
LVDSB_DATA#0 DDPC_HPD
DSWVRMEN A18 DSWVREN 8 AH47 LVDSB_DATA#1
AF49 AY47
C22 Change R220 from shortpad to 0Ω, reserve 0Ω R646 connect to DPWROK_EC. 01/05 LVDSB_DATA#2 DDPC_0N DDPC_HPD_PU R153 *2.2K_4

System Power Management

AF45 LVDSB_DATA#3 DDPC_0P AY49
SUS_PWR_ACK R257 *0_4 SUSACK#_R C12 E22 0_4 R220 PCH_RSMRST# AY43
C SUSACK# DPWROK *0_4 R646 DPWROK_EC DDPC_1N DDPD_HPD_PU R158 *2.2K_4 C
AH43 AY45

ne
XDP_DBRST# LVDSB_DATA0 DDPC_1P
3 XDP_DBRST# AH49 BA47
PCIE_WAKE# LVDSB_DATA1 DDPC_2N
K3
SYS_RESET# WAKE#
B9 PCIE_WAKE# 29 AF47
LVDSB_DATA2 DDPC_2P
BA48 Follow PDG DP disable guide
C607 *1u/10V_4 AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
SYS_PWROK R559 SYS_PWROK_R CLKRUN# DDPC_3P
P12
SYS_PWROK +3V CLKRUN# / GPIO32
N3 CLKRUN# 34
*SHORT_4
INT_CRT_BLU
R282 *0_4 SUS_STAT#
23 INT_CRT_BLU
INT_CRT_GRN
N48
CRT_BLUE DDPD_CTRLCLK
M43
DDPD_HPD_PU
Pin M36 ---> Enable
SBA L22 PWROK +3V_S5 SUS_STAT# / GPIO61 G8 TP129 23 INT_CRT_GRN P49 CRT_GREEN DDPD_CTRLDATA M36
23 INT_CRT_RED
INT_CRT_RED T49 CRT_RED
--->2.2K pull-up 3.3V

do
PWROK_EC R294 R609 NSBA@0_4 EC_PWROK_R L10 +3V_S5 N14 PCH_SUSCLK TP127 AT45

CRT
*SHORT_4 APWROK SUSCLK / GPIO62 DDPD_AUXN
23 INT_CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
C15 Add 0Ω R609 to net EC_PWROK_R. 12/29 M40 BH41
23 INT_CRT_DDCDAT CRT_DDC_DATA DDPD_HPD
15 PM_DRAM_PWRGD PM_DRAM_PWRGD B13 +3V_S5 D10 PCH_SLP_S5# TP128
DRAMPWROK SLP_S5# / GPIO63
BB43
R445 IOP@33_4 INT_CRT_HSYNC_R DDPD_0N
23 INT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
34 PCH_RSMRST# PCH_RSMRST# C21 H4 SUSC# 34 R446 IOP@33_4 INT_CRT_VSYNC_R M49 BF44
RSMRST# SLP_S4# 23 INT_VSYNC CRT_VSYNC DDPD_1N
BE44
DDPD_1P
The required series-resistors are: DDPD_2N
BF42

In
SUS_PWR_ACK K16 +3V_S5 F4 SUSB# 34 ‧Direct Connect - 33 Ω DAC_IREF T43 BE42
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# DAC_IREF DDPD_2P
‧Docking Topology - 20 Ω T42 BJ42
CRT_IRTN DDPD_3N
BG42
SLP_A# R179 DDPD_3P
34 DNBSWON# E20 G10 SLP_A# 34
PWRBTN# SLP_A# IOP@1K/F_4 PANTHER POINT

AC_PRESENT SLP_SUS#
R place close to PCH
H20
ACPRESENT / GPIO31 DSW SLP_SUS#
G16 TP130
R451 IOP@150/F_4INT_CRT_BLU

PM_BATLOW# R452 IOP@150/F_4INT_CRT_GRN

E10 BATLOW# / GPIO72 +3V_S5 AP14

i-
PMSYNCH PM_SYNC 3
R453 IOP@150/F_4INT_CRT_RED
PM_RI# A10 +3V_S5 K14 SLP_LAN#
B RI# SLP_LAN# / GPIO29 B

34,44 EC_PWROK_R EC_PWROK_R

PANTHER POINT
C698
*0.1u/10V_4
is
C35 Reserve 0.1u capacitor C698 to EC_PWROK_R. 01/17
kn

System PWR_OK(CLG) IMVP_PWRGD PU +3V

PCH Pull-high/low(CLG) +3V_S5 +3V_S5
PWROK_EC PD
so AND gate output dont need PD again
Te

+3V
PM_RI# R552 10K_4

CLKRUN# R535 8.2K_4 PM_BATLOW# R286 8.2K_4 C651

*0.1u/10V_4
XDP_DBRST# R543 4.99K/F_4 PCIE_WAKE# R530 10K_4
5

A R533 *1K_4 SLP_LAN# R260 *10K_4 to PCH Pin12, XDP and EE debug U24 A
2 IMVP_PWRGD 3,37
w.

PCH_RSMRST# R221 10K_4 SUS_PWR_ACK R251 10K_4 15 SYS_PWROK SYS_PWROK 4

1 PWROK_EC
PWROK_EC 34
AC_PRESENT R219 10K_4
TC7SH08FU
3

SYS_PWROK R558 *10K_4

R572
PM_DRAM_PWRGD R507 200/F_4 100K_4
Quanta Computer Inc.
wo S3 leakage, remove R
PROJECT : ZQS 45W
ww

Size Document Number Rev

3C
Panther Point 1/6
Date: Wednesday, February 08, 2012 Sheet 7 of 46
5 4 3 2 1
 5 4 3 2 1

PCH2(CLG)
RTC Circuitry(RTC)
20mils
+3VPCU
R568 *SHORT_6

+3V_RTC_1
D20 +3V_RTC

R564 20K_4 RTC_RST# C591 18p/50V_4

CPT/PPT (HDA,JTAG,SATA) 08

2
1
20MIL J1
BAT54C C623 Y3 U21A
1u/6.3V_4 32.768KHZ R502
R573 30mils *SHORT_PAD 10M_4 RTC_X1 A20 C38

2
RTCX1 FWH0 / LAD0 LPC_LAD0 25,34
1K_4 A38

LPC
LPC_LAD1 25,34

3
4
C590 18p/50V_4 RTC_X2 FWH1 / LAD1
C20 RTCX2 FWH2 / LAD2 B37 LPC_LAD2 25,34
20MIL CN12 FWH3 / LAD3 C37 LPC_LAD3 25,34
R566 20K_4 SRTC_RST# RTC_RST#

m
D20 RTCRST#
D 1 FWH4 / LFRAME# D36 LPC_LFRAME# 25,34 D

1
J2 SRTC_RST# G22
2 SRTCRST#
C630 C624 E36 PCH_DRQ#0 TP32

RTC
SM_INTRUDER# LDRQ0#
RTC_CON. 1u/6.3V_4 1u/6.3V_4 +3V_RTC R214 1M_4 K22 INTRUDER# +3V LDRQ1# / GPIO23 K36 PCH_DRQ#1 TP110

co
*SHORT_PAD

2
PCH_INVRMEN
Add MOSFET to separate CODEC SYNC signal C17 INTVRMEN SERIRQ V5
R265 8.2K_4
IRQ_SERIRQ 34
+3V
CN13 battery +5V
AM3 SATA_RXN0_C 26
DFWF02MS118 AHL03003022 SATA0RXN

2
ACZ_BITCLK_R N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0_C 26

SATA 6G
AHL03003024 SATA0TXN AP7 SATA_TXN0 26 SATA HDD
ACZ_SYNC_CODEC 1 3 ACZ_SYNC_R L34 AP5 SATA_TXP0 26
HDA_SYNC SATA0TXP
Q13 SPKR

a.
T10 AM10
HDA Bus(CLG) 27 PCH_AZ_CODEC_BITCLK R485 33_4 ACZ_BITCLK_R CRB 1.0
R184
2N7002K
27 SPKR
ACZ_RST#_R
SPKR SATA1RXN
SATA1RXP AM8
SATA_RXN_SSD
SATA_RXP_SSD
25
25
R185 33_4 ACZ_SYNC_CODEC 1M_4
K34 HDA_RST# SATA1TXN AP11
AP10
SATA_TXN_SSD 25 SSD
27 PCH_AZ_CODEC_SYNC SATA1TXP SATA_TXP_SSD 25

27 PCH_AZ_CODEC_RST# R195 33_4 ACZ_RST#_R 27 PCH_AZ_CODEC_SDIN0 E34 AD7

HDA_SDIN0 SATA2RXN
SATA2RXP AD5 DG recommended that AC coupling capacitors should be
R199 33_4 ACZ_SDOUT_R G34 AH5
27 PCH_AZ_CODEC_SDOUT TP37 HDA_SDIN1 SATA2TXN close to the connector (<100 mils) for optimal signal quality.
SATA2TXP AH4 TP120
C34

si IHDA
HDA_SDIN2
SATA3RXN AB8
A34 AB10
PCH JTAG Debug (CLG) +3V_S5 HDA_SDIN3 SATA3RXP
SATA3TXN AF3
SATA3TXP AF1 TP119
ACZ_SDOUT_R A36

SATA
HDA_SDO
SATA4RXN Y7
SATA4RXP Y5 Second HDD
PCH_GPIO33 C36 +3V AD3
TP112 HDA_DOCK_EN# / GPIO33 SATA4TXN
R295 R283 AD1 TP56
SATA4TXP

ne
210/F_4 210/F_4 PCH_GPIO13 N32 +3V_S5
TP39 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3 SATA_RXN5_C 26
PCH_JTAG_TMS_R Y1 SATA ODD
SATA5RXP SATA_RXP5_C 26
PCH_JTAG_TDI_R AB3 SATA_TXN5 26
C PCH_JTAG_TCK PCH_JTAG_TCK SATA5TXN C
J3 JTAG_TCK SATA5TXP AB1 SATA_TXP5 26
PCH_JTAG_TMS_R H7 Y11

JTAG
JTAG_TMS SATAICOMPO
R531 R269 R270 PCH_JTAG_TDI_R K5 Y10 SATA_COMP R232 37.4/F_4 +1.05V
JTAG_TDI SATAICOMPI

do
51_4 100/F_4 100/F_4
PCH_JTAG_TDO_R H1
TP121 JTAG_TDO
AB12 SATA3_COMP R229 49.9/F_4
SATA3RCOMPO

SATA3COMPI AB13

PCH_SPI_CLK T3 AH1 SATA3_RBIAS R529 750/F_4

PCH Dual SPI (CLG) (Default for WIN8) 34 PCH_SPI_CLK
PCH_SPI_CS0#
SPI_CLK SATA3RBIAS
Y14

In
SPI_CS0# R547 10K_4
W25Q64BVSSIG / AKE3EFP0N00----->8MB +3V
R537 *10K_4 PCH_SPI_CS1# T1

SPI
+3VPCU SPI_CS1#
W25Q32BVSSIG / AKE391P0N00----->4MB P3 SATA_ACT# SATA_ACT# 33
SATALED#
W25Q16BVSSIG / AKE38FP0N01----->2MB 34 PCH_SPI_SI PCH_SPI_SI V4 +3V V14 SATA0GP R277 10K_4 +3V
SPI_MOSI SATA0GP / GPIO21
34 PCH_SPI_SO PCH_SPI_SO U3 +3V P1 BBS_BIT0 SATA0GP/GPIO21
R144 NSBA@0_6 SPI_MISO SATA1GP / GPIO19
+3V_S5 +3V_PCH_ME SATA4GP/GPIO16
PCH Strap Table SATA5GP/GPIO49

i-
+3V_M R625 SBA@0_6 PANTHER POINT
If these pins are unused use 8.2k
+3V_PCH_ME to 10k pull-up to +Vcc3_3 or 8.2k
+3V_M SBA function. to 10k pull-down to ground
U20 Sampled
PCH_SPI_CS0# 1 8
Pin Name Strap description Configuration
PCH_SPI_CLK R626 33_4 6 CE# VDD
PCH_SPI_SI SCK 0 = Default (weak pull-down 20K) SPKR
R627 33_4 5 SPKR No reboot mode setting PWROK +3V R279 *1K_4
PCH_SPI_SO R628 33_4 2 SI
SO HOLD# 7 R149 3.3K_4 1 = Setting to No-Reboot mode

B
C242
*22p/50V_4
3 WP#
ROM-2M
VSS 4
C222
0.1u/10V_4
GNT3# / GPIO55
is
Top-Block Swap Override PWROK
0 = "top-block swap" mode
R458 *1K_4
PCI_GNT3# 9 Used as GPIO only. at chklist 1.2 B
1 = Default (weak pull-up 20K)

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up R500 330K_4 PCH_INVRMEN
+3V_RTC
+3V_PCH_ME R159 3.3K_4

GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK

kn

+3V_PCH_ME GNT1# GNT0# Boot Location

U19 Default weak pull-up on GNT0/1#
PCH_SPI_CS1# 1 1 SPI R456 *1K_4
PCH_SPI_CLK R629
1
33_4 6 CE# VDD 8 * BBS_BIT1 9
[Need external pull-down for LPC BIOS]
PCH_SPI_SI R630 33_4 5 SCK R536 *1K_4 BBS_BIT0
PCH_SPI_SO R631 33_4 2 SI GPIO19 Boot BIOS Selection 0 [bit-0] PWROK 0 0 LPC
SO HOLD# 7 R150 3.3K_4

C243
3 WP# VSS 4
C223
0 = effect (default)(weak pull-down 20K) R481 *SHORT_4 ACZ_SDOUT_R
HDA_SDO Flash Descriptor Security RSMRST ME_WR default EC setting folating
Te

34 ME_WR
*22p/50V_4 SP@ROM-4M 0.1u/10V_4 1 = overridden
0 = Set to Vss (weak pull-down 20K) R256 2.2K_4 +1.8V for future CPU, Sandy Bridge NC
DF_TVS DMI/FDI Termination voltage PWROK R255 1K_4 DF_TVS 10 DF_TVS needs to be pulled up to VccDFTERM power rail
+3V_PCH_ME R156 3.3K_4 1 = Set to Vcc through 2.2 kOhm ±5% - R8361 change to 0 or not??
H_SNB_IVB# 3
+3VPCU
0 = Disable
GPIO28 On-die PLL Voltage Regulator RSMRST# R292 *1K_4 PLL_ODVR_EN 10
R146 *0_4 PCH_SPI_CS0# 1 = Enable (weak pull-up 20K)
w.

R641 0 = Support by 1.8V (weak pull-down)

4.7K_4 HDA_SYNC On-Die PLL VR Voltage Select RSMRST R166 1K_4 ACZ_SYNC_R Needs to be pulled High for Huron River platform.
+3V_S5
1 = Support by 1.5V chklist 1.2
34 SPI_CS0#_UR_ME R147 0_4 PCH_SPI_CS1#
Intel ME Crypto Transport Layer 0 = Disable (Default)
C11 Change R641 from reserve to mount per EC request. 12/27
GPIO15 Security (TLS) cipher suite RSMRST R542 1K_4
1 = Enable +3V_S5 PCH_GPIO15 10
internal PD
ww

A A

DEEP S4/S5 well High = Enable (Default) +3V_RTC R503 330K_4 DSWVREN 7
DSWVREN On Die DSW VR Enable DSW
Low = Disable R504 *330K_4
11,23,25,26,31,33,34,35,36,43,44,46 +3VPCU
11,23,24,26,27,33,36,43,46 +5V
7,9,10,11,15,16,29,31,33,36,37,38,43,44 +3V_S5

Intel Anti-Theft HDD protection

3,5,7,9,11,23,34,37,38,42,43,46 +1.05V NV_ALE PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V R248 *1K_4
NV_ALE 9
Quanta Computer Inc.
,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V Only for Interposer
5,11,43,46 +1.8V PROJECT : ZQS 45W
Size Document Number Rev
3C
Panther Point 2/6
Date: Wednesday, February 08, 2012 Sheet 8 of 46
5 4 3 2 1
 5 4 3 2 1

4,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46
7,8,10,11,15,16,29,31,33,36,37,38,43,44
3,5,7,8,11,23,34,37,38,42,43,46
+3V
+3V_S5
+1.05V

CPT/PPT (PCI,USB,NVRAM)
CPT/PPT (PCI-E,SMBUS,CLK)
U21B
09
PER1- BG34 TP51
TP115 PERN1
U21E PER1+ BJ34 +3V_S5 E12 SMBALERT#
TP114 PERP1 SMBALERT# / GPIO11
AY7 PET1- AV32 C25
RSVD1 TP40 PETN1
AV7 PET1+ AU32 H14 SMB_PCH_CLK
RSVD2 TP36 PETP1 SMBCLK SMB_PCH_CLK 25
BG26 AU3
TP1 RSVD3 SMB_PCH_DAT
BJ26 BG4 BE34 C9
TP2 RSVD4 PERN2 SMBDATA SMB_PCH_DAT 25
BH25 BF34
TP3 PERP2
BJ16 AT10 BB32
TP4 RSVD5 PETN2
BG16 BC8 AY32

SMBUS
TP5 RSVD6 PETP2 DRAMRST_CNTRL_PCH
AH38
TP6 +3V_S5 SML0ALERT# / GPIO60
A12
TP118 DRAMRST_CNTRL_PCH 13,14,15
AH37 AU2 BG36

m
D TP7 RSVD7 29 PCIE_RX3- PERN3 D
AK43 AT4 BJ36 C8 SMB_ME0_CLK
TP8 RSVD8 29 PCIE_RX3+ PERP3 SML0CLK
C565 0.1u/10V_4 PCIE_TXN3_C
AK45
C18
TP9 RSVD9
AT3
AT1
LAN 29 PCIE_TX3-
C567 0.1u/10V_4 PCIE_TXP3_C
AV34
AU34
PETN3
G12 SMB_ME0_DAT For LAN
TP10 RSVD10 29 PCIE_TX3+ PETP3 SML0DATA
N30 AY3
TP11 RSVD11
H3 AT5 BF36
TP12 RSVD12 PERN4

co
AH12 AV3 BE36
TP13 RSVD13 PERP4 SML1ALERT#_R R512 *0_4
AM4
TP14 RSVD14
AV1 AY34
PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74
C13 SML1ALERT# 10,33
AM5 BB1 PET4+ BB34
TP15 RSVD15 TP34 PETP4
Y13 BA3 +3V_S5 E14 SMB_ME1_CLK

PCI-E*
TP16 RSVD16 SML1CLK / GPIO58
K24
L24
TP17 RSVD17
BB5
BB3
BG37
BH37
PERN5
+3V_S5 M16 SMB_ME1_DAT For EC
TP18 RSVD18 PERP5 SML1DATA / GPIO75
AB46 BB7 AY36
TP19 RSVD19 PET5+ PETN5
AB45 BE8 BB36

RSVD
TP20 RSVD20 TP38 PETP5
BD4
RSVD21 PER6-
BF6 TP111 BJ38
RSVD22 PER6+ PERN6
TP113 BG38

Controller
PERP6

a.
B21 AV5 NV_ALE 8 PET6- AU36 M7 CL_CLK1
TP21 RSVD23 TP33 PETN6 CL_CLK1 TP57
M20 AV10 PET6+ AV36
TP22 RSVD24 TP35 PETP6
AY16

Link
TX AC cap place at connector side, AC cap to TP23 CL_DATA1
BG46 AT8 BG40 T11 TP58
TP24 RSVD25 PERN7 CL_DATA1
connector < 400mils BJ40
PERP7
AY5 AY40
RSVD26 PET7+ PETN7 CL_RST1#
BA2 TP31 BB40 P10 TP52
TP44 USB30_RX1- RSVD27 PETP7 CL_RST1#
BE28 USB30_RX1N
TP41 USB30_RX2- TP25
BC30 AT12 BE38
USB3.0 31 USB30_RX3-
USB30_RX3- BE32
TP26 USB30_RX2N
USB30_RX3N
RSVD28
BF3
25 PCIE_RX8-
25 PCIE_RX8+ BC38
PERN8
TP117 USB30_RX4- TP27 RSVD29 C256 0.1u/10V_4 PCIE_TXN8_C PERP8
BJ32
TP28 USB30_RX4N Wireless 25 PCIE_TX8- AW38
PETN8

si
TP50 USB30_RX1+ BC28 USB30_RX1P Port1 and port9 can be used on debug mode C261 0.1u/10V_4 PCIE_TXP8_C AY38
TP29 25 PCIE_TX8+ PETP8
TP42 USB30_RX2+ BE30 USB30_RX2P
USB30_RX3+ TP30 CLK_PEGA_REQ#
31 USB30_RX3+ BF32
TP31 USB30_RX3P +3V_S5 PEG_A_CLKRQ# / GPIO47
M10 CLK_PEGA_REQ# 16
TP116 USB30_RX4+ BG32 C24 USBP0- TP131 TP132 Y40
TP32 USB30_RX4P USBP0N CLKOUT_PCIE0N
TP48 USB30_TX1- AV26 USB30_TX1N A24 USBP0+ TP133 Reserve for USB I/O function TP134 Y39
TP46 USB30_TX2- TP33 USBP0P CLKOUT_PCIE0P
BB26 USB30_TX2N C25 USBP1- 31 XHCI for USBP0-3 AB37 CLK_PCIE_VGA# 16

CLOCKS
USB30_TX3- TP34 USBP1N PCIE_CLK_USB30_REQ# CLKOUT_PEG_A_N
31 USB30_TX3- AU28
TP35 USB30_TX3N USBP1P
B25 USBP1+ 31 USB/B-USB1-1/USB debug J2
PCIECLKRQ0# / GPIO73 +3V_S5 CLKOUT_PEG_A_P
AB38 CLK_PCIE_VGA 16
TP43 USB30_TX4- AY30 C26
TP36 USB30_TX4N USBP2N USBP2- 31
TP49 USB30_TX1+ AU26 A26 MB USB
TP37 USB30_TX1P USBP2P USBP2+ 31
TP47 USB30_TX2+ AY26 K28 USBP3- TP135 AB49 AV22 CLK_CPU_BCLKN 3
TP38 USB30_TX2P USBP3N USBP3- 25 CLKOUT_PCIE1N CLKOUT_DMI_N
USB30_TX3+ AV28 H28 USBP3+ Mini-SSD TP136 AB47 AU22 CLK_CPU_BCLKP 3
31 USB30_TX3+ TP39 USB30_TX3P USBP3P USBP3+ 25 CLKOUT_PCIE1P CLKOUT_DMI_P

ne
TP45 USB30_TX4+ AW30 E28 EHCI1
TP40 USB30_TX4P USBP4N USBP4- 31
C D28 BLUETOOTH PCIE_CLKREQ1# M1 +3V C
USBP4P USBP4+ 31 PCIECLKRQ1# / GPIO18
C28 USBP5- TP137 AM12 CLK_DPLL_SSCLKN 3
USBP5N USBP5+ TP138 CLKOUT_DP_N
USBP5P
A28 Reserve for SIM card CLKOUT_DP_P
AM13 CLK_DPLL_SSCLKP 3
C29 TP139 AA48
USBP6N USB port6/7 may not be available on all PCH sku TP140 CLKOUT_PCIE2N
B29 AA47
PCI_PIRQA# USBP6P (HM55 support 12port only) CLKOUT_PCIE2P CLK_BUF_PCIE_3GPLLN
K40 N28 BF18
PCI_PIRQB# PIRQA# USBP7N PCIE_CLK_REQ2# CLKIN_DMI_N CLK_BUF_PCIE_3GPLLP
K38 M28 V10 +3V BE18
PCI

PCI_PIRQC# PIRQB# USBP7P PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

H38 L30 USBP8- 23
PCI_PIRQD# PIRQC# USBP8N
G38
PIRQD# USBP8P
K30 USBP8+ 23 Camera
G30 TP141 Y37 BJ30 CLK_BUF_BCLKN
USBP9N USBP9- 31 CLKOUT_PCIE3N CLKIN_GND1_N
dGPU_EDIDSEL# TP142 CLK_BUF_BCLKP

do
REQ1# / GPIO50 +3V USB/B-USB1-2
C46 E30 Y36 BG30
USB

USBP9P USBP9+ 31 CLKOUT_PCIE3P CLKIN_GND1_P

dGPU_SELECT#
REQ2# / GPIO52 +3V
C44 C30 USBP10- 25
REQ#3 USBP10N PCIE_CLKREQ3#
REQ3# / GPIO54 +3V MINI-CARD WLAN(MPC) +3V_S5
E40 A30 USBP10+ 25 A8
USBP10P USBP11- T25 PCIECLKRQ3# / GPIO25 CLK_BUF_DREFCLKN
USBP11N
L32 EHCI2 CLKIN_DOT_96N
G24
USBP11+ T26 CLK_BUF_DREFCLKP
GNT1# / GPIO51 +3V Reserve for card reader
8 BBS_BIT1 D47 K32 E24
USBP11P USBP12- TP145 TP146 CLKIN_DOT_96P
GNT2# / GPIO53 +3V
10 BOARD_ID2 E42 G32 Y43
USBP12N USBP12+ TP147 TP148 CLKOUT_PCIE4N
GNT3# / GPIO55 +3V Reserve for Touch pad
8 PCI_GNT3# F46 E32 Y45
USBP12P USBP13- TP149 CLKOUT_PCIE4P CLK_BUF_DREFSSCLKN
C32 AK7
USBP13N USBP13+ TP150 PCIE_CLKREQ4# CLKIN_SATA_N CLK_BUF_DREFSSCLKP
USBP13P
A32 Reserve for FP L12
PCIECLKRQ4# / GPIO26 +3V_S5 CLKIN_SATA_P
AK5
G_SENSOR_INT#_PCH
PIRQE# / GPIO2 +3V
26 G_SENSOR_INT#_PCH G42
dGPU_PWR_EN
PIRQF# / GPIO3 +3V
42 dGPU_PWR_EN G40
DGPU_HOLD_RST# USB_BIAS R482 22.6/F_4 R162 *SHORT_4 CLK_PCH_14M

In
PIRQG# / GPIO4 +3V
16 DGPU_HOLD_RST# C42 C33 25 CLK_PCH_SRC5# V45 K45
EXTTS_SNI_DRV1_PCH D44 USBRBIAS# R157 *SHORT_4 CLKOUT_PCIE5N REFCLK14IN
PIRQH# / GPIO5 +3V 25 CLK_PCH_SRC5 V46
CLKOUT_PCIE5P
B33
Wireless PCIE_CLKREQ5# L14 +3V_S5 H45 CLK_PCI_FB C553 27p/50V_4
USBRBIAS 25 PCIE_CLKREQ5# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
TP54 PCI_PME# K10

2
PME#
3 PCI_PLTRST# PCI_PLTRST# C6 +3V_S5 A14 USB_OC0# R175 *SHORT_4 CLK_PCIE_LOM#_R AB42 V47 XTAL25_IN Y2
PLTRST# OC0# / GPIO59 29 CLK_PCIE_LOM# CLKOUT_PEG_B_N XTAL25_IN
+3V_S5 K20 USB_OC1# USB_OC1# 31 R167 *SHORT_4 CLK_PCIE_LOM_R AB40 V49 XTAL25_OUT R454 25MHz
OC1# / GPIO40 29 CLK_PCIE_LOM CLKOUT_PEG_B_P XTAL25_OUT
+3V_S5 USB_OC2# 1M_4
B17 LAN

1
OC2# / GPIO41 USB_OC3# CLK_PCIE_LAN_REQ#
H49
CLKOUT_PCI0 +3V_S5 OC3# / GPIO42
C16 29 CLK_PCIE_LAN_REQ# E6
PEG_B_CLKRQ# / GPIO56+3V_S5
TP30 H43 +3V_S5 L16 USB_OC4# USB_OC4# 31 C552 27p/50V_4
CLK_PCI_FB R447 22_4 CLK_PCI_FB_C CLKOUT_PCI1 OC4# / GPIO43 USB_OC5# XCLK_RCOMP R450 90.9/F_4
+3V_S5

i-
J48 A16 Y47 +1.05V
R178 22_4 CLK_LPC_DEBUG_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# XCLK_RCOMP
25 CLK_LPC_DEBUG K42
CLKOUT_PCI3 +3V_S5 OC6# / GPIO10
D14 V40
CLKOUT_PCIE6N
R177 22_4 CLK_PCI_775_C H40 +3V_S5 C14 USB_OC7# TP151 CLK_PCH_SRC6P V42
34 CLK_PCI_775 CLKOUT_PCI4 OC7# / GPIO14 CLKOUT_PCIE6P
CLK_PCIE_REQ6# T13 +3V_S5
PANTHER POINT PCIECLKRQ6# / GPIO45
V38 +3V K43 SKU_ID1

FLEX CLOCKS
TP152 CLK_PCH_SRC7P CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
V37
B CLKOUT_PCIE7P B
+3V CLKOUTFLEX1 / GPIO65
F47 Zero_ODD_ID 10
CLK_PCIE_REQ7# K12 +3V_S5
PCIECLKRQ7# / GPIO46
+3V CLKOUTFLEX2 / GPIO66
H47 BOARD_ID4 10,33
TP154 CLK_ITPN AK14
is For XDP TP155 CLK_ITPP AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P +3V CLKOUTFLEX3 / GPIO67
K49 48M_CLK_CR TP156

PANTHER POINT

+3V
PLTRST#(CLG) PCI/USBOC# Pull-up(CLG) CLK_REQ/Strap Pin(CLG) SMBus(EC) SMBus(PCH)
PCI_PIRQA# R171 8.2K_4 +3V_S5
kn

C30 Change U22 PLTRST# power source from +3V_S5 to +3V. 01/17 +3V_S5 PCI_PIRQB# R192 8.2K_4 +3V_S5 +3V
R505 PCI_PIRQC# R165 8.2K_4 R556 10K_4 PCIE_CLK_USB30_REQ#
+3V 10 1 USB_OC6# PCI_PIRQD# R172 8.2K_4
USB_OC4# 9 2 USB_OC0#
USB_OC1# 8 3 USB_OC7#
USB_OC2# 7 4 USB_OC5# R528 10K_4 PCIE_CLKREQ3# R244 R580
USB_OC3# 6 5 +3V 2.2K_4 S5 4.7K_4 S0

2
C622 G_SENSOR_INT#_PCH R541 10K_4 R262 10K_4 PCIE_CLKREQ4#
0.1u/10V_4 10K_10P8R R259 10K_4 PCIE_CLKREQ5#
R284 10K_4 CLK_PCIE_LAN_REQ# 34 2ND_MBCLK 3 1 SMB_ME1_CLK SMB_PCH_DAT 3 1
5

+3V R258 10K_4 CLK_PCIE_REQ6# CLK_SDATA 13,14,26,33

Te

PCI_PLTRST# 2 R467 R273 10K_4 CLK_PCIE_REQ7# Q15 Q16

4 PLTRST# 16,25,29,34 10 1 DGPU_HOLD_RST# 2N7002K 2N7002K
1 9 2 EXTTS_SNI_DRV1_PCH +3V
8 3 dGPU_EDIDSEL# +3V_S5 +3V
U22 REQ#3 7 4 dGPU_SELECT# R534 10K_4 PCIE_CLKREQ1#
3

TC7SH08FU R551 dGPU_PWR_EN 6 5 R249 10K_4 PCIE_CLK_REQ2#

100K_4
10K_10P8R +3V_S5
*10K_4 R240 R579
dGPU_PW_CTRL# SKU_ID1 SKU_ID0 VGA H/W Setup R275 CLK_PEGA_REQ# 2.2K_4 4.7K_4

2
+3V (GPIO68) (GPIO64) (GPIO16) Signal Menu Pill-up in N13P side
w.

CTL : dGPU_VRON
R479 *1K_4 dGPU_PW_CTRL# 10 34 2ND_MBDATA 3 1 SMB_ME1_DAT SMB_PCH_CLK 3 1
A R480 EOP@100K_4 CLK_SCLK 13,14,26,33 A
UMA Only 1 0 0 UMA Hidden UMA boot Q14 Q17
2N7002K 2N7002K
CLK_PEGA_REQ# R632 *10K_4
+3V dGPU Only 0 0 1 GPU Hidden GPU boot
CLK_BUF_BCLKN R490 10K_4
R155 SP_OPT@10K_4 SKU_ID1 Switchable CLK_BUF_BCLKP R488 10K_4
R161 (Mux) UMA+GPU dGPU/SG UMA boot +3V_S5
SP_DIS_UMA@10K_4
ww

Optimize CLK_BUF_PCIE_3GPLLN R225 10K_4

(Muxless) 0 1 1 UMA UMA/SG UMA boot CLK_BUF_PCIE_3GPLLP R227 10K_4 R513 1K_4 DRAMRST_CNTRL_PCH
+3V CLK_BUF_DREFCLKN R206 10K_4

R560 10K_4 dGPU_PW_CTRL#

CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
R210
R238
10K_4
10K_4
R274
R298
10K_4
2.2K_4
SMBALERT#
SMB_PCH_CLK
Quanta Computer Inc.
SKU_ID0 10
R548 *10K_4 1 = GPU power is control by H/W (pure Discrete SKU) CLK_BUF_DREFSSCLKP R242 10K_4 R297 2.2K_4 SMB_PCH_DAT
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) CLK_PCH_14M R154 10K_4 R539 2.2K_4 SMB_ME0_CLK PROJECT : ZQS 45W
--->(Default) R250 2.2K_4 SMB_ME0_DAT Size Document Number Rev
CLOCK TERMINATION for FCIM R508 10K_4 SML1ALERT#_R 3C
Panther Point 3/6
Date: Wednesday, February 08, 2012 Sheet 9 of 46
5 4 3 2 1
 5 4 3 2 1

23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46
7,8,9,11,15,16,29,31,33,36,37,38,43,44
+3V
+3V_S5 CPT/PPT (GPIO,VSS_NCTF,RSVD)
U21F
10
S_GPIO R266 100_4 T7 +3V +3V C40 dGPU_PW _CTRL# 9
BMBUSY# / GPIO0 TACH4 / GPIO68
SIO_EXT_SMI# A42 +3V +3V B41
34 SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69 CABLE_ID 23 GPIO Pull-up/Pull-down(CLG)

m
USB_Charger_ID H36 +3V +3V C41 BOARD_ID3
D TACH2 / GPIO6 TACH6 / GPIO70 D

34 SIO_EXT_SCI# SIO_EXT_SCI# E38 +3V +3V A40 R475 10K_4 +3V +3V_S5
TACH3 / GPIO7 TACH7 / GPIO71

co
C10 +3V_S5 PCH_GPIO24 R271 *10K_4
GPIO8
C4 +3V_S5 PLL_ODVR_EN R293 10K_4
LAN_PHY_PWR_CTRL / GPIO12
SIO_A20GATE
8 PCH_GPIO15 G2 GPIO15 +3V_S5 A20GATE P4 SIO_A20GATE 34 +3V
AU16 PCH_PECI TP53
PECI SIO_EXT_SMI# R472 10K_4
U2 SATA4GP / GPIO16 +3V

a.
9 SKU_ID0
P5 SIO_RCIN# SIO_RCIN# 34 SIO_EXT_SCI# R173 10K_4
RCIN#

GPIO
20 DGPU_PW ROK D40 +3V AY11 H_PW RGOOD 3 STP_PCI# R532 *10K_4

CPU/MISC
TACH0 / GPIO17 PROCPWRGD SIO_A20GATE R287 10K_4
G_Sensor_ID# T5 +3V AY10 PCH_THRMTRIP# R243 390_4 PM_THRMTRIP# 3 SIO_RCIN# R280 10K_4
SCLOCK / GPIO22 THRMTRIP# CRIT_TEMP_REP# R549 10K_4
PCH_GPIO24 E8 GPIO24 / MEM_LED +3V_S5 INIT3_3V# T14

si
C28 Change PCH_GPIO27 to WK_GPIO27. 01/12 C14 Change R234 from mount to reserve. 12/27
34 W K_GPIO27 W K_GPIO27 E16 DSW AY1 DF_TVS 8
GPIO27 DF_TVS

8 PLL_ODVR_EN PLL_ODVR_EN P8 +3V_S5 W K_GPIO27 R234 *10K_4

GPIO28
TS_VSS1 AH8
STP_PCI# K1 +3V
STP_PCI# / GPIO34
TS_VSS2 AK11 GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.
K4 GPIO35 +3V

ne
41,42 dGPU_VRON
TS_VSS3 AH10
C DMI_OVRVLTG V8 +3V C
SATA2GP / GPIO36
TS_VSS4 AK10
FDI_OVRVLTG M5 +3V
SATA3GP / GPIO37
MFG_MODE N2 +3V P37
SLOAD / GPIO38 NC_1

do
BOARD_ID0 M3 +3V
SDATAOUT0 / GPIO39
TEST_SET_UP V13 +3V BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15

9,33 SML1ALERT# R561 *SHORT_4 CRIT_TEMP_REP# V3 +3V BG48

SATA5GP / GPIO49 VSS_NCTF_16
TP55 SV_DET_NC D6 GPIO57 +3V_S5 VSS_NCTF_17 BH3

In
VSS_NCTF_18 BH47
USB_Charger_ID Zero ODD ID
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 USB Charger------->High Zero ODD------->High

A45 BJ45 +3V None Charger------->Low None Zero ODD------->Low
VSS_NCTF_3 VSS_NCTF_21 +3V

i-
NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46
R160 CH@10K_4 R501 ZP@10K_4
Zero_ODD_ID 9
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
R174 NCH@10K_4 USB_Charger_ID R623 NZP@10K_4
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6
B B
B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47
is C48
VSS_NCTF_8 VSS_NCTF_26
BD1 D1 SV_SET_UP Reserve for future +3V
VSS_NCTF_9 VSS_NCTF_27
BD49 D49 R544 *10K_4 BOARD_ID0 R557 *10K_4
VSS_NCTF_10 VSS_NCTF_28 High = Strong (Default)
BE1 E1 +3V
kn

VSS_NCTF_11 VSS_NCTF_29 R477 *10K_4 BOARD_ID3 R476 10K_4

BE49 E49 TEST_SET_UP R289 10K_4 R448 *10K_4 R440 10K_4
VSS_NCTF_12 VSS_NCTF_30 R276 *1K_4
BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BOARD_ID4 9,33
BOARD_ID3
BOARD_ID3 33
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
Te

SGPIO BOARD_ID2
PANTHER POINT

8 Layer ------->High *
SATA2GP : strap for reserved at chklist 1.2 +3V 6 Layer ------->Low
Change BIO_REC to G_Sensor_ID# 10/21 +3V
SATA3GP : strap for reserved at chklist 1.2 Change MB ID for G-sensor S_GPIO R291 1K_4
w.

NOTE: The internal pull-down is disabled after PLTRST# deasserts. PCH GPIO22 R278 *1K_4 R163 10K_4
BOARD_ID2 9
NOTE: This signal should not be pulled high when strap is sampled. Pull high=no G-Sensor R170 *SP_6L@10K_4
A Pull low=have G-Sensor A

+3V +3V +3V

ww

R268 100K_4 FDI_OVRVLTG R281 *1K_4 DMI_OVRVLTG R267 *200K/F_4 G_Sensor_ID# R290 NGS@10K_4
R264 GS@1K_4
MFG-TEST Quanta Computer Inc.
+3V
Low = Tx, Rx terminated to
FDI TERMINATION LOW - Tx, Rx terminated DMI TERMINATION same voltage (DC Coupling Mode) High = Disable (Default) MFG_MODE R545 10K_4 PROJECT : ZQS 45W
VOLTAGE OVERRIDE to same voltage VOLTAGE OVERRIDE (DEFAULT) G Sensor ID R546 *1K_4 Size Document Number Rev
Low = Enable Panther Point 4/6 3C

Date: W ednesday, February 08, 2012 Sheet 10 of 46

5 4 3 2 1
 5 4 3 2 1

PCH5(CLG)
CPT/PPT (POWER)
+VCCA_DAC_1_2 +3V
11
VccADAC =1mA(8mils)
U21G POWER L16
BKP1608HS181-T/180ohm/1.5A_6
CPT/PPT (POWER)
+1.05V +1.05V_PCH_VCC R449 *0_8 +1.05V_VCCUSBCORE +1.05V
+1.05V
VccCORE =1.3 A(60mils) C231 C248 C247 C236
R261 0.002/F_1206 AA23
VCCCORE[1] VCCADAC
U48 22u/6.3V_8 0.01u/25V_4 0.1u/10V_4 10u/6.3V_6
C20 Change R230 from shortpad to 0Ω, add 0Ω R636 connect to +3VPCU. 01/05
U21J POWER R211 *SHORT_8
AC23 VCCCORE[2]

CRT
AD21 +VCCACLK AD49 N26
C279 C280 C273 C269 VCCCORE[3] +VCCALVDS +3V R636 *0_4 VCCACLK VCCIO[29] C274
AD23 VCCCORE[4] VSSADAC U47 +3VPCU

VCC CORE
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 AF21 VccALVDS=1mA(8mils) VCCDSW3_3= 3mA P26 1u/6.3V_4 VCCSUS3_3 = 119mA(15mils)
VCCCORE[5] R203 IOP@0_4 R230 0_4 +VCCPDSW VCCIO[30]
AF23 VCCCORE[6] +3V_S5 T16 VCCDSW3_3
AG21 P28 +3V_S5
D R5285 near PCH ball for VCCP GND sense VCCCORE[7] R201 EV@0_4 VCCIO[31] D
AG23
VCCCORE[8]

m
AG24 AK36 C305 PCH_VCCDSW V12 T27 R228 *SHORT_6
+1.05V +1.05V_PCH_VCCDPLL_EXP VCCCORE[9] VCCALVDS 0.1u/10V_4 DCPSUSBYP VCCIO[32]
AG26
VCCCORE[10]
When Dis sku, LVDS power can short to GND
AG27 VCCCORE[11] VSSALVDS AK37 VCCIO[33] T29
R215 *SHORT_6 AG29 +VCC_TX_LVDS +1.8V C325 +3V_SUS_CLKF33 T38 C308
VCCCORE[12] +1.05V +VCCAPLL_CPY_PCH *0.1u/10V_4 VCC3_3[5] 0.1u/10V_4
AJ23 VccTX_LVDS=60mA(10mils)

LVDS
VCCCORE[13] L34 +3V_VCCPUSB
AJ26 AM37 T23

co
+1.05V +1.05V_VCCAPLL_EXP VCCCORE[14] VCCTX_LVDS[1] [email protected]/250mA_8 L38 *10uH/100mA_8 VCCSUS3_3[7]
AJ27 BH23
VCCCORE[15] VCCAPLLDMI2
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 VCCSUS3_3[8] T24
L37 *1uH/25mA_6 AJ31 C265 C264 C549 R439 EV@0_4 +1.05V R441 *SHORT_6 +VCCDPLL_CPY AL29 R216 *SHORT_6
VCCCORE[17] [email protected]/[email protected]/25V_4IOP@22u/6.3V_8 C589 VCCIO[14]
AP36 V23

USB
VCCTX_LVDS[3] *10u/6.3V_6 VCCSUS3_3[9]
C588 AP37 +VCCSUS1 AL24 V24 C281
*10u/6.3V_6 VCCTX_LVDS[4] DCPSUS[3] VCCSUS3_3[10] 0.1u/10V_4
AN19 VCCIO[28]
P24 +3V_VCCAUBG
C278 VCCSUS3_3[6]
VCCME(+1.05V) = ??A(??mils)
BJ22 +3V_VCC_GIO +3V *1u/6.3V_4 AA19
+1.05V +1.05V_VCCIO VCCAPLLEXP VCCASW[1] +VCCAUPLL R223 *SHORT_6
VCCIO[34] T26 +1.05V
R200 *SHORT_6 +1.05V +1.05V_VCCEPW VCC5REFSUS=1mA
VccIO =2.925 A(140mils) V33 AA21

a.
HVCMOS
R516 0.002/F_1206 VCC3_3[6] VCCASW[2]
AN16
VCCIO[15] VccASW =1.01 A(60mils)
VCCDMI = 42mA(10mils) R550 [email protected]/F_1206 AA24 M26 +5V_PCH_VCC5REFSUS R233 10/F_4 +5V_S5
C268 +1.05V VCCASW[3] V5REF_SUS
AN17 VCCIO[16]

Clock and Miscellaneous

C313 C299 C303 V34 0.1u/10V_4 +1.1V_VCC_DMI +1.05V_M AA26 D3 RB500V-40
VCC3_3[7] VCCASW[4] +3V_S5
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C271 C275 C270 AN23 +VCCA_USBSUS C272
R224 *SHORT_4 R633 *SBA@0_8 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 DCPSUS[4] 0.1u/10V_4
AN21 AA27
VCCIO[17] VCCASW[5] +3V_VCCPSUS
+1.05V_M for SBA function. VCCSUS3_3[1] AN24
AN26 AA29 C294
VCCIO[18] VCCASW[6] *1u/6.3V_4
AN27 AT16 +VCCAFDI_VRM +VCCAFDI_VRM C304 AA31 V5REF= 1mA
VCCIO[19] VCCVRM[3] VCCASW[7]
1u/6.3V_4
C298 C309 +5V_PCH_VCC5REF R141 10/F_4

si
AP21 VCCIO[20] AC26 VCCASW[8] V5REF P34 +5V
1u/6.3V_4 10u/6.3V_6 C626 C282
AP23 AT20 VCCCLKDMI = 20mA(8mils) 22u/6.3V_8 22u/6.3V_8 AC27 D2 RB500V-40 +3V
VCCIO[21] VCCDMI[1] VCCASW[9] C266
N20

DMI

PCI/GPIO/LPC
+1.1V_VCC_DMI_CCI +VCC_DMI_CCI +1.05V VCCSUS3_3[2] 1u/6.3V_4
AP24 AC29

VCCIO
VCCIO[22] VCCASW[10]
VCCSUS3_3[3] N22
AP26 AB36 L33 R435 *1/F_4 AC31
VCCIO[23] VCCCLKDMI *10uH/100mA_8 VCCASW[11] +3V_VCCPSUS R235 *SHORT_6
P20 +3V_S5
R434 0_4 VCCSUS3_3[4]
AT24 AD29
+3V +3V_VCC_EXP VCCIO[24] C246 C545 VCCASW[12]
C
VCCSUS3_3[5] P22 VCCSUS3_3 = 119mA(15mils) C
1u/6.3V_4 *10u/6.3V_6 AD31 C297
R493 *SHORT_8 VCCASW[13] 1u/10V_4
AN33
VCCIO[25]

ne
W21 AA16
VCCASW[14] VCC3_3[1]
AN34 AG16
C579 VCCIO[26] VCCDFTERM[1] +VCCP_NAND +1.8V +3V_VCCPCORE R285 *SHORT_6
VCCPNAND = 190 mA(15mils) W23 VCCASW[15] VCC3_3[8] W16 +3V
0.1u/10V_4
BH29 AG17 R253 *SHORT_8 W24 T34 VCCPCORE = 28mA(10mils)

DFT / SPI
VCC3_3[3] VCCDFTERM[2] VCCASW[16] VCC3_3[4] +3V
C341
W26 0.1u/10V_4
C329 VCCASW[17] C239
VCCDFTERM[3] AJ16
0.1u/10V_4 W29 0.1u/10V_4
+VCCAFDI_VRM VCCASW[18]
+VCCAFDI_VRM AP16
VCCVRM[2] +1.05V
AJ17 W31 AJ2 +3V
VCCDFTERM[4] VCCASW[19] VCC3_3[2]

do
+1.05V R236 *0_8 +1.05V_VCCAPLL_FDI BG6 VCCSPI = 20mA(8mils) R563 *SHORT_6 W33
VccAFDIPLL VCCASW[20] C330
AF13
+3V_VCCME_SPI +3V_S5 VCCIO[5] 0.1u/10V_4
R231 *SHORT_8 +1.05V_VCCDPLL_FDI AP17 Reserve +3V_S5 to VCCSPI for EC 795 C628 C312 0.1u/10V_4 +VCCRTCEXT N16
VCCIO[27] DCPRTC
FDI

V1 R296 NSBA@0_6 1u/6.3V_4 AH13 +V1.05S_SATA3 R254 *SHORT_8 +1.05V

VCCSPI VCCIO[12]

+1.1V_VCC_DMI AU20 +VCCAFDI_VRM +VCCAFDI_VRM Y49 AH14

VCCDMI[2] +3V_M R164 *SHORT_6 VCCVRM[4] VCCIO[13] C323
R642 *SBA@0_6 1u/10V_4
PANTHER POINT AF14
C259 +1.05V_VCCA_A_DPL VCCIO[6]
+3V_M for SBA function. 65mA(10mils) BD47 ??mA(??mils)

SATA
1u/6.3V_4 VCCADPLLA +V1.1LAN_VCCAPLL L39
AK1 +1.05V

In
+1.05V_VCCA_B_DPL VCCAPLLSATA *10uH/100mA_8
8mA(8mils) BF47
VCCADPLLB
VCCVRM= 114mA(15mils)
C606
C342 R436 *SHORT_6 AF11 +VCCAFDI_VRM *10u/6.3V_6
1u/6.3V_4 +VCCDIFFCLK VCCVRM[1]
AF17
+VCCDIFFCLKN VCCIO[7]
AF33
C542 VCCDIFFCLKN[1] R222 *SHORT_6
VCCDIFFCLKN= 55mA(10mils) AF34
VCCDIFFCLKN[2] VCCIO[2]
AC16 +1.05V
1u/6.3V_4 AG34
+1.05V_M +1.05V VCCDIFFCLKN[3]
AC17
VCCIO[3] C310
VCCSSC= 95mA(10mils)
R217 *NSBA@0_6 +V1.05V_SSCVCC AG33 AD17 1u/6.3V_4 +1.05V_VCCEPW
+VCCAFDI_VRM VCCSSC VCCIO[4]

i-
R634 C296 C311 0.1u/10V_4 +VCCSST V16 VCCME = 1.01A(60mils)
B
*SBA@0_6 *1u/6.3V_4 DCPSST B
VCCVRM: 1.8V (Destop)
+1.5V R272 0_6 1.5V (Mobile) +1.05V_M for SBA function.
+1.05V T17 T21
R263 *0_6 +V1.05M_VCCSUS DCPSUS[1] VCCASW[22]
+1.05V V19

MISC
DCPSUS[2]
1mA(8mils)
R510 *SHORT_4 +VTT_VCCPCPU V21
VCCASW[23]

CPU
BJ8
C597 C600 V_PROC_IO
VCCASW[21] T19
C598 0.1u/10V_4 0.1u/10V_4
4.7u/6.3V_6 R463 *0_4
is VCCRTC<1mA(8mils) +1.5VSUS

RTC
A22 P32 +V3.3A_1.5A_HDA_IO R462 0_4 VCCSUSHDA= 10mA(8mils)

HDA
+3V_RTC VCCRTC VCCSUSHDA +3V_S5

C300 C314 C315 PANTHER POINT C559 C560

1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 *1u/6.3V_4 0.1u/10V_4

7,8,9,10,15,16,29,31,33,36,37,38,43,44 +3V_S5
27,31,36,37,38,39,40,41,45,46 +5V_S5

13,14,15,39,42,46 +1.5VSUS
kn

8,23,24,26,27,33,36,43,46 +5V
14,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
25,39,43 +1.5V +1.05V L36 10uH/100mA_8 +1.05V_VCCA_A_DPL
3,5,7,8,9,23,34,37,38,42,43,46 +1.05V

1
5,8,43,46 +1.8V
C564 C566
8 +3V_RTC 1u/6.3V_4
100U/6.3V_3528

2
+3V

L35 10uH/100mA_8 +1.05V_VCCA_B_DPL

Te

R151 1/F_4 L15 10uH/100mA_8 +3V_SUS_CLKF33

1
C562 C554
C241 C244 1u/6.3V_4
10u/6.3V_6 1u/10V_4 100U/6.3V_3528

2
A A

C38 Change C562, C564 from 220U to 100U for cost down. 02/08
w.

Quanta Computer Inc.

PROJECT :ZQS 45W
Size Document Number Rev
3C
Panther Point 5/6
ww

Date: Wednesday, February 08, 2012 Sheet 11 of 46

5 4 3 2 1
 5 4 3 2 1

PCH6(CLG)
12
U21I

AY4 H46
IBEX PEAK-M (GND) AY42
VSS[159]
VSS[160]
VSS[259]
VSS[260] K18

m
AY46 VSS[161] VSS[261] K26
D AY8 VSS[162] VSS[262] K39 D
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7

co
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
U21H F45 M12
VSS[172] VSS[272]
H5 BB12 P16

a.
VSS[0] VSS[173] VSS[273]
BB16 VSS[174] VSS[274] M18
AA17 VSS[1] VSS[80] AK38 BB20 VSS[175] VSS[275] M22
AA2 VSS[2] VSS[81] AK4 BB22 VSS[176] VSS[276] M24
AA3 VSS[3] VSS[82] AK42 BB24 VSS[177] VSS[277] M30
AA33 VSS[4] VSS[83] AK46 BB28 VSS[178] VSS[278] M32
AA34 VSS[5] VSS[84] AK8 BB30 VSS[179] VSS[279] M34
AB11 VSS[6] VSS[85] AL16 BB38 VSS[180] VSS[280] M38
AB14 AL17 BB4 M4

si
VSS[7] VSS[86] VSS[181] VSS[281]
AB39 VSS[8] VSS[87] AL19 BB46 VSS[182] VSS[282] M42
AB4 VSS[9] VSS[88] AL2 BC14 VSS[183] VSS[283] M46
AB43 VSS[10] VSS[89] AL21 BC18 VSS[184] VSS[284] M8
AB5 VSS[11] VSS[90] AL23 BC2 VSS[185] VSS[285] N18
AB7 VSS[12] VSS[91] AL26 BC22 VSS[186] VSS[286] P30
AC19 VSS[13] VSS[92] AL27 BC26 VSS[187] VSS[287] N47
AC2 VSS[14] VSS[93] AL31 BC32 VSS[188] VSS[288] P11
AC21 AL33 BC34 P18

ne
VSS[15] VSS[94] VSS[189] VSS[289]
AC24 VSS[16] VSS[95] AL34 BC36 VSS[190] VSS[290] T33
AC33 VSS[17] VSS[96] AL48 BC40 VSS[191] VSS[291] P40
AC34 VSS[18] VSS[97] AM11 BC42 VSS[192] VSS[292] P43
AC48 VSS[19] VSS[98] AM14 BC48 VSS[193] VSS[293] P47
C C
AD10 VSS[20] VSS[99] AM36 BD46 VSS[194] VSS[294] P7
AD11 VSS[21] VSS[100] AM39 BD5 VSS[195] VSS[295] R2
AD12 VSS[22] VSS[101] AM43 BE22 VSS[196] VSS[296] R48
AD13 VSS[23] VSS[102] AM45 BE26 VSS[197] VSS[297] T12

do
AD19 VSS[24] VSS[103] AM46 BE40 VSS[198] VSS[298] T31
AD24 VSS[25] VSS[104] AM7 BF10 VSS[199] VSS[299] T37
AD26 VSS[26] VSS[105] AN2 BF12 VSS[200] VSS[300] T4
AD27 VSS[27] VSS[106] AN29 BF16 VSS[201] VSS[301] W34
AD33 VSS[28] VSS[107] AN3 BF20 VSS[202] VSS[302] T46
AD34 VSS[29] VSS[108] AN31 BF22 VSS[203] VSS[303] T47
AD36 VSS[30] VSS[109] AP12 BF24 VSS[204] VSS[304] T8
AD37 VSS[31] VSS[110] AP19 BF26 VSS[205] VSS[305] V11

In
AD38 VSS[32] VSS[111] AP28 BF28 VSS[206] VSS[306] V17
AD39 VSS[33] VSS[112] AP30 BD3 VSS[207] VSS[307] V26
AD4 VSS[34] VSS[113] AP32 BF30 VSS[208] VSS[308] V27
AD40 VSS[35] VSS[114] AP38 BF38 VSS[209] VSS[309] V29
AD42 VSS[36] VSS[115] AP4 BF40 VSS[210] VSS[310] V31
AD43 VSS[37] VSS[116] AP42 BF8 VSS[211] VSS[311] V36
AD45 VSS[38] VSS[117] AP46 BG17 VSS[212] VSS[312] V39
AD46 VSS[39] VSS[118] AP8 BG21 VSS[213] VSS[313] V43

i-
AD8 VSS[40] VSS[119] AR2 BG33 VSS[214] VSS[314] V7
AE2 VSS[41] VSS[120] AR48 BG44 VSS[215] VSS[315] W17
AE3 VSS[42] VSS[121] AT11 BG8 VSS[216] VSS[316] W19
AF10 VSS[43] VSS[122] AT13 BH11 VSS[217] VSS[317] W2
AF12 VSS[44] VSS[123] AT18 BH15 VSS[218] VSS[318] W27
AD14 VSS[45] VSS[124] AT22 BH17 VSS[219] VSS[319] W48
AD16 VSS[46] VSS[125] AT26 BH19 VSS[220] VSS[320] Y12
AF16 VSS[47] VSS[126] AT28 H10 VSS[221] VSS[321] Y38
AF19
AF24
VSS[48]
VSS[49]
VSS[127]
VSS[128]
AT30
AT32
is
BH27
BH31
VSS[222]
VSS[223]
VSS[322]
VSS[323]
Y4
Y42
AF26 VSS[50] VSS[129] AT34 BH33 VSS[224] VSS[324] Y46
B AF27 AT39 BH35 Y8 B
VSS[51] VSS[130] VSS[225] VSS[325]
AF29 VSS[52] VSS[131] AT42 BH39 VSS[226] VSS[328] BG29
AF31 VSS[53] VSS[132] AT46 BH43 VSS[227] VSS[329] N24
AF38 VSS[54] VSS[133] AT7 BH7 VSS[228] VSS[330] AJ3
AF4 VSS[55] VSS[134] AU24 D3 VSS[229] VSS[331] AD47
AF42 AU30 D12 B43
kn

VSS[56] VSS[135] VSS[230] VSS[333]

AF46 VSS[57] VSS[136] AV16 D16 VSS[231] VSS[334] BE10
AF5 VSS[58] VSS[137] AV20 D18 VSS[232] VSS[335] BG41
AF7 VSS[59] VSS[138] AV24 D22 VSS[233] VSS[337] G14
AF8 VSS[60] VSS[139] AV30 D24 VSS[234] VSS[338] H16
AG19 VSS[61] VSS[140] AV38 D26 VSS[235] VSS[340] T36
AG2 VSS[62] VSS[141] AV4 D30 VSS[236] VSS[342] BG22
AG31 VSS[63] VSS[142] AV43 D32 VSS[237] VSS[343] BG24
AG48 AV8 D34 C22
Te

VSS[64] VSS[143] VSS[238] VSS[344]

AH11 VSS[65] VSS[144] AW14 D38 VSS[239] VSS[345] AP13
AH3 VSS[66] VSS[145] AW18 D42 VSS[240] VSS[346] M14
AH36 VSS[67] VSS[146] AW2 D8 VSS[241] VSS[347] AP3
AH39 VSS[68] VSS[147] AW22 E18 VSS[242] VSS[348] AP1
AH40 VSS[69] VSS[148] AW26 E26 VSS[243] VSS[349] BE16
AH42 VSS[70] VSS[149] AW28 G18 VSS[244] VSS[350] BC16
AH46 VSS[71] VSS[150] AW32 G20 VSS[245] VSS[351] BG28
AH7 VSS[72] VSS[151] AW34 G26 VSS[246] VSS[352] BJ28
w.

AJ19 VSS[73] VSS[152] AW36 G28 VSS[247]

AJ21 VSS[74] VSS[153] AW40 G36 VSS[248]
AJ24 VSS[75] VSS[154] AW48 G48 VSS[249]
AJ33 VSS[76] VSS[155] AV11 H12 VSS[250]
AJ34 VSS[77] VSS[156] AY12 H18 VSS[251]
AK12 VSS[78] VSS[157] AY22 H22 VSS[252]
AK3 VSS[79] VSS[158] AY28 H24 VSS[253]
H26 VSS[254]
ww

PANTHER POINT H30 VSS[255]

A H32 VSS[256] A
H34 VSS[257]
F3 VSS[258]

PANTHER POINT

Quanta Computer Inc.

PROJECT :ZQS 45W
Size Document Number Rev
Panther Point 6/6 3C

Date: W ednesday, February 08, 2012 Sheet 12 of 46

5 4 3 2 1
 5 4 3 2 1

+1.5VSUS
JDIM1B
4 M_A_A[15:0] JDIM1A M_A_DQ[63:0] 4
75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ4 76 48
M_A_A1 A0 DQ0 M_A_DQ0 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
M_A_A3 A2 DQ2 M_A_DQ3 VDD4 VSS19
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ1 88 60
M_A_A5 A4 DQ4 M_A_DQ5 VDD6 VSS21
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
A6 DQ6 2.48A VDD8 VSS23

m
M_A_A7 86 18 M_A_DQ7 99 66
M_A_A8 A7 DQ7 M_A_DQ12 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ13 105 72
M_A_A10 A9 DQ9 M_A_DQ11 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM

107 33 106 127

co
M_A_A11 A10/AP DQ10 M_A_DQ10 VDD12 VSS27
84 A11 DQ11 35 111 VDD13 VSS28 128
M_A_A12 83 22 M_A_DQ8 112 133
M_A_A13 A12/BC# DQ12 M_A_DQ9 VDD14 VSS29
119 A13 DQ13 24 117 VDD15 VSS30 134
M_A_A14 80 34 M_A_DQ14 118 138
M_A_A15 A14 DQ14 M_A_DQ15 VDD16 VSS31
78 A15 DQ15 36 123 VDD17 VSS32 139
M_A_DQ17

PC2100 DDR3 SDRAM SO-DIMM

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ20 145
4 M_A_BS#0

a.
BA0 DQ17 M_A_DQ18 VSS34
4 M_A_BS#1 108 BA1 DQ18 51 +3V 199 VDDSPD VSS35 150
79 53 M_A_DQ19 151
4 M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ16 77 155
4 M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
4 M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 R204 *10K_4 125 161
4 M_A_CLK0 CK0 DQ22 +3V NCTEST VSS39
103 52 M_A_DQ23 162
4 M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 PM_EXTTS#0 198 167
4 M_A_CLK1 CK1 DQ24 EVENT# VSS41

si
104 59 M_A_DQ28 30 168
4 M_A_CLK1# CK1# DQ25 14,15 DDR3_DRAMRST# RESET# VSS42
M_A_DQ25
4 M_A_CKE0 73
74
CKE0 DQ26 67
69 M_A_DQ26
M3 solution VSS43 172
173
4 M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ27 R226 *M3@0_6 +SMDDR_VREF_DQ0 1 178
4 M_A_CAS# CAS# DQ28 5 SMDDR_VREF_DQ0_M3 VREF_DQ VSS45
110 58 M_A_DQ29 126 179
4 M_A_RAS# RAS# DQ29 +SMDDR_VREF_DIMM VREF_CA VSS46
113 68 M_A_DQ31 184
4 M_A_WE# WE# DQ30 VSS47
R208 10K_4 DIMM0_SA0 197 70 M_A_DQ30 185
SA0 DQ31 VSS48

ne
R207 10K_4 DIMM0_SA1 201 129 M_A_DQ36 2 189
CLK_SCLK SA1 DQ32 M_A_DQ33 VSS1 VSS49
202 SCL DQ33 131 3 VSS2 VSS50 190
9,14,26,33 CLK_SCLK CLK_SDATA 200 141 M_A_DQ34 8 195

(204P)
9,14,26,33 CLK_SDATA SDA DQ34 M_A_DQ39 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ32 13
4 M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
4 M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
DQ38 VSS7

do
11 142 M_A_DQ35 20
DM0 DQ39 M_A_DQ45 VSS8
28 DM1 DQ40 147 25 VSS9
46 149 M_A_DQ44 26 203 +0.75V_DDR_VTT
63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ40 31
VSS10
VSS11
VTT1
VTT2 204
136 159 M_A_DQ42 32
DM4 DQ43 M_A_DQ47 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
170 148 M_A_DQ41 38 206
DM6 DQ45 VSS14 GND

In
187 158 M_A_DQ46 43
DM7 DQ46 M_A_DQ43 VSS15
DQ47 160
M_A_DQS0 12 163 M_A_DQ53
M_A_DQS1 DQS0 DQ48 M_A_DQ52
29 DQS1 DQ49 165 DDR3-DIMM1_H=9.2_Reverse
M_A_DQS2 47 175 M_A_DQ50 +1.5VSUS
M_A_DQS3 DQS2 DQ50 M_A_DQ55
64 DQS3 DQ51 177
M_A_DQS4 137 164 M_A_DQ49
DQS4 DQ52

i-
M_A_DQS5 154 166 M_A_DQ48
M_A_DQS6 DQS5 DQ53 M_A_DQ54 R213 +SMDDR_VREF_DIMM
171 DQS6 DQ54 174
M_A_DQS7 188 176 M_A_DQ51 change to 1K/F_4 1K/F_4
4 M_A_DQS[7:0] DQS7 DQ55
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ62 +SMDDR_VREF R188 *0_6 +SMDDR_VREF_DIMM 14
M_A_DQS#3 DQS#2 DQ58 M_A_DQ59
62 DQS#3 DQ59 193
M_A_DQS#4
M_A_DQS#5
135
152
DQS#4 DQ60 180
182
is M_A_DQ60
M_A_DQ61 R218 C307
M_A_DQS#6 DQS#5 DQ61 M_A_DQ63
B 169 DQS#6 DQ62 192 1K/F_4 470p/50V_4 B
M_A_DQS#7 186 194 M_A_DQ58 +1.5VSUS
4 M_A_DQS#[7:0] DQS#7 DQ63

DDR3-DIMM1_H=9.2_Reverse R198
kn

1K/F_4
change to 1K/F_4
M1 solution
Place these Caps near So-Dimm0. +SMDDR_VREF R193 *0_6 +SMDDR_VREF_DQ0
Te

SMDDR_VREF_DQ0_M3 1 3 C286
+1.5VSUS 470p/50V_4
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 REV:B Add
C252 C290 C285 C251 C289 Q12 R209

2
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 9,14,15 DRAMRST_CNTRL_PCH SBA@AP2302GN 1K/F_4

C254 + C345 C302 C293 C295 C301

w.

*330u/2V_7343
10u/6.3V_6 0.1u/16V_4 0.1u/16V_4

C249 C288 C253 C250 C287 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 C34 Mount Q12 at SBA sku. 01/17
ww

A
+3V 11,14,15,39,42,46 +1.5VSUS A
+0.75V_DDR_VTT 3,7,8,9,10,11,14,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
14,39,43 +0.75V_DDR_VTT

C258 C263 C276 C284 C577 C580 C583

C277
2.2u/6.3V_6
C283
0.1u/16V_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
14,15,39 +SMDDR_VREF
Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
3C
DDRIII SO-DIMM-0
Date: Wednesday, February 08, 2012 Sheet 13 of 46
5 4 3 2 1
 5 4 3 2 1

+1.5VSUS
4 M_B_A[15:0] JDIM2A M_B_DQ[63:0] 4 JDIM2B
M_B_A0 98 5 M_B_DQ5 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
M_B_A3 A2 DQ2 M_B_DQ3 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
M_B_A5 A4 DQ4 M_B_DQ4 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
A6 DQ6 VDD7 VSS22

m
M_B_A7 86 18 M_B_DQ7 94 65
M_B_A8 A7 DQ7 M_B_DQ13 VDD8 VSS23
D 89 A8 DQ8 21 2.48A 99 VDD9 VSS24 66 D
M_B_A9 85 23 M_B_DQ9 100 71
M_B_A10 A9 DQ9 M_B_DQ10 VDD10 VSS25
107 33 105 72

co
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ8 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ20

PC2100 DDR3 SDRAM SO-DIMM

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
4 M_B_BS#0

a.
BA0 DQ17 M_B_DQ23 VDD18 VSS33
4 M_B_BS#1 108 BA1 DQ18 51 VSS34 145
79 53 M_B_DQ18 199 150
4 M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ16 151
4 M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
4 M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ19 122 156
4 M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ22 R554 *10K_4 125 161
4 M_B_CLK0# CK0# DQ23 +3V NCTEST VSS39
102 57 M_B_DQ28 162
4 M_B_CLK1 CK1 DQ24 VSS40

si
104 59 M_B_DQ24 PM_EXTTS#1 198 167
4 M_B_CLK1# CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ31 30 168
4 M_B_CKE0 CKE0 DQ26 13,15 DDR3_DRAMRST# RESET# VSS42
M_B_DQ27
4 M_B_CKE1 74
115
CKE1 DQ27 69
56 M_B_DQ29
M3 solution VSS43 172
173
4 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ25 R189 *M3@0_6 +SMDDR_VREF_DQ1 1 178
4 M_B_RAS# RAS# DQ29 5 SMDDR_VREF_DQ1_M3 VREF_DQ VSS45
113 68 M_B_DQ30 126 179
4 M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R538 10K_4 DIMM1_SA0 197 70 M_B_DQ26 184
SA0 DQ31 VSS47

ne
R540 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
+3V SA1 DQ32 VSS48
202 131 M_B_DQ33 2 189
9,13,26,33 CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
9,13,26,33 CLK_SDATA 143 M_B_DQ35 8 195

(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
4 M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
4 M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
DQ38 VSS6

do
11 142 M_B_DQ39 19
DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
46 149 M_B_DQ41 25
63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ46 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
136 159 M_B_DQ43 31 204
DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
170 148 M_B_DQ45 37 205
DM6 DQ45 VSS13 GND

In
187 158 M_B_DQ47 38 206
DM7 DQ46 M_B_DQ42 VSS14 GND
DQ47 160 43 VSS15
M_B_DQS0 12 163 M_B_DQ49
M_B_DQS1 DQS0 DQ48 M_B_DQ53
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ55 DDR3-DIMM1_H=5.2_Reverse
M_B_DQS3 DQS2 DQ50 M_B_DQ54
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
DQS4 DQ52

i-
M_B_DQS5 154 166 M_B_DQ48
M_B_DQS6 DQS5 DQ53 M_B_DQ51
171 DQS6 DQ54 174
M_B_DQS7 188 176 M_B_DQ50
4 M_B_DQS[7:0] DQS7 DQ55
M_B_DQS#0 10 181 M_B_DQ60
M_B_DQS#1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ59
M_B_DQS#3 DQS#2 DQ58 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQS#4
M_B_DQS#5
135
152
DQS#4 DQ60 180
182
is M_B_DQ61
M_B_DQ57
M_B_DQS#6 DQS#5 DQ61 M_B_DQ62
B 169 DQS#6 DQ62 192 B
M_B_DQS#7 186 194 M_B_DQ63 +1.5VSUS
4 M_B_DQS#[7:0] DQS#7 DQ63

DDR3-DIMM1_H=5.2_Reverse M1 solution R181

kn

1K/F_4

R187 *0_6 +SMDDR_VREF_DQ1

+1.5VSUS Place these Caps near So-Dimm1. +SMDDR_VREF
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1 change to 1K/F_4
C337 C318 C317 C319 C333 C326
Te

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 SMDDR_VREF_DQ1_M3 1 3 470p/50V_4

C336 + C349 C257 C292 C322 C316 REV:B Add

330u/2V_7343 Q11 R239

2
10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 9,13,15 DRAMRST_CNTRL_PCH *AP2302GN 1K/F_4

C338 C320 C321 C332 C334 2.2u/6.3V_6 2.2u/6.3V_6

w.

10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

+3V +0.75V_DDR_VTT
ww

11,13,15,39,42,46 +1.5VSUS
A C586 C587 C611 C612 C574 C570 C610
3,7,8,9,10,11,13,16,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V A
C614 C608 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 13,39,43 +0.75V_DDR_VTT
2.2u/6.3V_6 0.1u/16V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
13 +SMDDR_VREF_DIMM
13,15,39 +SMDDR_VREF
Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
3C
DDRIII SO-DIMM-1
Date: Wednesday, February 08, 2012 Sheet 14 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

CPU XDP Connector(CPU) s3 leakage circuit

+1.5VSUS

R424
1K/F_4

m
A Q34 2N7002K A
13,14 DDR3_DRAMRST# R420 1K/F_4 3 1 CPU_DRAMRST# 3

co
2
9,13,14 DRAMRST_CNTRL_PCH
R433
C541 4.99K/F_4
0.047u/16V_4

a.
+3V_S5

+1.5V_CPU
C524

si
0.1u/10V_4

R416

5
U17 200/F_4
7 SYS_PWROK 2
4 PM_DRAM_PWRGD_Q R418 130/F_4 PM_DRAM_PWRGD_R 3
7 PM_DRAM_PWRGD 1

ne
74AHC1G09

3
R417 *39_4 3 1
B B

Q32 *2N7002K

2
MAINON_ON_G

do
In
+SMDDR_VREF +VDDR_REF_CPU +1.5VSUS

R430 *0_8 R429

*1K/F_4

i-
3 1

Q33
2N7002K R431

2
36,39,43 MAIND MAIND R432 *1K/F_4
100K_4

C C
is
4.5A +1.5VSUS +1.5V_CPU
R465 *0_8
kn

R464 *0_8 +1.5V_CPU

+VDDR_REF_CPU +VDDR_REF_CPU 5
Q37 AO4496
8 1 +1.5V_CPU +1.5V_CPU 5
7 2
6 3
5 +1.5VSUS 11,13,14,39,42,46
Te

+SMDDR_VREF 13,14,39

4
MAIND
R444
220_8
C548
470p/50V_4

3
w.

43 MAINON_ON_G MAINON_ON_G 2

Q35
DMN601K-7
D D

1
ww

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
XDP
Date: Wednesday, February 08, 2012 Sheet 15 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+1.05V_GFX
1000mA

To be placed no further from the GPU C44 EOP@22u/6.3V_8 U14A

than bewteen the PS and GPU C401 EOP@22u/6.3V_8 AG19 PEX_IOVDD_1 PEX_RX0 AN12 PEG_TX15 3
DIS.VGA-->EV@ + EOP@
C403 EOP@10u/6.3V_6 AG21 AM12
C402 EOP@10u/6.3V_6 AG22
PEX_IOVDD_2 [PEG Interface] PEX_RX0_N
AN14
PEG_TX#15 3
PEG_TX14 3
Optimize-->IOP@ + EOP@
PLACE UNDER BGA C115 [email protected]/6.3V_6 PEX_IOVDD_3 PEX_RX1
AG24 AM14 PEG_TX#14 3
C91 EOP@1u/6.3V_4 AH21
PEX_IOVDD_4
PEX_IOVDD_5
PEX_RX1_N
PEX_RX2 AP14 PEG_TX13 3 UMA-->IV@ + IOP@
PLACE NEAR BALLS C108 EOP@1u/6.3V_4 AH25 AP15 PEG_TX#13 3
PEX_IOVDD_6 PEX_RX2_N
Special-->SP@

m
AN15 PEG_TX12 3 +3V_S5
PEX_RX3 +3V_GFX
A +1.05V_GFX AG13 PEX_IOVDDQ_1 PEX_RX3_N AM15 PEG_TX#12 3 A
C407 EOP@22u/6.3V_8 AG15 AN17 PEG_TX11 3
To be placed no further from the GPU C406 EOP@22u/6.3V_8 PEX_IOVDDQ_2 PEX_RX4 R400 EOP@10K/F_4
AG16 PEX_IOVDDQ_3 PEX_RX4_N AM17 PEG_TX#11 3

co
than bewteen the PS and GPU C409 EOP@10u/6.3V_6 AG18 AP17
PEX_IOVDDQ_4 PEX_RX5 PEG_TX10 3
C408 EOP@10u/6.3V_6 AG25 AP18 PEG_TX#10 3 R396
PLACE UNDER BGA PEX_IOVDDQ_5 PEX_RX5_N CLK_PEGA_REQ# 9
C102 [email protected]/6.3V_6 AH15 AN18 PEG_TX9 3 EOP@10K/F_4
PEX_IOVDDQ_6 PEX_RX6

3
C84 EOP@1u/6.3V_4 AH18 AM18 PEG_TX#9 3
PLACE NEAR BALLS C75 EOP@1u/6.3V_4 PEX_IOVDDQ_7 PEX_RX6_N
AH26 PEX_IOVDDQ_8 PEX_RX7 AN20 PEG_TX8 3
AH27 AM20 PEG_TX#8 3 2 Q28
PEX_IOVDDQ_9 PEX_RX7_N EOP@DTC144EUA
AJ27 PEX_IOVDDQ_10 PEX_RX8 AP20 PEG_TX7 3

3
AK27 AP21
2500mA

a.
PEX_IOVDDQ_11 PEX_RX8_N PEG_TX#7 3
AL27 AN21 PEG_TX6 3

1
PEX_IOVDDQ_12 PEX_RX9 PEX_CLKREQ# Q26
AM28 PEX_IOVDDQ_13 PEX_RX9_N AM21 PEG_TX#6 3 2
AN28 PEX_IOVDDQ_14 PEX_RX10 AN23 PEG_TX5 3
PEX_RX10_N AM23 PEG_TX#5 3
AP23 PEG_TX4 3 EOP@PDTC143TT

1
PEX_RX11 +3V
PEX_RX11_N AP24 PEG_TX#4 3
PEX_RX12 AN24 PEG_TX3 3

si
PEX_RX12_N AM24 PEG_TX#3 3
AN26 +3V_GFX R85 *SHORT_4
PEX_RX13 PEG_TX2 3
PEX_RX13_N AM26 PEG_TX#2 3
AP26 PEG_TX1 3 R80 *0_4
PEX_RX14 C149
PEX_RX14_N AP27 PEG_TX#1 3
PEX_RX15 AN27 PEG_TX0 3 [email protected]/10V_4
PEX_RX15_N AM27 PEG_TX#0 3

5
ne
9,25,29,34 PLTRST# 2
AK14 R_PEG_RX15 C130 [email protected]/10V_4 PEG_RX15 3 4 PEGX_RST#
PEX_TX0 R_PEG_RX#15 C141 [email protected]/10V_4
PEX_TX0_N AJ14 PEG_RX#15 3 9 DGPU_HOLD_RST# 1
B AH14 R_PEG_RX14 C142 [email protected]/10V_4 PEG_RX14 3
B
PEX_TX1 R_PEG_RX#14 C145 [email protected]/10V_4 R71
AG14 PEG_RX#14 3

3
PEX_TX1_N R_PEG_RX13 C125 [email protected]/10V_4 U3
PEX_TX2 AK15 PEG_RX13 3
AJ15 R_PEG_RX#13 C129 [email protected]/10V_4 PEG_RX#13 3 EOP@100K_4
PEX_TX2_N

do
AL16 R_PEG_RX12 C118 [email protected]/10V_4 PEG_RX12 3 EOP@MC74VHC1G08DFT2G
PEX_TX3 R_PEG_RX#12 C121 [email protected]/10V_4
PEX_TX3_N AK16 PEG_RX#12 3
AK17 R_PEG_RX11 C110 [email protected]/10V_4 PEG_RX11 3
PEX_TX4 R_PEG_RX#11 C116 [email protected]/10V_4
PEX_TX4_N AJ17 PEG_RX#11 3
AH17 R_PEG_RX10 C105 [email protected]/10V_4 PEG_RX10 3
PEX_TX5 R_PEG_RX#10 C109 [email protected]/10V_4
AC6 NC_1 PEX_TX5_N AG17 PEG_RX#10 3
AJ28 AK18 R_PEG_RX9 C96 [email protected]/10V_4 PEG_RX9 3
NC_2 PEX_TX6 R_PEG_RX#9 C103 [email protected]/10V_4
AJ4 AJ18 PEG_RX#9 3

In
NC_3 PEX_TX6_N R_PEG_RX8 C95 [email protected]/10V_4
AJ5 NC_4 PEX_TX7 AL19 PEG_RX8 3
AL11 AK19 R_PEG_RX#8 C92 [email protected]/10V_4 PEG_RX#8 3
NC_5 PEX_TX7_N R_PEG_RX7 C90 [email protected]/10V_4
C15 NC_6 PEX_TX8 AK20 PEG_RX7 3
D19 AJ20 R_PEG_RX#7 C87 [email protected]/10V_4 PEG_RX#7 3
NC_7 PEX_TX8_N R_PEG_RX6 C86 [email protected]/10V_4
D20 AH20
D23
NC_8
NC_9
PEX_TX9
PEX_TX9_N AG20 R_PEG_RX#6
R_PEG_RX5
C82
C78
[email protected]/10V_4
[email protected]/10V_4
PEG_RX6 3
PEG_RX#6 3 FOR DIS & Optimus
D26 NC_10 PEX_TX10 AK21 PEG_RX5 3
R_PEG_RX#5 C74 [email protected]/10V_4

i-
H31 NC_11 PEX_TX10_N AJ21 PEG_RX#5 3
T8 AL22 R_PEG_RX4 C72 [email protected]/10V_4 PEG_RX4 3
NC_12 PEX_TX11 R_PEG_RX#4 C68 [email protected]/10V_4
V32 NC_13 PEX_TX11_N AK22 PEG_RX#4 3
AK23 R_PEG_RX3 C65 [email protected]/10V_4 PEG_RX3 3
PEX_TX12 R_PEG_RX#3 C62 [email protected]/10V_4
PEX_TX12_N AJ23 PEG_RX#3 3
AH23 R_PEG_RX2 C55 [email protected]/10V_4 PEG_RX2 3
PEX_TX13 R_PEG_RX#2 C52 [email protected]/10V_4
PEX_TX13_N AG23 PEG_RX#2 3
AK24 R_PEG_RX1 C61 [email protected]/10V_4 PEG_RX1 3
PEX_TX14
PEX_TX14_N
is
AJ24
AL25
R_PEG_RX#1
R_PEG_RX0
C60
C59
[email protected]/10V_4
[email protected]/10V_4
PEG_RX#1 3
PEG_RX0 3
C PEX_TX15 R_PEG_RX#0 C58 [email protected]/10V_4 C
PEX_TX15_N AK25 PEG_RX#0 3

AL13 CLK_PCIE_VGA CLK_PCIE_VGA 9

PEX_REFCLK CLK_PCIE_VGA#
PEX_REFCLK_N AK13 CLK_PCIE_VGA# 9
kn

AJ26 PEX_TSTCLK R42 *EOP@200_4

PEX_TSTCLK_OUT PEX_TSTCLK#
+3V_GFX J8 VDD33_1 PEX_TSTCLK_OUT_N AK26
K8 VDD33_2
L8 VDD33_3 PEX_WAKE_N AJ11 TP6
M8 AJ12 PEGX_RST# PEGX_RST# 19
VDD33_4 PEX_RST_N
Te

AK12 PEX_CLKREQ# R380 EOP@10K/F_4 +3V_GFX

PEX_CLKREQ_N
N13M-GS N13P- GL
AP29 PEX_TERMP R339 [email protected]/F_4
PEX_TERMP
N13P-GS N13P- PES PEX_RST timing
TESTMODE R358 EOP@10K/F_4
AK11 R41 EOP_GS@0_6
w.

+3V_GFX TESTMODE +1.05V_GFX

L5 *EOP_GL@160808-120 Stuff--> R Reserve--> R
PLACE CLOSE TO BGA
150mA
C132 [email protected]/6.3V_6 AG26 PEX_PLLVDD C48 [email protected]/6.3V_6 PLACE NEAR BGA I/O 3.3V
PEX_PLLVDD CLOSE TO CAPS
C133 EOP@1u/16V_6 210mA C63 EOP@1u/6.3V_4
Reserve -->L Stuff--> L
PEX_PLL_HVDD AH12
AG12 PLACE UNDER BGA PEX_RST
C139 [email protected]/10V_4 PEX_SVDD_3V3 C69 [email protected]/10V_4
ww

C140 [email protected]/10V_4 PLACE NEAR BALLS

D D
C143 [email protected]/10V_4 P8
C135 [email protected]/10V_4 NC
+3V_GFX
Trise >= 1uS Tfail <=500nS
L4 C126 [email protected]/10V_4
PLACE CLOSE TO GPU BALLS VDD_SENSE C482 [email protected]/6.3V_6

GND_SENSE L5 12~16 mils width PLACE NEAR BGA Quanta Computer Inc.
EOP@N13x
GPUVCC_SENSE 41 PROJECT : ZQS 45W
N13P GPUVSS_SENSE 41 17,18,20,42 +1.05V_GFX
Size Document Number Rev
18,19,20,41,42 +3V_GFX
3C
7,8,9,10,11,15,29,31,33,36,37,38,43,44 +3V_S5 DGPU 1/5 (PEG)
3,7,8,9,10,11,13,14,20,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
Date: W ednesday, February 08, 2012 Sheet 16 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U14B U14C
FBC_CMD0 D13 G9 VMC_DQ0
22 FBC_CMD[30:0] FBB_CMD0 (FBC_CMD25) FBC_D00
FBC_CMD1 E14 E9 VMC_DQ1
FBA_CMD0 VMA_DQ0 FBC_CMD2 FBB_CMD1 (FBC_CMD23) FBC_D01 VMC_DQ2 FBA_CMD2 R32 EOP@10K/F_4
U30 L28 F14 G8
21 FBA_CMD[30:0]
FBA_CMD1 FBA_CMD0 (FBA_CMD25) FBA_D00 VMA_DQ3 FBC_CMD3 FBC_CMD2 MEMORY I/F C FBC_D02 VMC_DQ3
FBA_CMD1 (FBA_CMD23) [MEMORY I/F A]
T31 M29 A12 F9
FBA_CMD2 FBA_D01 VMA_DQ2 FBC_CMD4 FBB_CMD3 (FBC_CMD0) FBC_D03 VMC_DQ4 FBA_CMD3 R330 EOP@10K/F_4
U29 FBA_CMD2 FBA_D02 L29 B12 FBB_CMD4 (FBC_CMD10) FBC_D04 F11
FBA_CMD3 R34 M28 VMA_DQ1 FBC_CMD5 C14 G11 VMC_DQ5
FBA_CMD4 FBA_CMD3 (FBA_CMD0) FBA_D03 VMA_DQ4 FBC_CMD6 FBB_CMD5 (FBC_CMD26) FBC_D05 VMC_DQ6 FBA_CMD5 R39 EOP@10K/F_4
R33 N31 B14 F12
FBA_CMD5 FBA_CMD4 (FBA_CMD10) FBA_D04 VMA_DQ6 FBC_CMD7 FBB_CMD6 (FBC_CMD14) FBC_D06 VMC_DQ7
U32 P29 G15 G12
FBA_CMD6 FBA_CMD5 (FBA_CMD26) FBA_D05 VMA_DQ5 FBC_CMD8 FBC_CMD7 FBC_D07 VMC_DQ8 FBA_CMD18 R25 EOP@10K/F_4
U33 R29 F15 G6
FBA_CMD7 FBA_CMD6 (FBA_CMD14) FBA_D06 VMA_DQ7 FBC_CMD9 FBB_CMD8 (FBC_CMD1) FBC_D08 VMC_DQ9
U28 P28 E15 F5

m
FBA_CMD8 FBA_CMD7 FBA_D07 VMA_DQ8 FBC_CMD10 FBB_CMD9 (FBC_CMD22) FBC_D09 VMC_DQ10 FBA_CMD19 R335 EOP@10K/F_4
V28 J28 D15 E6
A FBA_CMD9 FBA_CMD8 (FBA_CMD1) FBA_D08 VMA_DQ10 FBC_CMD11 FBB_CMD10 (FBC_CMD20) FBC_D10 VMC_DQ11 A
V29 FBA_CMD9 (FBA_CMD22) FBA_D09 H29 A14 FBB_CMD11 (FBC_CMD24) FBC_D11 F6
FBA_CMD10 V30 J29 VMA_DQ9 FBC_CMD12 D14 F4 VMC_DQ12 FBC_CMD2 R58 EOP@10K/F_4
FBA_CMD11 FBA_CMD10 (FBA_CMD20) FBA_D10 VMA_DQ11 FBC_CMD13 FBB_CMD12 (FBC_CMD18) FBC_D12 VMC_DQ13
U34 FBA_CMD11 (FBA_CMD24) FBA_D11 H28 A15 FBB_CMD13 (FBC_CMD9) FBC_D13 G4

co
FBA_CMD12 U31 G29 VMA_DQ12 FBC_CMD14 B15 E2 VMC_DQ14 FBC_CMD3 R344 EOP@10K/F_4
FBA_CMD13 FBA_CMD12 (FBA_CMD18) FBA_D12 VMA_DQ14 FBC_CMD15 FBB_CMD14 (FBC_CMD29) FBC_D14 VMC_DQ15
V34 FBA_CMD13 (FBA_CMD9) FBA_D13 E31 C17 FBB_CMD15 (FBC_CMD8) FBC_D15 F3
FBA_CMD14 V33 E32 VMA_DQ13 FBC_CMD16 D18 C2 VMC_DQ16 FBC_CMD5 R55 EOP@10K/F_4
FBA_CMD15 FBA_CMD14 (FBA_CMD29) FBA_D14 VMA_DQ15 FBC_CMD17 FBB_CMD16 (FBC_CMD27) FBC_D16 VMC_DQ17
Y32 FBA_CMD15 (FBA_CMD8) FBA_D15 F30 E18 FBB_CMD17 (FBC_CMD15) FBC_D17 D4
FBA_CMD16 AA31 C34 VMA_DQ16 FBC_CMD18 F18 D3 VMC_DQ18 FBC_CMD18 R341 EOP@10K/F_4
FBA_CMD17 FBA_CMD16 (FBA_CMD27) FBA_D16 VMA_DQ17 FBC_CMD19 FBB_CMD18 (FBC_CMD11) FBC_D18 VMC_DQ19
AA29 D32 A20 C1
FBA_CMD18 FBA_CMD17 (FBA_CMD15) FBA_D17 VMA_DQ18 FBC_CMD20 FBB_CMD19 (FBC_CMD16) FBC_D19 VMC_DQ20 FBC_CMD19 R44 EOP@10K/F_4
AA28 B33 B20 B3
FBA_CMD19 FBA_CMD18 (FBA_CMD11) FBA_D18 VMA_DQ19 FBC_CMD21 FBB_CMD20 (FBC_CMD28) FBC_D20 VMC_DQ21
AC34 C33 C18 C4
FBA_CMD20 FBA_CMD19 (FBA_CMD16) FBA_D19 VMA_DQ20 FBC_CMD22 FBB_CMD21 (FBC_CMD3) FBC_D21 VMC_DQ22
AC33 F33 B18 B5 For Fermi

a.
FBA_CMD21 FBA_CMD20 (FBA_CMD28) FBA_D20 VMA_DQ21 FBC_CMD23 FBB_CMD22 (FBC_CMD17) FBC_D22 VMC_DQ23
AA32 F32 G18 C5
FBA_CMD22 FBA_CMD21 (FBA_CMD3) FBA_D21 VMA_DQ22 FBC_CMD24 FBB_CMD23 (FBC_CMD5) FBC_D23 VMC_DQ24
AA33 H33 G17 A11
FBA_CMD23 FBA_CMD22 (FBA_CMD17) FBA_D22 VMA_DQ23 FBC_CMD25 FBB_CMD24(FBC_CMD4) FBC_D24 VMC_DQ25
Y28 H32 F17 C11
FBA_CMD24 FBA_CMD23 (FBA_CMD5) FBA_D23 VMA_DQ24 FBC_CMD26 FBB_CMD25 (FBC_CMD21) FBC_D25 VMC_DQ26 VMA_DQ[63:0]
Y29 P34 D16 D11 VMA_DQ[63:0] 21
FBA_CMD25 FBA_CMD24 (FBA_CMD4) FBA_D24 VMA_DQ25 FBC_CMD27 FBB_CMD26 (FBC_CMD6) FBC_D26 VMC_DQ27
W31 P32 A18 B11
FBA_CMD26 FBA_CMD25 (FBA_CMD21) FBA_D25 VMA_DQ26 FBC_CMD28 FBB_CMD27 (FBC_CMD13) FBC_D27 VMC_DQ28 VMC_DQ[63:0]
Y30 P31 D17 D8 VMC_DQ[63:0] 22
FBA_CMD27 FBA_CMD26 (FBA_CMD6) FBA_D26 VMA_DQ27 FBC_CMD29 FBB_CMD28 (FBC_CMD19) FBC_D28 VMC_DQ29
AA34 FBA_CMD27 (FBA_CMD13) FBA_D27 P33 A17 FBB_CMD29 (FBC_CMD12) FBC_D29 A8
FBA_CMD28 Y31 L31 VMA_DQ28 FBC_CMD30 B17 C8 VMC_DQ30
FBA_CMD29 FBA_CMD28 (FBA_CMD19) FBA_D28 VMA_DQ29 FBC_CMD30 FBC_D30 VMC_DQ31
Y34 L34 E17 B8

si
FBA_CMD30 FBA_CMD29 (FBA_CMD12) FBA_D29 VMA_DQ30 TP157 FBC_CMD31 (NC) FBC_D31 VMC_DQ34
Y33 FBA_CMD30 FBA_D30 L32 FBC_D32 F24
V31 L33 VMA_DQ31 G23 VMC_DQ37
TP158 FBA_CMD31 (NC) FBA_D31 VMA_DQ32 VMC_DM0 FBC_D33 VMC_DQ32
FBA_D32 AG28 22 VMC_DM[7:0] E11 FBC_DQM0 FBC_D34 E24
AF29 VMA_DQ33 VMC_DM1 E3 G24 VMC_DQ38
VMA_DM0 FBA_D33 VMA_DQ34 VMC_DM2 FBC_DQM1 FBC_D35 VMC_DQ36
21 VMA_DM[7:0] P30 AG29 A3 D21
VMA_DM1 FBA_DQM0 FBA_D34 VMA_DQ35 VMC_DM3 FBC_DQM2 FBC_D36 VMC_DQ33
F31 FBA_DQM1 FBA_D35 AF28 C9 FBC_DQM3 FBC_D37 E21
VMA_DM2 F34 AD30 VMA_DQ36 VMC_DM4 F23 G21 VMC_DQ35
VMA_DM3 FBA_DQM2 FBA_D36 VMA_DQ37 VMC_DM5 FBC_DQM4 FBC_D38 VMC_DQ39
M32 FBA_DQM3 FBA_D37 AD29 F27 FBC_DQM5 FBC_D39 F21
VMA_DM4 VMA_DQ38 VMC_DM6 VMC_DQ40

ne
AD31 AC29 C30 G27
VMA_DM5 FBA_DQM4 FBA_D38 VMA_DQ39 VMC_DM7 FBC_DQM6 FBC_D40 VMC_DQ41
AL29 AD28 A24 D27
VMA_DM6 FBA_DQM5 FBA_D39 VMA_DQ40 FBC_DQM7 FBC_D41 VMC_DQ47
AM32 FBA_DQM6 FBA_D40 AJ29 FBC_D42 G26
VMA_DM7 AF34 AK29 VMA_DQ41 E27 VMC_DQ46
FBA_DQM7 FBA_D41 VMA_DQ42 VMC_WDQS0 FBC_D43 VMC_DQ44
B FBA_D42 AJ30 22 VMC_WDQS[7:0] D10 FBC_DQS_WP0 FBC_D44 E29 B
AK28 VMA_DQ43 VMC_WDQS1 D5 F29 VMC_DQ45
VMA_WDQS0 FBA_D43 VMA_DQ44 VMC_WDQS2 FBC_DQS_WP1 FBC_D45 VMC_DQ43
21 VMA_WDQS[7:0] M31 AM29 C3 E30
VMA_WDQS1 FBA_DQS_WP0 FBA_D44 VMA_DQ45 VMC_WDQS3 FBC_DQS_WP2 FBC_D46 VMC_DQ42
G31 AM31 B9 D30
VMA_WDQS2 FBA_DQS_WP1 FBA_D45 VMA_DQ46 VMC_WDQS4 FBC_DQS_WP3 FBC_D47 VMC_DQ50
E33 AN29 E23 A32
FBA_DQS_WP2 FBA_D46 FBC_DQS_WP4 FBC_D48

do
VMA_WDQS3 M33 AM30 VMA_DQ47 VMC_WDQS5 E28 C31 VMC_DQ49
VMA_WDQS4 FBA_DQS_WP3 FBA_D47 VMA_DQ48 VMC_WDQS6 FBC_DQS_WP5 FBC_D49 VMC_DQ51
AE31 AN31 B30 C32
VMA_WDQS5 FBA_DQS_WP4 FBA_D48 VMA_DQ49 VMC_WDQS7 FBC_DQS_WP6 FBC_D50 VMC_DQ48
AK30 AN32 A23 B32
VMA_WDQS6 FBA_DQS_WP5 FBA_D49 VMA_DQ50 FBC_DQS_WP7 FBC_D51 VMC_DQ52
AN33 AP30 D29
VMA_WDQS7 FBA_DQS_WP6 FBA_D50 VMA_DQ51 FBC_D52 VMC_DQ53
AF33 AP32 A29
FBA_DQS_WP7 FBA_D51 VMA_DQ52 VMC_RDQS0 FBC_D53 VMC_DQ54
AM33 22 VMC_RDQS[7:0] D9 C29
FBA_D52 VMA_DQ53 VMC_RDQS1 FBC_DQS_RN0 FBC_D54 VMC_DQ55
FBA_D53 AL31 E4 FBC_DQS_RN1 FBC_D55 B29
VMA_RDQS0 M30 AK33 VMA_DQ54 VMC_RDQS2 B2 B21 VMC_DQ56
21 VMA_RDQS[7:0] FBA_DQS_RN0 FBA_D54 FBC_DQS_RN2 FBC_D56
VMA_RDQS1 H30 AK32 VMA_DQ55 VMC_RDQS3 A9 C23 VMC_DQ57
FBA_DQS_RN1 FBA_D55 FBC_DQS_RN3 FBC_D57

In
VMA_RDQS2 E34 AD34 VMA_DQ56 VMC_RDQS4 D22 A21 VMC_DQ58
VMA_RDQS3 FBA_DQS_RN2 FBA_D56 VMA_DQ57 VMC_RDQS5 FBC_DQS_RN4 FBC_D58 VMC_DQ59
M34 AD32 D28 C21
VMA_RDQS4 FBA_DQS_RN3 FBA_D57 VMA_DQ58 VMC_RDQS6 FBC_DQS_RN5 FBC_D59 VMC_DQ60
AF30 AC30 A30 B24
VMA_RDQS5 FBA_DQS_RN4 FBA_D58 VMA_DQ59 VMC_RDQS7 FBC_DQS_RN6 FBC_D60 VMC_DQ61
AK31 AD33 B23 C24
VMA_RDQS6 FBA_DQS_RN5 FBA_D59 VMA_DQ60 FBC_DQS_RN7 FBC_D61 VMC_DQ62
AM34 AF31 B26
VMA_RDQS7 FBA_DQS_RN6 FBA_D60 VMA_DQ61 FBC_D62 VMC_DQ63
AF32 FBA_DQS_RN7 FBA_D61 AG34 FBC_D63 C26
AG32 VMA_DQ62
FBA_D62 VMA_DQ63
AG33
FBA_D63 VMC_CLK0
+1.5V_GFX AA27 FBVDDQ_1 FBC_CLK0 D12 VMC_CLK0 22

i-
AA30 E12 VMC_CLK0# VMC_CLK0# 22
FBVDDQ_2 VMA_CLK0 FBC_CLK0_N VMC_CLK1
AB27 R30 VMA_CLK0 21 E20 VMC_CLK1 22
FBVDDQ_3 FBA_CLK0 VMA_CLK0# FBC_CLK1 VMC_CLK1#
AB33 R31 VMA_CLK0# 21 F20 VMC_CLK1# 22
FBVDDQ_4 FBA_CLK0_N VMA_CLK1 FBC_CLK1_N
AC27 FBVDDQ_5 FBA_CLK1 AB31 VMA_CLK1 21
AD27 AC31 VMA_CLK1# VMA_CLK1# 21
FBVDDQ_6 FBA_CLK1_N FBC_DEBUG R57 [email protected]/F_4
AE27
FBVDDQ_7
15mils width (FBC_DEBUG) FBB_DEBUG0
G14 +1.5V_GFX
AF27 G20 FBC_DEBUG1 R54 [email protected]/F_4
FBVDDQ_8 FBA_DEBUG R48 [email protected]/F_4 (NC) FBB_DEBUG1
AG27 R28 +1.5V_GFX
FBVDDQ_9 (FBA_DEBUG) FBA_DEBUG0 FBA_DEBUG1 R46 [email protected]/F_4
B13 AC28 C12
B16
B19
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
(NC) FBA_DEBUG1
FB_VREF
H26
is TP159
FBB_CMD_RFU0
FBB_CMD_RFU1
C20

C E13 R32 F8 C
FBVDDQ_13 FBA_CMD_RFU0 FBB_WCK01
E16 AC32 E8
FBVDDQ_14 FBA_CMD_RFU1 FBB_WCK01_N
E19 FBVDDQ_15 FBB_WCK23 A5
H10 K31 A6
FBVDDQ_16 FBA_WCK01 FBB_WCK23_N
H11 L30 D24
FBVDDQ_17 FBA_WCK01_N FBB_WCK45
H12 FBVDDQ_18 FBA_WCK23 H34 FBB_WCK45_N D25
H13 J34 B27
kn

FBVDDQ_19 FBA_WCK23_N FBB_WCK67

H14 FBVDDQ_20 FBA_WCK45 AG30 FBB_WCK67_N C27
H15 AG31
FBVDDQ_21 FBA_WCK45_N
H16 AJ34
FBVDDQ_22 FBA_WCK67
H18 FBVDDQ_23 FBA_WCK67_N AK34 FBB_WCKB01 D6
+1.5V_GFX H19
FBVDDQ_24 N13M-GS N13P- GL FBB_WCKB01_N
D7
H20 J30 C6
FBVDDQ_25 FBA_WCKB01 FBB_WCKB23
H21 FBVDDQ_26 FBA_WCKB01_N J31 FBB_WCKB23_N B6
H22
FBVDDQ_27 FBA_WCKB23
J32 N13P-GS N13P- PES/ GL FBB_WCKB45
F26
H23 J33 E26
Te

FBVDDQ_28 FBA_WCKB23_N FBB_WCKB45_N

PLACE CLOSE TO GPU BALLS H24 AH31 A26
FBVDDQ_29 FBA_WCKB45 FBB_WCKB67
C399 [email protected]/6.3V_6
H8 FBVDDQ_30 FBA_WCKB45_N AJ31 Stuff Ra Reserve Ra FBB_WCKB67_N A27
H9 FBVDDQ_31 FBA_WCKB67 AJ32
C398 [email protected]/6.3V_6 L27 AJ33
C40 1 FBVDDQ_32 FBA_WCKB67_N
2 EOP@1u/16V_6 M27 FBVDDQ_33 Ra FBB_PLL_AVDD H17 +FB_PLLAVDD C100 [email protected]/10V_4
C39 1 2 EOP@1u/16V_6 N27 E1 PS_FB_CLAMP R385 EOP_GS@10K_4
C80 [email protected]/10V_4 FBVDDQ_34 FB_CLAMP PLACE CLOSE TO BALL
P27
C431 [email protected]/10V_4 FBVDDQ_35 +FB_PLLAVDD C67 [email protected]/10V_4
R27 K27
C439 [email protected]/10V_4 FBVDDQ_36 FB_DLL_AVDD PLACE CLOSE TO BALL EOP@N13x
w.

T27
C120 [email protected]/10V_4 FBVDDQ_37 +FB_PLLAVDD L4 EOP@PBY160808T-30Y-N_6
T30 U27 +1.05V_GFX
C66 [email protected]/10V_4 FBVDDQ_38 FBA_PLL_AVDD C45 EOP@22u/6.3V_8
T33
C383 [email protected]/10V_4 FBVDDQ_39 FBVDDQ_SENSE_NC PLACE CLOSE TO BGA
V27 FBVDDQ_40 FBVDDQ_SENSE F1
C385 [email protected]/10V_4 W27 TP160 C70 [email protected]/10V_4
C64 [email protected]/10V_4 FBVDDQ_41 FB_GND_SENSE_NC C71 [email protected]/10V_4
W30 F2
FBVDDQ_42 FB_GND_SENSE TP161
W33 FBVDDQ_43
Y27 J27 FB_CAL_PD_VDDQ R49 [email protected]/F_4 +1.5V_GFX
C38 EOP@10u/6.3V_8 FBVDDQ_44 FB_CAL_PD_VDDQ
ww

C36 EOP@10u/6.3V_8 H27 FB_CAL_PU_GND R50 [email protected]/F_4

D C35 EOP@10u/6.3V_8 FB_CAL_PU_GND D
C396 EOP@10u/6.3V_8 H25 FB_CAL_TERM_GND R52 [email protected]/F_4
FB_CALTERM_GND
PLACE CLOSE TO BGA PLACE CLOSE TO GPU BALLS
EOP@N13x

20,21,22,42,46 +1.5V_GFX
Quanta Computer Inc.
16,18,20,42 +1.05V_GFX
PROJECT : ZQS 45W
Size Document Number Rev
3C
DGPU 2/5 (Memory)
Date: Wednesday, February 08, 2012 Sheet 17 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Optimize remove L & C

Pull down 10K (P/N:CS31002FB26)
C470 SP@1u/6.3V_4
C467 [email protected]/10V_4
C477 [email protected]/6.3V_6
U14D
+1.05V_GFX L27 EV@160808-120 IFPAB_PLLVDD 50 mA AH8 AN6 EV_TXLCLK- 23
IFPAB_PLLVDD IFPA_TXC_N
[IFPA/B_LVDS] IFPA_TXC AM6 EV_TXLCLK+ 23
AN3
+3V_GFX L28 EV@160808-0180P IFPAB_IOVDD 320 mAAG8 IFPA_TXD0_N
AP3
EV_TXLOUT0- 23
EV_TXLOUT0+ 23
C474 [email protected]/10V_4 IFPA_IOVDD IFPA_TXD0
IFPA_TXD1_N AM5 EV_TXLOUT1- 23

m
C471 [email protected]/10V_4 AG9 AN5 EV_TXLOUT1+ 23
C468 EV@1u/6.3V_4 IFPB_IOVDD IFPA_TXD1
A
IFPA_TXD2_N AK6 EV_TXLOUT2- 23 A
C480 [email protected]/6.3V_6 AL6 EV_TXLOUT2+ 23
IFPA_TXD2 +3V_GFX
IFPA_TXD3_N AH6

co
R62 *EV@1K/F_4 IFPAB_RSET AJ8 AJ6
IFPAB_RSET IFPA_TXD3
AH9 R100 [email protected]_4 EV_CRTDCLK
N13P-GS DIS IFPAB_IOVDD filter component from bead to 4.3ohm resistor. IFPB_TXC_N
IFPB_TXC AJ9
AP5 R99 [email protected]_4 EV_CRTDDAT
IFPB_TXD4_N
IFPB_TXD4 AP6
IFPB_TXD5_N AL7
AM7

a.
IFPB_TXD5 R378 [email protected]_4 EV_HDMI_DDCCK_C
IFPB_TXD6_N AM8
Optimize remove L & C IFPB_TXD6 AN8
AL8 R377 [email protected]_4 EV_HDMI_DDCDAT_C
Pull down 10K (P/N:CS31002FB26) IFPB_TXD7_N
IFPB_TXD7 AK8

EV@SBK160808T-301Y-N_6
+3V_GFX L30 +IFPCD_PLLVDD 110 mAAF7 AG3 EV_HDMI_DDCCK_C EV_HDMI_DDCCK_C 24
IFPC_PLLVDD IFPC_AUX_I2CW_SCL

si
[IFPC/D_TMDS]IFPC_AUX_I2CW_SDA_N AG2 EV_HDMI_DDCDAT_C EV_HDMI_DDCDAT_C 24
C479 [email protected]/10V_4 AG7 AK1
IFPD_PLLVDD IFPC_L0 EV_HDMITX2P 24
C472 EV@1u/6.3V_4 AJ1
IFPC_L0_N EV_HDMITX2N 24
C475 [email protected]/10V_4 AJ3
(1.05V +/- 3% ) C469 [email protected]/10V_4 IFPC_L1
AJ2
EV_HDMITX1P 24
IFPC_L1_N EV_HDMITX1N 24
C483 [email protected]/6.3V_6 AH3
IFPC_L2 EV_HDMITX0P 24
IFPC_L2_N AH4 EV_HDMITX0N 24
EV@BLM18PG221SN1D AG5
285 mAAF6

ne
IFPC_L3 EV_HDMICLK+ 24
+1.05V_GFX L29 +IFPCD_IOVDD AG4
IFPC_IOVDD IFPC_L3_N EV_HDMICLK- 24
C476 [email protected]/10V_4
C473 [email protected]/10V_4 AG6 AK3 EV_EDP-AUX+ 23
B C466 EV@1u/6.3V_4 IFPD_IOVDD IFPD_AUX_I2CX_SCL B
IFPD_AUX_I2CX_SDA_N AK2 EV_EDP-AUX- 23
C481 [email protected]/6.3V_6 AM1 EV_EDP-ML0+ 23
IFPD_L0
IFPD_L0_N AM2 EV_EDP-ML0- 23
IFPD_L1 AM3

do
R67 EV@1K/F_4 IFPC_RSET AF8 AM4
IFPC_RSET IFPD_L1_N
IFPD_L2 AL3
R362 EV@1K/F_4 IFPD_RSET AN2 AL4
IFPD_RSET IFPD_L2_N
IFPD_L3 AK4
IFPD_L3_N AK5

R61 EOP@10K/F_4 IFPEF_PLLVDD 220 mAAB8 AB3

In
IFPEF_PLLVDD IFPE_AUX_I2CY_SCL
[IFPE/F_DP] IFPE_AUX_I2CY_SDA_N AB4
IFPE_L0 AD2
IFPEF_IOVDD AC7 AD3
R60 EOP@10K/F_4 IFPE_IOVDD IFPE_L0_N
AC8 IFPF_IOVDD IFPE_L1 AD1
IFPE_L1_N AC1
IFPE_L2 AC2
AD6 IFPEF_RSET IFPE_L2_N AC3
TP162

i-
IFPE_L3 AC4
IFPE_L3_N AC5

IFPF_AUX_I2CZ_SCL AF3
IFPF_AUX_I2CZ_SDA_N AF2
Optimize remove L & C IFPF_L0 AE3
Pull down 10K (P/N:CS31002FB26) IFPF_L0_N AE4
IFPF_L1 AF4

EV@BLM18PG221SN1D
is IFPF_L1_N AF5
AD4
C L26 C464 SP@1u/6.3V_4 IFPF_L2 C
+3V_GFX IFPF_L2_N AD5
C465 [email protected]/6.3V_6 AG1
C127 *[email protected]/10V_4 IFPF_L3
IFPF_L3_N AF1

EV_CRT_RED R79 EV@150/F_4

+DACA_VDD 120 mA AG10 AK9 EV_CRT_RED
kn

DACA_VDD DACA_RED EV_CRT_RED 23

[DACA/B_CRT] AL10 EV_CRT_GRN EV_CRT_GRN 23 EV_CRT_GRN R70 EV@150/F_4
DACA_GREEN EV_CRT_BLU
DACA_BLUE AL9 EV_CRT_BLU 23
C459 [email protected]/10V_4 DACA_VREF AP9 EV_CRT_BLU R75 EV@150/F_4
DACA_VREF
AM9 EV_HSYNC_R R89 EV@33_4 HSYNC_COM 23
R363 EV@124/F_4 DACA_RSET DACA_HSYNC EV_VSYNC_R R84 EV@33_4
AP8 DACA_RSET DACA_VSYNC AN9 VSYNC_COM 23
Te

R4 EV_CRTDCLK EV_CRTDCLK 23
I2CA_SCL EV_CRTDDAT
I2CA_SDA R5 EV_CRTDDAT 23

+1.05V_GFX L32 EOP@160808-30Y NV_PLLVDD AD8 PLLVDD

w.

16,17,20,42 +1.05V_GFX
C488 C138 16,19,20,41,42 +3V_GFX
R395 [email protected]/10V_4
*EOP@0_4 EOP@22u/6.3V_8

SP_PLLVDD AE8 SP_PLLVDD

ww

D D

PLACE CLOSE TO GPU

H3 CLK_27M_VGA_2
L31 EOP@160808-0180P VID_PLLVDD XTAL_IN XTALOUT Y1
+1.05V_GFX AD7 VID_PLLVDD XTAL_OUT H2
[XTAL IN] J4 R379 EOP@10K/F_4 2 1
C484 C147 C136 C137 XTAL_OUTBUFF R386 EOP@10K/F_4
H1

EOP@N13x
XTAL_SSIN EOP@27MHZ
C151
Quanta Computer Inc.
[email protected]/6.3V_6 [email protected]/10V_4 C152 EOP@18P/50V_4
EOP@22u/6.3V_8 [email protected]/10V_4 EOP@18P/50V_4 PROJECT : ZQS 45W
Size Document Number Rev
PLACE CLOSE TO BALLS 3C
DGPU 3/5 (Display)
Date: W ednesday, February 08, 2012 Sheet 18 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U14E +3V_GFX +3V_GFX

16,18,20,41,42 +3V_GFX

[MIOA] R94
EOP_STRAP@20K/F_4 GPIO ASSIGNMENTS
R387 R389 R95
Resistor P/N R96 [email protected]/F_4 [email protected]/F_4 *[email protected]/F_4
*[email protected]/F_4 R82 GPIO I/O PIN USAGE
4.99K---> CS24992FB26 R64 STRAP0 *[email protected]/F_4 R392
ROM_SI EOP_STRAP@10K/F_4 STRAP1 *EOP_STRAP@10K/F_4 GPU_VID4
10K ---> CS31002FB26 ROM_SO STRAP2 0 O GPU CORE_VDD VID4
15K ---> CS31502FB24 ROM_SCLK STRAP3
1 O GPU_VID3 GPU CORE_VDD VID3
STRAP4
20K ---> CS32002FB29 R388 R90
2 O LCD_BL_PWM LCD BACKLIGHT PWM
34.8K---> CS33482FB22 R92 EOP_STRAP@15K/F_4 *EOP_STRAP@15K/F_4
[email protected]/F_4 R390 R91 LCD_VCC
45.3K ---> CS34532FB18 R66 [email protected]/F_4 EOP_STRAP@15K/F_4
3 O PANEL POWER ENABLE

m
EOP_STRAP@10K/F_4 R73 R382 LCD_BLEN
A
[email protected]/F_4 [email protected]/F_4
4 O PANEL BACKLIGHT ENABLE A

C19 5 O GPU_VID1 GPU CORE_VDD VID1

co
(Default: Hynix 2G) C33 R382 change from 30.1 KΩ to pull down GPU_VID2
R73 change from 34.8 KΩ to pull down 45.3KΩ for N13P-GS & GT strap4. 01/04 6 O GPU CORE_VDD VID2
ROM_SI 4.99KΩ for N13P-GS & GT STRAP1. 01/17
Q47 1G Hynix 64Mx16 -->15K PD 7 O 3D VISION 3D VISION LEFT/RIGHT VISION
EOP@DTC144EUA
SYS_SHDN# 3,36,43 Logical Strap Bit Mapping OVERT
dGPU_ACDC# 1 3 R142 0_4
1G Micron 64Mx16 -->20K PD 8 I/O ACTIVE LOW THERMAL OVER TEMP
2G Hynix 128Mx16 -->34.8K PD (B-Die) PU-VDD PD ALERT
R237 0_4
9 I/O ACTIVE LOW THERMAL ALERT
2G Hynix 128Mx16 -->30.1K PD (D-Die)
4.99K 1000 0000 10 O MEM VREF_CLT MEMMORY VREF CONTROL
GPU_TRIP# 34 [MIOB] 2G Micron 128Mx16 -->45.3K PD

a.
10.0K 1001 0001 11 O GPU_VID0 GPU CORE_VDD VID0
2

+3V_GFX 15.0K 1010 0010 12 I PWR_LEVEL Power Detect ,HIGH=AC, LOW=DC

PEGX_RST# 16
C12 Change Q47 from 2N7002 to DTC144EUA, change 20.0K 1011 0011 13 O GPU_VID5 GPU CORE_VDD VID5
Q47.2 from +3V_GFX to PEGX_RST#, connect HPD_AB
GPU_TRPI# to Q47, add 0Ω R142,R237. 12/27 dGPU_ACDC# R374 EOP@10K/F_4 24.9K 1100 0100 14 I HOT PLUG DETECT FOR IFPAB
JTAG_TMS R352 *EOP@10K/F_4 30.1K 1101 0101 15 I HPD_C HOT PLUG DETECT FOR IFPC

si
+3V_GFX JTAG_TDI R357 *EOP@10K/F_4 34.8K 1110 0110 16 O MEM VDD MEMMORY VDD CONTROL
VGA_OVT# R372 EOP@10K/F_4 45.3K 1111 0111 17 I HPD_D HOT PLUG DETECT FOR IFPD
ALERT 18 I HPD_E HOT PLUG DETECT FOR IFPE
R383 EOP@10K/F_4 QCI P/N QCI STN B/S P/N
C707 HPD_F
0.1u/10V_4 JTAG_TCK R59 *EOP@10K/F_4
Hynix 64x16 900/1G P/N: AKD5LZWTW02 / AKD5LZWTW05 19 I HOT PLUG DETECT FOR IFPF
Hynix 128X16 900/2G P/N: AKD5MGWTW00 / AKD5MGWTW03 RESERVE
JTAG_TRST# R349 EOP@10K/F_4 Micron 64X16 900/1G P/N: AKD5EGSTL00 / X 20/21

ne
DGPU_DPST_PWM R87 *EOP@2K/F_4
CRT flicker N13M-GS STRAP 0-3 Define by RVL 128M*16 Hynix DDR3-> 0X6. 11/08
B C03 Add GPU_TRIP# to EC GPIO47, connect to NV GPIO08. 12/23 Logical Logical Logical Logical B
Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0 BOM
TP5 JTAG_TCK AM10 P6 Strap Name GPU Sku
JTAG_TCK GPIO0 GPU_VID4 41
TP62 JTAG_TMS
JTAG_TMS [MISC_GPIO/I2C/JTAG/THER]
AP11 M3 GPU_VID3 41
TP63 JTAG_TDI GPIO1 DGPU_DPST_PWM
AM11
JTAG_TDI GPIO2
L6 DGPU_DPST_PWM 23 XCLK_417/FB[1] FB_0_BAR_SIZE/FB[0] SMB_ALT_ADDR VGA_DEVICE
TP60 JTAG_TDO AP12 P5

do
JTAG_TDO GPIO3 DGPU_DISP_ON 23
TP61 JTAG_TRST# AN11 P7 DGPU_LVDS_BLON 23 N13P-GL 0 0 0 1 Pull down 10K
JTAG_TRST_N GPIO4
L7 GPU_VID1 41
GPIO5
GPIO6
M7 GPU_VID2 41 N13P-GS ES 1 0 0 1 Pull up 10K
+3V_GFX R63 [email protected]_4 N13P_SCL R7 N8 TP65 ROM_SO
R65 [email protected]_4 N13P_SDA I2CB_SCL GPIO7 dGPU_ACDC#
R6
I2CB_SDA GPIO8
M1 N13P-GT ES 1 0 0 1 Pull up 10K
M2 ALERT
GPIO9 TP66
GPIO10
L1 N13M-GS ES 0 1 0 1 Pull down 10K
+3V_GFX R375 [email protected]_4 DGPU_EDIDCLK R2 M5
I2CC_SCL GPIO11 GPU_VID0 41
R376 [email protected]_4 DGPU_EDIDDATA R3 N3 VGA_OVT# PCI_DEVIDE[4] SUB_VENDOR PCI_DEVID[5] PEX_PLL_EN_TERM
I2CC_SDA GPIO12

In
M4 GPU_VID5 41
GPIO13 TP7
GPIO14
N4 N13P-GL 0 0 1 0 Pull down 15K
GFx_SCL T4 P2
I2CS_SCL GPIO15 EV_HDMI_HPD 24
GFx_SDA T3 R8 ROM_SCLK N13P-GS ES 1 0 0 0 Pull up 4.99K
I2CS_SDA GPIO16 GPU_DPRSLPVR 41
M6 EV_eDP_HPD 23
GPIO17 TP68
GPIO18
R1 N13P-GT ES 1 0 0 0 Pull up 4.99K
TP9 THERM+ K4 P3 TP64
TP10 THERM- THERMDN GPIO19 TP8
K3
THERMDP GPIO20
P4 N13M-GS ES 0 0 0 0 Pull down 10K
P1 TP67
GPIO21
RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

i-
23 DGPU_EDIDCLK DGPU_EDIDCLK ROM_SI Hynix X X X X
23 DGPU_EDIDDATA DGPU_EDIDDATA
Samsung X X X X
H4 ROM_SCLK
STRAP0 ROM_SCLK R97 EOP@10K_4
J2
STRAP0 [MISC2_ROM] ROM_CS_N
H6 +3V_GFX N13M-GS ES Pull down 10K
STRAP1 J7 H5 ROM_SI
STRAP2 STRAP1 ROM_SI ROM_SO
J6
STRAP2 ROM_SO
H7 USER[3] USER[2] USER[1] USER[0]
STRAP3 J5
STRAP4 STRAP3
J3
STRAP4 N13P-GL 1 1 1 1 Pull up 45.3K
is STRAP0 N13P-GS ES 1 1 1 1 Pull up 45.3K
C C
R391 [email protected]/F_4 J1 L2 R381 *EOP@10K_4 N13P-GT ES 1 1 1 1 Pull up 45.3K
MULTISTRAP_REF_GND BUFRST_N
N13M-GS ES 1 1 1 1 Pull down 10K
L3 R373 EOP_GL@10K_4 +3V_GFX
CEC
3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
EOP@N13x N13P-GL 0 1 1 1 Pull down 45.3K
kn

STRAP1 N13P-GS ES 0 0 0 0 Pull down 4.99K

VGA_OVT# 1 3 N13P-GT ES 0 0 0 0 Pull down 4.99K
dGPU_OVT# 34
Q24
N13M-GS N13P- GL
N13M-GS ES 0 1 1 0 Pull up 10K
EOP@2N7002
2

N13P-GS N13P- PES PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

+3V_GFX N13P-GL 1 0 0 1 Pull up 10K
Te

Reserve R373 Stuff R373

STRAP2 N13P-GS ES2 1 0 1 1 Pull down 15K
N13M-GS Straping table Pull up 20K
N13P-GT ES 1 0 1 1

Pin Name Strap Mapping Value GFx SMBus Isolation N13M-GS ES 1 0 0 1 Pull up 10K

GFx_SCL 1 3 GPUT_CLK 34 ** N13P-GL

SOR3_EXPOSED
0
SOR2_EXPOSED
0
SOR1_EXPOSED
0
SOR0_EXPOSED
0
Optimus
w.

ROM_SCLK SMB_ALT_ADDR 0 R76 Q4

Pull down 4.99K
[email protected]_4 EOP@2N7002 STRAP3 N13P-GS ES 0 0 0 0 Discrete
2

ROM_SI SUB_VENDOR 0 Pull down 15K

+3V_GFX N13P-GT ES 0 0 0 0
ROM_SO VGA_DEVICE 0 R77 N13M-GS ES 0 0 0 0 Pull down 10K
2

[email protected]_4 Q6
EOP@2N7002 RESERVED PCI SPEED CHANGE GEN3 PCI_MAX SPEED DP_PLL_VDD33
0010(Hynix 64Mx16) GFx_SDA 1 3 GPUT_DATA 34
ww

STRAP[3..0] RAM_CFG[3..0] N13P-GL 0 0 0 1 Pull down 10K

D 0110(Hynix 128Mx16) D
11/8 change for GPU temp detect STRAP4 N13P-GS QS 0 1 1 1 Pull down 45.3K

STRAP[4] PCIE_MAX_SPEED 0 N13P-GT QS 0 1 1 1 Pull down 45.3K

Remark : N13M-GS ES 0 0 0 1
Pull down 10K
0 -> 10K PD
1 -> 10K PU ALERT 1 3 dGPU_ALT# 34
Q21 Quanta Computer Inc.
EOP@2N7002
2

PROJECT : ZQS 45W

+3V_GFX Size Document Number Rev
3C
DGPU 4/5 (MIO/GPIO)
Date: Wednesday, February 08, 2012 Sheet 19 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U14G
50 A A2
AA17
GND_1
[GPU GND]
GND_101
D2
D31
GND_2 GND_102 +VGACORE
AA18 GND_3 GND_103 D33
+VGACORE AA20 E10
GND_4 GND_104
AA22 E22
U14F GND_5 GND_105 C85 EOP@1u/6.3V_4
AB12 GND_6 GND_106 E25
AA12 U1 AB14 E5 C97 [email protected]/10V_4
VDD_001 XVDD_001 GND_7 GND_107 C117 [email protected]/10V_4
AA14
VDD_002 [GPU VDD] XVDD_002
U2 AB16
GND_8 GND_108
E7
PLACE UNDER GPU C111 [email protected]/10V_4
AA16 U3 AB19 F28
VDD_003 XVDD_003 GND_9 GND_109 C128 [email protected]/10V_4
AA19 U4 AB2 F7
VDD_004 XVDD_004 GND_10 GND_110
AA21 U5 AB21 G10

m
VDD_005 XVDD_005 GND_11 GND_111
AA23 U6 A33 G13
A VDD_006 XVDD_006 GND_12 GND_112 C163 [email protected]/10V_4 A
AB13 VDD_007 XVDD_007 U7 AB23 GND_13 GND_113 G16
AB15 U8 AB28 G19 C170 [email protected]/10V_4
VDD_008 XVDD_008 GND_14 GND_114 C166 [email protected]/10V_4
AB17 VDD_009 XVDD_009 V1 AB30 GND_15 GND_115 G2

co
AB18 V2 AB32 G22 C162 [email protected]/10V_4
VDD_010 XVDD_010 GND_16 GND_116
AB20 VDD_011 XVDD_011 V3 AB5 GND_17 GND_117 G25
AB22 VDD_012 XVDD_012 V4 AB7 GND_18 GND_118 G28
AC12 V5 AC13 G3 +VGACORE
VDD_013 XVDD_013 GND_19 GND_119
AC14 VDD_014 XVDD_014 V6 AC15 GND_20 GND_120 G30
AC16 V7 AC17 G32
VDD_015 XVDD_015 GND_21 GND_121
AC19 V8 AC18 G33
VDD_016 XVDD_016 GND_22 GND_122
AC21 W2 AA13 G5
VDD_017 XVDD_017 GND_23 GND_123 C89 C81 C98 C76 C123 C104 C122 C114
AC23 W3 AC20 G7

a.
VDD_018 XVDD_018 GND_24 GND_124
M12 W4 AC22 K2
VDD_019 XVDD_019 GND_25 GND_125
M14 W5 AE2 K28
VDD_020 XVDD_020 GND_26 GND_126 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6
M16 W7 AE28 K30
VDD_021 XVDD_021 GND_27 GND_127 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6
M19 W8 AE30 K32
VDD_022 XVDD_022 GND_28 GND_128
M21 Y1 AE32 K33
VDD_023 XVDD_023 GND_29 GND_129
M23 Y2 AE33 K5
VDD_024 XVDD_024 GND_30 GND_130
N13 VDD_025 XVDD_025 Y3 AE5 GND_31 GND_131 K7
N15 Y4 AE7 M13
VDD_026 XVDD_026 GND_32 GND_132
N17 Y5 AH10 M15

si
VDD_027 XVDD_027 GND_33 GND_133
N18 VDD_028 XVDD_028 Y6 AA15 GND_34 GND_134 M17
N20 Y7 AH13 M18
VDD_029 XVDD_029 GND_35 GND_135
N22 VDD_030 XVDD_030 Y8 AH16 GND_36 GND_136 M20
P12 AA1 AH19 M22 +VGACORE
VDD_031 XVDD_031 GND_37 GND_137
P14 AA2 AH2 N12
VDD_032 XVDD_032 GND_38 GND_138
P16 VDD_033 XVDD_033 AA3 AH22 GND_39 GND_139 N14
P19 AA4 AH24 N16
VDD_034 XVDD_034 GND_40 GND_140
P21 VDD_035 XVDD_035 AA5 AH28 GND_41 GND_141 N19
C79 C77 C93 C99 C106 C112 C124

ne
P23 AA6 AH29 N2
VDD_036 XVDD_036 GND_42 GND_142
R13 AA7 AH30 N21
VDD_037 XVDD_037 GND_43 GND_143
R15 VDD_038 XVDD_038 AA8 AH32 GND_44 GND_144 N23
R17 AH33 N28 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6
VDD_039 GND_45 GND_145 [email protected]/6.3V_6 [email protected]/6.3V_6 [email protected]/6.3V_6
B R18 VDD_040 AH5 GND_46 GND_146 N30 B
R20 AH7 N32
VDD_041 GND_47 GND_147
R22 AJ7 N33
VDD_042 GND_48 GND_148
T12 AK10 N5
VDD_043 GND_49 GND_149
T14 AK7 N7
VDD_044 GND_50 GND_150

do
T16 AL12 P13
VDD_045 GND_51 GND_151
T19 AL14 P15
VDD_046 GND_52 GND_152
T21 AL15 P17
VDD_047 GND_53 GND_153
T23 AL17 P18
VDD_048 GND_54 GND_154
U13 AL18 P20
VDD_049 GND_55 GND_155
U15 AL2 P22
VDD_050 GND_56 GND_156
U17 VDD_051 AL20 GND_57 GND_157 R12
U18 AL21 R14
VDD_052 GND_58 GND_158
U20 AL23 R16
VDD_053 GND_59 GND_159

In
U22 AL24 R19
VDD_054 GND_60 GND_160
V13 AL26 R21
VDD_055 GND_61 GND_161
V15 AL28 R23
V17
VDD_056
VDD_057
AL30
GND_62
GND_63
GND_162
GND_163
T13 PLACE NEAR GPU +VGACORE
V18 AL32 T15
VDD_058 GND_64 GND_164
V20 VDD_059 AL33 GND_65 GND_165 T17
V22 AL5 T18
VDD_060 GND_66 GND_166
W12 AM13 T2
VDD_061 GND_67 GND_167 C94
W14 VDD_062 AM16 GND_68 GND_168 T20

i-
W16 AM19 T22 + C492 C491 C489 C490 C519 C487 C485
VDD_063 GND_69 GND_169
W19 AM22 AG11
VDD_064 GND_70 GND_170 [email protected]/25V_8 [email protected]/25V_8 [email protected]/25V_8 EOP@47u/6.3V_8
W21 AM25 T28
VDD_065 GND_71 GND_171 [email protected]/25V_8 [email protected]/25V_8 EOP@22u/6.3V_8
W23 VDD_066 AN1 GND_72 GND_172 T32
Y13 VDD_067 AN10 GND_73 GND_173 T5
Y15 AN13 T7 EOP@330u/2.5V_3528
VDD_068 GND_74 GND_174
Y18 VDD_069 AN16 GND_75 GND_175 U12
Y17 AN19 U14
VDD_070 GND_76 GND_176
Y20 AN22 U16
Y22
VDD_071
VDD_072
AN25
AN30
GND_77
GND_78
GND_79
is GND_177
GND_178
GND_179
U19
U21 +3V_GFX
C EOP@N13x AN34 U23 C13 Change R393 from reserve to mount. 12/27 C
GND_80 GND_180
AN4 V12
GND_81 GND_181
AN7 GND_82 GND_182 V14
AP2 V16 R393
GND_83 GND_183 +3V [email protected]_4
AP33 V19
GND_84 GND_184
B1 GND_85 GND_185 V21
B10 V23
kn

GND_86 GND_186 C31 Change DGPU_POK4 from +1.05V_GFX to +1.5V_GFX, DGPU_POK2 R384
B22 W13
for meet Power down sequence for +3V_GFX B25
GND_87 GND_187
W15 from +1.5V_GFX to +1.05V_GFX for possibly floating issue. [email protected]_4
DGPU_PWROK 10
GND_88 GND_188 01/17
B28 W17
GND_89 GND_189

3
B31 W18 R394
D9 EOP@RB500V-40 GND_90 GND_190
+VGACORE B34 W20 EOP@100K/F_4
GND_91 GND_191 DGPU_PGOK-1
B4 W22 2
GND_92 GND_192
+3V_GFX B7 GND_93 GND_193 W28
C10 Y12
GND_94 GND_194

3
D10 EOP@RB500V-40 C13 Y14 Q25
Te

+1.5V_GFX

1
GND_95 GND_195 R371 DGPU_POK4 C478 EOP@DTC144EUA
C19 Y16 +1.5V_GFX 2
GND_96 GND_196 [email protected]_4 Q23 EOP@1000P/50V_4
C22 GND_97 GND_197 Y19
C25 Y21 EOP@MMBT3904-7-F

1
GND_98 GND_198 C463
C28 Y23
GND_99 GND_199 *EOP@1000P/50V_4
C7 GND_100 GND_200 AH11

C16
GND_OPT_1

3
R364 DGPU_POK2
w.

W32 +1.05V_GFX 2
GND_OPT_2 [email protected]_4
Q22

1
EOP@N13x C461 EOP@MMBT3904-7-F
+VGACORE *EOP@1000P/50V_4

41 +VGACORE
ww

16,17,18,42 +1.05V_GFX
D D
17,21,22,42,46 +1.5V_GFX
+ + 16,18,19,41,42 +3V_GFX
3,7,8,9,10,11,13,14,16,23,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
C508 C497
EOP@330u/2V_7343 EOP@330u/2V_7343

Quanta Computer Inc.

Power request PROJECT : ZQS 45W
Size Document Number Rev
LSR 3C
DGPU 5/5 (Power/Ground)
Date: Wednesday, February 08, 2012 Sheet 20 of 46
1 2 3 4 5 6 7 8
 5 4 3 2 1

17 VMA_DQ[63..0]
17 VMA_DM[7..0]
17 VMA_WDQS[7..0]
17 VMA_RDQS[7..0] CHANNEL A: 256MB/512MB DDR3
VRAM2 VRAM5 VRAM1 VRAM6

VREFC_VMA1 M8 E3 VMA_DQ12 VREFC_VMA1 M8 E3 VMA_DQ25 VREFC_VMA3 M8 E3 VMA_DQ41 VREFC_VMA3 M8 E3 VMA_DQ58

VREFD_VMA1 VREFCA DQL0 VMA_DQ10 VREFD_VMA1 VREFCA DQL0 VMA_DQ26 VREFD_VMA3 VREFCA DQL0 VMA_DQ44 VREFD_VMA3 VREFCA DQL0 VMA_DQ59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMA_DQ15 F2 VMA_DQ31 F2 VMA_DQ42 F2 VMA_DQ60

m
FBA_CMD9 DQL2 VMA_DQ9 FBA_CMD9 DQL2 VMA_DQ29 FBA_CMD9 DQL2 VMA_DQ45 FBA_CMD9 DQL2 VMA_DQ61
D 17 FBA_CMD9 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 D
FBA_CMD11 P7 H3 VMA_DQ14 FBA_CMD11 P7 H3 VMA_DQ24 FBA_CMD11 P7 H3 VMA_DQ47 FBA_CMD11 P7 H3 VMA_DQ63
17 FBA_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBA_CMD8 P3 H8 VMA_DQ11 FBA_CMD8 P3 H8 VMA_DQ28 FBA_CMD8 P3 H8 VMA_DQ46 FBA_CMD8 P3 H8 VMA_DQ57
17 FBA_CMD8 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
FBA_CMD25 N2 G2 VMA_DQ13 FBA_CMD25 N2 G2 VMA_DQ27 FBA_CMD25 N2 G2 VMA_DQ40 FBA_CMD25 N2 G2 VMA_DQ62

co
17 FBA_CMD25 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
FBA_CMD10 P8 H7 VMA_DQ8 FBA_CMD10 P8 H7 VMA_DQ30 FBA_CMD10 P8 H7 VMA_DQ43 FBA_CMD10 P8 H7 VMA_DQ56
17 FBA_CMD10 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2
17 FBA_CMD24 A5 A5 A5 A5
FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8
17 FBA_CMD22 A6 A6 A6 A6
FBA_CMD7 R2 D7 VMA_DQ5 FBA_CMD7 R2 D7 VMA_DQ19 FBA_CMD7 R2 D7 VMA_DQ34 FBA_CMD7 R2 D7 VMA_DQ54
17 FBA_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
FBA_CMD21 T8 C3 VMA_DQ3 FBA_CMD21 T8 C3 VMA_DQ22 FBA_CMD21 T8 C3 VMA_DQ39 FBA_CMD21 T8 C3 VMA_DQ51
17 FBA_CMD21 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
FBA_CMD6 R3 C8 VMA_DQ6 FBA_CMD6 R3 C8 VMA_DQ17 FBA_CMD6 R3 C8 VMA_DQ32 FBA_CMD6 R3 C8 VMA_DQ55
17 FBA_CMD6 A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2
FBA_CMD29 L7 C2 VMA_DQ0 FBA_CMD29 L7 C2 VMA_DQ23 FBA_CMD29 L7 C2 VMA_DQ38 FBA_CMD29 L7 C2 VMA_DQ48
17 FBA_CMD29 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
FBA_CMD23 R7 A7 VMA_DQ4 FBA_CMD23 R7 A7 VMA_DQ16 FBA_CMD23 R7 A7 VMA_DQ33 FBA_CMD23 R7 A7 VMA_DQ52

a.
17 FBA_CMD23 A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
FBA_CMD28 N7 A2 VMA_DQ2 FBA_CMD28 N7 A2 VMA_DQ21 FBA_CMD28 N7 A2 VMA_DQ37 FBA_CMD28 N7 A2 VMA_DQ50
17 FBA_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
FBA_CMD20 T3 B8 VMA_DQ7 FBA_CMD20 T3 B8 VMA_DQ18 FBA_CMD20 T3 B8 VMA_DQ35 FBA_CMD20 T3 B8 VMA_DQ53
17 FBA_CMD20 A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
FBA_CMD4 T7 A3 VMA_DQ1 FBA_CMD4 T7 A3 VMA_DQ20 FBA_CMD4 T7 A3 VMA_DQ36 FBA_CMD4 T7 A3 VMA_DQ49
17 FBA_CMD4 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7
17 FBA_CMD14 A15 A15 A15 A15

FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

17 FBA_CMD12 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2
FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9

si
17 FBA_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7
17 FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K8 K8
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
17 VMA_CLK0 VMA_CLK0 J7 N9 VMA_CLK0 J7 N9 17 VMA_CLK1 VMA_CLK1 J7 N9 VMA_CLK1 J7 N9
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
17 VMA_CLK0# K7 R1 K7 R1 17 VMA_CLK1# K7 R1 K7 R1
FBA_CMD3 CK VDD#R1 FBA_CMD3 CK VDD#R1 FBA_CMD19 CK VDD#R1 FBA_CMD19 CK VDD#R1 +1.5V_GFX
17 FBA_CMD3 K9 R9 K9 R9 17 FBA_CMD19 K9 R9 K9 R9
CKE VDD#R9 CKE VDD#R9 +1.5V_GFX CKE VDD#R9 CKE VDD#R9

ne
FBA_CMD2 K1 A1 FBA_CMD2 K1 A1 FBA_CMD18 K1 A1 FBA_CMD18 K1 A1
17 FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 17 FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
C FBA_CMD0 L2 A8 FBA_CMD0 L2 A8 FBA_CMD16 L2 A8 FBA_CMD16 L2 A8 C
17 FBA_CMD0 CS VDDQ#A8 CS VDDQ#A8 17 FBA_CMD16 CS VDDQ#A8 CS VDDQ#A8
FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1
17 FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
17 FBA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
17 FBA_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9

do
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_WDQS1 F3 H2 VMA_WDQS3 F3 H2 VMA_WDQS5 F3 H2 VMA_WDQS7 F3 H2
VMA_RDQS1 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
G3 H9 G3 H9 G3 H9 G3 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9

VMA_DM1 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 DML VSS#A9 VMA_DM2 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM6 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1

In
G8 G8 G8 G8
VMA_WDQS0 VSS#G8 VMA_WDQS2 VSS#G8 VMA_WDQS4 VSS#G8 VMA_WDQS6 VSS#G8
C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2
VMA_RDQS0 B7 J8 VMA_RDQS2 B7 J8 VMA_RDQS4 B7 J8 VMA_RDQS6 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1
17 FBA_CMD5 T2 P9 T2 P9 T2 P9 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1

i-
VMA_ZQ1 L8 T9 VMA_ZQ2 L8 T9 VMA_ZQ3 L8 T9 VMA_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
R29 D1 R329 D1 R26 D1 R338 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
EOP@243/F_4 D8 EOP@243/F_4 D8 EOP@243/F_4 D8 EOP@243/F_4 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
B
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
is VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
B

J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3
kn

+1.5V_GFX +1.5V_GFX FBA_CMD17 TP1 +1.5V_GFX +1.5V_GFX

17 FBA_CMD17
FBA_CMD1 TP2
17 FBA_CMD1
VMA_CLK0 R332 R30 R28 R333
For sDDR3
Te

[email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4

R336 VMA_CLK1
160/F_4
For sDDR3
VREFC_VMA1 VREFD_VMA1 R337 VREFC_VMA3 VREFD_VMA3
VMA_CLK0# 160/F_4

Fermi : DDR3 Change to 160 ohm C381 VMA_CLK1# C22 C386

R331 R31 C26 R27 [email protected]/10V_4 R334 [email protected]/10V_4
1 : CS11602FB00 ,RES CHIP 160 1/16W +-1%(0402)
w.

[email protected]/10V_4 [email protected]/10V_4 Fermi : DDR3 Change to 160 ohm

2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) [email protected]/F_4 [email protected]/F_4 [email protected]/F_4 [email protected]/F_4
1 : CS11602FB00 ,RES CHIP 160 1/16W +-1%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)
+1.5V_GFX
A +1.5V_GFX A

Samsung 900MHz 1G AKD5LGHT500

ww

C427 EOP@10u/6.3V_8 C392 EOP@10u/6.3V_8 +1.5V_GFX

17,20,22,42,46 +1.5V_GFX
+1.5V_GFX C20 EOP@1u/10V_4 C397 EOP@10u/6.3V_8 C17 EOP@10u/6.3V_8
C389 EOP@1u/10V_4
+1.5V_GFX C393 EOP@10u/6.3V_8 C429 EOP@1u/10V_4 C391 [email protected]/10V_4 C83 EOP@10u/6.3V_8

C387 EOP@1u/10V_4
C21
C388
EOP@1u/10V_4
EOP@1u/10V_4 C42 EOP@1u/10V_4
C390
C394
[email protected]/10V_4
[email protected]/10V_4
Quanta Computer Inc.
C23 EOP@1u/10V_4 C41 EOP@1u/10V_4 C43 EOP@1u/10V_4 C382 [email protected]/10V_4
C384 EOP@1u/10V_4 C27 EOP@1u/10V_4 C19 EOP@1u/10V_4 C24 [email protected]/10V_4 C380 [email protected]/10V_4 PROJECT : ZQS 45W
C25 EOP@1u/10V_4 C395 EOP@1u/10V_4 C400 EOP@1u/10V_4 C379 [email protected]/10V_4 C88 [email protected]/10V_4 Size Document Number Rev
3C
DGPU Memory 1/2 (DDR3)
Date: Wednesday, February 08, 2012 Sheet 21 of 46
5 4 3 2 1
 5 4 3 2 1

17 VMC_DQ[63..0]
17 VMC_DM[7..0]
17 VMC_WDQS[7..0]
17 VMC_RDQS[7..0] CHANNEL B: 256MB/512MB DDR3
VRAM8 VRAM4 VRAM3 VRAM7

VREFC_VMC1 M8 E3 VMC_DQ4 VREFC_VMC1 M8 E3 VMC_DQ13 VREFC_VMC3 M8 E3 VMC_DQ41 VREFC_VMC3 M8 E3 VMC_DQ34

VREFD_VMC1 VREFCA DQL0 VMC_DQ2 VREFD_VMC1 VREFCA DQL0 VMC_DQ9 VREFD_VMC3 VREFCA DQL0 VMC_DQ44 VREFD_VMC3 VREFCA DQL0 VMC_DQ36
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMC_DQ5 F2 VMC_DQ12 F2 VMC_DQ46 F2 VMC_DQ32

m
FBC_CMD9 DQL2 VMC_DQ0 FBC_CMD9 DQL2 VMC_DQ11 FBC_CMD9 DQL2 VMC_DQ43 FBC_CMD9 DQL2 VMC_DQ39
D 17 FBC_CMD9 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 D
FBC_CMD11 P7 H3 VMC_DQ7 FBC_CMD11 P7 H3 VMC_DQ15 FBC_CMD11 P7 H3 VMC_DQ47 FBC_CMD11 P7 H3 VMC_DQ37
17 FBC_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBC_CMD8 P3 H8 VMC_DQ1 FBC_CMD8 P3 H8 VMC_DQ8 FBC_CMD8 P3 H8 VMC_DQ45 FBC_CMD8 P3 H8 VMC_DQ35
17 FBC_CMD8 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
FBC_CMD25 N2 G2 VMC_DQ6 FBC_CMD25 N2 G2 VMC_DQ14 FBC_CMD25 N2 G2 VMC_DQ40 FBC_CMD25 N2 G2 VMC_DQ38

co
17 FBC_CMD25 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
FBC_CMD10 P8 H7 VMC_DQ3 FBC_CMD10 P8 H7 VMC_DQ10 FBC_CMD10 P8 H7 VMC_DQ42 FBC_CMD10 P8 H7 VMC_DQ33
17 FBC_CMD10 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
FBC_CMD24 P2 FBC_CMD24 P2 FBC_CMD24 P2 FBC_CMD24 P2
17 FBC_CMD24 A5 A5 A5 A5
FBC_CMD22 R8 FBC_CMD22 R8 FBC_CMD22 R8 FBC_CMD22 R8
17 FBC_CMD22 A6 A6 A6 A6
FBC_CMD7 R2 D7 VMC_DQ19 FBC_CMD7 R2 D7 VMC_DQ27 FBC_CMD7 R2 D7 VMC_DQ48 FBC_CMD7 R2 D7 VMC_DQ59
17 FBC_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
FBC_CMD21 T8 C3 VMC_DQ20 FBC_CMD21 T8 C3 VMC_DQ29 FBC_CMD21 T8 C3 VMC_DQ52 FBC_CMD21 T8 C3 VMC_DQ61
17 FBC_CMD21 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
FBC_CMD6 R3 C8 VMC_DQ18 FBC_CMD6 R3 C8 VMC_DQ26 FBC_CMD6 R3 C8 VMC_DQ49 FBC_CMD6 R3 C8 VMC_DQ58
17 FBC_CMD6 A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2
FBC_CMD29 L7 C2 VMC_DQ23 FBC_CMD29 L7 C2 VMC_DQ28 FBC_CMD29 L7 C2 VMC_DQ54 FBC_CMD29 L7 C2 VMC_DQ63
17 FBC_CMD29 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
FBC_CMD23 R7 A7 VMC_DQ16 FBC_CMD23 R7 A7 VMC_DQ24 FBC_CMD23 R7 A7 VMC_DQ50 FBC_CMD23 R7 A7 VMC_DQ57

a.
17 FBC_CMD23 A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
FBC_CMD28 N7 A2 VMC_DQ22 FBC_CMD28 N7 A2 VMC_DQ30 FBC_CMD28 N7 A2 VMC_DQ55 FBC_CMD28 N7 A2 VMC_DQ62
17 FBC_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
FBC_CMD20 T3 B8 VMC_DQ17 FBC_CMD20 T3 B8 VMC_DQ25 FBC_CMD20 T3 B8 VMC_DQ51 FBC_CMD20 T3 B8 VMC_DQ56
17 FBC_CMD20 A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
FBC_CMD4 T7 A3 VMC_DQ21 FBC_CMD4 T7 A3 VMC_DQ31 FBC_CMD4 T7 A3 VMC_DQ53 FBC_CMD4 T7 A3 VMC_DQ60
17 FBC_CMD4 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
FBC_CMD14 M7 FBC_CMD14 M7 FBC_CMD14 M7 FBC_CMD14 M7
17 FBC_CMD14 A15 A15 A15 A15

FBC_CMD12 M2 B2 FBC_CMD12 M2 B2 FBC_CMD12 M2 B2 FBC_CMD12 M2 B2

17 FBC_CMD12 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2
FBC_CMD27 N8 D9 FBC_CMD27 N8 D9 FBC_CMD27 N8 D9 FBC_CMD27 N8 D9

si
17 FBC_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
FBC_CMD26 M3 G7 FBC_CMD26 M3 G7 FBC_CMD26 M3 G7 FBC_CMD26 M3 G7
17 FBC_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K8 K8
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
17 VMC_CLK0 VMC_CLK0 J7 N9 VMC_CLK0 J7 N9 17 VMC_CLK1 VMC_CLK1 J7 N9 VMC_CLK1 J7 N9
VMC_CLK0# CK VDD#N9 VMC_CLK0# CK VDD#N9 VMC_CLK1# CK VDD#N9 VMC_CLK1# CK VDD#N9
17 VMC_CLK0# K7 R1 K7 R1 17 VMC_CLK1# K7 R1 K7 R1
FBC_CMD3 CK VDD#R1 FBC_CMD3 CK VDD#R1 +1.5V_GFX FBC_CMD19 CK VDD#R1 FBC_CMD19 CK VDD#R1 +1.5V_GFX
17 FBC_CMD3 K9 R9 K9 R9 17 FBC_CMD19 K9 R9 K9 R9
CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

ne
FBC_CMD2 K1 A1 FBC_CMD2 K1 A1 FBC_CMD18 K1 A1 FBC_CMD18 K1 A1
17 FBC_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 17 FBC_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
C FBC_CMD0 L2 A8 FBC_CMD0 L2 A8 FBC_CMD16 L2 A8 FBC_CMD16 L2 A8 C
17 FBC_CMD0 CS VDDQ#A8 CS VDDQ#A8 17 FBC_CMD16 CS VDDQ#A8 CS VDDQ#A8
FBC_CMD30 J3 C1 FBC_CMD30 J3 C1 FBC_CMD30 J3 C1 FBC_CMD30 J3 C1
17 FBC_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
FBC_CMD15 K3 C9 FBC_CMD15 K3 C9 FBC_CMD15 K3 C9 FBC_CMD15 K3 C9
17 FBC_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
FBC_CMD13 L3 D2 FBC_CMD13 L3 D2 FBC_CMD13 L3 D2 FBC_CMD13 L3 D2
17 FBC_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9

do
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMC_WDQS0 F3 H2 VMC_WDQS1 F3 H2 VMC_WDQS5 F3 H2 VMC_WDQS4 F3 H2
VMC_RDQS0 DQSL VDDQ#H2 VMC_RDQS1 DQSL VDDQ#H2 VMC_RDQS5 DQSL VDDQ#H2 VMC_RDQS4 DQSL VDDQ#H2
G3 H9 G3 H9 G3 H9 G3 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9

VMC_DM0 E7 A9 VMC_DM1 E7 A9 VMC_DM5 E7 A9 VMC_DM4 E7 A9

VMC_DM2 DML VSS#A9 VMC_DM3 DML VSS#A9 VMC_DM6 DML VSS#A9 VMC_DM7 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1

In
G8 G8 G8 G8
VMC_WDQS2 VSS#G8 VMC_WDQS3 VSS#G8 VMC_WDQS6 VSS#G8 VMC_WDQS7 VSS#G8
C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2
VMC_RDQS2 B7 J8 VMC_RDQS3 B7 J8 VMC_RDQS6 B7 J8 VMC_RDQS7 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1
17 FBC_CMD5 T2 P9 T2 P9 T2 P9 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1

i-
VMC_ZQ1 L8 T9 VMC_ZQ2 L8 T9 VMC_ZQ3 L8 T9 VMC_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
R347 D1 R56 D1 R45 D1 R53 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
EOP@243/F_4 D8 EOP@243/F_4 D8 EOP@243/F_4 D8 EOP@243/F_4 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
B
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
is VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
J1
L1
NC#J1
NC#L1
VSSQ#E8
VSSQ#F9
E8
F9
B

J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3 SP_VRAM@VRAM _DDR3
kn

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMC_CLK0 R345 R68 VMC_CLK1 R47 R342

For sDDR3 [email protected]/F_4 [email protected]/F_4
For sDDR3 [email protected]/F_4 [email protected]/F_4
Te

R350 R340
160/F_4 160/F_4
VREFC_VMC1 VREFD_VMC1 VREFC_VMC3 VREFD_VMC3
VMC_CLK0# VMC_CLK1#

Fermi : DDR3 Change to 160 ohm Fermi : DDR3 Change to 160 ohm C73 C423
R346 C453 R72 C148 R51 [email protected]/10V_4 R343 [email protected]/10V_4
1 : CS11602FB00 ,RES CHIP 160 1/16W +-1%(0402) [email protected]/10V_4 [email protected]/10V_4 1 : CS11602FB00 ,RES CHIP 160 1/16W +-1%(0402)
w.

2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) [email protected]/F_4 [email protected]/F_4 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) [email protected]/F_4 [email protected]/F_4

A +1.5V_GFX A
17,20,21,42,46 +1.5V_GFX
FBC_CMD17 TP3
17 FBC_CMD17
ww

C113 EOP@10u/6.3V_8 +1.5V_GFX +1.5V_GFX

FBC_CMD1 TP4
17 FBC_CMD1
C378 [email protected]/10V_4 C51 EOP@1u/10V_4
C443 EOP@10u/6.3V_8 C458 [email protected]/10V_4 C49 EOP@1u/10V_4
+1.5V_GFX C150 [email protected]/10V_4 C47 EOP@1u/10V_4

C153 EOP@1u/10V_4
C456 EOP@1u/10V_4 C460
C434
[email protected]/10V_4
[email protected]/10V_4
C29
C131
EOP@1u/10V_4
EOP@1u/10V_4
Quanta Computer Inc.
C144 EOP@1u/10V_4 C54 EOP@1u/10V_4 C417 [email protected]/10V_4 C404 EOP@1u/10V_4
C101 EOP@1u/10V_4 C437 EOP@1u/10V_4 C405 [email protected]/10V_4 C462 EOP@1u/10V_4 PROJECT : ZQS 45W
C18 EOP@1u/10V_4 C410 EOP@1u/10V_4 C28 [email protected]/10V_4 C46 EOP@1u/10V_4 Size Document Number Rev
Samsung 900MHz 1G AKD5LGHT500 3C
DGPU Memory 2/2 (DDR3)
Date: Wednesday, February 08, 2012 Sheet 22 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

C531 0.1u/10V_4
CRT F1
D11 SSM22LLPT CRTVDD5

16
2 1
DIS.VGA-->EV@ + EOP@ +5V
CN13
From PCH SMD1206P110TFT/1.1A_1206 CRT
Optimize-->IOP@ + EOP@ 6
R356 IOP@0_4 CRT_RED_COM L14 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 1 11 CRT_11 TP163
UMA-->IV@ + IOP@ 7 INT_CRT_RED
7
R348 IOP@0_4 CRT_GRN_COM L12 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
7 INT_CRT_GRN
Special-->SP@ R351 IOP@0_4 CRT_BLU_COM L10 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1
8
CRTHSYNC
7 INT_CRT_BLU 3 13
9
4 14 CRTVSYNC
R83 IOP@0_4 VSYNC_COM R148 R143 R140 C233 C226 C215 C214 C225 C232 10
7 INT_VSYNC
R88 IOP@0_4 HSYNC_COM 5 15 DDCCLK_1
7 INT_HSYNC
150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
R137 IOP@0_4 CRT_DDCDAT_COM
7 INT_CRT_DDCDAT
R138 IOP@0_4 CRT_DDCCLK_COM
7 INT_CRT_DDCCLK

17

m
A From EXT VGA A
+3V
R78 EV@0_4 CRT_RED_COM
18 EV_CRT_RED
C218 U18
R69 EV@0_4 CRT_GRN_COM CRTVDD5 1 16 CRT_VSYNC2 R428 *SHORT_4 CRTVSYNC C533 0.1u/10V_4 CRTVDD5
18 EV_CRT_GRN

co
0.1u/10V_4 VCC_SYNC SYNC_OUT2 CRT_HSYNC2 R427 *SHORT_4 CRTHSYNC
14
R74 EV@0_4 CRT_BLU_COM SYNC_OUT1 C203 10p/50V_4 CRTVSYNC
18 EV_CRT_BLU 7 VCC_DDC
C537 0.22u/25V_6 CRT_BYP 8
BYP VSYNC_COM CRTVDD5 C210 10p/50V_4 CRTHSYNC
SYNC_IN2 15
VSYNC_COM 2 13 HSYNC_COM +3V
18 VSYNC_COM +3V VCC_VIDEO SYNC_IN1
HSYNC_COM C192 *10p/50V_4 DDCCLK_1
18 HSYNC_COM
C228 R419 R426
R130 EV@0_4 CRT_DDCDAT_COM CRT_R1 3 10 CRT_DDCCLK_COM R422 [email protected]_4 C213 *10p/50V_4 DDCDAT_1
18 EV_CRTDDAT VIDEO_1 DDC_IN1
R131 EV@0_4 CRT_DDCCLK_COM 0.1u/10V_4 CRT_G1 4 11 CRT_DDCDAT_COM R423 [email protected]_4 2.7K_4 2.7K_4
18 EV_CRTDCLK VIDEO_2 DDC_IN2
CRT_B1 5
VIDEO_3 DDCCLK_1
DDC_OUT1 9
6 12 DDCDAT_1

a.
GND DDC_OUT2
CM2009-02QR

LVDS & eDP LCD Power

From PCH From EXT VGA
R86 *0_4 +3V

si
19 DGPU_DPST_PWM
INT_LVDS_EDIDCLK RP22 4 3 IOP@0_4P2R LVDS_EDIDCLK_CON RP21 4 3 EV@0_4P2R
7 INT_LVDS_EDIDCLK DGPU_EDIDCLK 19
INT_LVDS_EDIDDATA 2 1 LVDS_EDIDDATA_CON 2 1 R126 EV@0_4 LVDS_BRIGHT
7 INT_LVDS_EDIDDATA DGPU_EDIDDATA 19 34 CONTRAST
RP1 4 3 IOP@0_4P2R TXLCLKOUT+_CON RP2 4 3 EV@0_4P2R R152 IOP@0_4 C34 U1
7 INT_TXLCLKOUT+ EV_TXLCLK+ 18 7 INT_LVDS_BRIGHT
2 1 TXLCLKOUT-_CON 2 1
7 INT_TXLCLKOUT- EV_TXLCLK- 18
RP5 4 3 IOP@0_4P2R TXLOUT0+_CON RP6 4 3 EV@0_4P2R 1u/6.3V_4 6 1 LCDVCC
7 INT_TXLOUT0+ EV_TXLOUT0+ 18 IN OUT
2 1 TXLOUT0-_CON 2 1
7 INT_TXLOUT0- EV_TXLOUT0- 18
RP3 4 3 IOP@0_4P2R TXLOUT1+_CON RP4 4 3 EV@0_4P2R R33 0_4 4 2 C11 C31 C9 C6 C33
7 INT_TXLOUT1+ EV_TXLOUT1+ 18 IN GND
2 1 TXLOUT1-_CON 2 1
7 INT_TXLOUT1- EV_TXLOUT1- 18 *RFCMF1632100M3T/200mA/90ohm
RP7 4 3 IOP@0_4P2R TXLOUT2+_CON RP8 4 3 EV@0_4P2R R35 IOP@0_4 3 5 *0.1u/10V_4 *2.2u/10V_8 0.1u/10V_4 0.01u/25V_4 22u/6.3V_8
7 INT_TXLOUT2+ EV_TXLOUT2+ 18 7 INT_LVDS_DIGON ON/OFF GND
2 1 TXLOUT2-_CON 2 1 3 3 USBP8+_R
7 INT_TXLOUT2- EV_TXLOUT2- 18 9 USBP8+ 4 4

ne
2 1 USBP8-_R R36 EV@0_4
9 USBP8- 2 1 19 DGPU_DISP_ON
G5243AT11U
L3
R34 0_4 R37
B Enable/Disable LVDS B
Pull Up--->Enable 100K_4
NC-->Disable

+3V R443 [email protected]_4 INT_LVDS_EDIDDATA

do
R442 INT_LVDS_EDIDCLK +3V VIN
[email protected]_4

+1.05V
C10 C13 C32 C30
Lid Switch (Hall sensor)
0.1u/10V_4 4.7u/25V_8 1000p/50V_4
R325 1000p/50V_4
3 INT_eDP_HPD_Q
IOP@1K_4
3

R8 0_4
+3VPCU
L1 C10 Change R328 from 47Ω to 0Ω. 12/27

In
2 R324 SP@0_4 eDP-HPD EDP-ML0+_R 2 1 EDP-ML0+_CON VIN R328 0_6
EDP-ML0-_R 2 1 EDP-ML0-_CON
3 4
Q20 3 4
IV & Optimize-->0 ohm
IOP@2N7002E *DLW21HN900SQ2L/330mA/90ohm C375 0.1u/10V_4
EV-->10K ohm R12 0_4
1

1
R23 R24
R17 0_4 *SHORT_8 *SHORT_8
R320 EV@0_4 2 LID591#
19 EV_eDP_HPD
L2

2
EDP-AUX+_R 2 1 EDP-AUX+_CON HE1
R321 EDP-AUX-_R 2 1 EDP-AUX-_CON APX9132H AI D8
3 4

3
100K_4 3 4 *VPORT_6
EM-6781-T3: AL006781000

i-
*DLW21HN900SQ2L/330mA/90ohm 0.8A INVCC0
R19 0_4
APX9132H AI-TRG: AL009132001

1
CN1 AH9249NTR-G1: AL009249000

G_5

G_6
40
39
From PCH 38 0923
3
3
EDP-ML0+
EDP-ML0-
2
4
1
3
COM_EDP-ML0+
COM_EDP-ML0-
C4
C7
0.1u/10V_4
0.1u/10V_4
EDP-ML0+_R
EDP-ML0-_R
EDP-ML0+_CON
EDP-ML0-_CON
37
36 Backlight Control +3VPCU

RP9 IOP@0_4P2R 35
COM_EDP-AUX+ C12 0.1u/10V_4 EDP-AUX+_R EDP-AUX+_CON 34

C
3
3
EDP-AUX+
EDP-AUX- RP11
2
4
1
3
IOP@0_4P2R
COM_EDP-AUX- C15 0.1u/10V_4 EDP-AUX-_R

TXLCLKOUT+_CON
is EDP-AUX-_CON 33
32
31 G_4
R40
*100K_4 C

TXLCLKOUT-_CON 30 +3V LID591#

29 LID591# 34
TXLOUT0+_CON 28
From EXT VGA 27 LID591#,EC intrnal PU

1
TXLOUT0-_CON
RP10 26
18 EV_EDP-ML0+ 4 3 EV@0_4P2R COM_EDP-ML0+ D1
COM_EDP-ML0- TXLOUT1+_CON 25 R38
18 EV_EDP-ML0- 2 1 BAS316
TXLOUT1-_CON 24
RP12 23
18 EV_EDP-AUX+ 4 3 EV@0_4P2R COM_EDP-AUX+ R7 10K_4

2
22
kn
2 1 COM_EDP-AUX- TXLOUT2+_CON BL_ON
18 EV_EDP-AUX- 21
TXLOUT2-_CON 10K_4
20

3
19

3
LVDS_EDIDDATA_CON
LVDS_EDIDCLK_CON 18
eDP-HPD 17 BL# 2 2 EC_FPBACK# 34
+3V LVDS_BRIGHT R11 16
15

3
BL_ON BLM15AG121SS1/0.5A/120ohm_4 R13 IOP@0_4 Q3 Q2
14 7 INT_LVDS_BLON
C16 C14 +3V 2N7002K DTC144EUA

1
*1u/6.3V_4 *1u/6.3V_4 13

1
LCDVCC 12 R10 EV@0_4
11 19 DGPU_LVDS_BLON 2
10 G_1
Te

R21 R15 CABLE_ID Q1

10 CABLE_ID 9
EV@100K_4 *EV@100K_4 C5 C8 CCD_PWR R18 2N7002K
*1u/6.3V_4 *1u/6.3V_4 8

1
COM_EDP-AUX+ EDP-AUX+_R 7 100K_4
+3V 6
COM_EDP-AUX- EDP-AUX-_R CCD-USB USBP8-_R
USBP8+_R 5
CCD +3V-current budget 0.2A 4
R14 R20 R22 R16 3
27 MIC2_INTL1 2
EV@100K_4 EV@100K_4 *EV@100K_4 EV@100K_4
G_0

1
3,7,8,9,10,11,13,14,16,20,24,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46 +3V
8,11,24,26,27,33,36,43,46 +5V
w.

8,11,25,26,31,33,34,35,36,43,44,46 +3VPCU
ADOGND GS12401-1011-40P-R-NH 3,5,7,8,9,11,34,37,38,42,43,46 +1.05V
35,36,37,38,39,41,42,43,44,45,46 VIN

+3V

eDP_EN# 6
R643
D D
ww

10K_4

2 R644
*0_4
3

+3V Q45
2N7002K
R327 10K_4 CABLE_ID 2
1

R326 *10K_4 Q46

DTC144EUA
1

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
CRT/LVDS/CAMERA/LID
Date: Wednesday, February 08, 2012 Sheet 23 of 46
1 2 3 4 5 6 7 8
 5 4 3 2 1

HDMI
From PCH
2 1 HDMITX2N_CAP C581 0.1u/10V_4 INT_HDMITX2N_C
7 INT_HDMITX2N
7 INT_HDMITX2P RP13
4 3
IOP@0_4P2R
HDMITX2P_CAP C584 0.1u/10V_4 INT_HDMITX2P_C HDMI connector
2 1 HDMITX1N_CAP C571 0.1u/10V_4 INT_HDMITX1N_C CN14
7 INT_HDMITX1N
4 3 HDMITX1P_CAP C573 0.1u/10V_4 INT_HDMITX1P_C 20
7 INT_HDMITX1P RP15 IOP@0_4P2R SHELL1
INT_HDMITX2P_C 1
RP17 D2+
7 INT_HDMITX0N 4 3 IOP@0_4P2R HDMITX0N_CAP C575 0.1u/10V_4 INT_HDMITX0N_C 2
HDMITX0P_CAP C578 0.1u/10V_4 INT_HDMITX0P_C INT_HDMITX2N_C D2 Shield
7 INT_HDMITX0P 2 1 3
D2-

m
INT_HDMITX1P_C 4
HDMICLK+_CAP C569 0.1u/10V_4 INT_HDMICLK+_C D1+
D 7 INT_HDMICLK+ 2 1 5 D
HDMICLK-_CAP C568 0.1u/10V_4 INT_HDMICLK-_C INT_HDMITX1N_C D1 Shield
7 INT_HDMICLK- 4 3 6
RP19 IOP@0_4P2R INT_HDMITX0P_C D1-
7
D0+
8

co
INT_HDMITX0N_C D0 Shield
9
R483 R486 R492 R491 R489 R487 R496 R494 INT_HDMICLK+_C D0-
EV@499/F_4 10
CK+
SP@510_4 SP@510_4 SP@510_4 SP@510_4 11
P/N: CS14992FB24 SP@510_4 SP@510_4 SP@510_4 SP@510_4 INT_HDMICLK-_C 12
CK Shield
CK-
UMA/Optimize-->590 Ohm +5V
13
CE Remote
F2 14
P/N: CS15902FB00 SMD1206P110TFT/1.1A_1206 HDMI_DDCCLK_MB 15
NC

3
D13 HDMI_DDCDATA_MB DDC CLK
16
DDC DATA

a.
2 1 HDMI_5V_R SSM22LLPT 17
Q41 HDMI_5V GND
18
DIS.VGA-->EV@ + EOP@ +5V R498 *0_4 2 Discrete stuff 499 Ohm 19
+5V
HP DET
C557 HDMI_MB_HP R186 *SHORT_4 HP_DET_CN 21
Optimize-->IOP@ + EOP@ +3V
R624 0_4 UMA/Optimize-->510 Ohm 470p/50V_4 SHELL2
2N7002E HDMI CONN
UMA-->IV@ + IOP@ R497 R182

1
EOP@100K/F_4
Special-->SP@ C02 Change R483,R486,R492,R491,R498,R487,R496,R494 100K_4

si
from 590Ω to 510Ω, and mount HDMI
R194,R205,R202,R212 120Ω at optimus sku for EMI.
12/21

From EXT VGA

ne
RP14 4 3 EV@0_4P2R HDMITX2N_CAP
18 EV_HDMITX2N
2 1 HDMITX2P_CAP
18 EV_HDMITX2P
RP16 4 3 EV@0_4P2R HDMITX1N_CAP
C 18 EV_HDMITX1N C
2 1 HDMITX1P_CAP +3V
18 EV_HDMITX1P
+3V
2 1 HDMITX0N_CAP
18 EV_HDMITX0N
18 EV_HDMITX0P RP18
4 3
EV@0_4P2R
HDMITX0P_CAP HDMI-detect R196

do
2 1 HDMICLK-_CAP R180 10K_4
18 EV_HDMICLK-
4 3 HDMICLK+_CAP 10K_4
18 EV_HDMICLK+ RP20 EV@0_4P2R R197 IOP@0_4
HDMI_HP 7

3
R484 EV@0_4
34 HDMI_HPD_EC# EV_HDMI_HPD 19
2

In

3
+5V R191 *10K_4 Q10
2N7002E

1
HDMI_MB_HP 2

Q9
2N7002E

i-

1
I2C
+3V +5V

2
R459 D14

+3V
is *SHORT_4 RB501V-40

1
B B

R468 Q38 R461

EMI
2

[email protected]_4 BSN20 2.2K_4

From EXT VGA 1 3 HDMI_DDCCLK_MB
kn

INT_HDMITX2P_C
R404 EV@0_4 HDMI_DDCCLK_COM
18 EV_HDMI_DDCCK_C
R212 120/F_4
R405 EV@0_4 HDMI_DDCDATA_COM
18 EV_HDMI_DDCDAT_C +3V INT_HDMITX2N_C
+5V
INT_HDMITX1P_C
2

R478 R202 120/F_4

Te

*SHORT_4 D15
RB501V-40 INT_HDMITX1N_C
+3V
INT_HDMITX0P_C
From PCH
1

Q39 R205 120/F_4

R455 IOP@0_4 HDMI_DDCCLK_COM R473 R474
7 HDMI_DDCCLK_SW
2

[email protected]_4 BSN20 2.2K_4 INT_HDMITX0N_C

w.

R457 IOP@0_4 HDMI_DDCDATA_COM 1 3 HDMI_DDCDATA_MB INT_HDMICLK+_C

7 HDMI_DDCDATA_SW
R194 120/F_4

INT_HDMICLK-_C
ww

A A
C02 Change R483,R486,R492,R491,R498,R487,R496,R494
from 590Ω to 510Ω, and mount HDMI
R194,R205,R202,R212 120Ω at optimus sku for EMI.
12/21

Quanta Computer Inc.

3,7,8,9,10,11,13,14,16,20,23,25,26,27,29,33,34,36,37,38,39,40,41,42,43,45,46
8,11,23,26,27,33,36,43,46
+3V
+5V
PROJECT : ZQS 45W
Size Document Number Rev
3C
HDMI (PS8101)
Date: Wednesday, February 08, 2012 Sheet 24 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

Check LED signal. (active high or low)

MINI-CARD WLAN(MPC) C37 Add Q50 connect to BT_POWERON# for WLAN ON/OFF function,
+3.3V: 1000mA pull up BT_PWRON by 10KΩ R671 to +WL_VDD, reserve 10KΩ
+WL_VDD +3V R672 to +3V. 01/31 +3V +WL_VDD
+3.3Vaux:330mA
R316 *0_8 +WL_VDD
+1.5V:500mA 31,34 BT_POWERON#
R671 R672

2
10K_4 *10K_4
Q50 C366 C659 C657 C654
DTC144EUA 10u/6.3V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4

1 3 BT_PWRON R637 *SHORT_4 CN20 C32 Add net WLAN_OFF to connect EC(GPIO66/G_PWM) to CN20.46
Debug 51 52 C07 ( LED_WPAN#) for IOAC feature, mount 0Ω R670. 01/18

m
TP125 Reserved +3.3V +WL_VDD
A CL_RST1#_WLAN 49 50 A
PLTRST# R314 0_4 CL_DATA1_WLAN Reserved GND C24 Change mini pcie power source from +3V_S5 to +3VPCU. 01/12
47 Reserved +1.5V 48 +1.5V_WLAN
R315 0_4 CL_CLK1_WLAN 45 46 WLAN_OFF_R R670 0_4
9 CLK_LPC_DEBUG Reserved LED_WPAN# WLAN_OFF 34
43 44 Q48 AO3413
GND LED_WLAN# LED_WLAN# 33

co
C26 Mount R314, R315. 01/12 +WL_VDD 41 42
+3.3Vaux LED_WWAN# C36 Remove R308 reserved 10KΩ for LED_WLAN# pull high +3V. 01/31
39 +3.3Vaux GND 40 +3VPCU 1 3
37 GND USB_D+ 38 USBP10+ 9
35 GND USB_D- 36 USBP10- 9
9 PCIE_TX8+ 33 34

2
PETp0 GND WL_CLK_SDATA R664 *0_4 C25 C708 R661
9 PCIE_TX8- 31 32
PETn0 SMB_DATA WL_CLK_SCLK R663 *0_4 SMB_PCH_DAT 9 0.33u/10V_6 47K/F_4
29 30
GND SMB_CLK SMB_PCH_CLK 9
27 28 +1.5V_WLAN
GND +1.5V C07 C25 Change CN20 pin 30 &28 from CLK_SDATA & CLK_SCLK to
25 26

a.
9 PCIE_RX8+ PERp0 GND SMB_PCH_CLK & SMB_PCH_DAT, reserve 0Ω R663,R664. 1/12
9 PCIE_RX8- 23 24 +WL_VDD
PERn0 +3.3Vaux PLTRST# R662
21 22 PLTRST# 9,16,29,34 34 IOAC_LANPWR#
GND PERST# 4.7K_4
19 20 RF_EN 34
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND C08 Connect EC GPIO46 IOAC_LANPWR# to WLAN, R662, add C708, R661, Q48, reserve R316. 12/23
A_LFRAME#_R R582 *SHORT_4
Debug
15 16 LPC_LFRAME# 8,34
R305 *SHORT_4 CLK_PCH_WIFI GND UIM_VPP A_LAD3_R R581 *SHORT_4
9 CLK_PCH_SRC5 13 REFCLK+ UIM_RESET 14 LPC_LAD3 8,34
R306 *SHORT_4 CLK_PCH_WIFI# 11 12 A_LAD2_R R578 *SHORT_4
9 CLK_PCH_SRC5# REFCLK- UIM_CLK LPC_LAD2 8,34
9 10 A_LAD1_R R577 *SHORT_4

si
GND UIM_DATA LPC_LAD1 8,34
3 1 PCIE_CLKREQ5#_R 7 8 A_LAD0_R R576 *SHORT_4
9 PCIE_CLKREQ5# CLKREQ# UIM_PWR LPC_LAD0 8,34
5 6 +1.5V_WLAN
DTC144EUA Reserved +1.5V +1.5V
3 4

GND

GND
Q49 Reserved GND C07
1 2 +WL_VDD
WAKE# +3.3V
MINI-CARD1
2

53

54
C27 Add Q49 connect PCIE_CLKREQ5# to CN20.7. 01/12 +1.5V_WLAN R608 *0_6

ne
+WL_VDD
C655 C658 C355
*1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
B B
2

Q42
DTC144EUA

do
3 1 PCIE_WAKE#_R
34 WAKE_WLAN
C07 Add R608 and reserve +1.5V to WLAN. 12/23

C06 Change PCH_GPIO27 to WAKE_WLAN, connect to Q42 & EC GPIO96, Q42 change from reserve to mount. 12/23

In
SSD-MINI module +3V_SATA

R309 *SHORT_8 +3V

C635 C633 C360

0.1u/10V_4 0.1u/10V_4 10u/10V_8

i-
+3V_SATA

C C

CN7
is
51 52
LED_OUT Reserved +3.3V
TP59 49 50
Reserved GND
47 Reserved +1.5V 48
45 46
Reserved LED_WPAN#
43 44
GND LED_WLAN#
41 +3.3Vaux LED_WWAN# 42
39 40
kn

+3.3Vaux GND
37 GND USB_D+ 38 USBP3+ 9
35 36 USBP3- 9
C362 0.01u/16V_4 SATA_TXP_SSD_R GND USB_D-
8 SATA_TXP_SSD 33 34
C361 0.01u/16V_4 SATA_TXN_SSD_R PETp0 GND
8 SATA_TXN_SSD 31 PETn0 SMB_DATA 32
29 30
GND SMB_CLK
27 28
C359 0.01u/16V_4 SATA_RXN_SSD_R GND +1.5V
8 SATA_RXN_SSD 25 PERp0 GND 26
C358 0.01u/16V_4 SATA_RXP_SSD_R 23 24
8 SATA_RXP_SSD PERn0 +3.3Vaux
21 22
Te

GND PERST#
19 20
UIM_C4 W_DISABLE#
17 UIM_C8 GND 18

15 16
GND UIM_VPP
13 REFCLK+ UIM_RESET 14
11 12
REFCLK- UIM_CLK
9 10
GND UIM_DATA
7 8
CLKREQ# UIM_PWR
w.

5 6
Reserved +1.5V
3 4
GND

GND

Reserved GND
1 2
WAKE# +3.3V
MINI-CARD1
53

54

D D
ww

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
MINI PCI-E / SSD
Date: Wednesday, February 08, 2012 Sheet 25 of 46
1 2 3 4 5 6 7 8
 1 2 3 4

MAIN SATA HDD(HDD) G Sensor

+3V
CN15

1 R302
1
2 SATA_TXP0_C C572 0.01u/25V_4 SATA_TXP0 8 GS@0_8
3 SATA_TXN0_C C576 0.01u/25V_4 U8

m
A SATA_TXN0 8 A
4 +VDD_3 1 4
SATA_RXN0 C582 0.01u/25V_4 VDD_IO SCL/SPC CLK_SCLK 9,13,14,33
5 SATA_RXN0_C 8
6 SATA_RXP0 C585 0.01u/25V_4 8 6

co
SATA_RXP0_C 8 CS SDA/SDI/SDO CLK_SDATA 9,13,14,33
7
8 +VDD_3 15 9 TP164
ADC2 INT2
9
10 C356 C348 14 11
VDD INT1 G_SENSOR_INT#_PCH 9
11
12 +5V_HDD [email protected]/10V_4 GS@10u/6.3V_8 13 16

a.
ADC3 ADC1
13
14 12 GND RES 10
15
16 5 7 R307 GS@0_4
GND SDO/SA0
17
18 2 NC NC 3

si
19 19
GS@LIS3DHTR

SATA HDD
B B

ne
R523 *SHORT_8 +5V_HDD
+5V G-Sensor -->GS@
C593 C599 C603 C596 C601 C602
+
*100u/6.3V_3528 10u/6.3V_6 *0.1u/16V_4 *0.1u/16V_4 0.01u/25V_4 0.01u/25V_4

do
+5V +5V_ODD

In
ODD (ODD) Zero Power (ODD) Q27
ZP@AO6402A
6
5 4
Zero Power -->ZP@ 2

i-
+3VPCU 1
CN11 No Zero Power -->NZP@ R403
C 14 ZP@22_8 C

3
GND14 R399 ZP@100K
+15V
1 R402
GND1

3
2 SATA_TXP5_C C211 0.01u/25V_4 SATA_TXP5 8 ZP@100K
RXP
RXN 3 SATA_TXN5_C C212 0.01u/25V_4 SATA_TXN5 8
is Zero Power Ra Reserve,
GND2 4
TXN 5 SATA_RXN5 C202 0.01u/25V_4
SATA_RXN5_C 8 No Zero Power Ra stuff ODD_POWER_R 2 2 ODD_POWER_R

1
6 SATA_RXP5 C198 0.01u/25V_4
TXP SATA_RXP5_C 8

3
7 +5V Q31 C493 Q30
GND3 +5V_ODD ZP@DMN601K-7 *[email protected]/50V_6 ZP@DMN601K-7

2
kn

1
SATA_DP R122 *1K_4
DP 8
9 R397
Ra NZP@0_8
34 EC_ODD_EN 2
+5V Q29
+5V 10
C161 C160 C494 C495 C496 C486 ZP@DMN601K-7
+

RSVD 11
12 R415

1
GND
Te

13 0.01u/25V_4 0.01u/25V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528 *ZP@100K

GND

GND15 15

C18534-11305-L
EC_ODD_EJ 34
D D
w.

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
SATA-HDD/ODD/G Sensor
Date: Wednesday, February 08, 2012 Sheet 26 of 46
1 2 3 4
 5 4 3 2 1

Codec(ADO)
Mute(ADO) +3V +5VA

reverse R441 R603 R616

R595 *0_4
HP 28 HP-L ADOGND
MIC1-VREFO-L
*10K_4 10K_4
28 HP-R R596 0_4
MIC1-VREFO-L 28
PD# *BAS316 D22 EAPD#
MIC1-VREFO-R 28
D D
MIC2-VREFO BAS316 D23 AMP_MUTE#

m
ADOGND
R600 *0_4 MIC1-VREFO-L
BAS316 D26 PCH_AZ_CODEC_RST#
C683 10u/6.3V_6 ADOGND
C675

co
+
2.2u/6.3V_6
Place next to pin 27
C689 C686
C672 ADOGND 2.2u/6.3V_6 0.1u/10V_4 +5VA
+5VA +
Place next to pin 25
2.2u/6.3V_6
C653 C652

a.
10u/6.3V_6 0.1u/10V_4 C691 C692

36

35

34

33

32

31

30

29

28

27

26

25
Place next to pin 38 U26
0.1u/10V_4 10u/6.3V_6

CBP

CPVEE

HP-OUT-L

MIC1-VREFO-L

MIC2-VREFO

LDO-CAP

AVSS1

AVDD1
CBN

HP-OUT-R

MIC1-VREFO-R

VREF
ADOGND
ADOGND
+5V_S5
37 24 ADOGND
AVSS2 LINE1-R TP165
ANALOG
Spilt by AGND 38 23 TP166 U25
AVDD2 LINE1-L

5
1

si
34 AMP_MUTE#
+5V R571 *SHORT_6 +5VPVDD1 39 22 4 R569 *SHORT_4 HP_MUTE# 28
PVDD1 MIC1-R MIC1-R 28
EAPD# 2
C632 C640 C648 C650 28 L_SPK+ L_SPK+ 40 21 MIC1-L 28
MIC TC7SH08FU C634

3
SPK-L+ MIC1-L *4.7u/10V_6
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 28 L_SPK- L_SPK- 41 20
C SPK-L- MONO-OUT C

R612 20K/F_4
42 PVSS1 (Vista Premium Version) JDREF 19 ADOGND
43 PVSS2 Sense-B 18

ne
28 R_SPK- R_SPK- 44 17 MIC2_INT_R C694 1u/16V_6 MIC2_INT_R_C R619 1K_4 MIC2_INTL1
SPK-R- MIC2-R
28 R_SPK+ R_SPK+ 45 16 MIC2_INT_L C693 1u/16V_6 MIC2_INT_L_C R618 1K_4
SPK-R+ MIC2-L MIC2_INT_R_C
+5V R570 *SHORT_6 +5VPVDD2 46 15
PVDD2 LINE2-R MIC2_INT_L_C

GPIO0/DMIC-DATA
C631 C639 C647 C649 EAPD# 47

GPIO1/DMIC-CLK
SPDIFO2/EAPD LINE2-L 14
C696 C697
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 48 13 SENSEA R610 20K/F_4 SENSEA_MIC

SDATA-OUT
SPDIFO Sense A *1000p/50V_4 *1000p/50V_4 SENSEA_MIC

SDATA-IN

DVDD-IO

do
PCBEEP
+5VA

RESET#
BIT-CLK
49 R611 39.2K/F_4SENSEA_HP
DVDD1

DVSS2
PGND

SYNC
ANALOG
PD#
Place next to pin 46 R638

3
Spilt by DGND ALC271X-VB6-GR ADOGND ADOGND 47K/F_4
1

10

11

12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion vendor suggest reserved for layout issue with noise
2 MIC1_JD
MIC1_JD 28
1.6Vrms
+3V R587 *SHORT_6 Q43

In
PCBEEP C687 1u/16V_6 BEEP_1 R601 47K/F_4 D24 BAS316 2N7002K
SPKR 8

1
C671 C670 C688 R602
0.1u/10V_4 10u/6.3V_6 4.7K_4 D25 BAS316
PCBEEP_EC 34
100p/50V_4 ADOGND

C684 *100p/50V_4
B SENSEA_HP B
Place next to pin 1 +5VA
PCH_AZ_CODEC_RST# 8
PCH_AZ_CODEC_SYNC 8

i-
+3V R639

3
47K/F_4
PD# C682 C681
0V : Power down Class D SPK amplifer
3.3V : Power up Class D SPK amplifer 0.1u/10V_4 10u/6.3V_6 2 HPOUT_JD
HPOUT_JD 28
Place next to pin 9 Q44
2N7002K
ACZ_SDIN0_R R598 22_4
PCH_AZ_CODEC_SDIN0 8

1
C677 *22p/50V_4
is ADOGND
PCH_AZ_CODEC_BITCLK 8

PCH_AZ_CODEC_SDOUT 8

Power (ADO) INT MIC array

MIC2_INTL1 23
kn

R599
MIC2_INTL1 MIC2-VREFO
R620 *SHORT_4
DIGITAL ANALOG C376 C680 2.2K_4
R555 *SHORT_4
+5V +5VA R288 *SHORT_4 *22p/50V_4 *22p/50V_4 1/7 by FAE's recommend
R604 *SHORT_4
A A
R299 *SHORT_4
Te

L41 UPB201209T-310Y-N/6A/31ohm_8 C638 *1000p/50V_4

C702 *1000p/50V_4 ADOGND ADOGND

ADOGND
C701 0.1u/10V_4

Tied at one point only under Quanta Computer Inc.

the codec or near the codec
PROJECT : ZQS 45W
w.

ADOGND
Size Document Number Rev
cap place close to MIC-connector 3C
REALTEK ALC271X-VB6-GR
Date: Wednesday, February 08, 2012 Sheet 27 of 46
5 4 3 2 1
ww
 5 4 3 2 1

MIC 27 MIC1-VREFO-R

27 MIC1-VREFO-L
Internal Speaker
Normal close Jack
R304 R300
4.7K/F_4 4.7K/F_4
CN18
1 CN17

m
D C347 4.7u/6.3V_6 MIC1_L2 R303 1K/F_4 MIC1_L3 L22 MIC1_L R591 0_6 L_SPK+_1 D
27 MIC1-L 2 27 L_SPK+ 1
BLM15AG121SS1/0.5A/120ohm_4 6 27 L_SPK- R590 0_6 L_SPK-_1
C346 4.7u/6.3V_6 MIC1_R2 R301 1K/F_4 MIC1_R3 L19 MIC1_R R589 0_6 R_SPK-_1 2
27 MIC1-R 3 27 R_SPK- 3
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 5 R588 0_6 R_SPK+_1

co
27 R_SPK+ 4
27 MIC1_JD MIC1_JD 4
50273-0047N-001
LINE-IN-SP6 C664 C665 C663 C662
C343 C350
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4
*0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6

a.
MIC1_JD ADOGND

1
ADOGND
D4

*VPORT_6

si
ADOGND

C C

ne
HP Change to Normal Close circuit 11/1

do
27 HP_MUTE# HP_MUTE# CN21
1
2

HP-L-2 R313 47/F_4 HPL-1 L24 BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS 2

HP-R-2 R310 47/F_4 HPR-1 L23 BLM15AG121SS1/0.5A/120ohm_4 HPR_SYS 6
27 HP-L 3 1 HP-L-2 3
HPOUT_JD

In
5
Q19 R311 R312 C354 C365 27 HPOUT_JD 4
*FDV301N
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 LINE-IN-SP6
R648 0_4
ADOGND

ADOGND

i-
HP_MUTE#
B HPOUT_JD B
2

1
27 HP-R 3 1 HP-R-2
D5
Q18
*FDV301N
is *VPORT_6

2
R649 0_4
ADOGND
kn
Te

A A
w.

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
AUDIO JACK CONN
Date: Wednesday, February 08, 2012 Sheet 28 of 46
5 4 3 2 1
 5 4 3 2 1

LAN/Card reader Transformer

(1.5A) 60 mils +3V_S5 R594 *SHORT_6 VDD33 40 mils R319 75/F_8 TXCT0
R3 75/F_8 TXCT1 L25
X'tal 25MHz R597 *SHORT_6 50 mils R4 75/F_8 TXCT2 24 TXCT0
VDDREG MCT0
LAN_XTALI R6 75/F_8 TXCT3 1
TCT0 RJ45-TX0+
TX0+ 23
R567 MDI0+ 2 TD0+

2
1M/F_4 SP16 SP15 22 RJ45-TX0-
SP14 R5 MDI0- TX0-
Y4 VDD33 3
LAN_XTAL2 LAN_XTALI SP13 SG@1M_8 C3 TD0- TXCT1
2 1 MCT1 21
LAN_XTAL2 VDD33/18 D7 220p/3KV_1808 4

m
C629 C636 SG@B88069X9231T203 TCT1 RJ45-TX1+
25MHz VDD10 VDD10 20
D R562 2.49K/F_4 LED0/SPICSB MDI1+ TX1+ D
5

1
27P/50_4 27P/50_4 GPO_NC R647 *10K_4 TD1+ RJ45-TX1-
VDD33 TX1- 19
LED1/SPICLK/EESK MDI1- 6 TD1-

co
18 TXCT2
GND_LAN MCT2
7
TCT2 RJ45-TX2+

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TX2+ 17
U23 C373 *6.8P/50V_4 MDI3+ MDI2+ 8
C374 *6.8P/50V_4 MDI3- TD2+ RJ45-TX2-
65 16

GPO
AVDD33
AVDD33

AVDD10
CKXTAL2
CKXTAL1
AVDD33
XD_CD#
MS_D0/xD_D1
MS_D4/xD_D0

VDD33/18
DVDD10
RSET

SD_CD#/MS_D5/xD_ALE

LED0/SPICSB

LED1/SPISCK
GND C371 *6.8P/50V_4 MDI2+ MDI2- TX2-
Power source mode: 9 TD2-
C372 *6.8P/50V_4 MDI2- 15 TXCT3
Pin45 :Pull-up VDD33 for SWR mode C369 *6.8P/50V_4 MDI1+ 10
MCT3
MDI1- TCT3 RJ45-TX3+
Pull-down for LDO mde

a.
C370 *6.8P/50V_4 14
C367 *6.8P/50V_4 MDI0+ C2 MDI3+ TX3+
11 TD3+
C368 *6.8P/50V_4 MDI0- 0.01u/25V_4 13 RJ45-TX3-
MDI3- TX3-
(1.5A) 70 mils 12
TD3-
Reserver for EMI
MDI0+ 1 48 REGOUT LFE9276C-R
MDI0- MDIP0 REGOUT +3V
2 47 VDDREG
MDIN0 VDDREG
VDD10 3 AVDD10 VDDREG 46
MDI1+ 4 45 ENSWREG R586 *SHORT_4 VDD33

si
MDI1- MDIP1 ENSWREG_H SDA/SPIDI
5 44
MDI2+
MDI2-
6
7
MDIN1
MIDP2
MDIN2
SDA/SPIDI
LED3/SPIDO
SCL/LED_CR
43
42
LED3/SPIDO/EEDO_NC
SCL/LED_CR_NC
TP123
TP124 R593 RJ45
VDD10 8 41 VDD10 1K_4 CN8
MDI3+ AVDD10 DVDD10 PCIE_WAKE# LED0/SPICSB
9 40 9
MDI3- 10
MDIP3 RTL8411 LANWAKEB
39 VDD33 +3V_S5 R318 220_8 ACT_LED_PWR 10
YELLOW_N
MDIN3 DVDD33 ISOLATEB YELLOW_P
VDD33 11 38
AVDD33 ISOLATEB
12 37 14
DVDD33 PERSTB GND2

ne
CARD_3V3 13 36 CLK_PCIE_LAN_REQ# RJ45-TX0+ 1 13
SP1 Card_3V3 CLKREQB SP12 R592 RJ45-TX0- 0+ GND1
14 SD_D7/xD_RDY SD_WP/MS_D1/xD_WP# 35 2 0-
SP2 15 34 SP11 RJ45-TX1+ 3 GND_LAN
SP3 SD_D6/MS_INS#/xD_RE# MS_BS/xD_CLE VDD33/18 15K/F_4 RJ45-TX2+ 1+
16 33 4

SD_CMD/MS_D6/xD_D3
SD_D1/MS_CLK/xD_D6

SD_CLK/MS_D3/xD_D4
C SD_D5/xD_CE# VDD33/18 RJ45-TX2- 2+ C
SD_D0/MS_D7/xD_D5

SD_D3/MS_D2/xD_D2
5 2-
RJ45-TX1- 6
RJ45-TX3+ 1-
7
SD_D4/xD_WE#

RJ45-TX3- 3+
8
SD_D2/xD_D7
3-

do
REFCLK_N
REFCLK_P

EVDD10
LED1/SPICLK/EESK11
GREEN_N

HSON
HSOP
R9 220_8 LNK_LED_PWR
HSIN
12
HSIP
GND

GND
+3V_S5 GREEN_P
9,16,25,34 PLTRST#
RJ45
CARD_3V3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
30,46 CARD_3V3
R323 *SHORT_6

In
SP1 SP4
30 SP1 SP2 SP5 R317 *SHORT_6
30 SP2 SP3 SP6 HSON_ C661 0.1u/10V_4
30 SP3 PCIE_RX3- 9
SP4 SP7 HSOP_ C660 0.1u/10V_4
30 SP4 PCIE_RX3+ 9
SP5 SP8 R322 *SHORT_6
30 SP5 EVDD10
SP6 SP9
30 SP6 SP7 SP10 CLK_PCIE_LOM# 9
30 SP7 SP8 CLK_PCIE_LOM 9
30 SP8 PCIE_TX3- 9
SP9 GND_LAN

i-
30 SP9 SP10 PCIE_TX3+ 9
30 SP10
SP11
30 SP11 SP12
30 SP12 SP13
30 SP13
SP14
30 SP14
SP15
30
30
SP15
SP16
SP16
SURGE SG@-------> Lan Surge

9 CLK_PCIE_LAN_REQ#
CLK_PCIE_LAN_REQ#
is
B B

PCIE_WAKE# U11 U10

7 PCIE_WAKE#
MDI1- 1 8 RJ45-TX1- 1 8
MDI1+ 1 8 RJ45-TX1+ 1 8
2 7 2 7
MDI0- 2 7 RJ45-TX0- 2 7
3 6 3 6
3 6 3 6
kn
MDI0+ 4 5 RJ45-TX0+ 4 5
4 5 4 5
[email protected] [email protected]

20 mils C23 Change L40 footprint from L2x1_6-1 to RC0805. 01/09

VDD33 VDD33/18
20 mils
Power-on Strapping
VDD33/18
Te

VDD10
U13 U12
SDA/SPIDI R585 1.5K/F_4 C678 C656
*4.7u/6.3V_6 0.1u/10V_4 REGOUT L40 C642 C641 MDI3- 1 8 RJ45-TX3- 1 8
PCIE_WAKE# R584 *10K_4 2.2uH/1A *4.7u/6.3V_6 0.1u/10V_4 MDI3+ 1 8 RJ45-TX3+ 1 8
(1.5A) 60 mils MDI2-
2
2 7
7
RJ45-TX2-
2
2 7
7
C669 C673 3 6 3 6
CLK_PCIE_LAN_REQ# R583 *10K_4 4.7u/6.3V_6 MDI2+ 3 6 RJ45-TX2+ 3 6
0.1u/10V_4 4 5 4 5
4 5 4 5
LED1/SPICLK/EESK R575 10K_4 [email protected] [email protected]
w.

Close to Chip Place close to pin 33

Place Close pins-- 48 Place close to pin 53

VDDREG EVDD10
VDD33 40 mils VDD10 30 mils
40 mils (1.5A) 60 mils
ww

A R574 7,8,9,10,11,15,16,31,33,36,37,38,43,44 +3V_S5 A

*SHORT_6
C616 C609 C666 C637 C619 C621 C674 C668 C667 C643 C627 C617 C618 C645
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 C644 0.1u/10V_4
1u/6.3V_4 Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
3C
LAN-RTL8411/CARD READER
Place Close to LAN chip, for VDD33 pins-- 11, 12, 39, 58, 63, 64 Place connect to Pin46/47 Place Close to LAN chip, for VDD33 pins-- 3, 8, 41, 52, 61 Close to Pin29 Date: Wednesday, February 08, 2012 Sheet 29 of 46

5 4 3 2 1
 A B C D E

CARD READER CONNECTOR XD,MMC 4.2/SD,MS/MSP

7 IN1 CARD READER
Share Pin
SP1 SD_D7 xD_RDY
SP2 SD_D6 MS_INS# xD_RE#
SP3 SD_D5 xD_CE# CN5

m
SP4 SD_D4 xD_WE#
4 CARD_3V3 4
SP5 SD_D1 MS_CLK xD_D6 13 SD-VCC
SP6 SD_D0 MS_D7 xD_D5 SP13=SD_CD#=MS_D5=XD_ALE 1 SD-CD-SW

co
SP7 SD_CLK MS_D3 xD_D4 SP12=SD_WP=MS_D1=XD_WP# 2 45 CARD_3V3
SP5=SD_D1=MS_CLK=XD_D6 SD-WP-SW XD-VCC
SP8 SD_CMD MS_D6 xD_D3 3 SD-DAT1
SP9 SD_D3 MS_D2 xD_D2 SP6=SD_D0=MS_D7=XD_D5 4
SP7=SD_CLK=MS_D3=XD_D4 SD-DAT0 SP16=XD_CD#
SP10 SD_D2 xD_D7 10 SD-CLK XD-CD 28
SP11 MS_BS xD_CLE SP8=SD_CMD=MS_D6=XD_D3 19 29 SP1=SD_D7=XD_RDY
SP9=SD_D3=MS_D2=XD_D2 SD-CMD XD-R/B SP2=SD_D6=MS_INS#=XD_RE#
SP12 SD_WP MS_D1 xD_WP# 23 SD-DATA3 XD-RE 30
SP13 SD_CD# MS_D5 xD_ALE SP10=SD_D2=XD_D7 25 31 SP3=SD_D5=XD_CE#
SP1=SD_D7=XD_RDY SD-DAT2 XD-CE SP11=MS_BS=XD_CLE
SP14 MS_D4 xD_D0 5 32

a.
SP2=SD_D6=MS_INS#=XD_RE# MMC-DATA7 XD-CLE SP13=SD_CD#=MS_D5=XD_ALE
SP15 MS_D0 xD_D1 8 MMC-DATA6 XD-ALE 33
SP16 xD_CD# SP3=SD_D5=XD_CE# 17 34 SP4=SD_D4=XD_WE#
SP4=SD_D4=XD_WE# MMC-DATA5 XD-WE SP12=SD_WP=MS_D1=XD_WP#
21 MMC-DATA4 XD-WP 35

7 SD-GND1
15 37 SP14=MS_D4=XD_D0
SD-GND2 XD-D0 SP15=MS_D0=XD_D1
26 38

si
SD-WP-GND XD-D1 SP9=SD_D3=MS_D2=XD_D2
27 SD-CD-GND XD-D2 39
40 SP8=SD_CMD=MS_D6=XD_D3
CARD_3V3 XD-D3 SP7=SD_CLK=MS_D3=XD_D4
22 MS-VCC XD-D4 41
SP11=MS_BS=XD_CLE 9 42 SP6=SD_D0=MS_D7=XD_D5
CARD_3V3 SP12=SD_WP=MS_D1=XD_WP# MS-BS XD-D5 SP5=SD_D1=MS_CLK=XD_D6
29,46 CARD_3V3 11 MS-DATA1 XD-D6 43
SP15=MS_D0=XD_D1 12 44 SP10=SD_D2=XD_D7
SP9=SD_D3=MS_D2=XD_D2 MS-DATA0 XD-D7
14 MS-DATA2

ne
R524 *SHORT_4 SP1=SD_D7=XD_RDY SP2=SD_D6=MS_INS#=XD_RE# 16
29 SP1 R520 *SHORT_4 SP2=SD_D6=MS_INS#=XD_RE# SP7=SD_CLK=MS_D3=XD_D4 MS-INS
29 SP2 18 MS-DATA3
R519 *SHORT_4 SP3=SD_D5=XD_CE# SP5=SD_D1=MS_CLK=XD_D6 20 36
29 SP3 R518 *SHORT_4 SP4=SD_D4=XD_WE# MS-SCLK XD-GND1
3 29 SP4 XD-GND2 46 3
6 MS-GND1
R526 *SHORT_4 SP5=SD_D1=MS_CLK=XD_D6 24
29 SP5 R525 *SHORT_4 SP6=SD_D0=MS_D7=XD_D5 MS-GND2
29 SP6

do
R511 *SHORT_4 SP7=SD_CLK=MS_D3=xD_D4
29 SP7 R514 *SHORT_4 SP8=SD_CMD=MS_D6=xD_D3 CM7S-102
29 SP8

R515 *SHORT_4 SP9=SD_D3=MS_D2=XD_D2 1 : DFHS44FR014

29 SP9 R517 *SHORT_4 SP10=SD_D2=XD_D7
29 SP10 R521 *SHORT_4 SP11=MS_BS=XD_CLE 2 : DFHS44FR018
29 SP11 R527 *SHORT_4 SP12=SD_WP=MS_D1=XD_WP#

In
29 SP12
R553 *SHORT_4 SP13=SD_CD#=MS_D5=XD_ALE
29 SP13 R622 *SHORT_4 SP14=MS_D4=XD_D0
29 SP14 R522 *SHORT_4 SP15=MS_D0=XD_D1
29 SP15 R621 *SHORT_4 SP16=XD_CD#
29 SP16

i-
SP7=SD_CLK=MS_D3=xD_D4 40 mils
SP5=SD_D1=MS_CLK=XD_D6 CARD_3V3
is
2 C620 2
C605 C604 4.7u/6.3V_6
*4.7p/50V_4 *4.7p/50V_4
kn

Place close to connector

Vendor recommend for EMI pin 14 or 23 or33
Te

40 mils

CARD_3V3
w.

C615 C703 C613

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
ww

1 1

Place close to connector Vendor recommend

pin 13/22/45
Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
3C
CARD READER CONNECTOR
Date: Wednesday, February 08, 2012 Sheet 30 of 46
A B C D E
 5 4 3 2 1

USB3.0/2.0 Blutooth Q40 AO3413

BLUETOOTH CONNECTOR for BT3.0
CN4
+3V_S5 1 3 BT_POWER 5 5
4 4
C267 USBP4+_R 3
+ C262 1000p/50V_4 USBP4-_R 3
USB 3.0 Connector 2 7

2
C706 R653 BT_LED 2 7
2.2u/6.3V_6 TP167 1 1 6 6
CN16 0.33u/10V_6 47K/F_4
USB3.0 CONN CON5_BT_L
USBPWR1 1 1 VBUS

m
D USB_CH2-_R USBP2-_R D
2 1 2 2 D-
USB_CH2+_R 4 3 USBP2+_R 3 R654
L18 0_4P2R 3 D+ 25,34 BT_POWERON#
4 4.7K_4
USB30_RX3-_R 4 GND
5 2 1

co
5 SSRX- 9 USBP4+
USB30_RX3+_R 6 4 3
6 SSRX+ 9 USBP4- L17 0_4P2R
7 7
USB30_TX3-_R 8 GND
USB30_TX3+_R 8 SSTX-
9 9 SSTX+

13
12
11
10
USB30_RX3+ 1 2 USB30_RX3+_R
USB30_RX3- 3 4 USB30_RX3-_R +5V_S5

a.
USB/B

13
12
11
10
RP24 U9
USB3@0_4P2R 2 8 +5V_S5_USBP0
IN1 OUT3
3 IN2 OUT2 7
C353 C351 C352

+
OUT1 6
4 EN#
34 USBON# 470P/50V_4 .1u/10V_4
1 GND
[email protected]/10V_4 USB2.0 connector P/N: 5

si
USB30_TX3+ C594 USB30_TX3+_C USB30_TX3+_R C364 OC# 100U/6.3V_3216
1 2
USB30_TX3- C595 USB30_TX3-_C 3 4 USB30_TX3-_R DFHS04FR487 1u/6.3V_4 G547E2P81U
RP25
[email protected]/10V_4 USB3@0_4P2R
C09 Change USB power Cap C306,C352 from 100U_3528 to 100U_3216. 12/23
9 USB_OC4#
C C
CN6

ne
+5V_S5_USBP0 1 13
1 13
2 2 14 14
3 3
+5VPCU 4
USBP2-_R RV2 1 USBP1+_R 4
2 *EGA_4 9 USBP1+ 2 1 5 5
C327 1u/6.3V_4 4 3 USBP1-_R USBP1+_R 6
9 USBP1- L21 0_4P2R 6
USBP2+_R RV3 1 2 *EGA_4 USBP1-_R

do
7 7
U5 8
USBPWR1 USB30_RX3-_R RV7 1 USBP9+_R 8
2 IN1 OUT3 8 2 *EGA_4 9 9
3 7 USBP9-_R 10
IN2 OUT2 C306 C324 USB30_RX3+_RRV6 1 10
OUT1 6 2 *EGA_4 11 11
USB_BC_EN 4 + 12
EN 1000p/50V_4 12
1 GND USB30_TX3-_R RV5 1 2 *EGA_4 88511-120N

In
OC# 5
100U/6.3V_3216 2 1 USBP9+_R
9 USBP9+
G547E1P81U USB30_TX3+_R RV4 1 2 *EGA_4 4 3 USBP9-_R
9 USBP9- L20 0_4P2R
9 USB_OC1#
C09 Change USB power Cap C306,C352 from 100U_3528 to 100U_3216. 12/23

i-
B B
CEN:SLG55584A----pull up +3VPCU
CB SELCDP Funcion
USB Charger DCP autodetect with mouse/keyboard wakeup
SLG55584----pull low
R241 CH@47K_4 C328 *[email protected]/10V_4
0 X
is

5
1 0 S0 charging with SDP only
BC_CEN 2
1 1 S0 charging with CDP or SDP only (depending on external device) 4 USB_BC_EN
USB_BC_ON 1
34 USB_BC_ON
U6

3
R247 CH@0_4 CH@TC7SH08FU
kn

USB_CHARGE_ON 34
U7
USBP2- BC_CEN 1 8 R246 *CH@0_4 MAINON 34,38,39,42,43
9 USBP2- CEN CB1
USBP2+ USB_CH2-_R 2 7 USBP2-
9 USBP2+ DM TDM
USB_CH2+_R 3 6 USBP2+ USB_BC_ON R245 USB_BC_EN
USB30_RX3+ DP TDP C331 [email protected]/10V_4
9 USB30_RX3+ 4 SELCDP VDD 5
USB30_RX3- 9 NCH@0_4
9 USB30_RX3- Thermal Pad
Te

USB30_TX3+ CH@SLG55584A
9 USB30_TX3+
USB30_TX3- USB Charger -->CH@
9 USB30_TX3-
R252 CH@10K_4 +5VPCU None Charger--> NCH@
A A

For BA
w.

USB 3.0 Ra, Rb Stuff

Ra USB_CH2-_R R506 NCH@0_4 USBP2-
Rb USB_CH2+_R R509 NCH@0_4 USBP2+ Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
USB/ BT/CHARGER
Date: Wednesday, February 08, 2012 Sheet 31 of 46
5 4 3 2 1
 5 4 3 2 1

Hole

GPU NUT FAN NUT

HOLE7 HOLE14 HOLE2 HOLE1 PCH NUT MINI PCIE
*HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *H-C315D110P2
7 6 7 6 7 6 HOLE17 HOLE3 HOLE16 HOLE22 HOLE21 HOLE9 HOLE4
D
MINI 8 5 8 5 8 5 H-C256D161PT H-TC256BC315D161P2 *H-C236D165P2 H-C224D123P2 H-C236D65PT *H-TC433BC315D110P2 *O-ZQS-1
D

m
9 4 9 4 9 4
CARD
NUT

1
2
3

1
2
3

1
2
3

1
co
HOLE10
H-C217D106PT
HOLE12 HOLE5 HOLE11 HOLE6
*HG-C315D110P2 *h-c315i150d110p2 *ZQS-HOLE2 *HG-C315D110P2 HOLE15 HOLE19 HOLE20 HOLE8
7 6 7 6 7 6 H-C256D161PT *H-C236D165P2 H-C224D123P2 *ZQS-HOLE1
8 5 8 5 8 5
9 4 9 4 9 4
1

a.
1
2
3

1
2
3

1
2
3

1
HOLE13 HOLE18
*HG-C315D110P2 *H-C236D165P2
7 6 C18 Change hole15, hole17 footprint to H-C256D161PT to h-c256d142pt. 12/30
8 5

si
9 4
1
2
3

1
C C

ne
do
In
B B

i-
is
kn
Te

A A

Quanta Computer Inc.

w.

PROJECT : ZQS 45W

Size Document Number Rev
3C
Hole
Date: Wednesday, February 08, 2012 Sheet 32 of 46
5 4 3 2 1
ww
 5 4 3 2 1

K/B CN2 CPU FAN

MY0 1
34 MY0
MY1 2
34 MY1
MY2 3 +3V
34 MY2
MY3 4
34 MY3
MY4 5
34 MY4
MY5 6
34 MY5
MY6 7 R43
34 MY6
MY7 8
34 MY7

m
D MY8 9 +5V 10K_4 D
34 MY8
MY9 10
34 MY9
MY10 11
34 MY10
MY11 12

co
34 MY11

2
MY12 13 C56
34 MY12 34 FANSIG
MY13 14 2.2u/6.3V_6
34 MY13
MY14 15 U2 CN9
34 MY14

1
MY15 16 2 3 TH_FAN_POWER
34 MY15 VIN VO 1
MY16 17 5
34 MY16 GND 2
MY17 18 1 6
34 MY17 9,10 SML1ALERT# /FON GND 3

2
MX7 19 7 C53 C57 C50

a.
34 MX7 GND
MX6 20 4 8 FAN_CONN.
34 MX6 34 CPUFAN#_DAC VSET GND
MX5 21 2.2u/6.3V_6 *0.01u/25V_4 53398-0310-3P-L
34 MX5

1
MX4 22 G991P11U 0.01u/25V_4 DFHD03MR026
34 MX4
MX3 23
34 MX3
MX2
34 MX2
MX1
24
25
27
28
FANPWR = 1.6*VSET
34 MX1
MX0 26

si
+3VPCU 34 MX0
KB CONN

RP23 10K_10P8R
10 1 MX3
MX4 9 2 MX2
C +3V C
MX5 8 3 MX1

ne
MX6
MX7
7 4 MX0 TOUCHPAD & Switch CONN. +5V L6 0_6
6 5 +3V
+5V
50mil
R651 0_4 L9 *0_6 +TPVDD
R652 *0_4 By Model
C157

do
TP/B
+3V_S5 R125 R127 0.1u/10V_4 +TPVDD 1
LED Power 10K_4 10K_4
TPDATA_R
2
LED4 3
PWRLED# R613 430_4 2 3 L7 0_6 TPCLK_R TPCLK_R 4
34 PWRLED# 34 TPCLK
L8 0_6 TPDATA_R 5
34 TPDATA
R614 261/F_4

In
34 SUSLED# 1 6
C159 C158 RIGHT# 7
LED_AMBER/BLUE *0.01u/25V_4 *0.01u/25V_4 8
9,10 BOARD_ID4
R655 1M_4 9
10 BOARD_ID3
R117 *0_4 10 13
9,13,14,26 CLK_SDATA R116 *0_4 11 14
Power Botton Blue 9,13,14,26 CLK_SCLK LEFT# 12
+3V_S5

i-
CN3
B PWRLED# R1 110/F_4 LED1 1 2 B
BEBL0089Z00
LTST-C190TBKT/BLUE
Model EA/EG/BA---->SW5,SW6
R656 1M_4 VA/VG--------->SW2,SW3
+3VPCU SW6 SW5
is RIGHT# 3 2 LEFT# 3 2
R657 1M_4 1 4 1 4
Battery
LED5 SWITCH_1.5 SWITCH_1.5

5
R607 430_4 2 3
34 BATLED0#
R606 261/F_4 SW4 SW3
kn

34 BATLED1# 1
RIGHT# 3 2 LEFT# 3 2
LED_AMBER/BLUE 1 4 1 4
R658 1M_4
SWITCH_1.5 SWITCH_1.5

5
+3V
HDD
Te

LED2
R605 330/F_4 1 3
8 SATA_ACT# C04 Change SW1,SW2 footprint & PN from DHP00DA1J01 to DHP00532W00. 12/23
HDD_LED
A R659 1M_4
For BA WLAN function A
w.

SW1

WLAN
Orange +3V 34 WL_SW#
WL_SW# 3
1
2
4 Quanta Computer Inc.

1
LED3
R615 523/F_4 1 3 RV1 SWITCH_1.5
25 LED_WLAN# PROJECT : ZQS 45W

5
WLAN_LED 2 BA@EGA-0402 Size Document Number Rev
ww

R660 1M_4 3C
KB/FAN/TP+FP/LED
Date: Wednesday, February 08, 2012 Sheet 33 of 46
5 4 3 2 1
 5 4 3 2 1

EC(KBC) L11 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
Power on button
C229 C227
30mil
0.1u/10V_4 10u/6.3V_6
C21 Reserve 0Ω R645 connect to DPWROK, add new net DPWROK_EC. 01/05 +3VPCU
+3VPCU E775AGND
R134 2.2_6 D12 C238 C237 DPWROK *0_4 R645
1 2 +3VPCU_EC 0.03A(30mils) DPWROK_EC 7
RB500V-40 4.7u/6.3V_6 0.1u/10V_4 R2
C220 C165 C199 C538 C518 C171 10K_4

115

102
19
46
76
88

4
4.7u/6.3V_6 0.1u/10V_4 *0.1u/16V_4 0.1u/10V_4 *0.1u/16V_4 0.1u/10V_4 U16
SW2

AVCC

VDD
VCC1
VCC2
VCC3
VCC4
VCC5

m
E775AGND C219 10u/6.3V_8 ICM C06 Connect to Q42 & EC GPIO91, Q42 change from reserve NBSWON# 3 2
D CLK_PCI_775 to mount. 12/23 D
1 4

1
C221 0.01u/25V_4
3 97 C1 D6 SWITCH_1.5
8,25 LPC_LFRAME# TEMP_MBAT 35

5
LFRAME GPIO90/AD0

co
126 98 WAKE_WLAN 0.1u/10V_4 *VPORT_6
8,25 LPC_LAD0 LAD0 GPIO91/AD1 WAKE_WLANC05 25
R145 127 A/D 99 WAKE_SRC_2 TP168
8,25 LPC_LAD1 LAD1 GPIO92/AD2
128 100 ICM
8,25 LPC_LAD2 ICM 35

2
*22_4 LAD2 GPIO93/AD3
8,25 LPC_LAD3 1 LAD3
9 CLK_PCI_775 2 LCLK
101 DRAMRST_GATE TP169
GPIO94/DA0
C224
7 CLKRUN# 8 GPIO11/CLKRUN D/A GPI95/DA1 105
WK_GPIO27
CPUFAN#_DAC 33 C04 Change SW1,SW2 footprint & PN from DHP00DA1J01 to DHP00532W00. 12/23
106 WK_GPIO27 10
GPI96/DA2
*10p/50V_4 10 SIO_A20GATE 121 GPIO85/GA20

a.
C28 Change EC GPI96 from WAKE_WLAN to WK_GPIO27, connect to PCH_GPIO27. 01/12
10 SIO_RCIN# 122 KBRST/GPIO86
64
10 SIO_EXT_SCI# 29
ECSCI/GPIO54 LPC
GPIO01/TB2
GPIO02
79 SUSACK# TP171
ACIN 35
C05 Change WL_SW# from EC GPIO91 to EC GPIO04. 12/23
SM BUS PU(KBC) +3VPCU
95 NBSWON#
GPIO03 WL_SW# MBCLK R124 10K_4
23 EC_FPBACK# 6 96 WL_SW# 33
GPIO24/LDRQ GPIO04 SUSWARN# MBDATA R123 10K_4
108 TP172
GPIO05
27 AMP_MUTE# 124 93 LID591# 23
GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1 M_PON_R R640 SBA@0_4 Connect EC_PWROK_R to EC GPIO30, GPUT_CLK R183 10K_4
94 M_PON 44
GPIO07 C17 reserve 0Ω R635 for SBA. 12/29

si
PLTRST# 7 114 SLP_A#_R R136 SBA@0_4 GPUT_DATA R169 10K_4
9,16,25,29 PLTRST# LREST GPIO16 SLP_A# 7
109 DPWROK *SBA@0_4 R635 EC_PWROK_R 7,44
GPIO30
123 15
25 RF_EN GPIO67/PWUREQ GPIO36/CTS1
GPIO41 80
dGPU_OVT# 19
VRON 37
SBA 2ND_MBCLK R408 10K_4
125 17 HWPG 2ND_MBDATA R413 10K_4
8 IRQ_SERIRQ SERIRQ GPIO42/SCL3B/TCK
20 dGPU_ALT#_R R128 *SHORT_4
GPIO43/SDA3B/TMS dGPU_ALT# 19
10 SIO_EXT_SMI# 9 21 SUSB# 7
GPIO65/SMI GPIO44/TDI GPU_TRIP# C03 Add GPU_TRIP# to EC GPIO47, connect
GPIO GPO47/SCL4
24 GPU_TRIP# 19 to NV GPIO08. 12/23
25 D/C# 35
GPIO50/PSCLK3/TDO

ne
54 26 S5_ON
33 MX0 KBSIN0 GPIO51 S5_ON 36,43
33 MX1 55 KBSIN1 GPIO52/PSDAT3/RDY 27 HDMI_HPD_EC# 24
56 28 GPU_PWR_ALERT#
33 MX2 KBSIN2 GPIO53/SDA4 GPU_PWR_ALERT# C01 41 Add GPU_PWR_ALERT# to EC GPIO53,
C 33 MX3 57 KBSIN3 GPIO70 73 SUSC# 7 C
58 74 connect to PU5.10. 12/21
33 MX4 KBSIN4 GPIO71 PWROK_EC 7
33 MX5 59 75 PCH_RSMRST# 7 H_PROCHOT# 3,37
KBSIN5 GPIO72
33 MX6 60 KBSIN6 GPIO75/SPI_SCK 82 MAINON 31,38,39,42,43

3
61 83 3G_ON TP177
33 MX7 KBSIN7 GPO76/SHBM
84 Q36
GPIO77 EC_ODD_EJ 26

do
33 MY0 53 91 DNBSWON# 7
KBSOUT0/JENK GPIO81 Do_not_ use_it PROCHOT_EC
33 MY1 52 110 TP178 2
KBSOUT1/TCK GPO82/IOX_LDSH/TEST
33 MY2 51 112 USBON# 31
KBSOUT2/TMS GPO84/IOX_SCLK/XORTR
33 MY3 50 107 USB_CHARGE_ON 31
KBSOUT3/TDI GPIO97 R139 2N7002K
33 MY4 49 KBSOUT4/JEN0 KB
33 MY5 48

1
KBSOUT5/TDO SLPSUS# 100K_4
33 MY6 47 31 TP179
KBSOUT6/RDY GPIO56/TA1
33 MY7 43 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO 117 SUSON 39
33 MY8 42 63 FANSIG 33
KBSOUT8 GPIO14/TB1

In
33 MY9 41
KBSOUT9/SDP_VIS
33 MY10 40
KBSOUT10/P80_CLK TIMER GPIO15/A_PWM
32 CONTRAST 23
33 MY11 39 118 PCBEEP_EC 27
KBSOUT11/P80_DAT GPIO21/B_PWM
33 MY12 38 62 PWRLED# 33
KBSOUT12/GPIO64 GPIO13/C_PWM
33 MY13 37 65 BATLED0# 33
KBSOUT13/GPIO63 GPIO32/D_PWM CPUFAN#
33 MY14 36 22 TP180
KBSOUT14/GPIO62 GPIO45/E_PWM SUSLED#
33 MY15 35 16 SUSLED# 33
KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1 WLAN_OFF
33 MY16 34 81 WLAN_OFF 25
GPIO60/KBSOUT16 GPIO66/G_PWM
33 MY17 33 66 BATLED1# 33
GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1

i-
C32 Add net WLAN_OFF to connect EC(GPIO66/G_PWM) to CN20.46
MBCLK 70 ( LED_WPAN#) for IOAC feature, reserve 0Ω. 01/18
35 MBCLK GPIO17/SCL1
MBDATA 69
35 MBDATA GPIO22/SDA1
9 2ND_MBCLK 2ND_MBCLK 67 SMB 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR USB_BC_ON 31
9 2ND_MBDATA 2ND_MBDATA 68 14
GPIO74/SDA2 GPIO34/SIN1/CIRRXL p75V_ON 39
GPUT_CLK 119 IR 23 IOAC_LANPWR#
19 GPUT_CLK GPIO23/SCL3 GPIO46/CIRRXM/TRST IOAC_LANPWR# 25
GPUT_DATA 120 111 PROCHOT_EC
19 GPUT_DATA GPIO31/SDA3 GPO83/SOUT_CR/TRIST

B 33 TPCLK 72
71
GPIO37/PSCLK1
is F_SDI/F_SDIO1 86
87
C08 Connect EC GPIO46 IOAC_LANPWR# to WLAN, R662, add C708, R661, Q48. 12/23
PCH_SPI_SO 8 B
33 TPDATA GPIO35/PSDAT1 F_SDO/F_SDIO0 PCH_SPI_SI 8
Reserve for writing ME ROM 8 ME_WR 10
GPIO26/PSCLK2 PS/2 FIU F_CS0
90 SPI_CS0#_UR_ME 8
25,31 BT_POWERON# 11 92 PCH_SPI_CLK 8
GPIO27PSDAT2 F_SCK
77 30 ECDB_CLOCK TP183
26 EC_ODD_EN GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO +3V
VCC_POR
85 VCC_POR# R133 47K/F_4 +3VPCU HWPG(KBC)
kn
R135 *SHORT_4 +1.05V_VTT_EC 12
VCORF

+1.05V VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6

3 EC_PECI R132 43_4 EC_PECR_R 13 104 +A3VPCU R565

PECI VREF

VTT - the power supply for the PECI signal WPCE885 10K_4
5
18
45
78
89
116

103

VCORF_uR 44

PECI - the PECI 3.0 data bus, bidirectional signal. D16 BAS316 HWPG
SM BUS ARRANGEMENT TABLE 40 HWPG_VCCSA
DG0.9 and chklist 0.9 apply one series 43ohm near EC side D21 BAS316
43 HWPG_1.8V
SM Bus 1 Battery
Te

L13 PBY160808T-250Y-N/3A/25ohm_6 D17 *BAS316

38,40 HWPG_VTT
C173 SM Bus 2 PCH D18 BAS316
39 HWPG_VDDR
1u/6.3V_4 D19 BAS316
pin14 +VCC_GFX pin13 GFX_PWRGD 36 SYS_HWPG
E775AGND SM Bus 3 VGA
pin22 +3V_D for ATI pin21 dGPU_VRON
pin24 +1V for ATI pin23 +VGPU_CORE
pin26 +1.8V_GPU for ATI pin25 +1.5V_GPU SM Bus 4 HDMI
w.

pin28 GPU_RST# pin27 dGPU_PWROK

Power sequence
NBSWON# TP193 S5_ON TP186
DNBSWON# TP192 PCH_RSMRST# TP187
A SUSON TP195 SUSC# TP189 A
ww

SUSB# TP194
MAINON +3VPCU
TP188
PWROK_EC TP197 VRON TP191
PLTRST# TP196 HWPG TP190 S5_ON R406 10K_4

M_PON R650 SBA@10K_4

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
WPCE885 & FLASH
Date: Wednesday, February 08, 2012 Sheet 34 of 46
5 4 3 2 1
 5 4 3 2 1

PR6
VA1 PD2 VA2 PQ1 0.01/F_0612 PQ38
PJ1 PL1 SBR1045SP5-13 AOL1413 VIN AOL1413
POWER_JACK FBMA-11-201209-800A50T 1 1 1
1 VA 3 VA2 2 5 1 2 2 5
2 2 3 3
3 PR22

1
4 short0402
PC7 PC83 PR179 24707_ACN PC1 PC2

4
0.1u/50V_6 0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_6 PR20
PL2 PD1 33K/F_4
FBMA-11-201209-800A50T SMAJ20A 24707_ACP

2
D D

m
PC6 PC5 PR23
0.1u/50V_6 2200p/50V_6 1 6 short0402
PD3
1N4148WS PR183 2 5 PR19

co
D/C# 34
220K_4 10K_4
recommend 200mA at least. 3 4 PR21

3
short0402
PQ4
IMD2AT108
2

PQ3

a.
24707_ACP 2N7002K

1
VA2 24707_ACN

PC20 PC19 PC18

0.1u/50V_6 0.1u/50V_6 0.1u/50V_6

si
PR187 PR186 PR31
*0_6 short0603 63.4K/F_4
VIN

1
PR32 PC17

ACP

ACN
10K/F_4 1u/16V_6
C
+3VPCU +3VPCU 24707_ACDET 6 16 24707_REGN C
ACDET REGN

ne
PD4 PC81 PC9 PC3 PC4
24707_VCC 20 RB500V-40 PC84 PC85 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206
PR191 PR190 VCC PR18 2200p/50V_6 4.7u/25V_8
100K_4 100K_4 PR184 PC15 short0603
20_1206 0.47u/25V_6
BTST 17 24707_BST

5
34 ACIN
PC16

do
3

47n/50V_6 For EMI

PQ36
18 24707_DH 4 MDV1528URH
HIDRV
2 5 ACOK#
PQ6 19 24707_LX

3
2
1
2N7002K PR33 PHASE PR180
short0402 0.01/F_0612
1

In
MBDATA 8 PU2 PL6
SDA BQ24707A 6.8uH_7X7X3
PR34 15 24707_DL 1 2 BAT-V
short0402 LCDRV
MBCLK 9 SCL

5
PC10 +3VPCU
0.1u/50V_6 PR27 14 PR8
10K_4 PGND *4.7_6

i-
24707_IFAULT# 11 4 PR185 PR189
PC13 IFAULT# PQ37 short0402
B short0402 B
*100p/50V_6 PL4 PR188 PR24 PC97 MDV1528URH
FBMA-11-201209-800A50T *10K_4 24707_CMPOUT 3 10_6 0.1u/25V_4

3
2
1
CMPOUT 24707_SRP 24707_SRP PC94 PC93 PC91
SRP 13
MBAT+ BAT-V PC8 2200p/50V_6 10u/25V_1206 10u/25V_1206
24707_ILIM 10 PC22 *680p/50V_6 24707_SRN
PJ2 ILIM 0.1u/25V_4
10 1 PR9
PL3
FBMA-11-201209-800A50T
PR36
316K/F_4
is 24707_CMPIN 4 12 24707_SRN
2 100_4 CMPIN SRN
3 TEMP_MBAT PR26

IOUT

GND
GND
GND
GND
GND
4 TEMP_MBAT 34
7.5_6 PC98
5 0.1u/25V_4
6 PR25 7
REGN MAX voltage 6.5V

21
22
23
24
25
7 PR14 1M_4
9 8 +3VPCU *100K_4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
kn

C114F3-108A1-L_Batt_Conn
PC12 PC11
=0.793V for 3.965A current limit
*47p/50V_6 *47p/50V_6

PR35 PC24
100K/F_4 0.01u/25V_4
PR13 PR11 PR12
Te

short0402 100_4 100_4

MBCLK 34
34 ICM
MBDATA 34
A A

PU1
w.

IP4223-CZ6 PC23
1 6 MBDATA 100P/50V_4
CH1 CH4
Quanta Computer Inc.
2

2 VN VP 5 +3VPCU
TEMP_MBAT 3 4 MBCLK
CH2 CH3 PROJECT : ZQS 45W
Size Document Number Rev
ww

Add ESD diode base on EC FAE suggestion 3C

Charger(bq24707A)
Date: Wednesday, February 08, 2012 Sheet 35 of 46
5 4 3 2 1
 5 4 3 2 1

MAIND SYS_SHDN#
MAIND 15,39,43 SYS_SHDN# 3,19,43

Ven=7.23V

34 SYS_HWPG VIN VIN

+3VPCU VL 8223REF VL

m
D VIN VIN D
1
PR162

10u/6.3V_8
4.7u/6.3V_6
+ PR154 10/F_8

co
665K/F_4 PC166
PC162 1u/6.3V_4
2

100u/25V_6X5.8 PR159

8223_EN
+5VPCU *0_4

8223_VIN
PC170 PC172 PC72 PC163 PC164

PC69

PC73
4.7u/25V_8 2200p/50V_6 PR165 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
*SHORT_4
+5VPCU 31

a.
PR158 PR157

5
PR163 PR155 PR249 *0_4 short0402
*100K/F_4 330K/F_4 short0402 +3VPCU

5
+5VPCU +3VPCU

16

17
8

3
5 Volt +/- 5% 4 3.3 Volt +/- 5%

VIN

VREG3

VREG5

REF
TDC : 6.63A PQ57 4 SYS_SHDN# 13 EN SKIPSEL 14 +3V_SKIP TDC : 7.8A

si
MDV1528URH

3
2
1
PEAK : 8.5A +3V_PG 23 PGOOD TONSEL 4 +3V_TON PQ53 PEAK : 8.5A
MDV1528URH
OCP : 9A OCP : 9A

1
2
3
5V_DH 21 10 +3V_DH
UGATE1 UGATE2
Width : 260mil PL15 PC74 PR164 22 BOOT1 BOOT2 9 PR152 PC68 PL14 Width : 220mil
2.2uH_7X7X3 0.1u/50V_6 1/F_6 PU6 1/F_6 0.1u/50V_6 2.2uH_7X7X3
5V_LX 20 RT8223P 11 +3V_LX

ne
PHASE1 PHASE2
5V_DL 19 12 3V_DL
LGATE1 LGATE2

5
C PR160 24 7 C
VOUT1 OUT2

ENTRIP1

ENTRIP2
15.4K/F_4 PR148 PR156
PQ58 +5VPCU_FB 2 5 +3VPCU_FB *4.7_6 6.81K/F_4

GND

GND
ENC
+ PR166 MDV1595SURH FB1 FB2 +
4
*4.7_6 4

do
PC173 PC169 PC168 PC165

18

25

15
330u/6.3V_6X5.7 0.1u/50V_6 1 PR243 0.1u/50V_6 330u/6.3V_6X5.7
2
3
short0402 PC66

3
2
1
8223_EN *680p/50V_6
PR250 PC75 PQ54 PR248

2
10K/F_4 *680p/50V_6 MDV1595SURH 10K/F_4
PR245 PC167
100K/F_4 0.1u/10V_4

In
1
PR246
PR251 113K/F_4
107K/F_4

i-
Change 11/1
OCP:9A
PC65 L(ripple current)
2 0.1u/50V_6
OCP:9A PD6 3V_DL =(9-3.3)*3.3/(2.2u*0.5M*9)
DA3J101F0L 3
L(ripple current) PR151
~1.9A
=(9-5)*5/(2.2u*0.4M*9) 1

=2.525A PC70
is short0603 Iocp=9-(1.9/2)=8.05A
B
0.1u/50V_6
2
PR247 Vth=8.05A*14mOhm=112.7mV B

Iocp=9-(2.525/2)=7.74A short0603
PD7
R(Ilim)=(112.7mV*10)/10uA
Vth=7.74A*14mOhm=0.10832mV 3
DA3J101F0L =112.7K
PC67
R(Ilim)=(108.32mV*10)/10uA 1 0.1u/50V_6
kn

~107K
+15V_ALWP
+15V
PR153
22_8
PC71
0.1u/50V_6
Te

VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU

+3VPCU
w.

PR150 PR242 PR161 PR244 PR252

5

5
1M_6 22_8 22_8 1M_6 *1M_6

3
S5D 4 MAIND 4 MAIND 4 S5D 2
ww

A A
3

PQ60 PQ59 PQ29 PQ55

3
2
1

3
2
1

3
2
1

2 MDV1528Q MDV1528Q MDV1528Q AO3404

34,43 S5_ON

1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR149 PQ28 PQ30
Quanta Computer Inc.
1

PQ27 1M_6 2N7002K 2N7002K

DTC144EUA PQ56 PC171
TDC : 2.63A TDC : 3.45A TDC : 3.2A TDC : 1.28A
1

2N7002K *2200p/50V_4
PROJECT : ZQS 45W
PEAK : 3.5A PEAK : 4.6A PEAK : 4.27A PEAK : 1.7A Size Document Number Rev
Width : 120mil Width : 140mil Width : 140mil Width : 60mil SYSTEM 5V/3V (RT8223P) 3C

Date: Wednesday, February 08, 2012 Sheet 36 of 46

5 4 3 2 1
 5 4 3 2 1

+VCC_CORE VIN

PR206 VIN
2.2/F_6
PC134 51650_CBST1

2200p/50V_4

1
PR95 *330p/50V_4

0.1u/50V_6

4.7u/25V_8

4.7u/25V_8
1

1
PC126 + +

PC42

PC43
PC141

PC140
Parallel *10_4

2
0.22u/25V_6
PC149 PC151

D1
D1
D1

2
5 VCC_SENSE PR94 short0402 51650_CDH1 100u/25V_6X5.8 100u/25V_6X5.8

5 VSS_SENSE PR96 short0402

1 G1 PL12

m
0.36uH_LDCR DCR=0.8mOhm 11/21
D D
51650_CSW1 S1/D2 9 51650_CSW1 1 2 +VCC_CORE
PR97
PC135 PQ48

PR89
*10_4

4
co 2.2_6
*0.01u/50V_4 8 G2 FDMS3606S

17.4K/F_4

short0402
Close to the 51650_CDL1 +

330u/2V_7343
51650_GSKIP#

S2

0.1u/10V_4

10u/6.3V_8
S2
S2
CPU side. 51650_GSKIP# 45

PC110

PC109

PC111
2200p/50V_6
51650_CPWM3

PC38
51650_CPWM3 45

7
6
5
51650_VREF 51650_CCSP3 51650_CCSP3 45

PR116

PR119
51650_VREF 51650_CCSN3 51650_CCSN3 45

a.
51650_VREF 51650_CCSP1
51650_GPWM2

47p/50V_4

8.25K/F_4

28.7K/F_4
51650_GPWM2 45

PR120
IOP@110K/F_4 51650_GCSP2 PC145

41.2K/F_4

39.2K/F_4
*22.6K/F_4

[email protected]/F_4
51650_GCSP2 45
*0.1u/25V_4
PR106

PR107

PR108

PR109

PR110

PR111
*0_4

51650_GCSN2 51650_GCSN2 45 Close to the

VR side.

100K/F_4_4250NTC
33n/25V_4
51650_COCP-R

PR98
PC133

PC137
51650_CCSN1

PR214
si
PR101
20K/F_4

160K/F_4
IOP@24K/F_4
IOP@100K/F_4

51650_VREF PC146
PR121

PR122

PR123

PR124

PR125

PR126
24K/F_4

56.2K/F_4
IOP@39K/F_4
VIN +5V_S5 *0.1u/25V_4

51650_CTHERM
51650_CCOMP

51650_CCSN3

51650_CCSN2

51650_CCSN1
51650_CCSP3

51650_CCSP2

51650_CCSP1
Close with

51650_CGFB

51650_CVFB

PR196
10K/F_4

short0603
0.1u/10V_4
phase1 inductor

PR93

PR87
PC136

10_6
PC129

ne
1u/6.3V_4

14

12

11

10

2.2u/6.3V_4

4.7u/6.3V_6
VIN

PC125
C C

CCSN3

CCSP3

CCSP2

CCSN2

CCSN1

CCSP1
VREF

CGFB

CVFB

CCOMP

CTHERM

PC128
2
COCP-R
51650_CF-IMAX 3 37 51650_VBAT PR200
CF-IMAX VBAT 2.2/F_6
Check pull up resister to +1.05V +3V +3V_S5 51650_GOCP-R 13 48 51650_V5 51650_CBST2

do

2200p/50V_4
1.05V for H_PROCHOT# GOCP-R V5

0.1u/50V_6

4.7u/25V_8

4.7u/25V_8
1

1
51650_SLEW 51650_V5DRV PC124

PC113

PC114

PC115

PC112
22 43

2
SLEW V5DRV 0.22u/25V_6
51650_GF-IMAX 24 47 51650_CDH1

D1
D1
D1

2
GF-IMAX CDH1 51650_CDH2
1.91K/F_4

1.91K/F_4

*100K/F_4

51650_GSKIP# 51650_CBST1
PR84

PR86

PR92
PR202

33 46
*499/F_4

GSKIP CBST1
15 45 51650_CSW1 1 G1 PL11
V3R3 CSW1 0.36uH_LDCR
51650_VRON PU9 51650_CDL1 51650_CSW2 S1/D2 51650_CSW2
DCR=0.8mOhm

In
34 VRON 16 44 9 1 2 +VCC_CORE
PR88 short0402 VR_ON TPS51650RSLR CDL1
51650_CDL2 PQ41

PR83
3,7 IMVP_PWRGD 17 41

4
CPGOOD CDL2

2.2_6
8 G2 FDMS3606S

17.4K/F_4
PR201 *0_4 23 40 51650_CSW2 +
+VCC_CORE

short0402
GPGOOD CSW2 51650_CDL2
51650_CBST2
21 39 TDC : 54A

S2

0.1u/10V_4

10u/6.3V_8
S2
S2

330u/2V_7343
3,34 H_PROCHOT# VR_HOT CBST2

PC142

PC143

PC139
2200p/50V_6
VR_SVID_CLK 51650_CDH2 PEAK : 94A

PC34
5 VR_SVID_CLK 18 38

7
6
5
PC36 VCLK CDH2
OCP : 100A

i-
43p/50V_4 PC127 VR_SVID_ALERT# 19 42

GTHERM
5 VR_SVID_ALERT# ALERT PGND

GPWM1

GPWM2
GCOMP

TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16
CPWM3

PR70

PR69
1u/6.3V_4
GCSN1

GCSN2
GCSP1

GCSP2

TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9
Width : 4000mil
GGFB
GVFB

5 VR_SVID_DATA VR_SVID_DATA 20

PAD
VDIO 51650_CCSP2
VCORE Load Line :

28.7K/F_4
PR68
26

25

27

28

29

30

31

32

34

35

36

49

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
PC148
*0.1u/25V_4
1.9mV/A
Close to the
51650_GTHERM
51650_GCOMP

51650_GPWM1

51650_GPWM2

51650_CPWM3
51650_GCSN1

51650_GCSN2
51650_GCSP1

51650_GCSP2

VR side.
51650_GGFB

100K/F_4_4250NTC
51650_GVFB

is

33n/25V_4
+VCC_GFX PR211

PC138
short0603 51650_CCSN2

PR193
B B
PC120

PR100
160K/F_4
*330p/50V_4 PC147
*0.1u/25V_4
Parallel PR77
PR76 *10_4 PC118
IOP@0_4 0.1u/10V_4 Close with
5 VCC_AXG_SENSE phase2 inductor
kn

VIN
5 VSS_AXG_SENSE
PR74
IOP@0_4
PC121
*0.01u/50V_4
PR241
[email protected]/F_6 +VCC_GT_VIN
AXG
VIN
PR75 PR285 PR286 51650_GBST1
*10_4 EV@0_4 EV@0_4
IOP@47p/50V_4

[email protected]/F_4

IOP@2200p/50V_4
PC157

[email protected]/50V_6

[email protected]/25V_8

[email protected]/25V_8

[email protected]/25V_8
1

1
PC59
[email protected]/25V_6
PC119

PC159

PC161

PC158

PC160
2
PR78
Te

Close to the PU10

D1
D1
D1

2
CPU side.
1 8 51650_GDH1
51650_GSKIP# BST DRVH 51650_GSW1
2 7
51650_GPWM1 SKIP SW
3 6 +5V_S5 1 G1 PL13
51650_VREF PWM VDD [email protected]_LDCR
4
GND DRVL
5 DCR=0.8mOhm
9 PC156 S1/D2 9 51650_GSW1 1 2 +VCC_GFX
PAD IOP@1u/10V_4
10 PQ52

IOP@2200p/50V_6 [email protected]_6

4
TPAD1 FDMS3606S

PR147
11 8 G2
w.

[email protected]/F_4
TPAD2 +
12
51650_VREF TPAD3 51650_GDL1
13

IOP@330u/2V_7343
+1.05V TPAD4
Close to VR

IOP@0_4
14

S2
S2
S2

[email protected]/10V_4

IOP@10u/6.3V_8
TPAD5

PC154

PC152

PC155
IOP@TPS51601DRBR

PC64
7
6
5
+3V +VCC_GFX
PR271
TDC : 38A
PR205

PR203

PR204

PR137

PR136
130/F_4

*75/F_4
54.9/F_4
0.1u/10V_4
PC35

EV@0_4
PEAK : 50A
ww

PR198 PR207 51650_GCSP1

A 15.8K/F_4 15.8K/F_4 A

[email protected]/F_4
VR_SVID_ALERT# OCP : 55A

PR135
PC116
51650_VRON VR_SVID_DATA 51650_GTHERM 51650_CTHERM 11/1 Add *[email protected]/25V_4 Width : 1840mil
Close to the
VR_SVID_CLK
PR91
VR side. GFX_CORE Load Line :

IOP@33n/25V_4

IOP@165K/F_4
PR197 PR99 -3.9mV/A for GT2

PC122
100K/F_4

IOP@100K/F_4_4250NTC
IOP@100K/F_4_4250NTC 100K/F_4_4250NTC 51650_GCSN1

PR221

PR82
PC117
PR272 *[email protected]/25V_4 Quanta Computer Inc.
+VCC_CORE 5,45,46 EV@0_4
Place NTC close to the Place NTC close to the PROJECT : ZQS 45W
GFX_CORE Hot-Spot. VCORE Hot-Spot. +VCC_GFX 5,45
Size Document Number Rev
Close with
IV@ for Internal VGA(+VCC_GFX enable) 3C
AXG inductor +VCC_CORE/+VGFX (TPS51650)
EV@ for External VGA(+VCC_GFX disable discrete only) Date: Wednesday, February 08, 2012 Sheet 37 of 46
5 4 3 2 1
 5 4 3 2 1

VIN

m
D D

PC92 PC95 PC96

+1.05V

co
+3V +5V_S5 2200p/50V_4 4.7u/25V_8 4.7u/25V_8
1.05 Volt +/- 2%
TDC : 13.2A
PEAK : 17A

5
PR15
PR177 10_6

a.
22

21

20

19

18

17
100K_4 OCP : 20A
51219_DH 4 Width : 680mil

PAD

PAD

PAD

PAD

PAD

PAD

1
2
3
16 11 PR181 PC89 PQ39 +1.05V
34,40 HWPG_VTT PGOOD DH 2_6 0.1u/25V_6 RJK03J6DPA

si
51219_EN 14 13 PL7 Close to output cap
31,34,39,42,43 MAINON EN BST 0.68uH_7X7X3
PR16 51219_V5 9 PU8 12 51219_SW
short0402 V5 TPS51219RTER SW
51219_MODE 15 10 51219_DL
MODE DL

5
51219_TRIP 6 8

ne
TRIP PGND PR28 PR7 +
4 *4.7_6 *100_4 PC103 PC102

COMP
REFIN
C C

GSNS

VSNS
VREF
0.1u/50V_6 560u/2.5V_6X5.7

GND

1
2
3
PC86 PC90 PR178 PR182 PQ40 PC21
*0.1u/10V_4 1u/6.3V_4 1K/F_4 64.9K/F_4 PR174 RJK03K5DPA *680p/50V_6

do
VREF=2V short0603
RDSon 3.9mOhm

51219_REFIN

51219_GSNS

51219_VSNS
51219_REF

PC87

In
0.01u/16V_4 PR10
+3V_S5 PC80 PR4 10_4 PR3
0.1u/10V_4 *10K/F_4 short0402
PR5
VTT_VCCP_SENSE 5
0.01u/25V_4
OCP=18A 10_4
L ripple current VTT_VSSP_SENSE 5

1n/50V_4

1n/50V_4

i-
=(19-1.05)*1.5/(0.68u*500k*19) PR1 PR175
short0402 short0402
=2.918A RC filter is for improve PR176
Vtrip=20-(2.918/2)*4.3mohm PR2
Jitter performance. *100_4
PC79

PC82

PC88
*11K/F_4
=0.07972V
B Rlimit = 0.07972/10uA*8=63.78Kohm
is B
kn

+1.05V 3,5,7,8,9,11,23,34,37,42,43,46
+3V_S5 7,8,9,10,11,15,16,29,31,33,36,37,43,44
VIN 23,35,36,37,39,41,42,43,44,45,46
Te

+5V_S5 11,27,31,36,37,39,40,41,45,46
+3V 3,7,8,9,10,11,13,14,16,20,23,24,25,26,27,29,33,34,36,37,39,40,41,42,43,45,46
w.

A A
ww

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
3C
+1.05V (TPS51219)
Date: Wednesday, February 08, 2012 Sheet 38 of 46
5 4 3 2 1
 5 4 3 2 1

TDC : 0.75A +0.75V_DDR_VTT

PEAK : 1A
Width : 40mil +0.75V_DDR_VTT 13,14,43

PC174 PC175
10u/6.3V_8 10u/6.3V_8
TDC : 0.38A

m
D D
PEAK : 0.5A +SMDDR_VREF
Width : 20mil

co
Close to IC Greater than or equal 40mil
PC177
0.22u/10V_4

+5V_S5

a.
+3V

PC176 PC180

22

21
10u/6.3V_8 1u/10V_4

2
PR253

si
VIN
100K/F_4

PAD

PAD

VTTGND

VLDOIN
VTTSNS
VTTREF

VTT

5
34 HWPG_VDDR 20 PGOOD V5IN 12
C
PC189 PC187 PC188 C
2200p/50V_4 4.7u/25V_8 4.7u/25V_8

ne
PR259 *0_4 51216_S3 17 14 51216_DRVH 4
31,34,38,42,43 MAINON S3 DRVH +1.5VSUS 11,13,14,15,42,46
PR287 short0402 PR262 PC181
34 p75V_ON
2_6 0.1u/50V_6

1
2
3
PR261 51216_S5 16 15 51216_VBST PQ61
34 SUSON S5 VBST
short0402 PU11 RJK03J6DPA
TPS51216RUKR
PR255 51216_MODE 19 51216_SW +1.5VSUS

do
MODE SW 13
200K/F_4
PL16

5
PR257 51216_TRIP 18 11 51216_DRVL 0.68uH_7X7X3
60.4K/F_4 TRIP DRVL
+1.5V_SUS
VDDQSNS

PR270
26 PAD PGND 10 4 *4.7_6 1.5 Volt +/- 5%
REFIN

In
GND
PAD

PAD

PAD
REF

PC183 PC182 TDC : 14.67A

1
2
3
PQ62 0.1u/50V_6 560u/2.5V_6X5.7
VREF=1.8V RJK03K5DPA PC195 PEAK : 18A
6

25

24

23

7 *680p/50V_6
51216_REF OCP : 20A
51216_REFIN

Width : 600mil

i-
PC178 PR258
B 0.1u/10V_4 short0603 RDSon=3.9mohm B
51216_S3 PR260 51216_S5
*0_4
PR256
10K/F_4 Close to output cap
+1.5VSUS
is

3
TDC : 0.38A
PR254 PC179 PEAK : 0.5A
kn

+1.5V 11,25,43
51K/F_4 0.01u/25V_4 2
+5V_S5 11,27,31,36,37,38,40,41,45,46 15,36,43 MAIND
Width : 20mil
+SMDDR_VREF 13,14,15
PQ35
AO3404

1
Te

+1.5V

OCP=20A
A L ripple current A
S3 S5 +1.5VSUS REF VTT
=(19-1.5)*1.5/(0.68u*400k*19)
w.

=5.079A
S0 1 1 ON ON ON Quanta Computer Inc.
Vtrip=20-(5.079/2)*4.3mohm
=0.07508V
S3 (mainon off) 0 1 ON ON OFF PROJECT : ZQS 45W
Rlimit=0.07508/10uA*8=60.063Kohm
Size Document Number Rev
ww

S4/S5 0 0 OFF OFF OFF 3C

DDR 1.5V(TPS51216)
Date: Wednesday, February 08, 2012 Sheet 39 of 46
5 4 3 2 1
 5 4 3 2 1

VID0 VID1 +VCCSA +3V

0 0 0.9V
0 1 0.8V
+VCCSA

m
D D
1 0 0.725V
0.9 Volt +/- 2%
1 1 0.675V
TDC : 4.2A

co
default 0.9V PC4002 PC4003 PC4004 PEAK : 6A
0.1u/10V_4 10u/10V_8 10u/10V_8
Width : 240mil
+5V_S5

a.
+VCCSA
PC4001
2.2u/6.3V_6
+3V +VCCSA 5

24

23

22

21

20

19
PC4006
0.1u/50V_6

si
VIN

VIN

VIN

PGND

PGND

PGND
PR4001 18 12 51461_BST
PC4005 short0603 V5DRV BST PL4001
PR4002 1u/6.3V_4 0.47uH_7X7X3
100K_4 51461_FILT 17 11
V5FILT SW

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8
C C

ne
34 HWPG_VCCSA 16 10 51461_SW
PGOOD TPS51461 SW
PU4001
51461_EN 13 9 PR4004
34,38 HWPG_VTT EN SW
100_4

PC4013

PC4014

PC4015

PC4016

PC4017

PC4018
PR4003
short0402

do
5 VCCSA_VID0 14 VID0 SW 8

PC4009
*0.1u/10V_4 15 7
5 VCCSA_VID1 VID1 SW

MODE

COMP

SLEW

VOUT
VREF
PC4008

GND
25 11/21 for layout issue 0.1u/50V_6
AGND

In
51461_MODE 6

5
PR4009 4.99K/F_4
PR4011 PR4005

51461_SLEW
51461_VREF
1K_4 1K_4

i-
51461_VOUT
VCCSA_SENSE 5
B PR4008 B
*0_4 PC4010 PR4010
0.01u/16V_4 short0402
is PC4011
0.22u/10V_4
PR4006 short0603 PC4012
3.3n/50V_4

PR4007 short0603
kn
Te

A A
w.

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
VCCSA(TPS51461)
Date: Wednesday, February 08, 2012 Sheet 40 of 46
5 4 3 2 1
 5 4 3 2 1

N13P-GL QS sample, boot up voltage set to 0.95V. VID2,3,5

+3V_GFX
N13P-GS ES sample, boot up voltage set to 0.90V. VID4,5
default 1.1V N13M-GS ES sample, boot up voltage set to 0.90V. VID4,5
H_VID0
PR212 EOP_VID0_H@10K/F_4
H_VID1
PR216 EOP_VID1_H@10K/F_4
VID
H_VID2
PR220 EOP_VID2_H@10K/F_4
VDAC(V)
H_VID3
PR225 EOP_VID3_H@10K/F_4
GPU SKU 6 5 4 3 2 1 0
H_VID4

m
D D
PR228 EOP_VID4_H@10K/F_4
H_VID5
PR130 EOP_VID5_H@10K/F_4
N13P-GL 0 1 0 1 1 0 0 0.9500 PR103
[email protected]/F_6

co
+3V VIN
51728_VBST2
EOP_VID5_L@10K/F_4

EOP_VID4_L@10K/F_4

EOP_VID3_L@10K/F_4

EOP_VID2_L@10K/F_4

EOP_VID1_L@10K/F_4

EOP_VID0_L@10K/F_4
N13P/M-GS 0 1 1 0 0 0 0 0.9000

1
EOP@2200p/50V_4
[email protected]/50V_6

[email protected]/25V_8

[email protected]/25V_8
5

PC130

PC39

PC131
PC45 + PC150

PC41
PR217 EOP@100K/F_4

PR139 EOP@100K/F_4
[email protected]/25V_6 EOP@100u/25V_6X5.8

PR128 *EOP@10K/F_4

EOP@56_4

2
51728_DRVH2 4

a.
+5V_S5 PR208

1
2
3
*EOP@10K/F_4 PQ43 PL10
EOP@AON6414AL [email protected]
DCR=1.1mOhm

PR146
51728_LL2 1 2 +VGACORE
PR235

PR231

PR226

PR222

PR218

PR213

4
5

PR85
[email protected]_6
PC47

[email protected]/F_4
si
[email protected]/10V_6 +
51728_DRVL2 4

[email protected]/10V_4

EOP@10u/6.3V_8
42 VGA_PG 4

PR71 EOP@0_4

PC107

PC123
EOP@2200p/50V_4
PC37
PC104

26
19 GPU_DPRSLPVR

1
2
3

1
2
3
PQ25 PQ45 EOP@330u/2V_7343
*EOP@AON6780 EOP@AON6780

V5IN
PR232 *EOP@100K/F_4 33 30 51728_DRVH2
PGD DRVH2

PR79
34 29 51728_VBST2

ne
C PR143 [email protected]_4 PG VBST2 C
51728_PCNT 13 28 51728_LL2
PCNT LL2 51728_CSP2
PR224 EOP@100K/F_4 12 27 51728_DRVL2
SLP DRVL2

EOP@200K/F_4
[email protected]/F_4
PR73

PR237
51728_EN 35 3 51728_CSP2 PC60
10,42 dGPU_VRON EN CSP2
PR223 EOP@0_4 *[email protected]/25V_4
34 GPU_PWR_ALERT#
GPU_PWR_ALERT# 10 4 51728_CSN2 Close to the
+VGPU_CORE (N13P-GS)

do
THAL CSN2

[email protected]/25V_4
VR side. Countinue current:50A

PC55
C01 Add GPU_PWR_ALERT# to EC H_VID0 20
GPIO53, connect to PU5.10. 19 GPU_VID0 PR113 EOP@0_4 VID0
12/21 H_VID1 19 21 51728_DRVH1 51728_CSN2 Peak current:55A
19 GPU_VID1 PR117 EOP@0_4 VID1 DRVH1
H_VID2 18 22 51728_VBST1 PC61 OCP minimum 60A
19 GPU_VID2 PR127 EOP@0_4 VID2 VBST1 *[email protected]/25V_4
H_VID3 17 23 51728_LL1 Loadline=0mV/A
19 GPU_VID3 VID3 LL1

In
PR131 EOP@0_4
H_VID4 16 24 51728_DRVL1 PR195
19 GPU_VID4 PR134 EOP@0_4 VID4 DRVL1 EOP@100K/F_4_3540NTC
H_VID5 15 6 51728_CSP1
19 GPU_VID5 PR115 EOP@0_4 VID5 CSP1
14 5 51728_CSN1
VID6 PU5 CSN1 +3V
51728_DROOP EOP@TPS51728RHAR
PC52 EOP@68p/50V_4

i-
PGND 25

39 PR104
DROOP PR112 [email protected]/F_6 VIN
PC51 PR140 *EOP@0_4 51728_VBST1

EOP@2200p/50V_4
36 51728_TONSEL

[email protected]/50V_6

[email protected]/25V_8

[email protected]/25V_8
EOP@1200p/50V_4 [email protected]/F_4
B
51728_V5FILT +3V 51728_VREF 40 TONSEL B
VREF

1
PC44

PC48

PC144

PC132
TRIPSEL 31 51728_TRIPSEL PC46
[email protected]/25V_6 + PC153
PC56
[email protected]/10V_6
PR233
EOP@113K/F_4
is OSRSEL 32 51728_OSRSEL
51728_DRVH1 4
EOP@100u/25V_6X5.8

2
EOP@0_4

*EOP@0_4
PR209

1
2
3
PR118

PR210
51728_SLEW 37 *EOP@10K/F_4 PQ46 PL9
SLEW +VGACORE 20
PR229 PR114 PR132 PR227 *EOP@316K/F_4 EOP@AON6414AL [email protected] DCR=1.1mOhm
*EOP@0_4 *EOP@0_4 EOP@0_4 51728_LL1 1 2 +VGACORE

[email protected]_6
9 THRM
kn

PR80 [email protected]/F_4
1

4
PU

5
EOP@0_4

PR90
*EOP@0_4
PR145 PR234
51728_TONSEL [email protected]/F_4 EOP@100K/F_4_3540NTC 38 51728_V5FILT +
V5FILT

PR72 EOP@0_4
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16
TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9

51728_DRVL1 4
PwPd

[email protected]/10V_4

EOP@10u/6.3V_8
IMON

Place NTC close to the 4

GND
GFB
VFB

PC108

PC106
EOP@2200p/50V_4
PC105
GPU Hot-Spot.

PC40
EOP@330u/2V_7343

1
2
3

1
2
3
PR219

PC50 PR215 PQ26 PQ44

8

11

41

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

+VGACORE
Te

[email protected]/10V_6 *EOP@AON6780 EOP@AON6780

51728_CSP1
PR238
51728_IMON

EOP@200K/F_4
[email protected]/F_4
EOP@100_4

PR81

PR236
PR144 PC63
EOP@0_4 *[email protected]/25V_4

[email protected]/25V_4
w.

51728_VFB PR240 Close to the

16 GPUVCC_SENSE
A EOP@0_8 A
VR side.

PC53
16 GPUVSS_SENSE 51728_GFB

PR142 PR141 PC54

EOP@0_4 [email protected]/F_4 EOP@3300p/50V_4
PR239 PC62
EOP@100_4 *[email protected]/25V_4
Quanta Computer Inc.
ww

51728_CSN1

Close to the PR199

PC58 PC57 EOP@100K/F_4_3540NTC PROJECT : ZQS 45W
GPU side. EOP@1n/50V_4 EOP@1n/50V_4 Size Document Number Rev
3C
VGPU Core (TPS51728)
Date: Wednesday, February 08, 2012 Sheet 41 of 46
5 4 3 2 1
 5 4 3 2 1

VIN +3V_GFX +15V +3V

PR168 PR167 PR170 TDC : 1.04A

m
D PR173
*EOP@0_4
EOP@1M_4 EOP@22_8 EOP@1M_4 PEAK : 1.38A D

31,34,38,39,43 MAINON dGPU_D

Width : 50mil
2

co
3

3
PQ34

3
PR171 EOP@AO3404
EOP@0_4 PR169

1
9 dGPU_PWR_EN 2 EOP@1M_4 2 2
PC76 +3V_GFX
PQ31 PQ32 *EOP@2200p/50V_4

a.
PR172 PQ33 EOP@2N7002K EOP@2N7002K

1
EOP@100K_4 EOP@PDTC143TT

si
VIN +1.5V_GFX +15V +1.5VSUS

TDC : 5.67A

ne
C C

PR105 PR230 PR17 PEAK : 7.56A

5
PR133 EOP@1M_4 EOP@22_8 EOP@1M_4
EOP@0_4 Width : 240mil
41 VGA_PG dGPU_D1 4

do
3

1
2
3
3

PR138 PQ5
*EOP@0_4 PR102 EOP@RJK03K5DPA
2 EOP@1M_4 2 2 +1.5V_GFX
10,41 dGPU_VRON PC14
PQ49 PQ2 *EOP@2200p/50V_4
PR129 PQ50 EOP@2N7002K EOP@2N7002K

In
1

PC49 EOP@100K_4 EOP@PDTC143TT

1
EOP@1u/10V_4

i-
B B

VIN +1.05V_GFX +15V +1.05V

is

5
PR46 PR51 PR50
EOP@1M_4 EOP@22_8 EOP@1M_4
TDC : 3.5A
PEAK : 5A
+1.5V_GFX dGPU_D2 Width : 120mil
kn

4
3

3
3

PR47 PQ9

3
2
1
EOP@0_4 PR49 EOP@MDV1528Q
2 EOP@1M_4 2 2
PC30 +1.05V_GFX
PQ10 PQ11 *EOP@2200p/50V_4
Te

PR48 PQ12 EOP@2N7002K EOP@2N7002K

1

EOP@100K_4 EOP@PDTC143TT
1

1
w.

A A

Quanta Computer Inc.

ww

PROJECT : ZQS 45W

Size Document Number Rev
3C
GPU_PWR
Date: Wednesday, February 08, 2012 Sheet 42 of 46
5 4 3 2 1
 5 4 3 2 1

+1.8V
+1.8V
+3VPCU 1.8 Volt +/- 5%
TDC : 1.61A
+3V_S5
PC77 PEAK : 2A
PC78 0.1u/25V_4
10u/6.3V_8 PU7 TPS54318RTER Width : 60mil
16 VIN PH 10

PR264 1 11 PL5

m
D VIN PH 1uH_7X7X3
D
*100K/F_4
2 12 PR263
VIN PH short0603
14 13

co
34 HWPG_1.8V PW RGD BOOT
15 6 PC185 R1 PR268
31,34,38,39,42 MAINON EN VSNS 0.1u/50V_6 100K/F_4
7 COMP GND 3

8 RT/CLK GND 4
PR265 PC184 +1.8V_VSNS

PAD
PAD
PAD
PAD
PAD
PAD
*100K/F_4 1000p/50V_4 PR267 9 5
SS AGND

a.
10K/F_4 PR266
121K/F_4 R2 PR269

22
21
20
19
18
17
78.7K/F_4
PC186 PC190 PC191
PC194 PC193 PC192 V0=0.8*(R1+R2)/R2 0.1u/25V_4 10u/6.3V_8 10u/6.3V_8
*100p/50V_4 1200p/50V_4 0.01u/25V_4

si
ne
C C
VIN

PD5
DA2J10100L

do
PR55
1M_6
Thermal protection
1

In
PQ16
AO3409
2
3

S5_ON 2

i-
34,36 S5_ON

PQ13 PR52
1

DTC144EUA short0603
VIN +3V +5V +0.75V_DDR_VTT +1.5V +1.05V +1.8V +15V
B B

VL VL
is SYS_SHDN# 3,19,36
PR67
1M_4
PR60
22_8
PR59
22_8
PR64
*22_8
PR58
22_8
PR61
*22_8
PR63
*22_8
PR65
1M_4
PR57
200K_6
PR53 PC32 MAINON_ON_G MAIND
PR54 200K/F_4 0.1u/50V_6 15 MAINON_ON_G MAIND 15,36,39
3

3
931/F_4
8

3
PR194
kn

10K_6_NTC 2.469V 3 PR66

+ MAINON PQ24
1 2 2 1M_4 2 2 2 2 2 2 2
2 DTC144EUA PC33
- PQ15 PQ19 PQ18 PQ22 PQ17 PQ20 PQ21 PQ23 *2200p/50V_4
3

PU4A 2N7002K 2N7002K 2N7002K *2N7002K 2N7002K *2N7002K *2N7002K 2N7002K

4

BA10393F PC31 PR62

1

1
0.1u/50V_6 *100K/F_6
S5_ON 2
Te

PR56
PQ14 200K/F_4
2N7002K
1

w.

A A
13,14,39 +0.75V_DDR_VTT
5
+
7
6
-
PU4B
Quanta Computer Inc.
ww

BA10393F

PROJECT : ZQS 45W

For EC control thermal protection (output 3.3V) Size Document Number Rev
3C
+1.8V/Discharge/Thermal
Date: Wednesday, February 08, 2012 Sheet 43 of 46
5 4 3 2 1
 5 4 3 2 1

+3VPCU

m
D D

+3V_S5 +1.05V_M

co
PC196 PC197
1.05Volt +/- 5%
SBA@10u/[email protected]/25V_6
PU12 SBA@TPS54318RTER
TDC : 0.8A +1.05V_M
PR278 16 VIN PH 10
PEAK : 1.1A
SBA@100K/F_4
SBA 1 11 PL17 Width : 40mil

a.
VIN PH SBA@1uH_5X5X3
2 VIN PH 12

7,34 EC_PWROK_R R617 SBA@0_4 1.05V_M_PG 14 13 PR274 SBA@0_6

PWRGD BOOT PR275
C16 Connect EC_PWROK_R to PU12.14, reserve 0Ω R617, for SBA. 12/29 PC198 [email protected]/F_4
34 M_PON
15 EN VSNS 6
[email protected]/50V_6
R1

si
PR273 7 3
SBA@0_4 COMP GND 1.05M_FB PC200
8 4 PC201 SBA@10u/6.3V_8
PC199 RT/CLK GND [email protected]/10V_4

PAD
PAD
PAD
PAD
PAD
PAD
SBA@1000p/50V_4 9 5 PR279
PR276 PR277 SS AGND [email protected]/F_4
C
[email protected]/F_4 SBA@182K/F_4
R2 C

ne 22
21
20
19
18
17
PC204
V0=0.8*(R1+R2)/R2
PC202 PC203 [email protected]/25V_4
*SBA@100P/50V_4 SBA@1200p/50V_4

do
11/7 modify

In
i-
B B

VIN +3V_M +15V +3VPCU

PR280
is PR281 PR282

3
SBA@1M_4 SBA@22_8 SBA@1M_4
TDC : 0.09A
SUSD 2 PEAK : 0.1A
3

Width : 10mil
kn
3

PQ63
SBA@AO3404

1
2 2 2
34 M_PON PR283 PC205
+3V_M
1

SBA@1M_4 PQ65 PQ66 *[email protected]/50V_4

PR284 PQ64 SBA@2N7002K SBA@2N7002K
1

*SBA@100K_4 SBA@DTC144EUA
Te
1

1
2

A A
w.

Quanta Computer Inc.

PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
+1.05V_M/+3V_M
Date: Wednesday, February 08, 2012 Sheet 44 of 46
5 4 3 2 1
 5 4 3 2 1

VIN
PR294
2.2/F_6
51650_CBST3

2200p/50V_4

1
0.1u/50V_6

4.7u/25V_8

4.7u/25V_8
PC216

1
PC100

PC209

PC215

PC214
0.22u/25V_6 +

2
+5V_S5
PU13 PC210

D1
D1
D1

m
D 100u/25V_6X5.8 D

1 8 51650_CDH3
BST DRVH 51650_CSW3
2 SKIP SW 7
51650_CPWM3 3 6 1 G1 PL18

co
37 51650_CPWM3 PWM VDD +5V_S5
4 5 0.36uH_LDCR DCR=0.8mOhm
GND DRVL PC211 S1/D2 51650_CSW3
PAD 9 9 1 2 +VCC_CORE
IOP@1u/10V_4

PR290
10 PQ67

4
TPAD1

2.2_6

17.4K/F_4
11 8 G2 FDMS3606S
TPAD2

short0402
TPAD3 12

330u/2V_7343
13 51650_CDL3 +

a.
TPAD4

0.1u/10V_4

10u/6.3V_8
S2
14

S2
S2
TPAD5

2200p/50V_6

PC212

PC208

PC213
PC99
TPS51601DRBR

7
6
5
+3V

PR192

PR291
PR293
*0_4

si
51650_CCSP3

100K/F_4_4250NTC 28.7K/F_4
PR292
PC217
*0.1u/25V_4
C Close to the C

ne
37 51650_CCSP3 VR side.

33n/25V_4
PC206

PR289
37 51650_CCSN3 51650_CCSN3

PR295
160K/F_4
PC207
PR288 *0.1u/25V_4
*0_4

do
Close with
VIN phase3 inductor

PR303
[email protected]/F_6 +VCC_GT_VIN

In
51650_GBST2

IOP@2200p/50V_4
[email protected]/50V_6

[email protected]/25V_8

[email protected]/25V_8

[email protected]/25V_8
PC229

1
PC220

PC101

PC224

PC225

PC230
[email protected]/25V_6

2
PU14

D1
D1
D1

2
i-
1 8 51650_GDH2
51650_GSKIP# BST DRVH 51650_GSW2
B 37 51650_GSKIP# 2 SKIP SW 7 B
37 51650_GPWM2 51650_GPWM2 3 6 +5V_S5 1 G1 PL19
PWM VDD [email protected]_LDCR
4 GND DRVL 5
51650_GSW2
DCR=0.8mOhm
9 PC223 S1/D2 9 1 2 +VCC_GFX
PAD IOP@1u/10V_4

IOP@2200p/50V_6 [email protected]_6
PQ68
10
is

4
TPAD1

PR304
FDMS3606S

[email protected]/F_4
11 8 G2
TPAD2 +
TPAD3 12

IOP@330u/2V_7343
13 51650_GDL2
TPAD4

IOP@0_4

[email protected]/10V_4

IOP@10u/6.3V_8
S2

14
S2
S2

TPAD5

PC221

PC219

PC218
PC227
IOP@TPS51601DRBR
7
6
5
kn

+3V

PR299

PR296
PR302
EV@0_4
51650_GCSP2

IOP@100K/F_4_4250NTC [email protected]/F_4
PR298

PC222
Te

*[email protected]/25V_4
Close to the
IOP@33n/25V_4

37 51650_GCSP2 VR side.
IOP@165K/F_4
PC226

A A
PR301

37 51650_GCSN2 51650_GCSN2
PR300
w.

PC228
PR297 *[email protected]/25V_4 Quanta Computer Inc.
+VCC_CORE 5,37,46 EV@0_4

+VCC_GFX 5,37
PROJECT : ZQS 45W
Size Document Number Rev
ww

3C
+VCC_CORE/+VGFX (TPS51650)
Date: Wednesday, February 08, 2012 Sheet 45 of 46
5 4 3 2 1
 5 4 3 2 1

VIN C563 C134 +1.05V +3V +5V +5V_S5

m
*0.1u/50V_6 *0.1u/50V_6 C592 C344 C291 C679 C685 C646
D D
*0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

co
C690
C119 C413 C339 *0.1u/16V_4 C561 C704
*0.1u/50V_6 C37 *0.1u/16V_4 C340 *0.1u/16V_4 *0.1u/50V_6 C357 C625 *0.1u/16V_4
*0.1u/50V_6 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

a.
si
+1.5VSUS +1.5V_GFX +1.8V +3VPCU
C540 C260 C107
*0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

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C C255 C509 C363 C377 C
*0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/50V_6 C154
*0.1u/16V_4

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+VCC_CORE

In
29,30 CARD_3V3 C335
*0.1u/16V_4 C695
*0.1u/16V_4

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*0.1u/16V_4 C676
*0.1u/16V_4
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Quanta Computer Inc.
PROJECT : ZQS 45W
Size Document Number Rev
3C
EMI
Date: Wednesday, February 08, 2012 Sheet 46 of 46
5 4 3 2 1
 5 4 3 2 1

REV CHANGE LIST

Model
C C01 Add GPU_PWR_ALERT# to EC GPIO53, connect to PU5.10. 12/21
C02 Change R483,R486,R492,R491,R498,R487,R496,R494 from 590 Ω to 510Ω, and mount HDMI R194,R205,R202,R212
120Ω at optimus sku for EMI. 01/17
ZQS MB C03 Add GPU_TRIP# to EC GPIO47, connect to NV GPIO08. 12/23
C04 Change SW1,SW2 footprint & PN from DHP00DA1J01 to DHP00532W00. 12/23
C05 Change WL_SW# from EC GPIO91 to EC GPIO04. 12/23
C06 Connect to Q42 & EC GPIO91, Q42 change from reserve to mount. 12/24
C07 Add R608 and reserve +1.5V to WLAN. 12/23
C08 Connect EC GPIO46 IOAC_LANPWR# to WLAN, R662, add C708, R661, Q48, reserve R316. 12/23

m
D D
C09 Change USB power Cap C306,C352 from 100U_3528 to 100U_3216. 12/23
C10 Change R328 from 47Ω to 0Ω, for hall sensor ESD & shudown issue. 12/28
C11 Change R641 from reserve to mount per EC request. 12/27

co
C12 Change Q47 from 2N7002 to DTC144EUA, change Q47.2 from +3V_GFX to PEGX_RST#, connect GPU_TRPI# to
Q47, add 0Ω R142,R237. For GPU thermal detect. 12/27
C13 Change R393 from reserve to mount. dGPU_PWROK pull high. 12/27
C14 Change R234 from mount to reserve. WAKE_WLAN function on. 12/27
C15 Add 0Ω R609 to net EC_PWROK_R. SBA 12/29
C16 Connect EC_PWROK_R to PU12.14, reserve 0Ω R617. SBA 12/29
C17 Connect EC_PWROK_R to EC GPIO30, reserve 0Ω R635. SBA 12/29

a.
C18 Change hole15, hole17 footprint to H-C256D161PT to h-c256d142pt. 12/30
C19 R382 change from 30.1 KΩ to pull down 45.3KΩ for N13P-GS & GT strap 4. 01/04
C20 Change R230 from shortpad to 0Ω, add 0Ω R636 connect to +3VPCU. 01/05
C21 Reserve 0Ω R645 connect to DPWROK, add new net DPWROK_EC. 01/05
C22 Change R220 from shortpad to 0Ω, reserve 0Ω R646 connect to DPWROK_EC. 01/05
C23 Change L40 footprint from L2x1_6-1 to RC0805. 01/09

si
C24 Change mini pcie power source from +3V_S5 to +3VPCU. 01/12
C25 Change CN20 pin 30 &28 from CLK_SDATA & CLK_SCLK to SMB_PCH_CLK & SMB_PCH_DAT, reserve 0Ω R663,R664.
1/12
C26 Mount R314, R315 for mini card debug. 01/12
C27 Add Q49 connect PCIE_CLKREQ5# to CN20.7. 01/12
C28 Change EC GPI96 from WAKE_WLAN to WK_GPIO27, connect to PCH_GPIO27. 01/12
C29 Reserve FDI Disabling (Discrete Only), add R665,R666,R667,R668,R669. 1/13

ne
C30 Change U22 PLTRST# power source from +3V_S5 to +3V. 01/17
C31 Change DGPU_POK4 from +1.05V_GFX to +1.5V_GFX, DGPU_POK2 from +1.5V_GFX to +1.05V_GFX for possibly
C floating issue. 01/17 C

C32 Add net WLAN_OFF to connect EC(GPIO66/G_PWM) to CN20.46 ( LED_WPAN#) for IOAC feature, mount 0Ω
R670. 01/18
C33 R73 change from 34.8 KΩ to pull down 4.99KΩ for N13P-GS & GT STRAP1. 01/17

do
C34 Mount Q12 at SBA sku. 01/17
C35 Reserve 0.1u capacitor C698 to EC_PWROK_R. 01/17
C36 Remove R308 reserved 10KΩ for LED_WLAN# pull high +3V. 01/31
C37 Add Q50 connect to BT_POWERON# for WLAN ON/OFF function, pull up BT_PWRON by 10KΩ R671 to +WL_VDD,
reserve 10KΩ R672 to +3V. 01/31
C38 Change C562, C564 from 220U to 100U for cost down. 02/08

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Quanta Computer Inc.

PROJECT : ZQS 45W DOC NO. PROJECT MODEL : ZQS APPROVED BY: DATE: 2011/12/23
Size Document Number Rev
3C
Change list PART NUMBER: DRAWING BY: REVISON: C
Date: Wednesday, February 08, 2012 Sheet 47 of 47

5 4 3 2 1