International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

Physical Design Implementation of Single Core 32 Bit RISC

Processor on 28nm Technology
Feroz Ahmed Choudhary1, Amay Shiva Naik2, Dr. Rajashekhar C Biradar3
1,2,3Dept. of Electronics and communication Engineering, REVA University, Bengaluru, India
----------------------------------------------------------------------***---------------------------------------------------------------------
Abstract – Physical Design implementation means the rule checking). At last we perceive Graphic Database
layout assembling and connectivity of digital logic gates as System (GDS II) file, it is database file format which is
per the design input file (called as netlist) of an Integrated industry standard for data substitute of IC layout artwork.
chip say a processor, by meeting the design specifications It is binary file representing planar geometric shapes, text
like timing, power and area. Here in this design we have labels and other information about layout in hierarchical
used the inputs given by the synthesis team and further
form.
physical design flow has been carried out in a proper
physical design flow i.e. from import design, floor plan
further placement till signoff using the Physical design
tools. At each stage checks are done such as timing (hold &
setup), quality of report, congestion, routing etc.

Key Words: Import Design, Floor Plan, Placement,

Place opt, Clock Tree Synthesis, Opt Clock Tree
Synthesis, Routing, opt Routing, Signoff.

1.INTRODUCTION

In physical design implementation of 32Bit RISC Processor

here we started with Design netlist which contains
information of the cells used, their interconnections, area,
and other details, this design netlist is synthesized means
constraints were applied to ensure the design meets the
functionality and speed. Next step was floor planning in
this die and core area are created with respect to aspect
ratio and utilization factor and then based on the macros Fig -1: Physical Design Flow shown in ASIC Flow
present we placed the macros in smart way so that in
further stages there are no congestions. Then partitioning 1.1 Design Specifications
was done to divide the chip into small blocks after that
power planning was done further before doing placement, ▪ Technology node: 28nm
all wire load models(WLM) were removed as placement ▪ Layers: 9 Routing metal Layers
used RC values from virtual route (VR) to calculate timing. ▪ Macro counts: 40
▪ No. of Clocks: 6 Clocks
Placement was done as pre-placement, in placement and
▪ Total Cells: 0.52 Million
post placement after placement optimization Clock tree ▪ Target clock Frequency: 416 MHz with 6 Clocks in Design
synthesis is done to balance the skew and minimize the ▪ Design Corners: 2
insertion delay after CTS Routing was carried out which is ▪ Voltage Domain: 1
divided into two global and detailed routing as this is done
further we have to do search and repair and cells later 2. IMPORT DESIGN
have to do ECO checks such as timing ECO, functional ECO,
metal ECO, power ECO and Clock ECO. As all this physical Import design is the fundamental rung in Physical Design.
design steps are done we have to do physical verification In this stage all the requisite inputs & essential references
as it checks the correctness of the generated layout design. are interpreted into the tool plus prime checks are done
This includes DRC (design rule check), LVS (layout vs i.e. design, technology consistency.
schematic), ARC (antenna rule checking), ERC (electrical

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 748
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

2.1 Inputs Required in Import Design 3. FLOORPLAN

Inputs Required Are Gate level netlist, Logical (Timing) & This is the first major step in getting the layout done. Here
Physical views of standard cells & all other IPs used in the floor plan determines your chip quality. At this step, we
design, Timing constraints (SDC), Power Intent (UPF / define the size of your chip/block, allocates power routing
CPF), FP DEF & Scan DEF, Technology file & RC Co-efficient resources, place the hard macros, and reserve space for
files. standard cells. A Satisfactory floorplan can make
2.2 Key checks to Qualify Import Design implementation method (place, CTS, route & timing
closure) cake walk. On similar lines a bad floorplan can
Here Checks of errors and warning have been done while create all kind issues in the design (congestion, timing,
reading netlist, timing constraints, UPF/CPF, black boxes, noise, IR, routing issues). A bad floorplan will propel up
MV design (equivalent to LP checks) and assign & tri the area, power & affects reliability, life of the IC and also it
statements (Usually its checked & fixed after Synthesis) can increase overall IC cost (more effort to closure, more
LVTs/ULVTs)
2.3 Sanity Checks
3.1 Deciding the Utilization factor & aspect ratio
Sanity checks essentially check the condition of
netlist in terminology of timing, it also consists of a. Utilization factor decides the size of the block meaning
read-through the issues allied to library files, timing suppose out of 100 percent we give utilization factor of 70
constraints, IOs and optimization directives. Sanity
percent it means 70 percent will be used for placing
checks which have been performed are as
macros and instances in the design and remaining 30
1. Library checks: to check the missing cell information, percent will be used for routing purpose to connect all the
missing pin information & if any Duplicate cells present or macros and instances in the design.
not.

2. Design checks: to check the Inputs with floating pins,

nets with tristate drivers, nets with multiple drivers,
Combinational loops, Empty modules, Assign statements b. Aspect ratio gives shape of the block i.e. width/height
3. Constraint checks: to check all flops are clocked or not, example: say height of 1.4 and width of 1.0 is given hence
unconstraint paths should not be present & Input and
it will form a rectangle shape design.
output delays.

Fig -2: Created Floorplan with aspect ratio and

Fig -2: Imported Design utilization factor

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 749
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

c. After utilization and aspect ratio we go for pin iii. Orient macros to minimize distance between pins.
placement. In pin placement we have to place pins legally When you decide the orientation of macros, you also have
to take account of pins positions and their connections.
3.2 Macros Placement
iv. Reserve enough room around macros. For regular
Method to place macros which have been followed in this net routing and power grid, you have to reserve enough
design as follows. routing space around macros. In this case estimating
routing resources with precision is very important. Use
i. place macros around chip periphery. If you don’t have the congestion map from trial Route to identify hot spots
reasonable rationale to place the macro inside the core between macros and adjust their placement as needed.
area, then place macros around the chip periphery. Placing The space between macros is given by equation
a macro inside the core can invite serious consequence
during routing due to a lot of detour routing, because
macros are equal to a large obstacle for routing. Another
advantage to placing the hard macros around the core v. Reduce open fields as much as possible. Except for
periphery is it's easier to supply power to them, and reserved routing resources, remove dead space to increase
reduces the change of IR drop problems to macros the area for random logic. Choosing different aspect ratio
consuming high amounts of power. (if that option is available) can eliminate open fields.

vi. Reserve space for power grid. The number of power

routes required can change based on power consumption.
You have to estimate the power consumption and reserve
enough room for the power grid. If you underestimate the
space required for power routing, you can encounter
routing problems 5. After macro placement we will place
physical cells like endcap and well tap cells

Fig -4: Before macro placement

ii. Consider connections to fixed cells when placing

macros. When you decide macro position, you have to pay
attention to connections to fixed elements such as I/O and
preplaced macros. Place macros near their associate fixed
element. Check connections by displaying flight lines in
the GUI.

Fig -6: Macros Placed

Further after placing the macro we have added keep

out margin to macros, physical cells and cut rows in
Fig -5: Fly line analysis the design.

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 750
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

placement constrains (e.g., there may be overlaps among

modules) while maintaining a global view of whole netlist.
here the Objective is to lessen the interconnect wire
lengths.

Fig -7: added keep out margin on macros

Fig -10: coarse placement of standard cell in the design

Legalization: Legalization makes the rough solution from

global placement legal (i.e., no placement constraint
violation) by moving modules around locally.

Detailed Placement: Detailed placement further

improves the legalized placement solution in an iterative
method by rearranging a small group of modules in a local
region while keeping all other modules fixed. Here the
Objective is to meet design constraints such as
Fig -8: Cut rows applied in the design Timing/Congestion and to conclude standard cell
placement.
4. PLACEMENT

Placement is the process of placing standard cells in the

rows created at Floorplanning stage. The goal is to
decrease the total area and interconnects cost. The trait of
routing is highly determined by the placement.

Fig -11: Detailed and legalized placement of standard cell

5. CLOCK TREE SYNTHESIS

Clock tree synthesis is a course of action which makes sure

that the clock gets circulated evenly to all the sequential
Fig -9: Standard cells placed in the core area elements in a design.

One way to overcome the complication concern is to CTS is the procedure of insertion of buffers or inverters
perform placement in several controllable steps as along the clock paths of ASIC design in order to achieve
discussed below. zero/minimum skew or balanced skew. The goal of CTS is
to reduce skew and insertion delay. Apart from these,
Global Placement: Global placement aims at generating a useful skew is also added in the design by way of buffers
coarse placement solution that may violate some and inverters.

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 751
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

5.1 Pre Clock Tree Synthesis

Setup slack was meeting whereas there where hold

violation present in the design as can be seen in the figure
below.

Fig -15: HTree clock and its schematic with added buffer
and inverter to remove hold violation

As the post CTS was competed the setup and hold timings
where meeting, results shown below

Fig -13: setup time met & hold time violated

Fig -14: clock propagated randomly & clock schematic

before post CTS

5.2 Post Clock Tree Synthesis

Fig -14: setup and hold timings met
After running post CTS scripts provided by the top level
we get well-structured clock tree and adding proper
buffers and inverters to solve the hold violation, results 6. ROUTING AND TIME CLOSURE
shown below.
In routing stage, metal and vias are used to create the
electrical connection in layout so as to complete all
connections defined by netlist this are carried out in two

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 752
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 02 | Feb 2019 www.irjet.net p-ISSN: 2395-0072

types of routing one is global routing and the other is the International Journal of Emerging Technology and
detailed routing. In case of the global routing the Advanced Engineering. IJETAE, 2012 April; 2(4):340–
interconnections between the standard cells connects 6.
loosely, while in case of the detailed routing the detouring 6. neeraj Jain. VLSI design and optimized
of connections are reduced. During the placement of the implementation of a risc processor using xilinx tool.
standard cells also trial route is done to estimate the static International Journal of Advanced Research in
timing analysis weather the design met the timing Computer Science and Electronics Engineering
. in detail routing router runs search and (IJARCSEE). 2012 Dec; 1(10):52–6.
repair routing here it locates shorts and opens and spacing 7. Reaz MBI, Amin N , Ibrahimy MI , Mohd-Yasin F,
violations so, it reroutes the effected area to eliminate Mohammad A. Zero skew clock routing for fast clock
violations. As the fixes are done and timings are met this tree generation. Canadian Conference on Electrical
procedure nothing but called as enginnering change and Computer Engineering. (CCECE). 2008 May; 4–
order(ECO) hence we conclude the physical design flow by 7:23–8.
handing the GDS II file to the further ASIC flow stage. 8. 10. Tsai JL, Chen TH and Chen CCP. Zeroskewclock
tree optimization with buffer insertion/sizing and
wire sizing. IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems. April 2004;
23(4):565–72.
9. 11. KV Rao, A Angeline, VSK Bhaaskaran. Design of a
16 bit RISC processor. Indian Journal of Science and
Technology. August 2015; 8(20):1–7.

Fig -16: Routing stage

7. CONCLUSION

The physical design implementation of the RISC processor

is done by achieving the each and every quality check
during the floorplan, placement, clock tree synthesis,
routing. As we did CTS to meet the skew, duty cycle,
latency, pulse width and the clock tree power compared to
the statistical . An Engineering Change Order
(ECO) is done to ensure the design to meet the required
specifications and timing.

REFERENCES

1. Devaraconda Dinesh and R. Manoj Kumar Physical

Design Implementation of 16 Bit Risc Processor Vol
9(36), DOI: 10.17485/ijst/2016/v9i36/102911,
September 2016
2. Ibrahim D.16-bit microprogrammable microcomputer
with writable control store”. IEEE Trans. Computers.
2011 Nov; 39(11):1385–90.
3. Kahng A, Lienig J, Markov I, Hu J. VLSI physical design:
From graph partitioning to timing closure. Springer,
2011, 27.
4. Mehrotra, Alok, Van Ginneken, Lukas P, Trivedi,
Yatin. Design flow and methodology for 50M gate
ASIC, IEEE Conference Publications, 2003.
5. Sharda PK, Jain GP. Design and implementation of 5
Stages pipelined architecture in 32 Bit RISC Processor.

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 753