A Presentation
On
Direct Memory Access
(DMA)
Department of Computer
Engineering,
M.S.P.V.L. Polytechnic College,
Introduction
• The transfer of data between the memory
and an external device without involving
the micro processor improves the speed of
transfer.
• This transfer technique is called DMA .
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DMA Controller
Address bus
Data bus Address bus
Data bus buffers
buffers
Internal bus
DMA select CS Address register
Register select RS
Read RD Word count register
Write WR
Control
Bus request BR logic Control register
Bus grant BG
DMA request
Interrupt Interrupt
to I/O device
DMA Acknowledge
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DMA Controller
• DMA controller is used to transfer the data between the memory
and i/o device.
• The DMA controller needs the usual circuits to communicate with
the CPU and i/o device.
• In addition to this, it needs an address register and address bus
buffer.
• The address register contains an address of the desired location in
memory.
• The word count register holds the number of words to be
transferred. The control register specifies the mode of transfer.
• The DMA communicates withwww.ustudy.in
the i/o devices through the DMA
Cont..,
• The RD (Read) and WR (write) signals are
bidirectional.
• When the BG (Bus Grant) signal are bidirectional.
• When the BG (Bus Grant) signal is 0, the CPU can
communicate with the DMA registers through the
data bus.
• When BG is 1, the www.ustudy.in
CPU has relinquished the
DMA Transfer ( I/O to Memory )
Interrupt
BG Random access
CPU
memory (RAM)
BR
RD WR Address Data RD WR Address Data
Read control
Write control
Data bus
Address bus
Address
select
RD WR Address Data
DMA acknowledge
DS
RS Direct memory I/O
access (DAM) Peripheral
BR controller device
DMA request
BG
Interrupt
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Process of DMA Transfer
• To initiate a DMA transfer, the CPU loads the
address of the first memory location of the
memory block (to be read or written from) into
the DMA address register. It does his via an I/O
output instruction, such as the OTPT instruction
for the relatively simple CPU.
• It then writes the no. of bytes to be transferred
into the DMA count register in the sane manner.
• Finally, it writes one or more commands to the
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Cont..,
• These commands may specify transfer options
such as the DMA transfer mode, but should
always specify the direction of the transfer, either
from I/O to memory or from memory to I/O.
• The last command causes the DMA controller to
initiate the transfer. The controller then sets BR
to 1 and, once BG becomes 1 , seizes control of
the system buses.
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Input-Output Processor
(IOP)
Central Processing
unit (CPU)
Memory bus
Peripheral devices
Memory unit PD PD PD PD
Input-output
processor (IOP) I/O bus
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Introduction
• IOP :
• Communicate directly with all I/O devices
• Fetch and execute its own instruction
– IOP instructions are specifically designed to
facilitate I/O transfer
– DMAC must be set up entirely by the CPU
• Designed to handle the details of I/O
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processing
Cont..,
• Command
• Instruction that are read form memory by
an IOP
– Distinguish from instructions that are read by
the CPU
– Commands are prepared by experienced
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CPU - IOP
Communication
CPU operations IOP operations
Send instruction
Transfer status word
to test IOP path
to memory location
If status OK. , send
start I/O instruction Access memory for
Message Center
to IOP IOP program
Conduct I/O transfer
CPU continues with
using DMA ; prepare
another program
status report IOP
CPU Program
Program I/O transfer completed
interrupt CPU
Request IOP status
Transfer status word
to memory location
Check status word
for correct transfer
Continue
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CPU - IOP Communication
• The communication between CPU and IOP may take
different forms depending on the particular computer
considered.
• The CPU sends a test I/O instruction to IOP to test the IOP
path.
• The responds by inserting a status word in memory
location.
• The CPU refers to the status word in memory. If everything
is in order, the CPU sends the start I/O instruction to start
the I/O transfer.
• The IOP accesses memory for IOP program.
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Cont..,
• When the IOP terminates the execution of its
program, it sends an interrupt request to the CPU.
• The CPU then issues a read I/O instruction to read
the status from the IOP.
• The IOP transfers the status word to memory
location.
• The status word indicates whether the transfer
has been completed satisfactorily or if any error
has occurred during thewww.ustudy.in
transfer.
The End
Thank U
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