Emerging Nonvolatile Memory (NVM) Technologies

An Chen
TD Research, GLOBALFOUNDRIES
Santa Clara, USA 95054
[email protected]

Abstract — Significant progress has been made recently in NVMs include memories based on novel materials and
emerging nonvolatile memories (NVMs). This paper will discuss mechanisms drastically different from mature memories based
advantages and challenges of several promising NVM devices, as on Si CMOS. They are made of ferroelectric oxides,
well as their potential applications. Changing market trends ferromagnetic metals, chalcogenides, metal oxides, carbon
toward mobile, IoT, and data-centric applications create new materials, etc. Their switching mechanisms extend beyond
opportunities for NVMs. High-performance NVMs may enable classical electronic processes, to quantum mechanical
novel architectures and designs, e.g., more uniform memory phenomena, ionic reactions, phase transition, molecular
hierarchy, co-located logic and memory, and fine-grained power reconfiguration, etc. Many of them also share some common
gating. Storage-class memories based on high-density NVMs
features, e.g., nonvolatile states, two-terminal structures, etc.
could fill the performance and density gap between memory and
storage. Some unique characteristics of emerging NVMs can be
Among these emerging NVMs, four major candidates will be
utilized to extend their applications beyond memory space, e.g., discussed in more details in this section.
synaptic functions, security elements, etc.
Memory
Keywords — nonvolatile memory, storage, memory hierarchy,
architecture, selectors, neuromorphics, security Volatile Nonvolatile
SRAM Baseline Prototypical Emerging

Flash FeRAM Ferroelectric Memory

I. INTRODUCTION DRAM
Stand-alone NOR PCM FeFET
Temporary and permanent data storage is required in any Embedded NAND MRAM FTJ
functional information processing systems, which has so far STT-RAM ReRAM
been fulfilled by CMOS-based SRAM, DRAM, and Flash Electrochemical Metallization Bridge
memory. The speed gap between logic and memory has Metal Oxide - Bipolar Filamentary
become a critical system performance bottleneck, i.e., the Metal Oxide - Unipolar Filamentary
“memory wall” [1]. Hierarchical memory systems made from Metal Oxide - Bipolar Nonfilamentary
devices with varying speed, density and cost have been Mott Memory
adopted to optimize the performance-cost tradeoff. With Carbon Memory
CMOS scaling approaching fundamental limits, some novel Macromolecular Memory
concepts of memory devices have been proposed in recent Molecular Memory
years [2]. Although high-performance computing is still a key
driver for semiconductor technology innovation, consumer Fig. 1. Memory taxonomy with variety of emerging NVMs.
electronics is shifting toward mobile, pervasive connectivity,
and data-centric applications. The changing market trends
impose different hardware requirements, e.g., ultra-low power, B. Phase change memory (PCM)
high-density low-cost data storage, etc. Emerging NVMs with PCM is based on reversible transition between crystalline
improved speed, scalability and retention may become more phase (low resistance) and amorphous phase (high resistance)
important technology enablers for efficient and intelligent of chalcogenides [3]. The transition from amorphous to
hardware systems. crystalline phase (set) limits PCM performance (speed) while
the reverse process (reset) is the power-limiting step. PCM
II. EMERGING NVM DEVICES AND ASSESSMENT performance depends critically on the property of phase change
materials and cell design. The microscopic mechanisms of
A. Variety of emerging NVM devices phase change in Ge-Sb-Te (GST) alloys have been thoroughly
studied, which help to guide material engineering to improve
Fig. 1 shows the memory taxonomy from the 2013 ITRS device characteristics [4]. PCM cells need to be designed to
Emerging Research Devices (ERD) chapter [2]. The so-called simplify processing, optimize power efficiency (i.e., improve
“prototypical” category contains memories with prototype test- thermal isolation), and reduce reset current. Overall, phase
chips or even products, which covers a wide range of maturity change materials demonstrate desirable scaling behaviors, e.g.,
levels. Some of them have been commercialized (e.g., phase transition at highly scaled dimension (several nm in thin-
FeRAM, MRAM), while some may still be considered film thickness or nanoparticle diameter), higher crystallization
“emerging” (e.g., STTRAM). Both prototypical and emerging

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temperature (i.e., longer retention) at smaller dimension, ≥60min), which is still an active target for STTRAM R&D [9].
decreasing thermal conductivity (i.e., higher power efficiency) STTRAM is highly sensitive to the fabrication process, e.g.,
with thinner films, linear dependence of threshold voltage on substrate smoothness, etching damage, encapsulation, etc.
device size, improved endurance at smaller dimension, etc. Optimization of the magnetic and electrical properties of MTJs
PCM cell size is limited mainly by access devices due to with many layers of ultra-thin ferromagnets, non-magnetic
relatively large current required for switching. Bipolar metals, and oxides depends on well-understood device physics
junction transistor (BJT), vertical transistor, and even diode and carefully controlled material engineering.
have been experimented as access devices to reduce PCM cell
size. PCM failures could be caused by void formation at Some recently reported spintronic phenomena may further
electrodes, change in mass density, elemental segregation, etc. improve STTRAM design and performance. A discovery of
large change of magnetic anisotropy of Fe(001)/MgO(001)
PCM is among the most developed novel NVMs and has junction by a small electric field may help to reduce STTRAM
demonstrated promising performance (e.g., <100ns switching switching power [10]. A giant spin Hall effect (SHE) may
speed, >109 cycle endurance). However, its initial target of provide a more efficient source of spin torque to switch MTJs
replacing incumbent memories (e.g., Flash or even DRAM) [11]. These discoveries offer new opportunities to continue the
has not been achieved due to both continuous improvement of advancement of STTRAM technologies.
incumbent memories and limitations of PCM itself (e.g., cost)
[5]. Although it is relatively easy for PCM to meet standalone D. Resistive random-access-memory (RRAM)
Flash memory requirements, achieving both high speed (~ns)
RRAM typically refers to the electrical switching between
and long endurance (>1012 cycles) for working memories is
different resistance states observed in numerous metal oxides
still very challenging for PCM. Atomic-level engineering by
(e.g., NiOx, HfOx, TiOx, TaOx, PrCaMnO4), although similar
doping GST materials may improve both speed and endurance
phenomenon has also been reported in non-oxide materials
[6]. Applications with high reliability targets (e.g., long
(e.g., silicon, sulfides, chalcogenides). An early report of
retention at high temperature for automotive) would require
RRAM based on simple binary metal oxide attracted great
much higher crystallization temperature. PCM has also
attention, owing to promising scalability, CMOS compatibility,
demonstrated the potential for novel applications, e.g., storage
and reasonable performance for post-Flash NVM solutions
class memory, ternary content addressable memory (TCAM),
[12]. Interest in RRAM was further enhanced by the discovery
neuromorphics, etc.
of resistive switching in ALD HfOx, usually with reactive caps
to create sub-stoichiometric oxide needed for switching [13].
C. Spin-transfer-torque random-access-memory (STTRAM) Recent focus is shifting to materials with more stable switching
STTRAM improves the writing mechanism of conventional behaviors (e.g., TaOx [14]) and multi-oxide stack with multiple
field-switching MRAM with spin transfer torques, which is optimization knobs (e.g., oxide compositions, interfaces) [15].
more efficient and more scalable. The memory element is the
same magnetic tunnel junction (MTJ) with two ferromagnetic Conductive-Bridge RAM (CBRAM) is a type of RRAM
layers separated by an ultra-thin oxide barrier (typically 1-2 nm with a reactive electrode that supplies mobile ions (e.g., Cu+,
thick MgO). The parallel and anti-parallel orientations of the Ag+) to migrate across insulating dielectrics (a.k.a. solid-state
two ferromagnetic layers contribute to low and high resistance electrolytes) and form metallic filaments in the on-state.
states, respectively. STTRAM with in-plane magnetic Various types of solid-state electrolytes have been tested for
anisotropy has entered early commercialization (64Mb with CBRAM, including oxides, sulfides, chalcogenides, Į-Si, etc.
90nm CMOS process) [7], while further scaling has focused on CBRAM has demonstrated large on/off ratio, fast speed, and
MTJs with perpendicular magnetic anisotropy (PMA) [8]. long endurance, although retention still needs improvement. A
Among all NVMs, STTRAM demonstrates the highest 16Gb CBRAM test chip has been reported recently [16].
performance (measured by <10ns write speed and >1012 cycle Tradeoffs exist among key RRAM parameters, e.g., speed-
endurance) and is the most promising candidate for embedded retention, power-speed, endurance-retention, etc. A major
NVMs. Although STTRAM bit-cell size is much larger than challenge of RRAM is reliability, mainly variability and
MTJ size (due to the large size of access transistors required by failure. RRAM switching is generally attributed to the
high switching current), STTRAM is still smaller than SRAM. formation and rupture of conductive filaments inside of
With nonvolatility, STTRAM can also save standby power and insulating oxides. The switching process is not controlled
simplify the memory hierarchy. microscopically and is intrinsically stochastic, which is
STTRAM still faces some critical challenges. With small reflected in the large variation of device resistance and
on/off ratio (measured by tunneling magneto-resistance, TMR), switching voltage from cycle to cycle and from device to
STTRAM needs well-designed reading methods and is device [17]. The failure mechanisms of RRAM are still not
sensitive to the increasing variability with scaling. Reducing well understood. Statistical characterization tools and
the MTJ size and switching current while maintaining dielectric breakdown models have been increasingly utilized in
sufficient thermal stability (i.e., retention) requires device and RRAM research.
material innovations, e.g., PMA, dual-MgO structure,
composite free-layer, etc. The distributions of read voltage, E. Ferroelectric-FET (FeFET) memory
write voltage and breakdown voltage have to be separated with In FeFET, a ferroelectric layer is used in the gate dielectrics
abundant margins in large arrays. Embedded memories have of a FET, where the change of ferroelectric polarization
to meet stringent BEOL thermal budget (typically 400°C for modulates FET channel conductance. FeFET is similar to

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Flash but with different data storage (ferroelectric polarization compatible with those of the memory elements. Bipolar
instead of floating gate). FeFET is not a new concept, but its switching memories require bi-directional selectors (e.g.,
development has been hindered by depolarization field and nonlinear devices), while rectifying diodes only work for
gate leakage [18]. Recent discover of ferroelectricity in doped unipolar switching memories. Selector assessment should be
HfOx has reignited interest in FeFET [19]. Ferroelectric HfOx conducted in a comprehensive framework incorporating array
may significantly improve the scalability of FeFET. With full design/operation parameters, memory element characteristics
CMOS-compatibility, simple 1-transistor (1T) structure, and and selector device properties.
the performance close to that of DRAM, HfOx-based FeFET
may provide another promising eNVM candidate. Both RRAM and STTRAM provide promising NVM
solutions, but each excels in different application space
(density vs. performance) [21]. The selector devices have
F. Comparison of other emerging NVMs mostly been explored for RRAM in high-density arrays.
Other emerging memory candidates in Fig. 1 will not be STTRAM has large cell size due to access transistors. With
discussed in details in this paper. Fig. 2 provides a comparison suitable two-terminal selectors, it may also be possible to build
of the six NVM candidates in the “emerging” category, based STTRAM in a CBA or a shared-access-transistor structure to
on a critical review conducted by ERD using eight criteria [2]. reduce effective bit size [22]. If successful, a high-density
1
Scalability
STTRAM array enabled by proper selectors may be integrated
CMOS
3 with a high-performance STTRAM array to meet the needs for
Architectural 8
2
2Speed both working memories and data storage.
Compatibility FeFET

1 RRAM Memory Selector Devices

CMOS Mott
Technological7 0 3Energy
Efficiency Macromolecular Transistor Diodes Volatile switch Nonlinear devices
Compatibility
Molecular
Planar Si diodes Threshold Tunneling-based
Room Carbon switch nonlinear selectors
6
Temperature
4 ON/OFF
"1"/"0" Ratio
Operation Vertical Oxide/oxide
heterojunctions MIT switch MIEC
Operational 5Reliability

Metal/oxide Schottky Complementary

Fig. 2. 2013 ITRS ERD critical review of emerging memories with eight junctions structures
criteria, where “3” and “1” represent the best and the worst assessment.
Reverse-conduction Intrinsic
diodes nonlinearity
RRAM stands out as the most promising among them,
followed by FeFET memory. “Carbon-based memory” refers Self-rectification
to mixed types of materials (e.g., carbon nanotube, graphene,
amorphous carbon, etc.) and has attracted growing interest.
“Molecular memory” is pursued mostly for ultimate scalability, Fig. 3. Different types of memory selector devices.
while its general performance is relatively poor. Progress has
been made on “Mott memory” based on metal-insulator IV. EMERGING NVM APPLICATIONS
transition, and materials with high transition temperature are
needed in practical applications. “Macromolecular memory” A. Replacing or improving incumbent memories
are useful in flexible electronics and low-cost applications, but
with limitations in performance and reliability. Replacing existing memories is often the first justification
for a new memory device, e.g., STTRAM to replace SRAM
(L2/L3 cache) or DRAM, RRAM to replace Flash memory,
III. SELECTOR DEVICES etc. Replacement is a straightforward objective with easily
A functional memory cell needs both a memory element quantified benchmark criteria. However, existing technology,
(i.e., an on/off switch) and a selector (to select it in an array). product requirements, and business infrastructure also impose
Flash memory combines the selector (FET) and the memory high entry barriers for new technologies. Overcoming such
element (floating gate) in one device. The simple two-terminal barriers would require new technologies to provide significant
structure of emerging NVMs contributes to their promising performance, scaling, or cost advantages.
scalability but also imposes the requirement of dedicated Although STTRAM may reach the speed and endurance
selectors for them to be functional. Transistors are the most comparable to SRAM, its initial application may target lower
effective selectors but may undermine the scaling advantages performance requirements (e.g., eFlash replacement) to ease
of these NVMs. High-density cross-bar arrays (CBAs) require the entry to production. Further process improvement and cost
two-terminal selectors, which could be rectifying diodes, reduction may help to exploit the full potential of STTRAM.
nonlinear devices, or volatile switches, as shown in Fig. 3. The The performance of different RRAM devices varies in a wide
asymmetry or nonlinearity in their characteristics helps to range, but their primary advantages lie in scalability and simple
reduce sneak leakage to ensure the operation of CBAs [20]. structures/processing, suitable for high-density data storage.
Selectors need to provide sufficiently high on-current required However, it is increasingly difficult to compete with vertical
for memory switching and their on/off ratio determines feasible 3D NAND in terms of density and bit-cost. More promising
CBA size. Their speed, endurance, and scalability need to be opportunities for RRAM may exist in applications requiring

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the performance beyond the capabilities of Flash memories, be kept in on-state to avoid data loss. SRAM can be turned off
e.g., low-voltage switching, fast speed, long endurance, etc. in long standby mode, but only after all the data have been
RRAM has also been experimented for flexible electronics. transferred to permanent storage which takes long time (up to a
few hundred μs). Low-voltage operation also has limitation for
Embedded NVMs (eNVMs) play increasingly important
SRAM due to robustness degradation and therefore larger cell
functions in micro-controller units (MCUs) for industry and
design (e.g., 10-transistor SRAM) may be required. Flash
automotive applications, as well as consumer electronics [23-
memories are not suitable for these applications because of
24]. The real-time code-execution/customization and data
their high writing voltage and power. Emerging NVMs with
management capabilities enabled by eNVM improve system
lower switching power/voltage offer opportunities to design
performance, enhance security, and lower cost. These have so
“normally-off” memory systems to eliminate standby power.
far been fulfilled by OTP, MTP, and eFlash (e.g., 1T NOR,
Nonvolatile cache would significantly accelerate data storage
split-gate flash). Embedded NVM needs to be compatible with
and enable more fine-grained power gating design. The benefit
logic platform, which becomes more challenging in advanced
of standby power saving needs to be balanced with the increase
nodes and may create opportunities for emerging NVMs
of active power, which depends on both activity factors in
typically built in BEOL. Emerging NVMs may even provide
memory hierarchy and NVM characteristics [27]. Reducing
higher performance beyond the capability of eFlash. At the
the active power of STTRAM through material and device
same time, reliability of emerging NVMs has to be further
engineering will determine the feasibility of utilizing STTRAM
improved for embedded applications, especially in automotive
for these low-power designs.
space with stringent thermal stability and zero defect rate
requirements. Optimization for eNVM is very different from Data movement in von Neumann architectures consumes
that for standalone memories, in terms of targeted robustness, high power and slows down system speed. New architectures
stability, power efficiency, and cell size; therefore, different with localized data (at or near computing units) may achieve
development strategies need to be adopted. Emerging NVM better speed and efficiency. Emerging NVMs offers promising
candidates in section II provide a wide range of potential technology options for non-von-Neumann architectures where
performance and scalability, and may fulfill the needs of logic and memory functions are more closely integrated or
different embedded applications. inter-mixed. By inserting simple two-terminal NVM elements
(e.g., MTJ, RRAM) in logic gates (e.g., SRAM, adder, look-
B. Memory hiearchy and storage-class memory (SCM) up-table), it is possible to create “nonvolatile logic” with built-
From high-speed L1 cache to high-density hard disk drive in memory. NV logic reduces data movement to increase
(HDD), access speed varies more than seven orders of throughput and reduce power. The built-in memory may also
magnitude in the memory/storage hierarchy designed to enable novel architecture and designs, e.g., latch-less pipeline
optimize the cost-performance tradeoff. SRAM-based cache design, systolic architectures.
has accounted for a major portion of power consumption in
mobile CPU or SoC. Scalable high-performance NVMs (e.g., V. BEYOND MEMORY SPACE
STTRAM) with speed and endurance close to those of Some unique characteristics of emerging NVMs may
SRAM/DRAM may provide nonvolatile working memory that extend their applications beyond the memory space.
could enable more “uniform” memory systems with
significantly improved performance. A. Brain-inspired computing and synaptic functions
5 6
While DRAM is ~ 100× slower than cache, it is (10 –10 )× Brain achieves very high performance with extremely low
faster than disk drive [25]. Closing this speed gap between power through massive parallelism, in comparison to today’s
memory and storage would have great impact on system computers. In neuro-networks, synapses connect neurons and
performance and cost. SCM defines such a perspective for play key functions in the learning process. One of the well-
emerging NVMs to reach access speed close to DRAM and at known learning rules is the “spike time dependent plasticity”
the same time have the bit-cost close to that of HDD [26]. It (STDP), i.e., synaptic weight modified by the timing difference
combines the benefits of random access of memories and the between pre- and post-synapsis neuron signals [28]. It has
archival capabilities of HDD. SCM requires a solid-state been shown that the analog behavior of some emerging NVMs
NVM with excellent scalability and preferably multi-level cell (e.g., PCM, RRAM) can be utilized to implement synaptic
(MLC) design, as well as extremely effective manufacturing at functions [29]. By fine-tuning the incremental change of NVM
ultra-high areal density. It would greatly simplify the memory resistance with switching pulses, potentiation and depression of
and storage hierarchy, and revolutionize large-scale computing “synaptic weight” (typically coded in the NVM resistance) can
systems. So far, PCM and RRAM have been considered the be imitated. The promising scalability of emerging NVMs
top candidates for SCM. may help solid-state neuro-network to reach the synaptic
density close to that in brains (~1010 cm-2).
C. Enabling novel architectures and low-power design
Wireless sensor network for Internet of Things (IoT) has B. Hardware security
more restrictive power budget than mobile devices. These Variability and stochastic mechanism are major challenges
systems spend much of their lifetime in sleep mode. The for RRAM. Another chaotic behavior frequently observed in
standby power of their memory system dominates total energy RRAM is the Random telegraph noise (RTN) that can be
consumption. Volatile SRAM in short standby state still has to attributed to the charging and discharging of traps in the oxides

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