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CHAPTER 1
INTRODUCTION

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INTRODUCTION
1.1 INTRODUCTION TO VLSI TESTING

The functionality of electronic equipment’s and gadgets has achieved an

outstanding growth over the last twenty decades whereas their physical sizes and weights
have shrunk drastically. The major reason is because of the fast advances in integration
technologies that permit fabrication of many transistors on a single microcircuit (IC) or
chip. Each IC within the industry follows Moore’s law. According to Moore’s law, the
number of transistors (transistor density) on a chip doubles for every 1.5 years. With the
advancement in the sub-micron technology a large number of cores are coordinates on a
single chip, however the density and complexness of the ICs continuously increasing, this
may leads to several manufacturing faults and device failure. As the transistor count
increases further, the device feature size is reduced. In reduction with the feature sizes
increases in the manufacturing faults and the fault detection becomes terribly
troublesome. VLSI testing plays an important role to verify whether a device works
properly or not. Testing can be used in various applications such as automotive, medical,
military, aviation, and telecom applications etc., where self testing of the circuit is
required.

Previously testing can be done through automatic test equipment (ATE), a

conventional testing method which is no longer able to handle the ever-growing
challenges. To resolve this issue the BIST schemes are widely used in which circuit
analysis in the chip turns into a simple task as the time and cost prerequisites are low.
Built in Self Test(BIST) is a technique that allows a machine to test itself and it is a
design for testability(DFT) technique which reduces the complexity, subsequently decline
the cost and reduce the dependence up on the external test equipment unlike Automatic
test equipment (ATE). For present day scan based designs mostly BIST is widely adopted
as the testing technique. The basic BIST architecture known as STUMPS consists of test
controller, pattern generator (PG), unit under test (UUT) and reaction/response analyzer.
PG, synchronizer and response analyzer are controlled by test controller which controls
the test execution. Selection of PPRG plays an important role in generating test patterns
which consists of a series of random numbers.

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1.2 INTRODCUTION TO BIST

Built in self test is a design for testability (DFT) scheme originated with the idea
of including pseudo random number generator and a cyclic redundancy check on the IC,
in which parts of the circuit are used to test the circuit itself and the circuit parts must be
operational to execute the self test. The main purpose is to reduce the complexity as well
as the cost and reduces the reliance up on the external test equipment. Engineers design
BIST’s to meet the requirements such as high reliability and lower repair cycle times and
cost of testing during manufacturing. A simple BIST architecture is shown in figure 1.1.
BIST mainly operated in two modes based on the operational conditions of the unit under
test that are as follows:

a) Online testing
b) Offline testing

Figure 1.1: A typical BIST architecture

testing that occurs under the normal functional operating conditions in which there is no
test mode is called as online testing which is known as real time testing where as testing a
system which is not under normal functions is called as offline testing it consists of test

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mode. BIST can be used for concurrent/non-concurrent testing of both logic and memory
parts of a system.

The main cause for the widespread of BIST schemes are the fast-rising costs of ATE
testing and the increasing in the complexity of integrated circuits. Now-a-days we can
see the complex devices that have functionally different blocks built on different
technologies inside them. Such complex devices require high-end mixed-signal testers
that possess both digital and analog testing capabilities. BIST can be used to perform
those special tests with additional on-chip test circuits, eliminating the need of such
high-end testers. BIST is also one of the solutions to the testing of complex circuits
that have no boundary connections to the external world, for example embedded
memories that are used internally by the devices. In the near future, even the most
advanced tester may no longer be adequate for the fastest chip, a situation where the
self testing is the best solution.

1.2.1 BUILDING BLOCKS OF BIST

The basic BIST architecture consists of consists of a test controller, pattern

generator, unit under test and a response analyzer also known as STUMPS architecture is
as shown in figure 1. Pattern generator, synchronizer and response analyzer are controlled
by the test controller and control the test execution. The inputs are provided by the
pattern generator which generates the test patterns are the inputs to unit under test.
Pattern generators are of different types, selection of pattern generator plays a major role
in testing of BIST architecture. The unit under test comprises of both combinational and
sequential circuits it is the application dependent. Depending up on the application the
UUT varies, the inputs that are provided to UUT are from the pattern generator. There is
also another input which is the normal input without any pattern generator. Depending
upon the mode of testing one of them will act as input to the UUT. Synchronizer
synchronizes the output of the unit under test. Response analyzers are used to compare
the obtained results with the expected results. The output will be either 1’s or 0’s.

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Figure.1: Basic BIST (STUMPS) architecture

1.2.1.1 Components of a BIST system

The contentable blocks of a BIST system is as follows
1. Logic to be tested or called as unit under test (UUT) In case of BIST, the
logic to be tested in the BIST is considered as unit under Test (UUT). Any
random logic residing on the chip can be brought under BIST following a certain
procedure.
2. PG (Pattern Generator) A PG generates input patterns that are applied to
internal scan chains of the UUT for BIST testing. In other words, PG acts as a
Test Pattern Generator (TPG) for BIST scheme. It can be either a counter or an
LFSR for pattern generation.
3. MISR (Multi-Input Signature Register) or Synchronizer obtains the response
of the device to the test patterns applied. An incorrect output indicates a defect in
the UUT. In traditional, MISR acts as ORA (Output Reaction Analyzer) for BIST
testing.

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4. A master (BIST controller) the controller controls the functioning of the

BIST i.e. clocks propagation, initialization and scan patterns in and out of the
scan chains and executes the testing.

1.2.2 TYPES OF BIST VERSIONS

BIST is a concept that allows a system to check itself and produced as a part of
the chip. There are several types of BIST that are differentiated according to the
implementation some of them are

A. Programmable Built in self test (PBIST)

B. Memory Built in self test (MBIST)
C. Logic Built in Self Test (LBIST)
D. Analog and Mixed signal Built in self test (AMBIST)
E. Continuous Built in self test (CBIST)
F. Automatic Built in self test (ABIST)
G. Periodic Built in self test (PuBIST)

PBIST is a memory design for test feature that incorporates all the test systems in
to the chip. Using this systems implemented on-chip are algorithmic address and data
generator, program storage unit and loop control mechanisms. PBIST mostly used for
large memory chips that operate at high frequency and have high pin count. The main
purpose of using this type of BIST is to avoid the expensive testing equipment. It enables
low-cost implementation by adopting a memory test algorithm that uses memory under
test for programming the test data.

MBIST is employed for testing the memory blocks; the logic of MBIST is within
the memory blocks only. To verify the functionality of the memory blocks several
algorithms are used such as March algorithms, checker board algorithms and varied
pattern background algorithms etc. The basic memory BIST interfacing is shown in
figure.2

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Figure.2: Basic BIST Memory

One controller can control all the memory blocks, memory share the resource
depending upon the test time requirement and the types of memories. In these all the
memories are tested in parallel with reduced time and cost using simple memory
algorithms.

Logic BIST is a self test mechanism used to test the random logic. In these a
simple pattern generator, synchronizer, unit under test, test controller and a response
analyzer are present. The lbist is embedded within the single IC chip. The basic LBIST
architecture is shown in figure.3 the logic to be tested are considered in unit under test.
The overall operations are controlled by the test controller. Finally the output may be
either 1 or 0. Using LBIST it can be tested even at higher frequencies and also reduces
the test time and also it can test the logic without any external peripherals.

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Figure.3 Basic LBIST architecture

The basic logic bist is a simple STUMPS (Self test using MISR and PPRG)
architecture. The compaction in the circuit can be done either by space or time
compaction. The controller controls overall test circuit there are some other types of
BIST schemes that are used to test the circuit under test, which can able to test the cores
parallel. Mostly LBIST and MBIST are used to test the logic circuits. This thesis focuses
on Logic BIST that has a random number generator for generating the test patterns to the
logic under test.

One other acronym “ABIST” which stands for two different BIST techniques: the
analog BIST approach for testing analog circuits and array BIST approach for testing

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embedded memories. It becomes an alternative method to the rising costs of external

testing and the increasing complexity of the systems. This approach can found great
deployment in a wide variety of applications as more and reliable BIST techniques are
developed. However the BIST replaces the automatic test equipment. Even now BIST
theory is optimistic but still someday there will be the preferred mode of testing. While
implementing the BIST we have to consider the total area occupied by the bist circuits,
external supply, requirements of bist, test time and effectiveness of bist, flexibility and
changeability of bist i.e., is it reprogrammable or not and finally impact of the BIST.

1.2.3 ADVANTAGES OF BIST

Implementing BIST architecture includes many applications such as

1) Reduced need for external test equipment

2) Easier customer support
3) Better fault coverage
4) Reduces the manufacturing test time and cost
5) Reduces the time to market
6) At-speed testing
7) More economical burn in testing
8) Capability to perform the tests outside the production environment
9) Reduces the storage and maintenance of test patterns
10) Can test many circuits in parallel

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1.2.4 APPLICATIONS OF BIST

Manufactures mostly employing BIST in real time products, it has been proposed
for many applications in the fields for testing such as: medical devices, communication
systems, automotive electronics, all types of complex machinery and integrated chips.
Some of the examples circuits in which bist are used: exhaustive test in the INTEL
80386, pseudo random test in IBM/RISC 6000, embedded cache memories of MC68060,
ALU based programmable misr of MC68HC11 etc.

Figure.4 Applications of BIST

1.3 CONTRIBUTION OF THESIS

The thesis mainly focuses on the realization of a non-linear function such as

substitution box (S-Box) random number generator for generating the various random
numbers. The designed random number generator is used in the application of Logic built
in self test for generating random patterns in PPRG and a simple LFSR based random
number generator was also designed and used as lbist sub-block. The design and
simulations of the proposed s-box based LBIST and conventional method was done using

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Xilinx Vivado 18.2 tool with the technology library of 22nm. The obtained results are
compared in terms of area and randomness and future scope of the s-box based random
number generator are explained.

1.4 ORIGIN OF THE PROBLEM

The following are the few problems that are considered in the design Logic BIST are as
follows:

 With the advancement in the sub-micron technology a number of cores are

coordinates on a single chip which increases the complexity of the chip, then testing
through ATE becomes complex.

 Testing of a device can do internally by itself through a BIST scheme which reduces
the complexity and the test time of the device.

 The BIST scheme mainly classified in to two types for testing the device those are
Logic BIST to test the logic circuits and Memory BIST to test the memory cores.

 In LBIST, selection of random number generator plays a major role that challenges
the operation of the BIST.

 A non linear substitution box has been considered to provide more secure and
randomness to the pattern generator, which used in the design of lbist.

1.5 SCOPE OF THE PROBLEM

The thesis presents, work on the design of the Logic built in self test using a non linear
substitution box as pattern generator. The major contributions of the thesis are as follows:

 To design the linear feedback shifter register based random number generator.

 To design the linear feedback shifter register based random number generator.
 To design non linear substitution box and use this in the design of random number
generator with the combination of lfsr.

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 To design all the contentable blocks present in Logic BIST using lfsr as pattern
generator for generating test patterns.
 Replacing the pattern generator by s-box based random number generator and design
the LBIST.
 Comparison of both lfsr based LBIST and the s-box based LBIST in terms of test
pattern coverage, randomness, gate count and the area.

1.6 THESIS ORGANISATION

The thesis is organized into 5 chapters and their contents is briefly outlined as follows:

In chapter 1, a brief introduction of VLSI testing, built in self test and types of bist architectures
also, problem definition and scope of thesis are mentioned.

In chapter 2, literature survey for the progression of project is presented on the topics of etc.

In chapter 3, a brief introduction of Logic bist and internal architectures are mentioned.

In chapter 4, a brief explanation of the Xilinx vivado tool

In chapter 5, methodology of the proposed substitution box and the other type of random number
generators are explained.

In chapter 6, the synthesized and simulation results of all thee logic bist blocks are described

In chapter 7, the conclusion for the overall thesis and project future scope is mentioned

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CHAPTER 2
BACKGROUND LITERATURE

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