1

EE254 D2 Buck Converter

Analysis and Design
Neil Hildick-Smith
Dept. of Electrical Engineering
Stanford University

Abstract—A D2 buck converter was designed as a front-end

bus converter for a 48V high-reliability compute application. The
stage directly accepts a wide bus voltage range while generating
an output voltage sufficiently low to directly power the many
POL converters need to drive a high-powered SoC.
In the context of this application, this unusual topology
presents enticing benefits relative to a traditional buck. The step-
down ratio of buck converters are practically constrained by the
linear scaling of input-output to duty cycle–with ratios above
ratios of 15:1 encountering minimum on-time limitations. The
D2 sidesteps these issues, making for an interesting paper study
into what a non-traditional buck front-end could look like.
Fig. 1. The two intervals in a switching cycle–D and D’ respectively.
Requirement Units Min Typ Max
Input Voltage V 34 48 60
Output Voltage V 3.8 4 4.21 By examining these two states, the following equations were
Output Current A 10 20 30 developed. There is one equation per energy storage element
Load Slew Rate A/µs - - ±100
in addition to an equation for the input current of the converter.
This paper provides detailed analysis of the D2 topology. Once hVL1 i = DVin − Vcx
derived, analytical expressions are used to guide component
selection, compensate the stage and design a CISPR-22 compliant
hVL2 i = DVcx − Vout
EMI filter. The end result is a fast, AECQ bus converter that is hICx i = IL1 − DIL2
able to meet tight output requirements with a small footprint.
hICl i = IL2 − Iout
Nonetheless, in spite of the compelling aspects of this design,
practical considerations will ultimately still drive the selection hIin i = DIL1
of a traditional buck topology. The additional complexity of D2
could reasonably be weighed with the benefits however the lack These equations, derived from KCL and KVL applied
of applicable off-the-shelf controllers is a deal-breaker. Ironically to Figure 1, were subsequently re-represented as equivalent
however, the same practical considerations that result in the circuits. The inductors and capacitors have been represented
topology being impractical also lend purpose to this investigation. in light gray. This coloration emphasizes that volts-second
None of the equations and analysis presented here exists on
the internet. As a result this paper represents a compelling litmus
balance and charge-balance of Periodic Steady State (PSS)
test of analytical experience and practical design known-how. dictate that there is no net voltage or current across these
respective elements over a switching period.

I. D ESIGN
A. Steady State Behavior

T HE topology was examined across its switching cycle.

The converter goes through two states in a given switch-
ing cycle. These states are shown in Figure 1.

Fig. 2. Circuit representations of the periodic steady state behavior of the

four energy storage elements and input source.

1 Combine transient and steady state worst case. Assumes transient load These five circuits can be combine through ideal transform-
step goes from 10% above IMIN to 90% of IMAX ers and basic manipulation to result in Figure 3.
 2

Vout D2
=
Vin Rind,1 2 Rind,2 Ron
1+ D + + (1 + D + D2 )
Rload Rload Rload
| {z } | {z }
Inductor Loss MOSFET Loss
1
Fig. 3. Non-linear average circuit model of the converter. η= Rind,1 2 Rind,2 Ron
1+ Rload D + Rload + Rload (1 + D + D2 )

This circuit captures the equivalent, non-linear Average

Circuit Model (ACM) behavior of the converter. By letting the Lastly, the derived efficiency expression was explored
input frequency go to zero, the inductors and capacitors fall graphically. Efficiency partials were plotted in Figure 5. Each
out of Figure 3 and the DC transfer function of the converter plot focuses only on the effect of that given source of ineffi-
can be seen by inspection. The PSS equations for hVL1 i and ciency, with the other sources zeroed out. The worst-case ratios
hVL2 i, can be used to derive VCx . of the subsequently selected components were back-annotated
on to this plot.
Vout Vout
= D2 VCx = DVin =
Vin D
From here the converter requirements can be revisited and
one can solve for other operating characteristics–including the
converter’s required range of duty cycles.

TABLE I
S TEADY S TATE N UMERIC VALUES

Parameter Units Min Nom Max

D - 0.26 0.29 0.34
RL,eff mΩ 400 200 133

B. Loss Components
ACM equations of the previous section were revisited with
an additional level of detail: the modeling of synchronous
loss components. The power level of the application drives
a synchronous implementation of the topology–for treatment
of a non-synchronous implementation, see Appendix B.

hVL1 i = DVin − Vcx − IL1 Rind,1

hVL2 i = DVcx − Vout − IL2 Rind,2 − DIL2 Ron Fig. 5. Efficiency partials showing the relative duty cycle and load dependency
of each loss mechanism included in the model. The highlighted regions
hICx i = IL1 − DIL2 indicate the operating points of the converter.
hICl i = IL2 − Iout
hIin i = DIL1 One take away is that the efficiency of this topology is
substantially more sensitive to MOSFET on-resistance than
This system of equations was translated into individual circuits inductor DCR in the regions associated with this application.2
and solved to result in the ACM in Figure 4. This insight is helpful in determining how to prioritize opti-
mization trade-offs during the component selection process.

C. Boundary Mode Condition

From here, the Boundary Mode Condition (BMC) of con-
verter was analyzed. As the converter is being designed to
operate exclusively in CCM, it is important to know the bound-
ary condition to appropriately select inductor and switching
Fig. 4. Non-linear ACM of a lossy the synchronous converter. When loss frequency values to ensure CCM operation across the entire
elements are set to zero, the circuit reduces to that of Figure 3.
specified load range.
From here, the ACM was again analyzed at DC–yielding 2 Note only resistive loss mechanism are considered here. Core losses and
equations for the conversion ratio and efficiency as functions AC winding are address latter. Switching, deadtime and COX switch loss
of: the loss elements, duty cycle, input voltage and load. mechanisms are not treated in this paper.
 3

it becomes visually apparent how large K must be for CCM

operation across the full range of loads.

Fig. 6. Annotated waveforms of inductor current in CCM.

Fig. 7. Plots of Kcritical against duty cycle and K for each of the two
Figure 6 shows the annotated inductor current waveforms. inductors. The range of duty cycles over which the converter will operate has
been emphasized and the DCM-CCM regions of the plots annotated.
These waveforms directly follow from the previously pre-
sented (lossless) PSS inductor volt-second balance equations.
Lastly, the above-derived equations can be rearranged to
With the waveforms presented visually, the IL and ∆iL
express the Ripple Ratio (RR) of the inductor.
components of the inductor currents can be solved by visual
inspection.
RL D 0
Period Slope L1,RippleRatio =
z }| { z }| { 2fs L1 D2
DTs D0 Vin Vin DD0 RL
∆iL1 = = L2,RippleRatio = D0
2 L1 2fs L1 2fs L2
3
Vin D
IL1 = DIout = The Ripple Ratios of both inductors are found to be maxi-
RL mized when D is at its minimum and the load is at its lightest.
This observation is consistent with other topologies: a lighter
Period Slope load decreases the DC current through the converter however
z }| { z }| {
DTs DVin − V out Vin D2 D0 will has no effect on the current ripple.
∆iL2 = = A switching frequency of 500kHz was selected as a rea-
2 L2 2fs L2
Vin D2 sonable baseline for a non-POL bus regulator. From here the
IL2 = Iout = inductors were size to result in both: a K value that places the
RL
converter in CCM across the full range of operating conditions,
Knowing the ripple and DC component of the inductor cur- and a worst-case ripple ratio of around 0.5.
rent, the BMC definition can be applied to find the conditions
under which CCM operation occurs. This inequality can be TABLE II
decomposed into a duty cycle dependent portion Kcrit (D), S ELECTED I NDUCTOR S IZING
and the duty cycle independent portion K.
Value RRMAX Ipeak,MAX IRMS,MAX
For CCM: IL1 > ∆iL1 L1 8.2µH 0.54 11.2A 10.3A
L2 0.68µH 0.44 34.4A 30.1A
2fs L1 D0
>
R D2
| {zL } |{z} ◦ C/W
eff Tc,MAX DCRMAX ACMAX Trise,MAX
K Kcrit (D)
L1 13.1 165◦ C 945mW 231mW 15.4∆◦ C
L2 17.2 165◦ C 1540mW 160mW 29.2∆◦ C
For CCM: IL2 > ∆iL2
2fs L2 With this information, specific MPNs could be selected. The
D0
> |{z} effective core-to-ambient of each inductor was back-calculated
RL
| {z } Kcrit (D) from IRMS,40C . IRMS was used to derive DCR losses, while
K
lumped AC winding + core losses were arrived at using the
Next, for each of the two inductors, Kcrit (D) can be plotted manufacturer’s calculator. From here the core temperature rise
across the full range of duty cycles (Figure 7). In doing so, was calculated and compared against Tcore,MAX .
 4

Detailed information about the selected components can be

found in Table VII. Inductance versus current derating curves
can be found in Appendix C.

D. Output Capacitor Sizing

The next effort was the output capacitor selection. In general
there are three conditions that constrain the minimum output
capacitance needed for a given stage: output ripple, rising
transient requirements and falling transient requirements.
The output ripple sizing was approached with a simplified
model that neglected output ESR and ESL. The canonical
output voltage ripple equation for triangle output current
topologies was used (as distinct from trapezoidal such as in
Fig. 9. Output capacitor sizing is shown to be driven by transient performance
the case of a boost). requirements. Vout,trans was set at 250mV, Vout,ripple 25mV and ISR to 100A/µs.

2∆IP L2
Cout,ripple−min = TABLE III
8fSW Vout,P P O UTPUT C APACITOR S ELECTION

Nominal Tol. Total (derated, min)

In order to account for the idealized representation of zero- MLCC (3x) 47µF 10% 100.4µF
Electrolytic 150µF 20% 120µF
ESR/L capacitors, an aggressive Vout,PP of 25mV was selected.
The input voltage was sweep and the resulting ripple-derived
With this constraint, specific parts were selected. The re-
minimum output capacitance plotted in Figure 9.
quired capacitance was split between a combination of ceramic
Next the transient-derived minimum output capacitance was
and electrolytic capacitors. This ratio was loosely informed
analyzed. The derivation of the subsequent equations considers
by having sufficient ceramic capacitance for the output ripple
the load transient shown in Figure 8.
requirement with electrolytic covering the remaining gap.
Voltage derating and worst-case tolerance stackups are
found in the final column in Table III. Detailed information
can be found in Table VII, derating curves in Appendix C.

E. Switching Stresses
One of the primary drawbacks to the D2 topology, contribut-
ing to its sparse use, are the high stresses experienced by its
switching elements. PSS analysis of the voltages across the
Fig. 8. Limited output slew rate implications for output capacitor sizing. switches was performed and, from there, the peak VDS value
analytically evaluated.
For a load step of a given slew rate (SR), the converter will hVDS,1L i = D0 Vin hVDS,1U i = D Vin
respond by slewing the current of the output inductor. The |{z} |{z}
VDS,peak VDS,peak
rate of increase however is constrained by ∆iL2 . The resulting
residual must be covered by the output capacitors. hVDS,2U i = D0 (Vin − VL1 ) = D0 Vin (1 + D)
| {z }
The area of this triangle can be calculated by visual inspec- VDS,peak
tion. From there, one can calculate the capacitance required to hVDS,2L i = D(Vin − VL1 ) = D DVin
stay within the voltage bounds budged for transient deviations | {z }
VDS,peak
when accepting/providing that charge-delta.
Peak switch currents are expressed below. Numerical values
for VDS and ID of this application are compiled in Table IV.
(Iend − Istart )2 1 1
Q+,min = ( − )
2 SRL2+ SRstep+
ID,1U,peak = IL1,peak = IL1 + ∆iL1
Q+
Cout,trans−min = ID,1L,peak = ICx,peak = ∆iCx
Vout,trans+
ID,2U,peak = IL2,peak = IL2 + ∆iL2
Frequently the transient performance ends up resulting in 
1 D0

2
the more stringent of these conditions and ultimately driving = Vin D +
RL 2fs L2
the capacitors sizing. This general rule of thumb was seen to
hold for this application. ID,2L,peak = ID,2U,peak
 5

TABLE IV amount of circuit manipulation (reproduced in full in Ap-

S WITCH R EQUIREMENT N UMERIC VALUES pendix G), the linear small-signal model was expressed in the
Switch Blocking Voltage Carrying Current canonical form of Figure 10. Doing so required passing several
Q1U Over 60V 11.2A dependent sources around passive elements via Thevenin-
Q1L Over 60V 23.7A Norton transformations.
Q2U Over 75.5V 34.4A
Q2L Over 15.5V 34.4A

The practical implication of these device stresses are that

junction temperatures will be a pinch-point in the design.
While analysis of thermals is outside the scope of this in-
vestigation, what is clear is that effort needs to be made to
minimize switch losses. Fig. 10. The linearized, small signal model of the converter–manipulated into
the canonical form.
As a result, the decision was made to use half-bridge GAN
DrMOS stages. The move to GAN provides thermal relief
by substantially lowering QG losses and removing reverse re- When in the canonical form, the parameters j(s) and e(s)
covery losses. Meanwhile, the decision to use integrated half- evaluate to the following expressions.
bridge stages means lower switch-node ringing–resulting in
lower VDS stresses, smaller footprint and higher efficiency.[1]
2D3 Vin D2 RL Cx
 
A EPC 100VDS stage was selected. Details can be found in j(s) = 1−s
Table VII. While thermals were not analyzed, it is assumed RL 2
L1 D2 (RL + 1)
 
that a thin gap pad ( 1mm) would be used to interface the e(s) = 2DVin 1 + s
0.3◦ C/W half-bridges to the cold-plate used to cool the SoC. 2RL

F. Perturbation Analysis From here, this circuit is solved for the duty-cycle-to-output-
Next, a small-signal, linear ACM of the converter was voltage, Gvout−d (s), relationship when the input perturbation
developed. The first step in this process was perturbing the is set to zero. Expressed symbolically, the transfer function is
previously-presented PSS equations. Here, the resulting terms found below, where Zx is the voltage divider formed by the
have been grouped into DC, first-order AC, and higher order 2nd order L-C low-pass filter and the load resistance.
non-linear (which were dropped in the subsequent analysis).

Gvout/d (s)|vg
in (s)
= e(s)Zx
L1 (t) = DVin − VCx + d1 (t)vf
VL1 + vg (t)
} | {zin }
e
| {z
DC Non-linear
+ Vin d(t)
e + Dvfin (t) − vCx G. Compensation
| {z }
Linear A PID voltage-domain loop was added around the stage D2
L2 (t) = DVCx − Vout + d(t)g
VL2 + vg e vCx (t) in order to provide compensation. The integrator-component
| {z } | {z
increases gain at low frequency, thereby minimizing steady
}
DC Non-linear
state output regulation error. Meanwhile the lead-component
+ VCx d(t) Cx (t) − v
e + Dvg g out (t)
| {z } introduces a PM improvement with an inverted-zero and pole
Linear
that fall on either side of fc .
Cx (t) = IL1 − DIL2 − d(t)iL2 (t)
ICx + ig e f
| {z } | {z }
DC Non-linear

L1 (t) − D iL2 (t) − IL2 d(t)

+ if f e
| {z }
Linear
Iin + if
in (t) = DIL1 + d(t)iL1 (t)
e f
| {z } | {z }
DC Non-linear
+ IL1 d(t)
e + Dif L1 (t)
| {z }
Linear Fig. 11. Schematic of the op amp implementation of the selected PID
compensation scheme.
Cl (t) = IL2 − Iout + |{z}
ICl + if 0
| {z }
DC Non-linear
An op amp was used to implement the PID compensator
L2 (t) − iout (t)
+ if g
| {z } (see Figure 11). The passive components of the compensation
Linear stage provide control over the placement of the salient features
Each of these equations were re-represented as circuits of the resulting TF. These relationships are described by the
and combine through ideal transformers. Through a lengthy below equations.
 6

In the case of an automotive environment, the standard–and

(1 + ωL s consummate filter–would need updating to CISPR-25.
s )(1 + ωz )
H(s) = KP ID The first step in designing an EMI filter to meet these
(1 + ωsp1 )
requirements is assessing the level of attenuation needed to
R2s 1 meet the given maximum limits outlined by CISPR-22.[2] To
KP ID = ωL =
R1p R2s C2s this end, the converter was simulated without an input filter,
1 1 operating in conditions maximizing the input current ripple.
ωz = ωp1 =
R1s R1p R1s C1s An FFT was performed on the voltage drop across a 50Ω
From here the following numeric values in Table V were LISN (modeled by a behavioral source) placed at the input
selected for having resulted in proper compensator of the stage. to the converter. A Gaussian windowing function was applied
to the FFT for the most accurate EMI measurement.[3] The
result was plotted against CISPR limits in Figure 13.
TABLE V
C OMPENSATOR N UMERIC VALUES

Component Value Filter Value

R1p 40kΩ KP ID 1.1 (0.83dB)
R1s 5kΩ fL 0.18kHz
C1s 0.2nF fz 17.7kHz
R2s 44kΩ fp1 159.2kHz
C2s 20nF

The uncompensated and compensated loops were explored

in both LTSpice (non-linear ACM) and Matlab (linearized
SSM). The Matlab results plotted in Figure 12.

Fig. 13. Baseline conducted EMI as measured across a 50Ω LISN at the
input to the converter without any input filtering. H1 is 165.1dBµV.

Attenuation however is not the only consideration when

sizing the EMI filter–care must also be taken to ensure that it
does not meaningfully disturb the TF of the converter. Mid-
dlebrook’s Extra Element Theorem (EET) was employed as a
means to systematically approach meeting this requirement.
The process begins with finding the three impedances shown
in Figure 14: the driving-point impedance (Zd ), the null
impedance (Zn ) and the impedance looking into the filter (Zo ).

Fig. 12. Hand-calculation results plotted in Matlab showing both the open
and close loop Gvout,d (s) transfer function.

This double bookkeeping of Matlab (numeric) and LTSpice

(analytic) shows a high degree of agreement between the
hand-derived, linearized small signal model and the non-linear
behavior of the circuit shown in simulation, both showing
around 60◦ PM.
Fig. 14. Circuits showing the impedances that were used in the extra-element
theorem (EET). These impedances were solved analytically.
H. Input Filter Design
The final significant hurtle is the design of the EMI filter for Solving for these three impedances results in the below
the power stage. This application was designed to CISPR-22. (unsimplified) expressions.
 7

With the EMI input filter now fully designed, the original
1
 1

conducted EMI test was re-performed. The results in Figure 16
sCf

sCb + Rf
Zo =  show that the desired attenuation was achieved–the converter
1 1


sLf + + Rf
sCf

sCb now meets CISPR-22.
 
2 1  1 
Zd = sL1 D + sL2 + RL
sCx D2 sCL
L1 D 2 (RL +1)
vt −e(s) −RL 1 − s 2RL
Zn = = =
it j(s) D2 1 + s D2 R2L CL

Per the Middlebrook theorem, the impedance looking into

the EMI filter (Zo ) must be less than both the driving-point
impedance (Zd ) and the null impedance (Zn ) of the converter
across all frequencies. This requirement ensures that the TF
of the converter is not meaningfully altered by the filter.
Fig. 16. Conducted EMI as measured across a 50Ω LISN at the input to the
kZo (s)k  kZD (s)k kZo (s)k  kZN (s)k converter with input EMI filter present.

Cf and Lf were selected to achieve the required attenuation.

II. A NALYSIS
1
ff ilter = p = 5.37KHz
2π Lf Cf A. Floorplanning
From here values of Cb and its associated damping Rf A preliminary placement of the key selected power compo-
were experimentally explored.3 The high output current of nents was undertaken. The end result is a converter is around
the application results in a very low Zn |DC . As a result a 0.7x1” with a comparably sized filter.
practical trade-off was needed between no TF modification
and a reasonable filter size.

TABLE VI
F ILTER S IZING

Parameter Value Parameter Value

Lf 22µH Cb 470µF
Cf 40µF Rf 160mΩ

The outcome this balancing can be readily–and analytically–

observed in Figure 15. The filter is seen to impact the TF
however ultimately does not meaningfully skew the PM or fc .
Fig. 17. A to-scale proposed placement of the converter with power stage
components shown in yellow and filter components shown in blue. Note:
asterisks and dotted lines indicate double-sided placement.

It should be noted that DFM spacing considerations would

need to be accounted for in a final implementation. Likewise,
depending on vibration and shock requirements respectively,
supplemental caulking might be needed on the electrolytics
and underfill on the GAN BGAs.
One will note that a Flux Canceling layout was employed
on input and output capacitors. The implications of the fast
di/dt of the input current waveform (Figure 6) are such that a
small amount of loop-inductance in the decoupling path will
show up with a meaningful effect on the switch node.
This parasitic inductance is minimized by using same-side
placement and adjacent ground return directly below on ISL2.
This approach results in a minimum loop area, leading to
reduced switch node overshoot that can cause a measurable
Fig. 15. Plot of key impedances per EET analysis of the filter + converter.
efficiency improvement.[1] Given that this application is a
high-performance compute module, the stackup is already
3 See Appendix D for discussion of techniques laid out by Erickson that virtually guaranteed to support the via in-pad and laser-vias
allows for further optimization of Cb , Cf and Rf . needed to make this approach effective.
 8

B. Stability Check Two aggressive load steps–with SR, Istart , Iend characteristics
From here, the initial design requirements were revisited to as defined by the requirement section–were applied to the
show compliance–starting with the frequency domain. converter. The converter can be seen to quickly respond and
keep the output voltage within specification.

Fig. 18. AC simulations of the close-loop transfer function were performed

in LTspice across a fully sweep of input voltage and output current.

The converter close-loop behavior was simulated across a

two dimensional sweep of input voltage and output current.
The resulting PM and fc were extracted via .meas commands,
exported to Matlab and subsequently plotted.
Fig. 19. Transient response zoomed-in to rising edge portion of the step.

Figure 19 shows the selected sawtooth-based PWM genera-

tor scheme. When the error signal is larger than the sawtooth
(VM ) the converter enters the D portion of the switching cycle.
By this manner the error signal is translated to gate PWM and
thereby enabling transient requirements to be met.

III. C ONCLUSION
This paper traverses a sample of the full design process of
translating a basic set of requirements to a physical implemen-
tation. These explored intermediary stages include selection
of key design parameters (e.g. fsw , Cout ), practical consid-
erations pertaining to component selection and placement,
and verification of requirement compliance. Additionally, the
obscure nature of the D2 topology necessitated a deep set of
fundamental analysis and derivations as a precursor to design.
The end result is a clear demonstration that the design is
The analytically intensive and rigorous nature of the adopted
stable and fast across the full range of operating conditions.
approach allowed several insights to be revealed. Among
these: the non-trivial nature of designing an EMI filter for
C. Transient Response Check
a very low output impedance power stage, and the specific
Lastly, the transient response of the converter was assessed. loss mechanisms as a function of duty cycle.
Next steps in the physical implementation of this design
would include detailed thermal analysis. From there control
components selection, schematic capture and layout would
need to be performed.

R EFERENCES
[1] P. David Reusch, “Optimizing PCB Layout,” EPC, Tech. Rep., 2014.
[2] I. E. Commission, “Guidance for users of the CISPR Standards,” Inter-
national Special Committee on Radio Interference (CISPR), Tech. Rep.,
October 2016.
[3] Tektronix, “An Introduction To FFT EMI Receivers,” Tech. Rep.
[4] D. M. Robert Erickson, Fundamentals of Power Electronics, 2nd ed.

A PPENDIX A
C OMPONENT S ELECTION
Throughout the preceding design flow component selections
have been presented. These selections have been collated in
the consolidated list found below in Table VII.
 9

TABLE VII Lastly, this ACM is analyzed at DC–yielding the below

C OMPONENT S ELECTION equations for the conversion ratio and efficiency as functions
Component Manufacturer MPN AECQ of: the loss elements, duty cycle, input voltage and load.
Lf Panasonic ETQ-P4M220KVC * Diode Loss
Cf TDK CKG57NX7S2A226M500JJ *
z }| {
CB Vishay MAL215099707E3 * 2 Vf wd
D − (1 + D)
CIN Murata GGM32DC72A475KE02 * Vout Vin
L1 Coilcraft XAL1010-682 * =
Vin Rind,1 2 Rind,2 Ron
L2 Coilcraft XAL8080-681 * 1+ D + + D
CX Murata GGM32DC72A475KE02 * Rload Rload Rload
Q1/2 EPC EPC2104
| {z } | {z }
Inductor Loss MOSFET Loss
CL,cerm Murata GCM32EC71A476KE02 *
CL,bulk Panasonic EEE-FP1A151AP *
Vf wd
Mlossy 1−Vout (1 + D)
Component Value Description η= =
Mideal Rind,1 2 Rind,2 Ron
Lf 22µH Composite, 5.0ASAT , 7.4ARMS , 66mΩ 1+ Rload D + Rload + Rload D
Cf 22µF Ceramic, 100V, X7S, 20%
CB 470µF Electrolytic, 80V, 160mΩ, 20% These equations are plotted below in Figure 22.4 The
CIN 4.7µF Ceramic, 100V, X7S, 10% primary take away is that a diode implementation rapidly
L1 8.2µH Composite, 21.8ASAT , 18.5ARMS , 8.9mΩ
L2 0.68µH Composite, 38ASAT , 37ARMS , 1.7mΩ becomes infeasible as the duty cycle and input voltage drop.
CX 4.7µF Ceramic, 100V, X7S, 10%
Q1/2 - GAN, 100VDS , 180A, 6.8mΩ, 0.3C◦ /WJC
CL,cerm 47µF Ceraminc, 10V, X7S, 10%
CL,bulk 150µF Electrolytic, 10V, 260mΩ, 20%

A PPENDIX B
L OSS C OMPONENTS : N ON -S YNCHRONOUS C ONVERTER
The loss mechanisms of a non-synchronous implementation
of this topology is considered below.

Fig. 22. Plots showing the effect of RDS,on and Vf wd on the efficiency of
the non-synchronous converter.
Fig. 20. Non-synchronous implementation using three diodes and one FET.
A PPENDIX C
The ACM equations of Section I-B can be leveraged with C OMPONENT D ERATING C URVES
only minor modifications to include the Vf wd loss mechanism. Derating curves were extracted from inductor and MLCC
datasheets.
hVL1 i = DVin − Vcx − Vf wd − IL1 Rind,1
hVL2 i = DVcx − Vout − Vf wd − IL2 Rind,2 − DIL2 Ron
hICx i = IL1 − DIL2
hICl i = IL2 − Iout
hIin i = DIL1
This system of equations can in-turn be translated into indi-
vidual circuits that are then manipulated back into a single
non-linear ACM with loss elements (Figure 21).

4 Plots showing the effect of inductor DCR have been omitted as the
Fig. 21. The lossy non-synchronous non-linear average circuit model. behavior is identical to the synchronous implementation (see Figure 5).
 10

All presented analysis and simulations assume worst-case +L1 = 8.2u

+L2 = 0.68u
ceramic capacitor derating (e.i. VMAX ) and the worst case +Rl = dcvout/iout
tolerance stackup (large circle). +esr = 0.1m
+dcin = 48
+D = sqrt(dcvout/dcin)
+Cf = 50u
+Lf = 22u
+Rf = 160m
+Cb = 470u

*---Duty Cycle
Vc nd 0 dc={D} ac=1

*---EMI Filter
Vin n1f 0 dc={dcin}
Lf n1f n2f {Lf}
Cf n2f 0 {Cf}
Rf n2f n3f {Rf}
Cb n3f 0 {Cb}

*---Converter (n2f)
Vjmp n1 n2f 0
Xtm1 n1 0 n2 0 nd tmodel
L1 n2 n3 {L1*D*D}
Cx n3 n3r {Cx*D*D}
Rxr n3r 0 {esr}
L2 n3 no {L2}
Cl no nor {cl}
Resr nor 0 {esr}
Rl no 0 {rl}

*---Compensator
Bcin n2c 0 V=V(no)
Vref n1c 0 1.2
Xc1 n1c n3c n5c opamp
R1pc n2c n3c 40k
R1sc n2c n4c 5k
C1sc n4c n3c 0.2n
R2sc n3c n6c 44k
C2sc n6c n5c 20n

*---Close-loop Output
A PPENDIX D Bout ncloseloop 0 V=V(n5c)+V(no)

I NPUT F ILTER O PTIMIZATION *---Transformer

.subckt tmodel np1 np2 ns1 ns2 nd
Erickson proposes a method that builds on the EET analysis Bp np1 np2 I=I(Vsns)
to further optimize Cb and Rf .[4] The associated flow drives Bs ns1_ ns2 V=V(nd)*V(nd)*(V(np1)-V(np2))
Vsns ns1_ ns1 0 dc=0 ac=0
selection of a preliminary R0,filter and Zo,max . .end tmodel
s
Lf *---Auxiliary Models
R0,f ilter = .model swideal SW(Ron=1n Roff=10g Vt=0.5 Vh=1u)
Cf .subckt opamp in_p in_n out
Bop out 0 V=10meg*(V(in_p)-V(in_n))
Zo,max |f =ff ilter  ZD |f =ff ilter .end tmodel

From here, the following equations are employed: *---Analysis

.ac dec 200 10 1meg
2  s .step param dcin 34 60 1
R0,f 2
Zo,max

Cb ilter .step param iout 10 30 1
n= = 2 1+ 1+4 2 .meas phasemargin find (v(ncloseloop)/v(nd)) when mag(v(
Cf Zo,max R0,f ilter ncloseloop)/v(nd))=1
s .end
(2 + n)(4 + 3n)
Rf = R0,f ilter B. Time Domain Simulation: FFT Analysis
2n2 (4 + n)
*---Analysis
.PARAM:
A PPENDIX E +NCYCLES = 4 ;number of switching cycles to save
LTS PICE N ETLISTS +SIMEND = 10m ;simulation end time
+PPSW = 100 ;number of sim points per switching cycle
LTSpice netlists of the converter have been reproduced .TRAN {1/(PPSW*fsw)} {SIMEND} {SIMEND-(NCYCLES/fsw)} {1/(
below. PPSW*fsw)} uic

*---Parameters
.PARAM:
A. AC Simulation: Non-Linear ACM Parametric Sweeps +Fsw = 500k
+D1 = 0.2582
*---Parameters +Cl = 260u
.PARAM: +Cx = 8u
+dcvout = 4 +L1 = 8.2u
+iout = 20 +L2 = 0.68u
+Cl = 260u +Rl = 0.133
+Cx = 8u +Ron = 5m
 11

+R_ind1 = 8.9m Vjmp n2f n1 0 ;use to bypass filter stage

+R_ind2 = 1.7m D1 n2 n1 dmodel
+Cf = 40u D2 0 n2 dmodel
+Lf = 22u Cx n3 n2 {cx}
+Rf = 160m L1 n1 n3 {L1} Rser={R_ind1}
+Cb = 470u Xq nq n3 n4 qmodel
D3 0 n4 dmodel
*---EMI Filter L2 n4 no {L2} Rser={R_ind2}
Vin n1f 0 60 Cl no 0 {cl}
Lf n1f n2f {Lf}
Cf n2f 0 {Cf} *---Compensator
Rf n2f n3f {Rf} Bcin n2c 0 V=V(no)
Cb n3f 0 {Cb} Vref n1c 0 4
Xc1 n1c n3c n5c opamp
*---Converter R1pc n2c n3c 40k
Vjmp n2f n1 0 ;use to bypass filter stage R1sc n2c n4c 5k
D1 n2 n1 dmodel ;q1U C1sc n4c n3c 0.2n
D2 0 n2 dmodel ;q1L R2sc n3c n6c 44k
Cx n3 n2 {cx} C2sc n6c n5c 20n
L1 n1 n3 {L1} Rser={R_ind1}
Xq nq n3 n4 qmodel ;q2U *---PWM Generator
D3 0 n4 dmodel ;q2L Vgen n1g 0 pulse(0 1 0 {1/fsw} 0 0 {1/fsw})
L2 n4 no {L2} Rser={R_ind2} Bdg nq 0 V={if(V(n5c)>V(n1g), 1, 0)}
Cl no 0 {cl} Rq nq 0 1meg
Rl no 0 {rl}
*---Load Step
*---Gating Signal Il no 0 {Istart}
Vq nq 0 pulse(-1 1 0 1n 1n {D1/fsw} {1/fsw})
Rq nq 0 1meg *---MOSFET
.subckt qmodel gate drain source
*---LISN Model SW drain n1 gate 0 swideal ;ideal switch
Bin nlisn 0 I=I(Vin) DSW n1 source dmodel ;series diode
Rlisn nlisn 0 50 DA source drain dmodel ;anti-parallel diode
RBIG gate 0 1meg ;charge draining resistor at
*---MOSFET gate
.subckt qmodel gate drain source .model swideal SW(Ron={ron} Roff=10meg Vt=0.5 Vh=1u)
SW drain n1 gate 0 swideal ;ideal switch .ends idmos
DSW n1 source dmodel ;series diode
DA source drain dmodel ;anti-parallel diode *---Auxiliary Models
RBIG gate 0 1meg ;charge draining resistor at .model dmodel D (Ron={Ron} Vfwd=1n)
gate .subckt opamp in_p in_n out
.model swideal SW(Ron={ron} Roff=10meg Vt=0.5 Vh=1u) Bop out 0 V=10meg*(V(in_p)-V(in_n))
.ends idmos .end tmodel

*---Auxiliary Models A PPENDIX F

.subckt opamp in_p in_n out
Bop out 0 V=10meg*(V(in_p)-V(in_n)) M ATLAB
.end tmodel
.model dmodel D (Ron={Ron} Vfwd=1n) A. Efficiency Analysis
C. Time Domain Simulation: Load Transient Analysis D = linspace(0.05,1,200);
Rind1_l = linspace(0.000001,0.01,200); %8.9mohm to 133mohm
*---Analysis (6.7%)
.PARAM: Rind2_l = linspace(0.000001,0.01,200); %1.7mohm to 133mohm
+SIMSTART = 10m (2.0%)
+SIMEND = 20m Ron_l = linspace(0.000001,0.01,200); %6.8mohm to 133mohm
+PPSW = 1000 ;points per switching cycle (5.1%)
.TRAN {1/(PPSW*fsw)} {SIMEND} {SIMSTART} {1/(PPSW*fsw)} uic Vd_in = linspace(0.000001,0.005,200); %0.6V to 34V (1.8%)
n_ind1 = 1./(1+Rind1_l’*(D.ˆ2));
*---Parameters n_ind2 = 1./(1+Rind2_l’);
.PARAM: n_onold = 1./(1+Ron_l’*D);
+Fsw = 500k n_onnew = 1./(1+Ron_l’*(1+D+D.ˆ2));
+Cl = 260u n_fwd = 1-Vd_in’*(D.ˆ-2+D.ˆ-1);
+Cx = 8u n_fwd(n_fwd<0)=0;
+L1 = 8.2u
+L2 = 0.68u figure(1)
+Ron = 5m subplot(3,1,1);
+R_ind1 = 8.9m imagesc(D,Rind1_l,(1-n_ind1))
+R_ind2 = 1.7m ylabel(’R_{L1}/R_{load}’);
+Istart = 30 ylabel(colorbar,’Partial Efficiency (\eta)’);
+Iend = 30 title(’Efficiency Partials of Syncronous Converter’,’
+Islew = 100 ;A/us fontweight’,’bold’);
+Cf = 40u
+Lf = 22u subplot(3,1,2);
+Rf = 160m imagesc(D,Rind2_l,(1-n_ind2))
+Cb = 470u ylabel(’R_{L2}/R_{load}’);
ylabel(colorbar,’Partial Efficiency (\eta)’);
*---EMI Filter xlim([0.05 1])
Vin n1f 0 48 ;pulse(60 65 {SIMEND-(NCYCLES/fsw/2)} 10n 10n
1) subplot(3,1,3);
Lf n1f n2f {Lf} imagesc(D,Ron_l,(1-n_onnew))
Cf n2f 0 {Cf} ylabel(’R_{on}/R_{load}’);
Rf n2f n3f {Rf} xlabel(’Duty Cycle (D)’);
Cb n3f 0 {Cb} ylabel(colorbar,’Partial Efficiency (\eta)’);

*---Converter figure(2)
 12

subplot(2,1,1); hold on;

imagesc(D,Ron_l,1-n_onold) opt.Title.String = ’Close-loop Control-Output Transfer
ylabel(’R_{on}/R_{load}’); Function’;
ylabel(colorbar,’Partial Efficiency (\eta)’); bode(Vout_d_comp, opt);
title(’Efficiency Partials of Nonsyncronous Converter’,’ bode(Vout_d_comp_filter, opt);
fontweight’,’bold’); set(gca,’fontsize’,14);
q=legend(’Without Filter’,’With Filter’);
subplot(2,1,2); hold off;
imagesc(D,Vd_in,1-n_fwd)
xlabel(’Duty Cycle (D)’); figure(3)
ylabel(’V_{fwd}/V_{in}’); hold on;
ylabel(colorbar,’Partial Efficiency (\eta)’); opt.Title.String = ’EMI Filter Sizing’;
opt.PhaseVisible = ’off’;
B. Filter and Loop Gain Analysis opt.Title.FontWeight = ’bold’;
bode(Zo, opt);
bode(Zn, opt);
Vin = 48;
bode(Zd, opt);
Cl = 260e-6;
hold off;
Cx = 8e-6;
L1 = 8.2e-6;
L2 = 0.68e-6;
Rl = 0.133;
D = 0.29;
s = tf(’s’);

% Uncompensated Control TF w/o filter

Zz = Rl/(1+s*Cl*Rl);
Zy = s*L2+Zz;
Zx = Zy/(1+s*Cx*Dˆ2*Zy);
Vx_in = Zx/(Zx+s*L1*Dˆ2);
Vout_x = 1/(1+s*L2/Zz);
Vout_in = Vx_in*Vout_x;
Vin_d = 28.8; %opamp DC gain (in dB)
Vout_d_uncomp = Vout_in*Vin_d;
[Gm,Pm_openloop,Wgm,Wpm] = margin(Vout_d_uncomp);
Pm_openloop; %phase margin
fc_openloop = Wpm/2/pi; %cross-over frequency

% PI Compensator
K_pid=1.1;
w_l=180*2*pi;
w_z = 17680*2*pi;
w_p = 159150*2*pi;
PID = K_pid*(1+w_l/s)*(1+s/w_z)/(1+s/w_p);

% Compensated Loop Gain

G_sensor = 0.3/1.2;
Vout_d_comp=G_sensor*Vout_d_uncomp*PID;
[Gm,Pm_closeloop,Wgm,Wpm] = margin(Vout_d_comp);
Pm_closeloop; %phase margin
fc_closeloop = Wpm/2/pi; %cross-over frequency

opt = bodeoptions;
opt.Xlim = [10,10E5];
opt.PhaseWrapping = ’off’;
opt.MagUnits = ’dB’;
opt.FreqUnits = ’Hz’;
opt.FreqScale = ’log’;
opt.grid = ’on’;
opt.PhaseVisible = ’on’;

figure(1)
hold on;
opt.Title.String = ’Control-Output Transfer Function’;
opt.Title.FontWeight = ’bold’;
bode(Vout_d_uncomp, opt);
bode(PID, opt);
bode(Vout_d_comp, opt);
set(gca,’fontsize’,14);
q=legend(’Open-loop’,’PI Compensator’,’Close-loop’);
set(q,’FontSize’,14, ’FontName’, ’Avenir Next’);
hold off;

% Filter Sizing
Lf = 22e-6;
Cf = 40e-6;
Rf = 0.16;%sqrt(Lf/Cf);
Cb = 470e-6;
Zd = s*L1*Dˆ2 + (Rl+s*L2*(1+s*Cl*Rl))/(1+s*Cl*Rl+s*Cx*Dˆ2*(
Rl+s*L2*(1+s*Cl*Rl)));
Zn = -Rl/Dˆ2*(1-s*L1*Dˆ2*(Rl+1)/2/Rl)/(1+s*Dˆ2*Rl*Cx/2);
Zo = 1/(1/(Rf+1/s/Cb) + s*Cf + 1/s/Lf);

% Loop Gain w/ Filter

Vout_d_comp_filter = Vout_d_comp*(1+Zo/Zn)/(1+Zo/Zd);

figure(2)
 13

A PPENDIX G
D ETAILED D ERIVATION OF C ANONICAL M ODEL

Fig. 23. Detailed, step-by-step canonical model derivation.