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ECE 424L-3 : Digital Communications - Laboratory
Experiment No. 9
Line Coding and Bit Clock Regeneration
July 17, 2018 October 20, 2018
Date Performed Date Submitted
Remarks Grade
Teruel, Samuel Isaac B.
BSECE / 4th Year
Engr. Jerry V. Turingan, ECE
Instructor
Data Results
EXP 9: Table 2
Line Code Lobes
(In 40KHz span)
NZR-L 20???
Biɸ-L 10???
RZ-AMI 30???
NZR-M ????
EXP 9: Table 3
Line Code Frequency of first
null
NZR-L 2.3KHz
Biɸ-L 4.2KHz
RZ-AMI 2.310KHz
NZR-M 2.3KHz
Exp 9: Table 4
Line Code Bit-clock Bit-clock Comp.
Component (in dB) (as a ratio)
NZR-L 3.44 -1.31
Biɸ-L 26.60 8.07
RZ-AMI 7.40 -2.31
NZR-M 2.75 -1.16
EXP 9: table 5
Line Code Bit-clock
Component (in dB)
NZR-L 38.56
Biɸ-L 37.90
RZ-AMI 16.30
NZR-M 39.85
Discussion of Results
Oversampling can be done blind using multiple phases of a
free-running clock to create multiple samples of the input
and then selecting the best sample. Or, a counter can be
used that is driven by a sampling clock running at some
multiple of the data stream frequency, with the counter
reset on every transition of the data stream and the data
stream sampled at some predetermined count. These two
types of oversampling are sometimes called spatial and time
respectively. The best bit error ratio (BER) is obtained when
the samples are taken as far away as possible from any data
stream transitions. While most oversampling designs using a
counter employ a sampling clock frequency that is an even
multiple of the data stream, an odd multiple is better able to
create a sampling point further from any data stream
transitions and can do so at nearly half the frequency of a
design using an even multiple. In oversampling type CDRs,
the signal used to sample the data can be used as the
recovered clock.
Clock recovery is very closely related to the problem of
carrier recovery, which is the process of re-creating a phase-
locked version of the carrier when a suppressed carrier
modulation scheme is used. These problems were first
addressed in a 1956 paper, which introduced a clock-
recovery method now known as the Costas loop. Since then
many additional methods have been developed.
Conclusion
In serial communication of digital data, clock recovery is
the process of extracting timing information from a serial
data stream to allow the receiving circuit to decode the
transmitted symbols. Clock recovery from the data stream is
expedited by modifying the transmitted data. Wherever a
serial communication channel does not transmit the clock
signal along with the data stream, the clock must be
regenerated at the receiver, using the timing information
from the data stream. Clock recovery is a common
component of systems communicating over wires, optical
fibers, or by radio.
Some digital data streams, especially high-speed serial
data streams (such as the raw stream of data from the
magnetic head of a disk drive and serial communication
networks such as Ethernet) are sent without an
accompanying clock signal. The receiver generates a clock
from an approximate frequency reference, and then phase-
aligns the clock to the transitions in the data stream with a
phase-locked loop (PLL). This is one method of performing a
process commonly known as clock and data recovery (CDR).
Other methods include the use of a delay-locked loop and
oversampling of the data stream.
