International Journal of Soft Computing and Artificial Intelligence, ISSN: 2321-404X, Volume-2, Issue-1, May-2014

IMPLEMENTATION OF ELECTRONIC VOTING MACHINE

THROUGH FPGA
1
TIMARDEEPKAURARNEJA, 2JASLEENKAURBASSI, 3DAMANJEETKAUR

Department of E&C Engineering, Department of E&C Engineering, Department of E&C Engineering, G.G.S.I.P University,
Delhi, India, G.G.S.I.P University, Delhi, India, G.G.S.I.P University, Delhi, India
Email: [email protected], [email protected], [email protected]

Abstract— Electronic Voting machine is a simple electronic device used to record votes automatically without the need of
manual operation of ballot papers. Fundamental right to vote forms the basis of any Democracy. In all earlier elections,
voters casted their votes to their favourite candidates by putting the stamp against his/her name. This is a long time
consuming process and is prone to errors and can at times be an unfair process. To overcome all these difficulties and make
the electoral process a fair one, implementation of electronic voting machine in digital domain is presented in this paper. It is
difficult to tamper votes in digital domain and provides a secure and safe method for conducting elections.

Keywords—Electronic Voting, Elections, Security, Software, XILINX, Voting, Ballot, VHDL, FPGA

I. INTRODUCTION The various signals that are used are

S.no Signal Description
Voting is the sole criteria for choosing their 1 Selection Signal This signal is to select the
candidate to whom vote is
representatives by people in any democracy, so, this being casted. The size of this
entire process should be done with utmost care so that signal will depend on number
only a fair and deserving candidate is selected that is of candidates who will stand in
solely based on public opinion. In earlier days, elections.
2 Clock Signal This signal is used to cast the
elections were conducted using ballot paper system vote. Vote will be casted on
whereby people casted their votes to their favourite positive or negative edge of
candidate, merely, by putting stamp against his/her clock depending on priority of
name but this method often suffered from various programmer. The clock will
last for particular period of
flaws such as stealing of votes and unfair results[6]. time in which voter has to cast
To overcome all these discrepancies, electronic his/her vote.
voting machine was designed. But the design of 3 Password Signal This signal will mark the initial
simple electronic voting machine with removable stage of opening of Electronic
voting machine. The machine
memory card was not enough as access to memory will work only when valid
card[7] for even a minute can tamper all the votes password is applied to
with some other malicious code. So we needed the machine. The password can be
system which could provide some better way of as long as intended by
programmer. A 32 bit
implementing Electronic Voting Machine.Since we password pattern will yield
all know that it is very difficult to manipulate signals, 4294967296 permutations and
so we have designed electronic voting machine in combination of patterns which
VHDL using XILINX ISE 9.2i as a platform which is very difficult to hack.
can be implemented on FPGA (Field Programmable 4 Candidate The number of such signals
Gate Array) hardware using SPARTAN 3E kit. Since Signals will depend on the number of
candidates standing in the
FPGA’s have in built RAM and each vote requires elections.
only one bit of memory, this implementation is quite
memory and cost efficient. Further, this 5 Winning Signals The winning signal=1
implementation also contains password which itself is corresponding to particular
digital in nature and is very difficult to be hacked. candidate will indicate that
candidate has won the
elections.
II. DESCRIPTION OF SIGNALS USED IN
IMPLEMENTATION 6 Equality Signals There may be a case where
equal number of votes are
casted to two or more
The IEEE standard used for implementation purpose candidates leading to tie
of various modules condition. The equality signal
areIEEE.STD_LOGIC_1164.ALL,IEEE.STD_LOGI in that condition will signify a
tie.
C_ARITH.ALL and
IEEE.STD_LOGIC_UNSIGNED.ALL[2]

Implementation Of Electronic Voting Machine Through FPGA

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International Journal of Soft Computing and Artificial Intelligence, ISSN: 2321-404X, Volume-2, Issue-1, May-2014

design issues in beginning of design process[4]. The

Technology Schematic of designed logic is shown in
figure3

Figure 1
Basic Schematic for four candidates standing in Elections

III. RTL (Register Transfer Language) AND

TECHNOLOGY SCHEMATIC

RTL is a design abstraction which models the digital Figure.3

Technology Schematic for Electronic Voting Machine
synchronous signals in terms of flow of digital signals
between hardware registers and logical operations
IV. GENERATION OF TEST BENCH
performed on that signals[1]. It creates high level
representation from the circuit from which lower
The testbench stores the clock period set by the
levels can be derived and ultimately actual wiring can
programmer, for the process of casting of votes[1].
be derived.
The vote is casted when the clock is high and is
RTL view of the designed circuit is shown in the
recorded when the clock goes low. In our
figure 2
implementation, the clock period is set to be 100 ns,
where 50 ns is for positive edge and 50 ns when
negative edge. If the voter is not able to cast his/her
vote in the positive edge, then he has to wait for the
next clock cycle to cast his vote. The generated
testbench is used for casting of votes by the voter and
the recorded votes are then displayed in the form of
signals as shown.

Figure.2
RTL Schematic for implementation of Electronic Voting
Machine

Technology schematic opens the NGC file that can be Figure 4. Generation of Test Bench
viewed as architecture specific schematic. The
schematic is generated after the optimization and V. SIMULATION
technology targeting phase of synthesis process. It
shows a representation of the design in terms of logic After all the votes have been recorded, Behavioural
elements optimized to the target Xilinx device. The simulation[5] is done to obtain the final results. The
schematic enables the user to see a technology level behavioural simulation of the test bench gives the
representation of HDL optimised for specific authenticated results in the form of high and low of
XILINX architecture which may help user discover signals. The winner gets his/her signal high at the end

Implementation Of Electronic Voting Machine Through FPGA

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International Journal of Soft Computing and Artificial Intelligence, ISSN: 2321-404X, Volume-2, Issue-1, May-2014

of behavioural simulation and it marks the end of the Since on a typical SPARTAN 3E kit provided by
voting process. In case of tie of two or more Texas Instruments, we have only four input ports, in
candidates, a signal high corresponding to two or order to accommodate our signals we can interface a
more candidate is shown against their corresponding 100 pin female connector[1] with the SPARTAN 3E
signal. kit.

CONCLUSION

The designed Electronic Voting Machine can be used

for secure voting, where the tampering of votes has
very less probability. It is easy to build and a large
number of votes can be casted and recorded
depending on the memory of the system. Since it does
not contain any memory card and has a password
which is digital in nature. It provides a secure system
for conducting elections. This system is also memory
efficient as it uses only one bit for recording a vote
casted by user.Since the cost incurred in its
manufacturing is less, therefore it can easily replace
the paper ballot system present in certain areas.

REFERENCES

Figure 5. Result of Simulation [1].http://www.xilinx.com/itp/xilinx10/books/docs/qst/qst.pdf

[2].Digital System Design Using V.H.D.L by Charles H. Roth,
JrChapter.2, Chapter 3
VI. HARDWARE IMPLEMENTATION [3]. Digital System Design Using V.H.D.L by Charles H. Roth, Jr
Appendix A (VHDL Language Summary)
The Electronic Voting Machine can be implemented [4]. www.xilinx.com ISE Tutorial in Depth Chapter 2, Chapter 3
on hardware using SPARTAN 3E FPGA kit by [5]. www.xilinx.com ISE Tutorial in Depth Chapter 4,Chapter
5,Chapter 6
burning the VHDL code into it. Once the VHDL code [6]. Benjamin B., Bederson, Bongshin Lee., Robert M. Sherman.,
is burned and the FPGA chip is ready, we can Paul S., Herrnson, Richard G. Niemi., "Electronic Voting
designate various ports to various signals present in System Usability Issues", In Proceedings of the SIGCHI
our software.After designating ports a PROM file is conference on Human factors in computing systems, 2003.
[7].Rubin A.D. "Security considerations for remote electronic
generated and load FPGA with specified bit file and
voting", ACM, 5(12):39-44, Dec.2002.
the designed logic is ready for implementation..

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Implementation Of Electronic Voting Machine Through FPGA