Scribd
Upload
56 views

Systems Programming For The Intel Architecture

This document provides an overview of operating system kernels and system-level concepts in 3 sentences: It discusses core registers like EFLAGS and segments that define memory layout. Key data structures include segment descriptors, segment selectors, and tables like the GDT that map segments to memory. The document also covers processes and task management, with tasks defined by a TSS that stores state and segments, and tasks scheduled via task gates in the GDT.

Uploaded by

Debashish Pal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
56 views

Systems Programming For The Intel Architecture

This document provides an overview of operating system kernels and system-level concepts in 3 sentences: It discusses core registers like EFLAGS and segments that define memory layout. Key data structures include segment descriptors, segment selectors, and tables like the GDT that map segments to memory. The document also covers processes and task management, with tasks defined by a TSS that stores state and segments, and tasks scheduled via task gates in the GDT.

Uploaded by

Debashish Pal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 14

CSCE 351

Operating System Kernels

Systems Programming
for the Intel Architecture

Steve Goddard
[email protected]

http://www.cse.unl.edu/~goddard/Courses/CSCE351

System Level Registers and


Data Structures

2
System Flags in the
EFLAGS Register

Segmented Memory Model

4
Segmented Memory Model

Segment Descriptor

6
Segment Selector

Logical Address to Linear


Address Translation

8
Segment Registers

System Level Registers and


Data Structures

10
Memory Management
Registers

11

Global Descriptor Table (GDT)


and the GDT Register (GDTR)

12
Gate Descriptors
◆ To provide controlled access to code segments
with different privilege levels, the processor
provides a special set of descriptors called gate
descriptors. There are four kinds of gate
descriptors:
» Call gates
» Trap gates
» Interrupt gates
» Task gates

13

Call Gates
◆ A call-gate descriptor may reside in the GDT or in an
LDT, but not in the interrupt descriptor table (IDT). It
performs six functions:
1. It specifies the code segment to be accessed.
2. It defines an entry point for a procedure in the specified code
segment.
3. It specifies the privilege level required for a caller trying to access
the procedure.
4. If a stack switch occurs, it specifies the number of optional
parameters to be copied between stacks.
5. It defines the size of values to be pushed onto the target stack: 16-
bit gates force 16-bit pushes and 32-bit gates force 32-bit pushes.
6. It specifies whether the call-gate descriptor is valid.

14
Call Gate Mechanism

15

Segment Descriptor vs.


Gate Descriptor

Segment Descriptor

Gate Descriptor

16
Interrupt Descriptor Table (IDT)
◆ Associates each exception or interrupt vector with
a gate descriptor for the procedure or task used to
service the associated exception or interrupt.

17

IDT Gate Descriptors

18
Task Management
◆ The Intel Architecture provides a mechanism for
» saving the state of a task,
» for dispatching tasks for execution, and
» for switching from one task to another.
◆ When operating in protected mode, all processor
execution takes place from within a task.
◆ A task is made up of two parts:
» a task execution space
» task-state segment (TSS).

19

Task State Segment (TSS)


◆ The TSS specifies the segments that make up the task
execution space and provides a storage place for task state
information.

20
Task State
◆ The following items define the state of the currently
executing task:
» The task’s current execution space, defined by the segment
selectors in the segment registers (CS, DS, SS, ES, FS, and GS).
» The state of the general-purpose registers.
» The state of the EFLAGS register.
» The state of the EIP register.
» The state of control register CR3.
» The state of the task register.
» The state of the LDTR register.
» The I/O map base address and I/O map (contained in the TSS).
» Stack pointers to the privilege 0, 1, and 2 stacks (contained in the
TSS).
» Link to previously executed task (contained in the TSS).

21

TSS Structure

22
Task Register

23

TSS Descriptor

24
Task Gate Descriptor

25

Task Gates Referencing the


Same Task

26
Putting It All Together

27

You might also like