Decoders, Multiplexers and

Programmable Logic
 Decoders
• Next, we’ll look at some commonly used circuits: decoders and
multiplexers.
– These serve as examples of the circuit analysis and design
techniques from last week.
– They can be used to implement arbitrary functions.
– We are introduced to abstraction and modularity as hardware
design principles.
• Throughout the semester, we’ll often use decoders and multiplexers as
building blocks in designing more complex hardware.

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 What is a decoder
• In older days, the (good) printers used be like typewriters:
– To print “A”, a wheel turned, brought the “A” key up, which then
was struck on the paper.
• Letters are encoded as 8 bit codes inside the computer.
– When the particular combination of bits that encodes “A” is
detected, we want to activate the output line corresponding to A
– (Not actually how the wheels worked)
• How to do this “detection” : decoder
• General idea: given a k bit input,
– Detect which of the 2^k combinations is represented
– Produce 2^k outputs, only one of which is “1”.

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 What a decoder does
• A n-to-2n decoder takes an n-bit input and produces 2n outputs. The n
inputs represent a binary number that determines which of the 2n
outputs is uniquely true.
• A 2-to-4 decoder operates according to the following truth table.
– The 2-bit input is called S1S0, and the four outputs are Q0-Q3.
– If the input is the binary number i, then output Qi is uniquely true.
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

• For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is

true, and Q0, Q1, Q3 are all false.
• This circuit “decodes” a binary number into a “one-of-four” code.

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 How can you build a 2-to-4 decoder?
• Follow the design procedures from last time! We have a truth table, so
we can write equations for each of the four outputs (Q0-Q3), based on
the two inputs (S0-S1).

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

• In this case there’s not much to be simplified. Here are the equations:

Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0

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 A picture of a 2-to-4 decoder

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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 Enable inputs
• Many devices have an additional enable input, which is used to “activate”
or “deactivate” the device.
• For a decoder,
– EN=1 activates the decoder, so it behaves as specified earlier.
Exactly one of the outputs will be 1.
– EN=0 “deactivates” the decoder. By convention, that means all of
the decoder’s outputs are 0.
• We can include this additional input in the decoder’s truth table:
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

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 An aside: abbreviated truth tables
• In this table, note that whenever EN S1 S0 Q0 Q1 Q2 Q3
EN=0, the outputs are always 0, 0 0 0 0 0 0 0
regardless of inputs S1 and S0. 0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

EN S1 S0 Q0 Q1 Q2 Q3
• We can abbreviate the table by
0 x x 0 0 0 0
writing x’s in the input columns 1 0 0 1 0 0 0
for S1 and S0. 1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

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 Blocks and abstraction
• Decoders are common enough that we want to encapsulate them and
treat them as an individual entity.
• Block diagrams for 2-to-4 decoders are shown here. The names of the
inputs and outputs, not their order, is what matters.

Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0

• A decoder block provides abstraction:

– You can use the decoder as long as you know its truth table or
equations, without knowing exactly what’s inside.
– It makes diagrams simpler by hiding the internal circuitry.
– It simplifies hardware reuse. You don’t have to keep rebuilding the
decoder from scratch every time you need it.
• These blocks are like functions in programming!

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 A 3-to-8 decoder
• Larger decoders are similar. Here is a 3-to-8 decoder.
– The block symbol is on the right.
– A truth table (without EN) is below.
– Output equations are at the bottom right.
• Again, only one output is true for any input
combination.

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 Q0 = S2’ S1’ S0’
0 1 0 0 0 1 0 0 0 0 0 Q1 = S2’ S1’ S0
0 1 1 0 0 0 1 0 0 0 0 Q2 = S2’ S1 S0’
1 0 0 0 0 0 0 1 0 0 0 Q3 = S2’ S1 S0
1 0 1 0 0 0 0 0 1 0 0
Q4 = S2 S1’ S0’
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 Q5 = S2 S1’ S0
Q6 = S2 S1 S0’
Q7 = S2 S1 S0

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 So what good is a decoder?
• Do the truth table and equations look familiar?

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0 Q0 = S1’ S0’
1 0 0 0 1 0 Q1 = S1’ S0
1 1 0 0 0 1 Q2 = S1 S0’
Q3 = S1 S0

• Decoders are sometimes called minterm generators.

– For each of the input combinations, exactly one output is true.
– Each output equation contains all of the input variables.
– These properties hold for all sizes of decoders.
• This means that you can implement arbitrary functions with decoders.
If you have a sum of minterms equation for a function, you can easily
use a decoder (a minterm generator) to implement that function.

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 Design example: addition
• Let’s make a circuit that adds three 1-bit inputs X, Y and Z.
• We will need two bits to represent the total; let’s call them C and S,
for “carry” and “sum.” Note that C and S are two separate functions of
the same inputs X, Y and Z.
• Here are a truth table and sum-of-minterms equations for C and S.

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1 C(X,Y,Z) = Σm(3,5,6,7)
0 + 1 + 1 = 10 0 1 1 1 0 S(X,Y,Z) = Σm(1,2,4,7)
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 1 + 1 + 1 = 11

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 Decoder-based adder
• Here, two 3-to-8 decoders implement C and S as sums of minterms.

C(X,Y,Z) = Σm(3,5,6,7)
S(X,Y,Z) = Σm(1,2,4,7)

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 Using just one decoder
• Since the two functions C and S both have the same inputs, we could
use just one decoder instead of two.

C(X,Y,Z) = Σm(3,5,6,7)
S(X,Y,Z) = Σm(1,2,4,7)

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 Building a 3-to-8 decoder
• You could build a 3-to-8 decoder directly from the truth table and
equations below, just like how we built the 2-to-4 decoder.
• Another way to design a decoder is to break it into smaller pieces.
• Notice some patterns in the table below:
– When S2 = 0, outputs Q0-Q3 are generated as in a 2-to-4 decoder.
– When S2 = 1, outputs Q4-Q7 are generated as in a 2-to-4 decoder.

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 Q0 = S2’ S1’ S0’ = m0
0 1 0 0 0 1 0 0 0 0 0 Q1 = S2’ S1’ S0 = m1
0 1 1 0 0 0 1 0 0 0 0
Q2 = S2’ S1 S0’ = m2
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0 Q3 = S2’ S1 S0 = m3
1 1 0 0 0 0 0 0 0 1 0 Q4 = S2 S1’ S0’ = m4
1 1 1 0 0 0 0 0 0 0 1
Q5 = S2 S1’ S0 = m5
Q6 = S2 S1 S0’ = m6
Q7 = S2 S1 S0 = m7

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 Decoder expansion
• You can use enable inputs to string decoders together. Here’s a 3-to-8
decoder constructed from two 2-to-4 decoders:

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Modularity
• Be careful not to confuse the “inner” inputs and outputs of the 2-to-4
decoders with the “outer” inputs and outputs of the 3-to-8 decoder
(which are in boldface).
• This is similar to having several functions in a program which all use a
formal parameter “x”.

• You could verify that this circuit is a 3-to-8 decoder, by using equations
for the 2-to-4 decoders to derive equations for the 3-to-8.

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 A variation of the standard decoder
• The decoders we’ve seen so far are active-high decoders.
EN S1 S0 Q0 Q1 Q2 Q3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

• An active-low decoder is the same thing, but with an inverted EN input

and inverted outputs.

EN’ S1 ’ S0’ Q0’ Q1 ’ Q2’ Q3’

0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 x x 1 1 1 1

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 Separated at birth?
• Active-high decoders generate minterms, as we’ve already seen.

Q3 = S1 S0
Q2 = S1 S0’
Q1 = S1’ S0
Q0 = S1’ S0’

• The output equations for an active-low decoder are mysteriously

similar, yet somehow different.

Q3’ = (S1 S0)’ = S1’ + S0’

Q2’ = (S1 S0’)’ = S1’ + S0
Q1’ = (S1’ S0)’ = S1 + S0’
Q0’ = (S1’ S0’)’ = S1 + S0

• It turns out that active-low decoders generate maxterms.

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 Product of maxterms form
• Every function can be written as a unique product of maxterms:
– Only AND (product) operations occur at the “outermost” level.
– Each term must be maxterm.
• If you have a truth table for a function, you can write a product of
maxterms expression by picking out the rows of the table where the
function output is 0.

x y z f(x,y ,z) f’ (x,y ,z) f = M4 M5 M7

0 0 0 1 0
= ∏M(4,5,7)
0 0 1 1 0
= (x’ + y + z)(x’ + y + z’)(x’ + y’ + z’)
0 1 0 1 0
0 1 1 1 0 f’ = M0 M1 M2 M3 M6
1 0 0 0 1
= ∏M(0,1,2,3,6)
1 0 1 0 1
1 1 0 1 0 = (x + y + z)(x + y + z’)(x + y’ + z)
1 1 1 0 1 (x + y’ + z’)(x’ + y’ + z)

f’ contains all the maxterms not in f.

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 Active-low decoder example
• So we can use active-low decoders to implement arbitrary functions
too, but as a product of maxterms.
• For example, here is an implementation of the function from the
previous page, f(x,y,z) = ΠM(4,5,7), using an active-low decoder.

• The “ground” symbol connected to EN represents logical 0, so this

decoder is always enabled.
• Remember that you need an AND gate for a product of sums.

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 Converting between standard forms
• We can easily convert a sum of minterms to a product of maxterms.

f = Σm(0,1,2,3,6)
f’ = Σm(4,5,7) -- f’ contains all the minterms not in f
= m4 + m 5 + m7
(f’)’ = (m4 + m5 + m7)’ -- complementing both sides
f = m4’ m5’ m7’ -- DeMorgan’s law
= M4 M5 M7 -- from the previous page
= ∏M(4,5,7)
• The easy way is to replace minterms with maxterms, using maxterm
numbers that don’t appear in the sum of minterms:

f = Σm(0,1,2,3,6)
= ∏M(4,5,7)
• The same thing works for converting in the opposite direction, from a
product of maxterms to a sum of minterms.

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 Summary
• A n-to-2n decoder generates the minterms of an n-variable function.
– As such, decoders can be used to implement arbitrary functions.
– Later on we’ll see other uses for decoders too.
• Some variations of the basic decoder include:
– Adding an enable input.
– Using active-low inputs and outputs to generate maxterms.
• We also talked about:
– Applying our circuit analysis and design techniques to understand
and work with decoders.
– Using block symbols to encapsulate common circuits like decoders.
– Building larger decoders from smaller ones.

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 Multiplexers/demultiplexers
PLD components

Acknowledgment: Most of the following slides are adapted from Prof.

Kale's slides at UIUC, USA.
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 In the good old times
• Multiplexers, or muxes, are used to choose between resources.
• A real-life example: in the old days before networking, several
computers could share one printer through the use of a switch.

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 Multiplexers
• A 2n-to-1 multiplexer sends one of 2n input lines to a single output line.
– A multiplexer has two sets of inputs:
• 2n data input lines
• n select lines, to pick one of the 2n data inputs
– The mux output is a single bit, which is one of the 2n data inputs.
• The simplest example is a 2-to-1 mux:

Q = S’ D0 + S D1
• The select bit S controls which of the data bits D0-D1 is chosen:
– If S=0, then D0 is the output (Q=D0).
– If S=1, then D1 is the output (Q=D1).

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 More truth table abbreviations
• Here is a full truth table for this 2-to-1 mux, S D1 D0 Q
based on the equation: 0 0 0 0
0 0 1 1
0 1 0 0
Q = S’ D0 + S D1 0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Here is another kind of abbreviated truth table.

– Input variables appear in the output column.
– This table implies that when S=0, the output S Q
Q=D0, and when S=1 the output Q=D1. 0 D0
1 D1
– This is a pretty close match to the equation.

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 A 4-to-1 multiplexer
• Here is a block diagram and abbreviated truth table for a 4-to-1 mux.

EN’ S1 S0 Q
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 x x 1

Q = S1’ S0’ D0 + S1’ S0 D1 + S1 S0’ D2 + S1 S0 D3

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 Implementing functions with multiplexers
• Muxes can be used to implement arbitrary functions.
• One way to implement a function of n variables is to use an n-to-1 mux:
– For each minterm mi of the function, connect 1 to mux data input Di.
Each data input corresponds to one row of the truth table.
– Connect the function’s input variables to the mux select inputs.
These are used to indicate a particular input combination.
• For example, let’s look at f(x,y,z) = Σm(1,2,6,7).

x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

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 A more efficient way
• We can actually implement f(x,y,z) = Σm(1,2,6,7) with x y z f
just a 4-to-1 mux, instead of an 8-to-1. 0 0 0 0
0 0 1 1
• Step 1: Find the truth table for the function, and 0 1 0 1
group the rows into pairs. Within each pair of rows, x 0 1 1 0
and y are the same, so f is a function of z only. 1 0 0 0
1 0 1 0
– When xy=00, f=z 1 1 0 1
– When xy=01, f=z’ 1 1 1 1
– When xy=10, f=0
– When xy=11, f=1

• Step 2: Connect the first two input variables of the

truth table (here, x and y) to the select bits S1 S0 of
the 4-to-1 mux.

• Step 3: Connect the equations above for f(z) to the

data inputs D0-D3.

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 Example: multiplexer-based adder
• Let’s implement the adder carry function, C(X,Y,Z), with muxes.
• There are three inputs, so we’ll need a 4-to-1 mux.
• The basic setup is to connect two of the input variables (usually the
first two in the truth table) to the mux select inputs.

X Y Z C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
With S1=X and S0=Y, then
Q=X’Y’D0 + X’YD1 + XY’D2 + XYD3

Equation for the multiplexer

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 Multiplexer-based carry
• We can set the multiplexer data inputs D0-D3, by fixing X and Y and
finding equations for C in terms of just Z.

X Y Z C
0 0 0 0
0 0 1 0
When XY=00, C=0
0 1 0 0
0 1 1 1
1 0 0 0 When XY=01, C=Z
1 0 1 1
1 1 0 1
1 1 1 1 When XY=10, C=Z

When XY=11, C=1

C = X’ Y’ D0 + X’ Y D1 + X Y’ D2 + X Y D3
= X’ Y’ 0 + X’ Y Z + X Y’ Z + X Y 1
= X’ Y Z + X Y’ Z + XY
= Σm(3,5,6,7)

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 Multiplexer-based sum
• Here’s the same thing, but for the sum function S(X,Y,Z).

X Y Z S
0 0 0 0
0 0 1 1
0 1 0 1 When XY=00, S=Z
0 1 1 0
1 0 0 1 When XY=01, S=Z’
1 0 1 0
1 1 0 0
1 1 1 1 When XY=10, S=Z’

When XY=11, S=Z

S = X’ Y’ D0 + X’ Y D1 + X Y’ D2 + X Y D3
= X’ Y’ Z + X’ Y Z’ + X Y’ Z’ + X Y Z
= Σm(1,2,4,7)

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 Summary
• A 2n-to-1 multiplexer routes one of 2n input lines to a single output line.
• Just like decoders,
– Muxes are common enough to be supplied as stand-alone devices for
use in modular designs.
– Muxes can implement arbitrary functions.
• We saw some variations of the standard multiplexer:
– Smaller muxes can be combined to produce larger ones.
– We can add active-low or active-high enable inputs.
• As always, we use truth tables and Boolean algebra to analyze things.

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The following slides are adapted from David
Culler’s slides used at Electrical Engineering and
Computer Sciences, University of California, Berkeley
 Binary Addition: Half Adder

Ai 0 Ai
1 0 1
Ai Bi Sum Carry Bi Bi
0 0 0 0 0 0 1 0 0 0
0 1 1 0
1 0 1 0 1 0
1 1 0 1
1 1 0 1

Sum = Ai Bi + Ai Bi Carry = Ai Bi
= Ai + Bi
Ai
Sum
Bi Half-adder Schematic
Carry

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 Full-Adder

1
0011 A B CI S CO AB
Co Cin
0 0 0 0 0 CI 00 01 11 10
+ 0010 B 0 0 1 1 0 0 0 1 0 1
0 1 0 1 0 S
0101 A 0 1 1 0 1 1 1 0 1 0
1 0 0 1 0
S 1 0 1 0 1
1 1 0 0 1 AB
1 1 1 1 1 CI 00 01 11 10
0 0 0 1 0
CO
1 0 1 1 1
S = CI xor A xor B

CO = B CI + A CI + A B = CI (A + B) + A B

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 Ripple Carry

A3 B3 A2 B2 A1 B1 A0 B0

+ + + +

S3 C3 S2 C2 S1 C1 S0

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 Full Adder from Half Adders

A S
A+B S
A + B + CI S
Half Half
AdderCO A B AdderCO CI (A + B)
B
CI
CO

A B + CI (A xor B) = A B + B CI + A CI

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 Delay in the Ripple Carry
Adder
Critical delay: the propagation of carry from low to high order stages

@0 A @1
late @0 B
@N+1

arriving @N CI CO
signal
@0 A @N+2 two gate delays
@0 B
@1 to compute CO

C0

A0 S0 @2
0
B0 C1 @2
4 stage
adder A1
1
S1 @3
B1 C2 @4
A2 S2 @5
2
B2 C3 @6

A3 S3 @7
B3
3
C4 @8 final sum and
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 Ripple Carry Timing

Critical delay: the propagation of carry from low to high order stages
S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid

1111 + 0001
worst case
addition

T0 T2 T4 T6 T8

T0: Inputs to the adder are valid

T2: Stage 0 carry out (C1) 2 delays to compute sum

T4: Stage 1 carry out (C2)
but last carry not ready
T6: Stage 2 carry out (C3) until 6 delays later
T8: Stage 3 carry out (C4)

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 What really happens with the carries

b0 a0
c7 c6 c5 c4 c3 c2
c0
FA

s7 s6 c1 s0

A B Cout S Carry action

Ai
0 0 0 Cin kill Gi
Propagate Bi
0 1 Cin ~Cin
4 0 Cin ~Cin propagate Ai
Pi
1 1 1 Cin generate
Bi

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here
All generates and propagates in parallel at first stage. No ripple.
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 Carry Look Ahead Logic

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here

Sum and Carry can be reexpressed in terms of generate/propagate:

Si = Ai xor Bi xor Ci = Pi xor Ci Ci

Si
Pi
Ci+1 = Ai Bi + Ai Ci + Bi Ci

= Ai Bi + Ci (Ai + Bi)
Gi
= Ai Bi + Ci (Ai xor Bi)
Ci Ci+1
= Gi + Ci Pi Pi

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 All Carries in Parallel

Reexpress the carry logic for each of the bits:

C1 = G0 + P0 C0

C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

Each of the carry equations can be implemented in a two-level logic

network

Variables are the adder inputs and carry in to stage 0!

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