AP7173
AP7173
Features Applications
● Low VIN and wide VIN range: 1.0V to 5.5V • PCs, Servers, Modems, and Set-Top-Boxes
● Bias voltage (VVCC) range: 2.7V to 5.5V • FPGA Applications
● Low VOUT range: 0.8V to 3.3V • DSP Core and I/O Voltages
● Low dropout: 165mV typical at 1.5A, VVCC = 5V • Post-Regulation Applications
● 2% accuracy over line, load and temperature range • Applications With Sequencing Requirements
● Power-Good (PG) output for supply monitoring and for
sequencing of other supplies
● Programmable soft-start provides linear voltage startup
● Bias supply permits low VIN operation with good transient
response
● Stable with any output capacitor ≥ 2.2µF
● DFN3030-10 and SO-8EP: available in “Green” molding
compound (No Br, Sb)
● Lead-free finish/ RoHS Compliant (Note 1)
Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at
http://www.diodes.com/products/lead_free.html.
R3 VOUT
VIN
IN OUT R1 C2
C1 PG FB
VVCC AP7173
VCC SS R2
EN GND CSS
C3
Pin Descriptions
PIN #
Pin Name Description
SO-8EP DFN3030-10
IN 1 1, 2 Power Input pin.
Power-Good pin, open-drain output. When the VOUT is below the
PG threshold the PG pin is driven low; when the VOUT exceeds the
PG 2 3 threshold, the PG pin goes into a high-impedance state. To use the PG
pin, use a 10kΩ to 1MΩ pull-up resistor to pull it up to a supply of up to
5.5V, which can be higher than the input voltage.
Bias Input pin, provides input voltage for internal control circuitry. This
VCC 3 4
voltage should be higher than the VIN.
Enable pin. This pin should be driven either high or low and must not
EN 4 5 be floating. Driving this pin high enables the regulator, while pulling it
low puts the regulator into shutdown mode.
GND 5 6 Ground.
Soft-Start pin. Connect a capacitor between this pin and the ground to
SS 6 7 set the soft-start ramp time of the output voltage. If no capacitor is
connected, the soft-start time is typically 100µS.
Feedback pin. Connect this pin to an external voltage divider to set the
FB 7 8
output voltage.
OUT 8 9, 10 Regulated Output pin.
Solder this pad to large ground plane for increased thermal
Thermal Pad — —
performance.
IN OUT
VCC SS
+ 0.8V
-
PG FB
-
+ 0.72V
GND
Electrical Characteristics
At VEN = 1.1V, VIN = VOUT + 0.5V, CVCC = 0.1uF, CIN = COUT = 10uF, IOUT = 50mA, VVCC = 5.0V, and TA = –40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C.
Symbol Parameter Test Conditions Min Typ. Max Unit
VIN Input Voltage Range VOUT + VDO 5.5 V
Bias Pin Voltage Range
VVCC 2.7 5.5 V
(Note 7)
Internal Reference
VREF TA = +25 ºC 0.792 0.8 0.808 V
(Adj.)
Output Voltage Range VIN= 5V, IOUT= 1.5A 0.8 3.3 V
VOUT 2.97V≤VVCC≤5.5V,
Accuracy (Note 8) –2 ±0.5 2 %
50mA≤IOUT≤1.5A
ΔVOUT /ΔVIN /
Line Regulation VOUT (NOM) + 0.5≤VIN, 5.5V 0.03 %/V
VOUT
ΔVOUT /VOUT
Load Regulation 50mA≤IOUT≤1.5A 0.09 %/A
/ΔIOUT
Dropout Voltage IOUT = 1.5A,VVCC–VOUT(NOM)≥3.25V 165 270 mV
VDO
(Note 9) IOUT= 1.5A, VIN = VVCC 1.5 1.7 V
ICL Current Limit VOUT = 80% x VOUT (NOM) 2 3 4 A
ISHORT Short-Circuit Current VOUT < 0.2V 0.6 1 A
IVCC Bias Pin Current 1 2 mA
Shutdown Supply
ISHDN VEN≤0.4V 1 50 µA
Current (IGND)
IFB Feedback Pin Current –1 0.1 1 µA
1KHz, IOUT= 1A,
60
Power-Supply Rejection VIN= 1.8V, VOUT= 1.5V
dB
(VIN to VOUT) 300KHz, IOUT =1A,
30
VIN= 1.8V, VOUT =1.5V
PSRR
1KHz, IOUT = 1A,
50
Power-SupplyRejection VIN= 1.8V, VOUT =1.5V
dB
(VVCC to VOUT) 300KHz, IOUT = 1A,
30
VIN= 1.8V, VOUT =1.5V
TST Startup Time RLOAD for IOUT = 1.0A, CSS = open 100 µS
Soft-Start Charging
ISS VSS= 0.4V 440 nA
Current
VEN, HI Enable Input High Level 1.1 5.5 V
VEN, LO Enable Input Low Level 0 0.4 V
VEN, HYS Enable Pin Hysteresis 50 mV
IEN Enable Pin Current VEN= 5V 0.1 1 µA
VPG, TH PG Trip Threshold VOUT decreasing 85 90 94 %VOUT
VPG, HYS PG Trip Hysteresis 3 %VOUT
VPG, LO PG Output Low Voltage IPG= 1mA (sinking), VOUT<VPG, TH 0.3 V
IPG, LKG PG Leakage Current VPG= 5.25V, VOUT>VPG, TH 0.1 1 µA
Thermal Shutdown Shutdown, temperature increasing +150
TSD ºC
Temperature Reset, temperature decreasing +130
Thermal Resistance DFN3030-10 (Note 10) 35 o
θJA C/W
Junction-to-Ambient SO-8EP (Note 11) 23
Thermal Resistance DFN3030-10 (Note 10) 4.9 o
θJC C/W
Junction-to-Case SO-8EP (Note 11) 1.8
Notes: 7. VVCC should be higher or equal to VIN in this chip.
8. Tested at 0.8V; resistor tolerance is not taken into account.
9. Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
10. Test condition for DFN3030-10: Device mounted on FR-4 substrate (2s2p), 2"*2" PCB, with 2oz copper trace thickness and large pad pattern.
11. Test condition for SOP-8L-EP: Device mounted on FR-4 substrate (2s2p), 2"*2" PCB, with 2oz copper trace thickness and large pad pattern.
Typical Characteristics
At TA = +25℃, VIN = VOUT(TYP) + 0.3V, VVCC = 5V, IOUT = 50mA, VEN = VIN, CIN = 1µF, CVCC = 4.7µF, and COUT = 10µF, unless otherwise noted.
0.20 0.5
0.4
0.15
0.3
0.10
o o o o
25 C 125 C
change in Vout(%)
25 C 125 C 0.2
0.05
0.1
Vout(V)
0.00 0.0
-0.05 o -0.1
-40 C
-0.2 o
-0.10 -40 C
-0.3
-0.15
-0.4
-0.20 -0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Vin-Vout(V) Vvcc-Vout(V)
Figure. 3 VIN Line Regulation Figure. 4 VVCC Line Regulation
1.0
o
0.8 25 C
0.6
o
125 C
0.4
Change Vout(%)
0.2
0.0
-0.2
-0.4
o
-0.6 -40 C
-0.8
-1.0
50 200 350 500 650 800 950 1100 1250 1400 1500
Iout(mA)
Figure. 5 Load Regulation
Figure .6 Load Regulation
240 300
220 280
260
200 o
240 125 C
VDropout(Vin-Vout)(mV)
180
VDropout(Vin-Vout)(V)
o 220
25 C
160 200 o
180
25 C
140 o
125 C
160
120 o
140 -40 C
100 120
80 100
80
Iout=1.5A
60
60
40 o
-40 C 40
20 20
0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Iout(mA) Vvcc-Vout(V)
Figure. 7 VIN Dropout Voltage vs. Figure. 8 VIN Dropout Voltage vs.
IOUT and Temperature (TA) (VVCC-VOUT) and Temperature (TA)
200 2000
180
1800
Iout=0.5A
160
VDropout(Vvcc-Vout)(mV)
VDropout(Vin-Vout)(mV)
1600
140 o
125 C
120 1400
o
25 C o
100 125 C o
-40 C
1200
80
o
60 1000 25 C
40
800
20 o
-40 C
0 600
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.00 0.25 0.50 0.75 1.00 1.25 1.50
Vvcc-Vout Iout(A)
Figure. 9 VIN Dropout Voltage vs. Figure. 10 VVCC Dropout Voltage vs.
(VVCC-VOUT) and Temperature (TA) IOUT and Temperature (TA)
90 90
80 80
Power Supply Rejection Ratio(dB)
Io=0.1A
70 70
Io=0.1A
60 60
50 Io=1.5A 50
40 40
Vin=1.8V Vin=1.8V
30 30
Vout=1.2V Vout=1.2V
Vvcc=5V Vvcc=5V
20 20 Io=1.5A
Css=1nF
Css=1nF
10 10
0 0
10 100 1000 10000 100000 10 100 1000 10000 100000 1000000 1E7
500000
Frequency(Hz) Frequency(Hz)
Figure. 11 VIN PSRR vs. Frequency Figure. 12 VVCC PSRR vs. Frequency
90 0.8
Power Supply Rejection Ratio(dB)
80 Vout=1.2V 0.7
Iout=1.5A
70 1KHz
Css=1nF 0.6
60
10KHz 0.5
50
100KHz 0.4
40
0.3
30
500KHz 0.2
20
10 0.1
0
0.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
0 2 4 6 8 10 12
Vin-Vout(V) PG Current(mA)
Figure. 13 VIN PSRR vs. (VIN-VOUT) Figure. 14 Low-Level PG Voltage vs Current
1.8 1.8
1.6 1.6
o o
25 C 125 C o
25 C
o
125 C
1.4 1.4
1.2
Ivcc(mA)
1.2
Ivcc(mA)
1.0 1.0
0.8 0.8
0.6 0.6 o
o
-40 C
-40 C
0.4 0.4
0.2 0.2
0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
Iout(A) Vvcc(V)
Figure. 19 VCC Pin Current vs. IOUT and Temperature Figure. 20 VCC Pin Current vs. VVCC and Temperature
1.15
Io=0A
Quiescent Current(mA)
1.25
1.10 Io=1.5A
Vin=2.5V
1.05
1.00
1.00
0.95
0.90
Vin=1.8V
Vin=1.8V 0.75
0.85 Vout=1.2V
Io=0.5A
0.80
0.75
0.50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 2.50 2.75 3.00 3.25 3.50
Iout(A) Vvcc(V)
Figure. 21 Quiescent Current vs. IOUT Figure 22. Quiescent Current vs. VVCC
1.50 3.0
2.9
Vvcc=5V 2.8
Quiescent Current(mA)
1.25
2.7
Current limit(A)
2.6
o o
25 C -40 C
1.00 2.5
2.1
0.50 2.0
-50 -25 0 25 50 75 100 125 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Temperature( C)
o Vvcc-Vout(V)
Figure. 23 Quiescent Current vs. Temperature Figure. 24 Current Limit vs. (VVCC-VOUT)
500
475
450
425
Iss(nA)
400
375
350
325
300
-50 -25 0 25 50 75 100 125
o
Temperature( C)
Application Notes
POWER DISSIPATION
Thermal shutdown is intented to protect the AP7173
against abnormal overheating. For normal operation,
excessive power dissipation should be avoided and good
heatsinking should be provided. Power dissipation in the
device is the product of the device dropout voltage and
the load current,
Figure 30. Delayed Start Using an RC PD = (VIN - VOUT) x IOUT
Circuit to Enable AP7173
As can be seen, power dissipation can be minimized by
POWER-GOOD using the lowest input voltage necessary to achieve the
required output voltage regulation.
The power-good (PG) pin is an open-drain output and can
To ensure that the device junction temperature does not
be pulled up through a resistor of 10kΩ to1MΩ to VIN, VOUT
exceed the specified limit of 125°C, an application should
or any other rail that is 5.5V or lower. When the VOUT ≥
provide heat conduction paths that have junction-to-
VPG,TH+VPG,HYS, the PG output is high-impedance; if the
ambient thermal resistance lower than the calculated
VOUT drops to below VPG,TH, VVCC ≤ 1.9V or the device is
value here:
disabled, the PG pin is pulled to low by an internal
MOSFET. RθJA = (125°C –TA ) / PD
Ordering Information
AP 7173 - XX G - X
Marking Information
(1) DFN3030-10
( Top View )
XX : Identification Code
XX Y : Year : 0~9
YWX W : Week : A~Z : 1~26 week;
a~z : 27~52 week; z represents
52 and 53 week
X : A~Z : Green
(2) SO-8EP
( Top View )
8 5
Logo G : Green
YY : Year : 08, 09,10~
Part No . AP7173 WW : Week : 01~52; 52
YY WW X X E represents 52 and 53 week
X : Internal Code
SO-8EP
1 4
Detail "A"
Exposed pad
7°~9°
3.85/3.95
5.90/6.10
3.70/4.10
2.4Ref.
45°
0.35max.
7°~9° 1 0.15/0.25 1
3.3Ref.
1.30/1.50
Bottom View
1.75max.
1.27typ 0.3/0.5
0.254
0/0.13
6x-1.27
8x-1.55
Tape Orientation
For DFN3030-10
Notes: 13. The taping orientation of the other package type can be found on our website at http://www.diodes.com/datasheets/ap02007.pdf
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