Exercise ::

Digital Arithmetic Operations and

Circuits
- General Questions A. 1110 1101
1. For a 4-bit parallel adder, if the carry-in is
connected to a logical HIGH, the result is: B. 1111 1001
the same as if the carry-in is tied C. 1111 0011
A. LOW since the least significant
carry-in is ignored. D. 1110 1001

B. that carry-out will always be HIGH. Answer: Option C

a one will be added to the final

C.
result. 5. Multiply the following binary numbers.
1010 1011 1001
D. the carry-out is ignored.
×0011 ×0111 ×1010
Answer: Option C
A 0001 1110 0100 1101 0101 10
. 11
2. What is the first thing you will need if you
B 0001 1110 0100 1100 0101 10
are going to use a macrofunction?
. 10
A. A complicated design project
C 0001 1110 0100 1101 0101 10
B. An experienced design engineer . 10

C. Good documentation D 0001 1101 0100 1101 0101 10

. 10
D. Experience in HDL
Answer: Option C
Answer: Option C Explanation:

3. Perform subtraction on each of the 6. Add the following BCD numbers.

following binary numbers by taking the 0110 0111 1001
two's-complement of the number being 0101 1000 1000
subtracted and then adding it to the first
number. A 0000 1011 0000 1111 0001 00
01001 01100 . 01
00011 00111
B 0001 0001 0001 0101 0001 00
A. 01100 10011 . 01

B. 00110 00101 C 0000 1011 0000 1111 0001 01

. 11
C. 10110 10101
D 0001 0001 0001 0101 0001 01
D. 00111 00100 . 11
Answer: Option B Answer: Option D

4. Solving –11 + (–2) will yield which two's- 7. Add the following hexadecimal numbers.
complement answer?
 3C 14 3B Answer: Option B
+25 +28 +DC
A. 60 3C 116 11. The most commonly used system for
representing signed binary numbers is
B. 62 3C 118 the:
A. 2's-complement system.
C. 61 3C 117
B. 1's-complement system.
D. 61 3D 117
Answer: Option C C. 10's-complement system.

D. sign-magnitude system.
8. Solve this BCD problem: 0100 + 0110 = Answer: Option A
A. 00010000BCD

B. 00010111BCD 12. What is the major difference between half-

adders and full-adders?
C. 00001011BCD
Nothing basically; full-adders are
A.
D. 00010011BCD made up of two half-adders.

Answer: Option A Full adders can handle double-digit

B.
numbers.

Full adders have a carry input

9. What are constants in VHDL code? C.
capability.
Fixed numbers represented by a
A.
name Half adders can handle only single-
D.
digit numbers.
B. Fixed variables used in functions
Answer: Option C
C. Fixed number types

Constants do not exist in VHDL 13. The decimal value for E16 is:
D.
code.
A. 1210
Answer: Option A
B. 1310

C. 1410
10. The 2's-complement system is to be used D. 1510
to add the signed binary numbers
11110010 and 11110011. Determine, in Answer: Option C
decimal, the sign and value of each
number and their sum.
A. –113 and –114, –227 14. Fast-look-ahead carry circuits found in
most 4-bit full-adder circuits:
B. –14 and –13, –27 A. determine sign and magnitude
C. –11 and –16, –27 B. reduce propagation delay
D. –27 and –13, –40 C. add a 1 to complemented inputs
 D. increase ripple delay A. 111010
Answer: Option B B. 110110

C. 110101
15. Add the following hex numbers: 011016 +
1001016 D. 101011
A. 1012016 Answer: Option C

B. 1002016
19. Convert each of the following signed
C. 1112016 binary numbers (two's-complement) to a
signed decimal number.
D. 0012016
00000101 11111100 11111000
Answer: Option A
A. –5 +4 +8

16. The binary subtraction 0 – 0 = B. +5 –4 –8

difference = 0 C. –5 +252 +248

A.
borrow = 0
D. +5 –252 –248
difference = 1
B. Answer: Option B
borrow = 0

difference = 1
C.
borrow = 1 20. How many basic binary subtraction
operations are possible?
difference = 0
D. A. 4
borrow = 1
Answer: Option A B. 3

C. 2
17. Convert each of the decimal numbers to D. 1
8-bit two's-complement form and then
perform subtraction by taking the two's- Answer: Option A
complement and adding.
21. If [A] = 1011 1010, [B] = 0011 0110, and
[C] = [A] • [B], what is [C 4..2] in decimal?

A. 0001 0011 A. 1

B. 0000 1110 B. 2

C. 0010 1110 C. 3

D. 1110 0000 D. 4

Answer: Option B Answer: Option D

18. Adding in binary, a decimal 26 + 27 will 22. Using 4-bit adders to create a 1See
produce a sum of: Section 6-bit adder:
 A. requires 16 adders. 25. When 1100010 is divided by 0101, what is
the decimal remainder?
B. requires 4 adders. A. 2
requires the carry-out of the less B. 3
significant adder to be connected
C.
to the carry-in of the next significant C. 4
adder.
D. 6
requires 4 adders and the
Answer: Option B
connection of the carry out of the
D.
less significant adder to the carry-in
of the next significant adder. 26. One way to make a four-bit adder perform
Answer: Option D subtraction is by:
A. inverting the output.

23. When performing subtraction by addition B. inverting the carry-in.

in the 2's-complement system:
C. inverting the B inputs.
the minuend and the subtrahend
A. are both changed to the 2's- D. grounding the B inputs.
complement.
Answer: Option C
the minuend is changed to 2's-
B. complement and the subtrahend is
left in its original form. 27. What is the most important operation in
binary-coded decimal (BCD) arithmetic?
the minuend is left in its original
C. form and the subtrahend is A. addition
changed to its 2's-complement.
B. subtraction
the minuend and subtrahend are
D. C. multiplication
both left in their original form.
Answer: Option C D. division
Answer: Option A

24. The two's-complement system is to be

used to add the signed numbers 28. The range of positive numbers when
11110010 and 11110011. Determine, in using an eight-bit two's-complement
decimal, the sign and value of each system is:
number and their sum.
A. 0 to 64
A. –14 and –13, –27
B. 0 to 100
B. –113 and –114, 227
C. 0 to 127
C. –27 and –13, 40
D. 0 to 256
D. –11 and –16, –27
Answer: Option C
Answer: Option A
29. What are the two types of basic adder 32. If B[7..0] = 10100101, what is the value of
circuits? B[6..2]?
A. sum and carry A. 10100

B. half-adder and full-adder B. 01001

C. asynchronous and synchronous C. 10010

D. one- and two's-complement D. 00101

Answer: Option B Answer: Option B

30. The truth table for a full adder is shown 33. How many inputs must a full-adder have?
below. What are the values of X, Y, A. 4
and Z?
B. 2

C. 5

D. 3
Answer: Option D

34.

A. 10011110
A. X = 0, Y = 1, Z = 1 B. 01211110
B. X = 1, Y = 1, Z = 1 C. 000100000100
C. X = 1, Y = 0, Z = 1 D. 001000001000
D. X = 0, Y = 0, Z = 1 Answer: Option C
Answer: Option B

35. Determine the two's-complement of each

31. A half-adder circuit would normally be binary number.
used each time a carry input is required in 00110 00011 11101
an added circuit. A. 11001 11100 00010
A. True
B. 00111 00010 00010
B. False
C. 00110 00011 11101
Answer: Option B
D. 11010 11101 00011
Answer: Option D
36. Solve this binary problem: 01110010 – 40. Perform the following hex subtraction:
01001000 = ACE16 – 99916 =
A. 00011010 A. 23516

B. 00101010 B. 13516

C. 01110010 C. 03516

D. 00111100 D. 33516
Answer: Option B Answer: Option B

41. Which of the following is correct for full

37. What distinguishes the look-ahead-carry
adders?
adder?
Full adders have the capability of
It is slower than the ripple-carry A.
A. directly adding decimal numbers.
adder.
Full adders are used to make half
It is easier to implement logically B.
B. adders.
than a full adder.
Full adders are limited to two inputs
C. It is faster than a ripple-carry adder.
C. since there are only two binary
It requires advance knowledge of digits.
D.
the final answer.
In a parallel full adder, the first
D.
Answer: Option C stage may be a half adder.
Answer: Option D

38. Solve this binary problem:

42. Convert each of the signed decimal
numbers to an 8-bit signed binary number
(two's-complement).
A. 1001 +7 –3 –12
A 0000 0111 1111 1101 1111 0
B. 0110 . 100
C. 0111 B 1000 0111 0111 1101 0111 0
. 100
D. 0101
Answer: Option C C 0000 0111 0000 0011 0000 1
. 100

D 0000 0111 1000 0011 1000 1

39. Half-adders can be combined to form a . 100
full-adder with no additional gates.
Answer: Option A
A. True

B. False
43. What is one disadvantage of the ripple-
Answer: Option B carry adder?
 The interconnections are more Answer: Option C
A.
complex.

More stages are required to a full 47. When multiplying 13 × 11 in binary, what
B.
adder. is the third partial product?

C. It is slow due to propagation time. A. 1011

D. All of the above. B. 00000000

Answer: Option C C. 100000

D. 100001
44. Solve this binary problem: 01000110 ÷ Answer: Option B
00001010 =
A. 0111
48. How many BCD adders would be required
B. 10011 to add the numbers 97310 + 3910?

C. 1001 A. 3

D. 0011 B. 4

Answer: Option A C. 5

D. 6
45 Divide the following binary numbers. Answer: Option A
.

49. The selector inputs to an arithmetic/logic

A 0000 0010 0000 0010 1000 11
unit (ALU) determine the:
. 11
A. selection of the IC
B 0000 0010 0001 0010 0000 01
. 00 B. arithmetic or logic function

C 0000 0011 0000 0010 0000 01 C. data word selection

. 00
D. clock frequency to be used
D 0000 0010 0000 0010 0000 01 Answer: Option B
. 00
Answer: Option D
46 Convert the decimal numbers 275 and 965 50. What is wrong, if anything, with the circuit
. to binary-coded decimal (BCD) and add. . in the given figure based on the logic
Select the BCD code groups that reflect the analyzer display accompanying the circuit?
final answer.
A. 1101 1110 1010

B. 1110 1010 1110

C. 0001 0010 0100 0000

D. 0010 0011 0100 0000

 Full-carry adder; Sum = 1, Carry =
C.
0

Full-carry adder; Sum = 1, Carry =

D.
1
Answer: Option A

52. An 8-bit register may provide storage for

two's-complement codes within which
decimal range?
A. +128 to –128

B. –128 to +127

C. +128 to –127

D. +127 to –127
The CO terminal is shorted to
A. Answer: Option B
ground.

B. The S1 output is shorted to Vcc.

53. A full-adder adds ________.
The P1 input is not being added into
C. A. two single bits and one carry bit
the total.

Nothing is wrong; the circuit is B. two 2-bit binary numbers

D.
functioning correctly.
C. two 4-bit binary numbers
Answer: Option C
D. two 2-bit numbers and one carry bit
51. Which of the statements below best Answer: Option A
describes the given figure?

54. The carry propagation delay in 4-bit full-

adder circuits:
is cumulative for each stage and
A. limits the speed at which arithmetic
operations are performed

is normally not a consideration

B. because the delays are usually in
the nanosecond range

decreases in direct ratio to the total

C.
number of full-adder stages
Half-carry adder; Sum = 0, Carry =
A.
1 increases in direct ratio to the total
number of full-adder stages, but is
Half-carry adder; Sum = 1, Carry = D.
B. not a factor in limiting the speed of
0 arithmetic operations
Answer: Option A
 59. Which of the following is the primary
advantage of using binary-coded decimal
55. An input to the mode pin of an (BCD) instead of straight binary coding?
arithmetic/logic unit (ALU) determines if
the function will be: Fewer bits are required to
A. represent a decimal number with
A. one's-complemented the BCD code.
B. arithmetic or logic BCD codes are easily converted
B.
from decimal.
C. positive or negative
the relative ease of converting to
D. with or without carry C.
and from decimal
Answer: Option B
BCD codes are easily converted to
D.
straight binary codes.
56. Could the sum output of a full-adder be Answer: Option C
used as a two-bit parity generator?
A. Yes
60. How many inputs must a full-adder have?
B. No
A. 2
Answer: Option A
B. 3

57. In VHDL, what is a GENERATE C. 4

statement?
D. 5
A. The start statement of a program
Answer: Option B
B. Not used in VHDL or ADHL 61. Convert each of the decimal numbers to
two's-complement form and perform the
A way to get the computer to addition in binary.
C. generate a program from a circuit +13 –10
diagram add –7 add +15
A way to tell the compiler to A. 0001 0100 0000 0101
D.
replicate several components
Answer: Option D B. 0000 0110 0001 1001

C. 0000 0110 0000 0101

58. Binary subtraction of a decimal 15 from 43 D. 1111 0110 1111 0101

will utilize which two's complement? Answer: Option C
A. 101011

B. 110000 62. Add the following binary numbers.

C. 011100 0010 0011 0011
0110 1011 1100
D. 110001 +0101 +0001 +0001
Answer: Option D 0101 1110 1111
0111
A.
1011 0100 0001 0101 1011
 0111 B. theta
B.
1011 0101 1001 0101 1011
C. lambda
0111
C. D. sigma
0111 0101 1001 0101 1011
Answer: Option D
0111
D.
0111 0100 0001 0101 1011
Answer: Option B 66. Subtract the following hexadecimal
numbers.
47 34 FA
63. The carry propagation delay in full-adder –25 –1C –2F
circuits:
A. 22 18 CB
is normally not a consideration
A. because the delays are usually in B. 22 17 CB
the nanosecond range.
C. 22 19 CB
decreases in a direct ratio to the
B. D. 22 18 CC
total number of FA stages.
Answer: Option A
is cumulative for each stage and
C. limits the speed at which arithmetic
operations are performed.
67. What is the correct output of the adder in
increases in a direct ratio to the the given figure, with the outputs in the
total number of FA stages but is order:
D.
not a factor in limiting the speed of
arithmetic operations.
Answer: Option C

64. What is the difference between a full-

adder and a half-adder?
A. Half-adder has a carry-in.

B. Full-adder has a carry-in.

Half-adder does not have a carry-

C.
out.

Full-adder does not have a carry-

D.
out.
A. 10111
Answer: Option B
B. 11101

C. 01101
65. The summing outputs of a half- or full-
adder are designated by which Greek D. 10011
symbol?
Answer: Option A
A. omega
68. Solve this binary problem: C 0011 0101 0110 1010 1000 0
. 111

D 0011 0101 0110 1010 1000 0

. 110
A. 11001001
Answer: Option B
B. 10010000 71. Why is a fast-look-ahead carry circuit used
in the 7483 4-bit full-adder?
C. 01101110 A. to decrease the cost
D. 01110110 B. to make it smaller
Answer: Option B
C. to slow down the circuit

D. to speed up the circuit

69. The BCD addition of 910 and 710 will give
initial code groups of 1001 + 0111. Answer: Option D
Addition of these groups generates a
carry to the next higher position. The
correct solution to this problem would be 72. Find the 2's complement of –1101102.
to:
A. 1101002
ignore the lowest order code group
because 0000 is a valid code group B. 1010102
A.
and prefix the carry with three
zeros C. 0010012

add 0110 to both code groups to D. 0010102

B. validate the carry from the lowest Answer: Option D
order code group

disregard the carry and add 0110

C. 73. What logic function is the sum output of a
to the lowest order code group
half-adder?
add 0110 to the lowest order code A. AND
group because a carry was
D.
generated and then prefix the carry B. exclusive-OR
with three zeros
Answer: Option D C. exclusive-NOR

D. NAND

70. Subtract the following binary numbers. Answer: Option B

0101 1010 1101
1000 0011 1110
–0010 –0011 –0101 74. The binary adder circuit is designed to
0011 1000 0111 add ________ binary numbers at the
same time.
A 0011 0100 0110 1010 1000 0 A. 2
. 110
B. 4
B 0011 0101 0110 1011 1000 0
. 111 C. 6
 D. 8 6. A binary sum is made up of only 1s and
0s.
Answer: Option A
A. True

B. False
Exercise :: Digital Arithmetic
Operations and Circuits - True or False Answer: Option A
1. An ALU is a multipurpose device capable
of providing several different logic
operations. 7. Overflow indicators in ALU circuits
indicate when add or subtract operations
A. True produce results that are too large to fit into
four bits.
B. False
A. True
Answer: Option A
B. False
Answer: Option A
2. BCD arithmetic is performed using base
10 numbers.
A. True 8. The inputs of a full adder are
labeled A1, B1, and Cin.
B. False
A. True
Answer: Option B
B. False
Answer: Option A
3. A full adder has a carry-in.
A. True 9. Larger number capacities may be
obtained from 2-bit adders by paralleling
B. False
them.
Answer: Option A
A. True

B. False
4. Hexadecimal is a base 4 numbering Answer: Option A
system.
A. True
11. 111010002 is the 2's-complement
B. False
representation of –24.
Answer: Option B
A. True

B. False
5. The solution to the binary problem Answer: Option B
00110110 – 00011111 is 00011000.
A. True
12. The look-ahead-carry adder is slower than
B. False
the ripple-carry adder because it requires
Answer: Option B additional logic circuits.
A. True
 B. False
Answer: Option B 18. A sign bit of "1" in the difference of a 2's-
complement subtraction problem indicates
the magnitude is negative and in true
binary form.
13. The solution to the binary problem 1011 ×
0110 is 01100110. A. True
A. True B. False
B. False Answer: Option B
Answer: Option B

19. Constants must be included in a package.

14. The solution to the BCD problem 0101 + A. True
0100 is 00001001BCD.
B. False
A. True
Answer: Option A
B. False
Answer: Option A
20. 10011100 in two's-complement notation
has a decimal value of –100.
15. A macrofunction is a self-contained A. True
description of a logic circuit with all of its
inputs, outputs, and operational B. False
characteristics defined. Answer: Option B
A. True

B. False 21. There are four possible combinations for

subtracting two binary numbers.
Answer: Option A
A. True

16. A half-adder circuit would normally be B. False

used each time a carry input is required in Answer: Option A
an adder circuit.
A. True
22. It is not necessary to have the same
B. False number of bits when adding or subtracting
Answer: Option B signed binary numbers in the 2's-
complement system.
A. True
17. The binary subtraction 0 – 1 = is
difference = 1 B. False
borrow = 0 Answer: Option B
A. True

B. False 23. Full adder results are typically stored in

Answer: Option B registers.
 A. True B. False

B. False Answer: Option A

Answer: Option A
29. The carry-out of a binary adder is
identified using the summation symbol,
24. The representation of –110 in eight-bit sigma.
two's-complement notation is 11110111.
A. True
A. True
B. False
B. False
Answer: Option B
Answer: Option B

30. The 74LS382 ALU is a 24-pin

25. Binary division and decimal division use arithmetic/logic unit.
the same procedure.
A. True
A. True
B. False
B. False
Answer: Option B
Answer: Option A

31. The two's-complement method is used in

26. When the 2's-complement system is used, computer systems that perform arithmetic.
the number to be subtracted is changed to
its 2's complement and then added to the A. True
minuend. B. False
A. True Answer: Option A
B. False
Answer: Option A
32. Digital computers use an easier method to
subtract binary numbers, called one's
complement.
27. Full adders can add two numbers and
need not have a carry input or a carry A. True
output. B. False
A. True Answer: Option B
B. False
Answer: Option B
33. Binary multiplication is like decimal
multiplication except you deal only with 1s
and 0s.
28. The VHDL compiler requires libraries to
be specified at the beginning of the code if A. True
components from those libraries are being B. False
used.
Answer: Option A
A. True
34. The solution to the binary problem 1011 – Answer: Option A
0111 is 1000.
A. True
40. ALU circuits cannot be cascaded to
B. False perform functions on more than four bits.
Answer: Option B A. True

B. False
35. A 74HC283 can be used to implement a Answer: Option B
4-bit full adder.
A. True
Exercise :: Digital Arithmetic
B. False Operations and Circuits - Filling the
Blanks
Answer: Option A
1. In VHDL, the architecture declaration
always begins with the ________ of
36. The range of negative numbers when variable signals or components that will
using an eight-bit two's-complement be used in the concurrent description
system is –1 to –128. between BEGIN and END.
A. True A. type

B. False B. vectors
Answer: Option A C. functions

D. declarations
37. If no bits are designated inside square Answer: Option D
braces, [ ], it means the variable is the null
set.
A. True 2. When decimal numbers with several digits
are to be added together using BCD
B. False adders ________.
Answer: Option B a separated BCD adder is required
A.
for each digit position

38. This logic gate is used to produce an the BCD adders must have the
B.
arithmetic sum XOR. carry-outs grounded
A. True C. the BCD's must be grouped in twos
B. False D. full adders are also used
Answer: Option A Answer: Option A

39. The solution to the binary problem 0101 + 3. The binary adder circuit is designed to
1111 is 10100. add ________ binary number(s) at a time.
A. True A. 1
B. False B. 3
 C. 2 D. 5077

D. 5 Answer: Option C

Answer: Option C
8. In BCD addition, the value ________ is
added to any invalid code group.
4. The 74HC382 ALU can perform
________ operations. A. 010101

A. 2 B. 0U812

B. 4 C. 100110

C. 8 D. 0110

D. 16 Answer: Option D

Answer: Option C
9. In AHDL macrofunctions, the first thing
that should go into any source file is
5. Subtraction of the 2's-complement system ________ your code.
actually involves the operation of
________. A. a field of comments that documents

A. multiplication B. a library of

B. subtraction C. a function name of

C. addition D. the universal global definition of

D. division Answer: Option A

Answer: Option C
10 The circuit shown is a(n) ________.
6. The carry-out of a full adder is ________. .

A.

B.

C.

D.
Answer: Option D A. multiplexer

B. adder
7. FC48 – AB91 = ________.
C. comparator
A. 5B77
D. converter
B. 5267
Answer: Option B
C. 50B7
11. The binary addition of 1 + 1 = ________.
sum = 1 15. –910 represented in eight-bit two's-
A.
carry = 1 complement notation is ________.
sum = 0 A. 11110111
B.
carry = 0
B. 11111001
sum = 1
C. C. 11110110
carry = 0

sum = 0 D. 01111101
D.
carry = 1 Answer: Option A
Answer: Option D
16. Solve this binary problem: 01011000 ÷
00001011 = ________.
12. A 74HC283 can be used to implement
a(n) ________ adder. A. 1010

A. 4-bit BCD B. 0110

B. 8-bit BCD C. 1000

C. 4-bit full D. 1110

D. 8-bit full Answer: Option C

Answer: Option C
17. If [A] = 10 and [B] = 01, then [A] [b] =
________.
13. The two's complement of 00001111 is
________. A. [00]
A. 11111111 B. 00
B. 11110000 C. 11
C. 11110001 D. [11]
D. 11110111 Answer: Option C
Answer: Option C

18. Binary numbers can be added together in

a basic parallel-adder circuit when
14. Inside a computer all arithmetic
________.
operations take place in the ________.
negative numbers are in 2's-
A. accumulator register A.
complement form
B. ALU
negative numbers are in 1's-
B.
C. CPU complement form

D. B register C. all carry pins are grounded

Answer: Option B D. all negative numbers are noted

Answer: Option A
19. To make an eight-bit adder from two four- 23. A four-bit adder can perform ________.
bit adders you must connect ________. A. addition
A. the high-order carry-in to ground
B. subtraction
the low-order carry-out to the high-
B. C. logical AND
order carry-in

C. the high-order carry-out to ground D. All of the above

Answer: Option A
the low-order sum to the high-order
D.
data input
Answer: Option B 24. The concurrent section of the hardware
description is where the ________ are
interconnected.
20. Packages are used to contain ________ A. functions
and other information that must be
available to all entities in the design file. B. components
A. types
C. circuits
B. vectors
D. macrofunctions
C. components Answer: Option B
D. variables
Answer: Option C 25. The contents of the A register
after is
21. 34FC + AD31 = ________. ________.
A. E22D A. 0000
B. E31D B. 0001
C. E21D C. 1001
D. E42D D. 1010
Answer: Option A Answer: Option D

22. Solve this binary problem: 1001 × 1100 = 26. The binary subtraction 1 – 1 = ________.
________. difference = 0
A.
A. 01110001 borrow = 0

B. 01111000 difference = 1
B.
borrow = 0
C. 01101100
difference = 1
C.
D. 01101110 borrow = 1
Answer: Option C
 difference = 0 30. Solve this BCD problem: 0101 + 0110 =
D. ________.
borrow = 1
Answer: Option A A. 00010111BCD

B. 00001001BCD

27. When subtracting 6 from 9 using 2's- C. 00010001BCD

complement methods, the ________ is 2's
complemented before the addition. D. 00010011BCD
A. six Answer: Option C

B. multiplier

C. nine

D. two
Answer: Option A

28. When performing binary addition using

the 2's-complement method, an ________
can occur if ________ are of the same
________; the error is indicated by a(n)
________.
error, both numbers, magnitude,
A.
negative sign

overflow, both numbers, sign,

B.
incorrect sign bit

overflow, signs, magnitude,

C.
incorrect sum

error, the signs, polarity, incorrect

D.
polarity
Answer: Option B

29. Negation is performed by simply

performing the ________ operation.
A. 1's-complement

B. sign

C. surrogate

D. 2's-complement
Answer: Option D