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ASIC interview Question & Answer

A blog to collect the interview questions and answer for ASIC related positions

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Previous Interview Questions (1)
  e.g.  program automatic initialization;
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         ......
Verilog Interview Questions (6)         endprogram

2. What's the packed array and unpacked array?

Blog Archive
▼ 2010 (49)
    unpacked array is an array with gap between variables.
▼ November (1)
   e.g.  bit[7:0]  b_unpack[3];   // unpacked
SystemVerilog Q&A
          The system verilog simulators store each element on a 32-bit word boundary. In other words, you are
► October (2)
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using only lower 8 bits, the other 24 bits per word space is wasted.
► May (2)
► April (7)
    Packed array is an array without gap. Unpacked array is good for local individual variable access.
► February (12)
► January (23)    e.g. bit[3:0] [7:0] bytes; // 4 bytes packed into 32 bits

    In this case, all 32 bits word are packed with 4 bytes. A packed array is handy if you need to convert to and
from scalars.
Visitor's counter
3.  What's different between logic and wire?

     Logic and wire are almost the same except wire can be driven by multiple sources. Logic can only driven by
Visitor Counter single source.
Posted by Roy Chan at 6:47 AM No comments:
Labels: ASIC SystemVerilog

About Me
Roy Chan Saturday, June 5, 2010

Specialties in ASIC Design and Verification from front-

SystemVerilog Interview Questions
1.   How many array types in SystemVerilog? How do you use them?
end to back-end activities, including RTL coding,
verification (testbench development, testcase
      array_name[ ]  dynamic array
generation and test regression), logic synthesis, static
timing analysis, Place and route, power analysis, ECO
      e.g .   dyna_arr_1 = new[100] (dyna_arr_1);
and final tapeout process. Currently, I am still looking
               dyna_arr_2 = new[4]('{4,5,6}); // elements are {4,5,6,0}
for a new career.
     
View my complete profile       array [5]    fixed array
      e.g.   register1 [6][7:0] = `1;
 
      array[$]   queue
     e.g.  int q[$] = { 2, 4, 8 };
             q = {};                // clear the queue (delete all items)
             e = q[0];              //  read the first (leftmost) item
             e = q[$];              //  read the last (rightmost) item 

      array[string] or array[%] associate array

     e.g.  //associative array of 4-state integers indexed by strings, default is '1.
      integer tab [string] = '{"Peter":20, "Paul":22, "Mary":23, default:-1 };
  
2)  What is the Polymorphism?

    Polymorphism allows an entity to take a variety of representations. Polymorphism means the ability to
request that the same Operations  be performed by a wide range of different types of things. Effectively, this
means that you can ask many different objects to perform the same action.  Override polymorphism is an
override of existing code. Subclasses of existing classes are given a "replacement method" for methods in the
superclass. Superclass objects may also use the replacement methods when dealing with objects of the subtype.
The replacement method that a subclass provides has exactly the same signature as the original method in the
superclass. 

EXAMPLE: with virtual

      class A ;
      virtual  task disp ();
                $display(" This is class A ");
           endtask
      endclass
     
      class EA extends A ;
            task disp ();
                $display(" This is Extended class A ");
            endtask
      endclass
     
      program main ;
           EA my_ea;
           A my_a;
          
           initial
           begin
                my_a = new();
                my_a.disp();
               
                my_ea = new();
                my_a = my_ea;
                my_a.disp();
           end
      endprogram

RESULTS

 This is class A
 This is Extended class A

3)  how the copy works?

Answers:  
    There are 2 types of copy. Show copy or deep copy

    For example:

    class B; 

        int 
    endclass

   

     program main;
         initial
         begin
             B b1;
             B b2;
             b1 = new();
             b1.i = 123;
             b2 = b1;                   // b1 and b2 point to the same memory. The properties did not get copied.
             $display( b2.i );
         end
     endprogram
RESULTS:

123

 A shallow copy of an object copies all of the member field values.

  program main;
          initial
          begin
              B b1;
              B b2;
              b1 = new();
              b1.i = 123;
              b2 = new b1;    // shallow copy of b1
              b2.i = 321;
              $display( b1.i );
              $display( b2.i );
          end
     endprogram
    
RESULTS:

        123
        321
 
If the value of b1 change, it will also change the value of b1. It's because it's pointing to the same memory.

To avoid this, we need to use the deep copy.

Deep Copy

A deep copy copies all fields, and makes copies of dynamically allocated memory pointed to by the fields. To
make a deep copy, you must write a copy constructor and overload the assignment operator, otherwise the
copy will point to the original, with disasterous consequences.

EXAMPLE:
    class A;
        int i;
    endclass
   
    class B;
        A a;

        task copy(A a);
            this.a = new a;
        endtask

    endclass
   
    program main;
        initial
        begin
            B b1;
            B b2;
            b1 = new();
            b1.a = new();
            b1.a.i = 123;
            b2 = new b1;
            b2.copy(b1.a);
            $display( b1.a.i );
            $display( b2.a.i );
            b1.a.i = 321;
            $display( b1.a.i );
            $display( b2.a.i );
           
        end
    endprogram

RESULTS:

        123
        123
        321
        123

Posted by Roy Chan at 8:04 AM No comments:

Labels: ASIC SystemVerilog

Wednesday, April 21, 2010

SystemVerilog Interview Question 9
1)  How to kill a process in fork/join?

The kill() task terminates the given process and all its sub-processes, that is, processes spawned using fork
statements by the process being killed. If the process to be terminated is not blocked waiting on some other
condition, such as an event, wait expression, or a delay then the process shall be terminated at some
unspecified time in the current time step.

2)  What is cross coverage ?

Cross allows keeping track of information which is received simultaneous on more than one cover point. Cross
coverage is specified using the cross construct.

    program main;

    bit [0:1] y;
    bit [0:1] y_values[$]= '{1,3};
   
    bit [0:1] z;
    bit [0:1] z_values[$]= '{1,2};
   
    covergroup cg;
        cover_point_y : coverpoint y ;
        cover_point_z : coverpoint z ;
        cross_yz : cross cover_point_y,cover_point_z ;                 
    endgroup
   
    cg cg_inst = new();
    initial
       foreach(y_values[i])
       begin
           y = y_values[i];
           z = z_values[i];
           cg_inst.sample();
       end
   
    endprogram

3)  Why always block is not allowed in program block?

The program block does not allow always block. Only initial and methods are allowed, which are more
controllable.

4) What is final block ?

SystemVerilog final blocks execute in an arbitrary but deterministic sequential order. This is possible because
final blocks are limited to the legal set of statements allowed for functions.

EXAMPLE :
   module fini;
 
      initial
         #100 $finish;
     
      final
         $display(" END OF SIMULATION at %d ",$time);
   endmodule
RESULTS:
Posted by Roy Chan at 9:29 PM No comments:
Labels: ASIC SystemVerilog

SystemVerilog Interview Questions 7

1)  Difference between Associative array and Dynamic array ?

Answer: 

    Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes
dynamically.
    e.g.            int array[];
    When the size of the collection is unknown or the data space is sparse, an associative array is a better
option. In associative array, it uses the transaction names as the keys in associative array.
   e.g.            int array[string];

2)  What are the advantages of SystemVerilog DPI?

SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). The
DPI provides a very simple, straightforward, and efficient way to connect SystemVerilog and foreign language
code unlike PLI or VPI. 

3)  What is bin?

A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. If
the bin designates a set of values, the count is incremented every time the coverage point matches one of the
values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the
coverage point matches the entire sequence of value transitions.

e.g.
program main;
    bit [0:2] y;
    bit [0:2] values[$]= '{3,5,6};
   
    covergroup cg;
      cover_point_y : coverpoint y
                      { option.auto_bin_max = 4 ; }
    endgroup
   
    cg cg_inst = new();
    initial
      foreach(values[i])
      begin
         y = values[i];
         cg_inst.sample();
      end
   
  endprogram

4) What are void functions ?

The function does not have return value

5)   What is coverage driven verification?

Coverage Driven Verification is a result oriented approach to functional verification. The manager and
verification terms define  functional coverage points, and then work on the detail of process.
Used effectively coverage driven verification focuses the Verification team on measurable progress toward an
agreed and comprehensive goal.

6)  Explain about pass by ref and pass by value?

Pass by value is the default method through which arguments are passed into functions and tasks. Each
subroutine retains a local copy of the argument. If the arguments are changed within the subroutine
declaration, the changes do not affect the caller.

In pass by reference functions and tasks directly access the specified variables passed as arguments.Its like
passing pointer of the variable.

example:
task pass(int i)    //  task pass(var int i) pass by reference
{
delay(10);
i = 1;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
delay(10);
i = 2;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
}

7)  What is the difference between program block and module ?

The module is the basic building block in Verilog which works well for Design. However, for the testbench, a lot
of effort is spent getting the environment properly initialized and synchronized, avoiding races between the
design and the testbench, automating the generation of input stimuli, and reusing existing models and other
infrastructure.

Systemverilog adds a new type of block called program block. Systemverilog adds a new type of block called
program block. The program construct serves as a clear separator between design and testbench, and, more
importantly, it specifies specialized execution semantics in the Reactive region for all elements declared within
the program. Together with clocking blocks, the program construct provides for race-free interaction between
the design and the testbench, and enables cycle and transaction level abstractions.

8)   Describe the difference between Code Coverage and Functional Coverage Which is more important and Why
we need them.

      Code Coverage indicates the how much of RTL has been exercised. The Functional Coverage indicates which
features or functions has been executed. Both of them are very important.  With only Code Coverage, it may
not present the real features coverage. On the other hand, the functional coverage may miss some unused RTL
coverage.

     

Posted by Roy Chan at 9:19 PM 8 comments:

Labels: ASIC SystemVerilog

SystemVerilog Interview Questions 6

1)  What is the difference between $random and $urandom?

 Answer:

    The functionality of the seed arguments are different for $random and $urandom. The seed argument to
$random is an inout. It updates its seed argument after each call to $random. This means the internal random
number generator (RNG) state variable is a 32-bit number.

The seed argument to $urandom is an input. This seed is used to set the internal RNG to a value that is over 32-
bits (typically 96-bits or greater).

In SystemVerilog, each thread has its own RNG, so only use the the seed argument on the first call to $urandom
in each thread. There is also a way to set the seed without generated a random value by using the built-in
process class and using the srandom() method.

class packet;
rand bit [7:0] header;

function new(int seed);

this.srandom(seed);
endfunction
endclass

initial begin
packet p=new;
p.new(33);
end

2) How do we get seed or use single seed in the VMM ?

  Method 1: Let it random by itself
   In VMM , VCS usually prints it to log file.  Recently it added a system task to get the seed, something like:
$get_initial_random_seed()
  
   Use the following command to put seed back to get the same result "+nbt_random_seed=".

   Method: Fix the seed.

   The better approach is to use srandom task/function to fix the seed. We can increase the seed by 1 or use
other script to generate the seed. The start seed is only start the regression. It has enough randomize with the
test environment. 
   
EXAMPLE:
class Rand_seed;
 rand integer Var;
 function new (int seed);
   srandom(seed);
   $display(" SEED is initised to %0d ",seed);
 endfunction

 function void post_randomize();

   $display(": %0d :",Var);
 endfunction
endclass

program Rand_seed_p_80;
  Rand_seed rs;
  initial
  begin
    rs = new(20);
    repeat(5)
      void'(rs.randomize());
    rs = new(1);
    repeat(5)
      void'(rs.randomize());
    rs = new(20);
    repeat(5)
      void'(rs.randomize());
  end
endprogram
Posted by Roy Chan at 5:41 PM No comments:
Labels: ASIC SystemVerilog

SystemVerilog Interview Question 5

1) What is the use of modports ?

Answer:
Modport restrict interface access within a module based on the direction declared. Directions of signals are
specified as seen from the module.

e.g.
interface intf (input clk);
        logic read, enable,
        logic [7:0] addr,data;
       
        modport dut (input read,enable,addr,output data);
        modport tb (output read,enable,addr,input data);
    endinterface :intf

2) How parallel case and full cases problems are avoided in SV?

The full_case and parallel_case directives are dangerous because they tell the synthesis tool
something different about the design than what is told to the simulator.

To the Verilog simulator, full_case and parallel_case are buried inside of Verilog
comments and are completely ignored. To the synthesis tool, full_case and parallel_case
are command-directives that instruct the synthesis tools to potentially take certain actions or
perform certain optimizations that are unknown to the simulator.

A full case statement is a case statement in which all possible case-expression binary patterns
can be matched to a case item or to a case default.

e.g. Full case, sel=2'b11 will be covered by default statement.

     The x-assignment will also be treated as a don'tcare for synthesis, which may allow the synthesis tool to
further optimize the synthesized design. It's the potentially causing a mismatch to occur between simulation
and synthesis. To insure that the pre-synthesis and post-synthesis simulations match, the case default could
assign the y-output to either a
predetermined constant value, or to one of the other multiplexer input values

module mux3c
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule

// Use synopsys full_case statement to create the full case , but it treated differently in simulation and
synthesis.
module mux3b (y, a, b, c, sel);
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel) // synopsys full_case
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
endcase
endmodule

SystemVerilog use priority modified case statement to solve the full case problem.
The biggest difference between a full_case directive and a priority modified case statement
is that the priority keyword is part of the SystemVerilog syntax that will be interpreted the
same by simulators, synthesis tools and formal verification tools. In essence, the priority case
statement is a "safe" full_case case statement.

e.g.
priority case (...)
...
endcase

A parallel case statement is a case statement in which it is only possible to match any case
expression to one and only one case item.

e.g. A parallel case statement

module intctl1b
(output reg int2, int1, int0,
input [2:0] irq );
always @* begin
{int2, int1, int0} = 3'b0;
casez (irq) // synopsys parallel_case
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule

This is an example that demonstrates that adding the parallel_case directive makes the design
smaller and faster, but in the process it also adversely changes the functionality of the design.

SystemVerilog adds the new case statement modifier called "unique."

The unique keyword shall cause the simulator to report a run-time error if a case expression is
ever found to match more than one of the case items. In essence, the unique
case statement is a "safe" parallel_case case statement.

unique case (...)

...
default: ...
endcase

Guideline: Code all intentional priority encoders using if-else-if statements. It is easier for
the typical design engineer to recognize a priority encoder when it is coded as an if-else-if
statement.
Posted by Roy Chan at 4:23 PM No comments:
Labels: ASIC SystemVerilog

SystemVerilog interview Questions 4

1) How to call the task which is defined in parent object into derived class ?

Answer:
The super keyword is used from within a derived class to refer to members of the parent class. It is necessary to
use super to access members of a parent class when those members are overridden by the derived class.

EXAMPLE:
    class parent;
        task printf();
            $display(" THIS IS PARENT CLASS ");
        endtask
    endclass
   
    class subclass extends parent;
        task printf();
            super.printf();
        endtask
    endclass
   
    program main;
   
        initial
        begin
            subclass s;
            s = new();
            s.printf();
        end
    endprogram

RESULT

 THIS IS PARENT CLASS

2)  What is the difference between rand and randc?

Answer:
rand  are standard random variables. When there are no other control on distrubution, these variables are
uniformly distributed across valid values.

 randc are random cyclic that randomly iterates over all the values in the range and no value is repeated with
in an iteration until every possible value has been assigned.    
 
3) What is solve...before constraint ?

Answer:
constraint order { solve a before b ;}
This guides the solver to give highest priority to a than b while picking the solution from solution space.

Answer:
4) What is the difference between fork/joins, fork/join_none fork/join_any ?

Fork Join None: The parent process continues to execute concurrently with all the processes spawned by the
fork. The spawned processes do not start executing until the parent thread executes a blocking statement.

Fork Join Any:  The parent process blocks until any one of the processes spawned by this fork completes.

For Join All:   The parent process blocks until all the processes spawned by this fork complete.
Posted by Roy Chan at 3:32 PM 1 comment:
Labels: ASIC SystemVerilog

Systemverilog Interview Questions 3

1) What is the difference between mailbox and queue?

Answer:

A queue is a variable-size, ordered collection of homogeneous elements. A Queue is analogous to one

dimensional unpacked array that grows and shrinks automatically. Queues can be used to model a last in, first
out buffer or first in, first out buffer.

// Other data type as reference

// int q[]; dynamic array
// int q[5]; fixed array
// int q[string]; associate array
// include <
// List#(integer) List1;    //

int q[$] = { 2, 4, 8 };
int p[$];
int e, pos;
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q[0] = e; // write the first item
p = q; // read and write entire queue (copy)

A mailbox is a communication mechanism that allows messages to be exchanged between processes. Data can
be sent to a mailbox by one process and retrieved by another. 

2) What data structure you used to build scoreboard?

Answer:

    In SV, we use mailbox to get data from different modules and compare the result.

class Scoreboard;

mailbox drvr2sb;
mailbox rcvr2sb;

function new(mailbox drvr2sb,mailbox rcvr2sb);

  this.drvr2sb = drvr2sb;
  this.rcvr2sb = rcvr2sb;
endfunction:new

task start();
  packet pkt_rcv,pkt_exp;
  forever
  begin
    rcvr2sb.get(pkt_rcv);
    $display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time);
    drvr2sb.get(pkt_exp);
    if(pkt_rcv.compare(pkt_exp))
    $display(" %0d : Scoreboardd :Packet Matched ",$time);
    else
      $root.error++;
  end
endtask : start

endclass

In VMM, we use channels to connect all the modules and compare the result.

class Scoreboard extends vmm_xactor;

   Packet_channel   drvr2sb_chan;
   Packet_channel   rcvr2sb_chan;

function new(string inst = "class",

             int unsigned stream_id = -1,
             Packet_channel   drvr2sb_chan = null,
             Packet_channel   rcvr2sb_chan = null);

      super.new("sb",inst,stream_id);
   
      if(drvr2sb_chan == null)
           `vmm_fatal(this.log,"drvr2sb_channel is not constructed");
      else
           this.drvr2sb_chan = drvr2sb_chan;
     
      if(rcvr2sb_chan == null)
           `vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
      else
           this.rcvr2sb_chan = rcvr2sb_chan;
     
      `vmm_note(log,"Scoreboard created ");

endfunction:new

task main();
  Packet pkt_rcv,pkt_exp;
  string msg;
  super.main();
  forever
  begin
    rcvr2sb_chan.get(pkt_rcv);
    $display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time);
    drvr2sb_chan.get(pkt_exp);
    if(pkt_rcv.compare(pkt_exp,msg))
    $display(" %0d : Scoreboard :Packet Matched ",$time);
    else
    `vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg));
  end
endtask : main

endclass

3) What are the advantages of linkedlist over the queue ?

   
 Answer:

 Queue has a certain order. It's hard to insert the data within the queue. But Linkedlist can easily insert the
data in any location.

4) What is the use of $cast?

Using Casting one can assign values to variables that might not ordinarily be valid because of differing data
type. SystemVerilog adds 2 types of casting. Static casting and dynamic casting.

e.g.  i = int '(10.0-0.1); // static cast convert real to integer

// Dynamic casting
function int $cast( singular dest_var, singular source_exp );
or
task $cast( singular dest_var, singular source_exp );

e.g. $cast( col, 2 + 3 );

Posted by Roy Chan at 3:16 PM 1 comment:
Labels: ASIC SystemVerilog

Wednesday, January 27, 2010

Basic OPP questions, SystemVerilog Interview Question 1
What is object oriented programming :
OOP Can be described with following concepts :

Follows bottom up approach.

Emphasis is on data.
Programs are divided into objects.
Functions and data are bound together.
Communication is done through objects.
Data is hidden.

The following are the basic concepts of OOPs:

Classes, Objects, Data abstraction and encapsulation, Polymorphism, Inheritance, Message Passing, and
Dynamic Binding.
Q. What is a class?
Class is an entity which consists of member data and member functions which operate on the member data
bound together.

Q. What is an object?
Objects are instances of classes. Class is a collection of similar kind of objects. When a class is created it
doesn’t occupy any memory, but when instances of class is created i.e., when objects are created they occupy
memory space.
Q. What is encapsulation?
A1. Encapsulation is welding of code and data together into objects.

Q. What is inheritance?
A2. Inheritance is a mechanism through which a subclass inherits the properties and behavior of its superclass.
The derived
class inherits the properties and method implementations of the base class and extends it by overriding
methods and adding additional properties and methods.
 Q. What is polymorphism?
A3. In Greek this means "many shapes."As a consequence of inheritance and virtual functions, a single task (for
example, drawing
a geometrical shape) can be implemented using the same name (like draw()) and implemented differently (via
virtual functions) as each type in object hierarchy requires(circle.draw() or rectangle.draw()). Later, when a
polymorphic  object (whose type is not known at compile time) executes the draw() virtual function, the
correct implementation is chosen andexecuted at run time.
Q. What is the difference between function overloading and function overriding?
A. Overloading is a method that allows defining multiple member functions with the same name but different
signatures. The compiler will pick the correct function based on the signature. Overriding is a method that
allows the derived class to redefine the behavior of member functions which the derived class inherits from a
base class. The signatures of both base class member function and derived class member function are the same;
however, the implementation and, therefore, the behavior will differ
Q. What are the advantages of OOP?

Data hiding helps create secure programs.

Redundant code can be avoided by using inheritance.
Multiple instances of objects can be created.
Work can be divided easily based on objects.
Inheritance helps to save time and cost.
Easy upgrading of systems is possible using object oriented systems.

Q. Explain about the virtual task and methods .

Virtual tasks and functions are the ways to achieve the polymorphism in system verilog. Try to fun the following
example and see it will help you understand the concept.

class base ;
virtual function int print;
$display("INSIDE BASE \n");
endfunction : print
endclass : base

class derived extends base;

function int print;
$display("INSIDE DERIVED \n");
endfunction : print
endclass : derived

program test ;

derived d1;
initial
begin
d1 = new();
d1.print();
callPrint (d1);
end

task callPrint (base b1);

$display("Inside callPrint \n");
b1.print;
endtask : callPrint

endprogram

 
What is the use of the abstract class?

A virtual class is a temple or place holder for the child classes. A virtual class is also called as the abstract class.
A virtual class is declared with a virtual keyword like :
virtual class base;
   virtual task1;
   endtask;
   virtual task2;
   endtask;
endclass;
A virtual class instance or object can not be constucted but you can define the hadle to the virtual class.

 
virtual class baseframe;
...
virtual function void iam();
endfunction
...
endclass

class shortframe extends baseframe;

...
function void iam();
$display ("Short Frame");
endfunction
endclass

class longframe extends baseframe;

...
function void iam();
$display ("Long Frame");
endfunction
endclass

baseframe two; // OK

initial begin
two = new(4); // ERROR
...

What is the need of virtual interfaces ?

Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals
that make up the design. A virtual interface allows the same subprogram to operate on different portions of a
design and to dynamically control the set of signals associated with the subprogram. Instead of referring to the
actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying
design do not require the code using virtual interfaces to be rewritten. By abstracting the connectivity and
functionality of a set of blocks, virtual interfaces promote code reuse.
Virtual interfaces can be declared as class properties, which can be initialized procedurally or by an argument
to new(). This allows the same virtual interface to be used in different classes. The following example shows
how the same transactor class can be used to interact with various different devices:

interface SBus; // A Simple bus interface

logic req, grant;
logic [7:0] addr, data;
endinterface

class SBusTransctor; // SBus transactor class

virtual SBus bus; // virtual interface of type Sbus
function new( virtual SBus s );
bus = s; // initialize the virtual interface
endfunction

task request(); // request the bus

bus.req <= 1'b1;
endtask

task wait_for_bus(); // wait for the bus to be granted

@(posedge bus.grant);
endtask

endclass

module devA( Sbus s ) ... endmodule // devices that use SBus

module devB( Sbus s ) ... endmodule
module top;
SBus s[1:4] (); // instantiate 4 interfaces
devA a1( s[1] ); // instantiate 4 devices
devB b1( s[2] );
devA a2( s[3] );
devB b2( s[4] );
initial begin

SbusTransactor t[1:4]; // create 4 bus-transactors and bind

t[1] = new( s[1] );
t[2] = new( s[2] );
t[3] = new( s[3] );
t[4] = new( s[4] );
// test t[1:4]
end
endmodule

In the preceding example, the transaction class SbusTransctor is a

simple reusable component. It is written without any global or
hierarchical references and is unaware of the particular device with
which it will interact. Nevertheless, the class can interact with any
number of devices (four in the example) that adhere to the interface’s
protocol.
Posted by Roy Chan at 11:02 AM 2 comments:
Labels: ASIC SystemVerilog

System Verilog Interview Questions 2

1) What's the OpenVera?

Its an intuitive, easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java with
additional constructs targeted at functional verification that makes it ideal for developing testbenches,
assertions and properties.
   
2) What is SVA?

Answer: SVA is System Verilog Assertion.

3) What is Callback?

Callback in system verilog or verification : Callback is mechanism of changing to behavior of a verification

component such as driver or generator or monitor without actually changing to code of the component.
It's used for functional coverage, inject error and output transaction in a scoreboard.

4) What is "factory pattern" concept?

The term factory method is often used to refer to any method whose main purpose is creation of objects.

e.g.

// Normal Type based object creation

// Class object
class my_class;
int i;
endclass

program main;
// Create object type my_class
my_class obj1;
obj1 = new
endprogram
 
// Using Factory I should be able to do the following

program main;
base_class my_class_object;
base_class = factory.create_object("my_class"); // See here the type of the object to be created is passed
as a string so we dont know the exact type of the object
endprogram

5) What's the difference between data type logic, reg and wire?

Wire Reg Logic

Data Type
Both continuous assignment
blocking/non blocking
Assignments Continuous assignments or blocking/non
assignment
blocking assignment
extends the rand eg type so
Storage element, store
it can be driven
Limitation Wire, cannot hold data data until next
by a single driver such as
assignment
gate or module.

6) What is the need of clocking blocks?

- It is used to specify synchronization characteristics of the design

- It Offers a clean way to drive and sample signals
- Provides race-free operation if input skew > 0
- Helps in testbench driving the signals at the right time
-  Features
    - Clock specification
    - Input skew,output skew
    - Cycle delay (##)
- Can be declared inside interface,module or program

e.g.

Module M1(ck, enin, din, enout, dout);

input ck,enin;
input [31:0] din ;
output enout ;
output [31:0] dout ;

clocking sd @(posedge ck);

input #2ns ein,din ;
output #3ns enout, dout;
endclocking:sd

reg [7:0] sab ;

initial begin
sab = sd.din[7:0];
end
endmodule:M1

7) What are the ways to avoid race condition between testbench and RTL using SystemVerilog?

There are mainly following ways to avoid the race condition between testbench and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

According to the eRM and OVM monitors and drivers should always be completely separate. This approach was
adopted mainly in order to facilitate reuse of block level agents in a top level testbench: at block level both
driver and monitor are used, while at top level only the monitor is used.

8)  Explain Event regions in SV?

 A systemverilog event is now a handle to a synchronization object that can be passed around to routines. The
events can be shared across objects without having to make the events global.

9) What are the types of coverages available in SV?

Both Code Coverage and Functional Coverage are available in SV. You can use the following examples:

Using covergroup : variables, expression, and their cross

Using cover keyword : properties

class eth_frame;

// Definitions as above
covergroup cov;
coverpoint dest {
bins bcast[1] = {48'hFFFFFFFFFFFF};
bins ucast[1] = default;
}
coverpoint type {
bins length[16] = { [0:1535] };
bins typed[16] = { [1536:32767] };
bins other[1] = default;
}
psize: coverpoint payload.size {
 bins size[] = { 46, [47:63], 64, [65:511], [512:1023], [1024:1499], 1500 };
}

sz_x_t: cross type, psize;

endgroup
endclass

module Amod2(input bit clk);

bit X, Y;
sequence s1;
@(posedge clk) X ##1 Y;
endsequence
CovLavel: cover property (s1);
...
endmodule
Posted by Roy Chan at 10:45 AM 1 comment:
Labels: ASIC SystemVerilog

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