Analog and Digital VLSI Design

(EEE/ INSTR F313)

BITS Pilani
Pilani Campus
Instructor : Dr. KAVINDRA KANDPAL
Note to students
• The slides are introductory and doesn’t include all the syllabus.
• Most of the lectures are taken without the help of ppt. So this ppt. does not
include all the content.
• Read Kang, Chapter 7 for combinational MOS logic circuits, Chapter 6:
Designing Combinational logic gates in CMOS from J.M. Rabaey.
• For RC delay students can refer to Text book “Rabaey”. Moreover, reading
this section also from CMOS VLSI Design A circuit and systems perspective
by Neil H.E. Weste and David M. Harris will be an added advantage for
learning the concepts.

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Dissipation due to direct path currents

Assumption: the(reasonable) assumption that the resulting current spikes can be approximated as
triangles and that the inverter is symmetrical in its rising and falling responses

Follow Text book: Rabaey

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Dissipation due to direct path currents

The finite slope of the input signal causes a direct current path between VDD and GND for a short
period of time during switching, while the NMOS and the PMOS transistors are conducting
simultaneously.

If ts represents 0-100 % transition time and tr represents rise time, then tsc can be expressed as:

Follow Text book: Rabaey

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Combinational logic

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Generalized NOR Structure

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Combinational logic

The DC analysis : By considering the structural similarities between

this circuit and the simple pseudo nMOS inverter, the circuit can be
simplified significantly.

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Combinational logic

Cload  Cgd , A  Cgd , B  Cgd , p  Cdb, A  Cdb, B  Cdb, p  Cwire

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Combinational logic: NAND Gate

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Combinational logic: Example

Fig. implements a logic function F using nMOS

enhancement type load. All the nMOS pull down
transistors ratio are 10/1. Find out the following:
a) logic function F
b) VOH
c) Calculate the W/L of load transistor such that VOL
does not exceeds 0.25 V.
Given: μnCOX = 140 μA/V2, Vtn = 0.7 V. (neglect body
bias effect)

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Combinational logic: Example

a) Find out the function F, as shown in Fig.2.

b) Find out the (W/L)eq for pull down network.
c) Size the load transistor such that VOL does not
exceed 0.2 V . Given, VTdriver = 0.7 V, VTload = -1.2 V.

(W/L)load ≤ 0.462

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Combinational Logic: CMOS VDD

In1
In2 PUN PMOS Only
In3

F=G

In1
In2 PDN NMOS Only
In3

VSS

PUN and PDN are Dual Networks

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Combinational logic: CMOS NOR Gate

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Combinational logic: CMOS NOR Gate

VTH ?

VT ,n 
1 kp
2 kn

VDD  VT , p 
Vth  NOR 2  
1 kp
1
2 kn

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Combinational logic: CMOS NAND Gate

VTH ?

V 
kp
VT ,n  2 DD  VT , p
kn
Vth  NAND 2  
kp
1 2
kn

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RC Delay Model: Elmore’ s delay model

N
 Di   C j R k
j 1 for all
kPij

Let Pi denote the unique path from the input node to node i, i = 1, 2, 3, ..., N. Let Pij = Pi « Pj denote the
portion of the path between the input and the node i, which is common to the path between the input
and node j.
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RC Delay Model: Elmore’ s delay model

Rule : Multiply every R in the

path from source to end
node with all its downstream
capacitance

Delay = ln2 * τ  D 7  R1C1  R1C2  R1C3  R1C4  R1C5   R1  R6  C6

  R1  R6  R7  C7   R1  R6  R7  C8
 D 5  R1C1   R1  R2  C2   R1  R2  C3   R1  R2  R4  C4
  R1  R2  R4  R5  C5  R1C6  R1C7  R1C8
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RC Delay Model: Transistor

Assumption: µn: µp = 2:1

Resistance of a transistor is proportional to L/W. The pMOS transistor has approximately
twice the resistance of the nMOS transistor because holes have lower mobility than
electrons
Capacitances are gate capacitance and diffusion capacitances.
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RC Delay Model: Transistor

We define C to be the gate capacitance of a unit transistor of either flavor. A transistor of

k times unit width has capacitance kC.

Diffusion capacitance depends on the size of the source/drain region. we assume the
contacted source or drain of a unit transistor to also have capacitance of about C. Wider
transistors have proportionally greater diffusion capacitance. Increasing channel length
increases gate capacitance proportionally but does not affect diffusion capacitance

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Example: FO-1 inverter

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Example: 3 input NAND

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Example: 3 input NAND

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Example: 3 input NAND

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Example: 3 input NAND

Estimate TPHL and TPLH for the 3-

input NAND gate from if the output
is loaded with h identical NAND
gates. Use RC delay model.

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Symmetrical response: VDD
V DD

1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
Valid if CL dominates. A
D 1
B 2C 2

Here it is assumed that Rp = Rn

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Design technique for large Fan-in

Transistor Sizing: also check, how long you can increase size
as parasitic capacitance also increases.

Progressive Sizing: From elmore’s delay. Example:

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Design technique for large Fan-in

Progressive Sizing:
Example:

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Design technique for large Fan-in

Input reordering

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Design technique for large Fan-in

Logic restructuring: Will be explained in more details while

explaining logical effort.

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Find out the logic function implemented by stick diagram
shown in figure

CMOS Technology
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