Power MOS FET R07ZZ0009EJ0300

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Absolute Maximum Ratings and Rev.3.00
Electrical Characteristics Aug 18, 2014

1. Absolute Maximum Ratings and Electrical Characteristics

1.1 Absolute Maximum Ratings
The following absolute maximum rating items are stipulated independently of each other: Sustained drain-source
voltage VDSS
Drain current ID
Channel dissipation Pch
Also, these items express rating values which cannot be exceeded no matter what the service condition. In many cases,
absolute maximum rating items are closely interrelated with other characteristics, and so correct operation cannot be
guaranteed when two or more values are at their maximum rated levels.
(1) Drain-Source Voltage VDSS
When a short-circuit is created between the gate and source, the resulting applied voltage between the drain and
source is at its maximum value. VDSS varies along with temperature. A shown if Figure 1, a rise in junction
temperature Tj above 100°C causes a corresponding increase in V(BR)DSS of approximately 10%. It should also be
noted that a drop in Tj causes a proportional drop in V(BR)DSS.
1.20

1.15
Temperature Change Ratio

1.10

1.05

1.00

0.95
ID = 10 mA
0.90
VGS = 0
0.85

0.80
–50 –25 0 25 50 75 100 125 150
Junction Temperature Tj (°C)

Figure 1 Change in V(BR)DSS Relative to Junction Temperature

(2) Gate-Source voltage VGSS
The device incorporating a protection diode is assumed for the case when a short-circuit is created between the drain
and source, The protection diode must be included in the device.
(3) Drain current ID and drain peak current ID(peak) or ID(pulse)
The peak value of the DC drain current is expressed by ID(peak) or ID(pulse), under the limitations imposed by the
allowable channel loss, and assuming that the maximum value of the continuous DC to the drain does not exceed ID
and the average current does not exceed ID.
The generally allowable ID value during operation can be calculated using the following formula.
Tch max. − Tc
IDmax. = (A) ············································································ (1)
θch − c ⋅ RDS(on)max.
Similarly, the allowable ID(peak) value can be calculated as shown below.
Tch max. − Tc
ID(peak)max. = (A) ··································································· (2)
θch − c(t) ⋅ RDS(on)max.
Tch max.: Maximum channel temperatures (150°C)
Tc: Case temperatures

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
θch–c: DC thermal impedance
θch–c(t): transient thermal impedance
RDS(on)max.: maximum drain-source on-resistance value
γS(t): normalized transient thermal impedance (here, 1 shot pulse)

The following formula can be used to obtain pulse width PW and θch-c(t) for duty cycle n%.
⎧ n ⎛ n ⎞ ⎫
θch − c (t) = θch − c ⎨ + ⎜1 − ⎟ γ S(t) ⎬ ··································································· (3)
⎩ 100 ⎝ 100 ⎠ ⎭
The RDS(on) in formulas (1) and (2) takes waste conditions into consideration, and the RDS(on) max value at Tch =
150°C (in accordance with the RDS(on) – TC characteristics curve of the data sheet) is used.
Calculation example:
Calculate the ID(peak) allowable value when the 2SK1166 is used under the conditions PW = 10 μs, duty = 10%, TC =
80°C.
(i) According to the transient thermal impedance shown on the data sheet (Fig 2), PW = 10 μs and duty = 10%
result in γs(t) ≅ 0.12. Therefore, θch-c(t) = γs(t), and θch-c = 0.12 × 1.25 = 0.15°C / W.
(ii) According to the data sheet, the RDS(on) maximum value for 0.6 Ω and Tch = 150°C is approximately 2.4 × 0.6 =
1.44 Ω.
Substituting the above values in Formula (2) results in the following calculation of the approximate value 18 A.
150 − 80
ID(peak) = ≅ 18A
0.15 × 1.44

Important
The RDS(on) value is based upon values obtained under the test conditions noted in the catalog. RDS(on) should be
confirmed under actual ID(peak) conditions.
(4) Reverse drain current IDR
Reverse drain current IDR represents the maximum value of the reverse direct current flowing continuously to the
equivalent built-in diode formed between the source and drain, within the limitations imposed by the allowable
channel loss. In applications such as H bridge circuit output for motor control, the built-in diode is equivalent to a
commutation diode. However, breakdown can occur depending on the circuit operating conditions, so the
precautions in handling the built-in diode outlined in section 8.1 should be noted.
Normalized Transient Thermal Impedance γS (t)

3
TC = 25°C
D=1
1.0
0.5

0.3 0.2
0.1 θch–c (t) = γ S (t) • θch–c
0.1 0.05 θch–c = 1.25°C/W, TC = 25°C
PDM
0.02
0.03 0.01 D = PW
lse T
ho t Pu T
PW
1S
0.01
10 μ 100 μ 1m 10 m 100 m 1 10
Pulse Width PW (s)

Figure 2 2SK1165, 2SK1166 Transient Thermal Impedance Characteristics (Data Sheet)

(5) Channel dissipation Pch or PD
Allowable channel dissipation is the drain loss maximum value continuously consumed by the transistor within the
limitations imposed by the prescribed heat dissipation conditions. Derating in accordance with the following
formula is required in accordance with case temperature TC.
Tch max. − Tc
Pch(Tc) = Pch(25°C) × ········································································ (4)
Tch max. − 25

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Also, the transition duration’s allowable channel loss Pch(1) can be calculated using Formula (5) below, in
accordance with the transient thermal impedance noted on the data sheet.
Tch max. − Tc
Pch(t) = ·························································································· (5)
θch − c(t)

Temperature derating is performed using a method similar to Formula. (4).

(6) Channel temperature Tch
As with the transistor’s Tj, the allowable channel temperature is the upper limit junction temperature value, which
cannot exceed the temperature rise (θch-c • Pd) caused by operating case temperature (TC) and internal loss (Pd) of
the transistor itself, or the sum of such temperatures (TC + θch-c • Pd).
(7) Storage temperature Tstg
The storage temperature represents the upper and lower ambient temperature limits which the transistor should not
exceed when in a non-operational storage condition.

1.2 Electrical Characteristics

(1) Drain-source breakdown voltage V(BR)DSS
The test conditions for the drain-source breakdown voltage prescribe ID and VGS = 0. Temperature fluctuates as
previously described.
(2) Gate-source breakdown voltage V(BR)GSS
Gate-source breakdown voltage applies to the DII Series, SIII Series and S Series, in which a protect diode is
included between the gate and source. Test conditions prescribe IG (= ±100 μA) and VDS = 0.
(3) Reverse gate current IGSS
Test condition prescribe VGS and VDS = 0. The IGSS for models without a gate protect diode (D Series) is a value of
1 nA or less. Temperature has virtually no affect on this value. For models with a gate protect diode (DII, DIII
Series), IGSS is a value in the range of a few hundred nA to 1 μA. Temperature has somewhat of an affect on this
value, up to a few μA to a few ten μA when TC ≅ 110°C.
(4) Drain current IDSS
Drain current is the drain-source DC leakage current. Test conditions prescribe VDS and VGS = 0. These values are
most susceptible fluctuation caused by temperature changes. As shown in Figure 3, a rise in junction temperature Tj
to 100°C makes IDSS a double-digit figure. However, the 25°C IDSS is as illustrated by (B) and (C) when the MOS
FET channel current overrides the PN junction leakage current.
100
50
(C)
20
10
Drain Current IDSS (μA)

2 (B)
1.0
0.5
(For 2SK1165)
0.2
VDS = 360 V, VGS = 0
0.1
0.05 (A) : IDSS (25°C) = Small SPL
(B) : IDSS (25°C) = Medium SPL
(A)
0.02 (C): IDSS (25°C) = Relatively Large
SPL
0.01
–25 0 25 50 75 100 125 150
Junction Temperature Tj (°C)

Figure 3 Example of Differences in IDSS for Various Junction Temperatures

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
(5) Gate-source cutoff voltage VGS(off)
The gate threshold voltage at which the Power MOS FET begins to conduct is represented by the symbol VGS(off) or
VGS(th). VGS(off) fluctuates with changes in temperature, and carries the negative temperature coefficients shown in
Figure 3. Though temperature coefficients differ somewhat according to the model, the range of the fall is
–5 to 7 mV / °C. Test conditions prescribe VDS and ID.
3.8

Gate-Source Cutoff Voltage VGS (off) (V)

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2
–50 –25 0 25 50 75 100 125 150
Junction Temperature Tj (°C)

Figure 4 Differences in VGS(off) for Various Junction Temperatures

(6) Drain-source on-resistance RDS(on)
On-resistance RDS(on) is one of the most important parameters of the Power MOS FET. Test conditions prescribe ID,
VGS.
RDS(on) fluctuates widely with changes in VGS. This means that at least 10 V must be applied in order to operate the
device within the resistance region (resistance loss) with RDS(on) at its minimum. Note, however, that with the DIII-
L Series which can be driven by 4 V, the application of 5 V is sufficient to attain the resistance region. Even when
VGS is greater than 12 to 15 V, the reduction is RDS(on) is negligible. Making the gate voltage unnecessarily high
results in high charging current, an increase in drive loss, and a tendency towards generation of gate-source spike
voltage. In addition, turn-off delay time becomes longer (and rise time tr becomes shorter).
RDS(on) changes along with drain current ID, and increases above the maximum rated current. RDS(on) also has
positive temperature dependency, and the drain current for each set of parameters and temperature characteristics for
each model can be found on the data sheet.
(7) Forward transfer admittance |yfs|
The Power MOS FET expresses gain similarly to the hFE used by bipolar transistors to express gain. The |yfs| on the
data sheet is defined as the rate of change in drain current in relation to changes in gate voltage (|yfs| = ΔID / ΔVGS).
|yfs| is an important parameter when a device is operated with in the active region (linear circuit), but it is usually not
significant in saturation region operation. Test conditions prescribe VDS (VDS > ID • RDS(on)max), and ID.
(8) Capacitance Ciss, Coss, Crss
Input capacitance Ciss, output capacitance Coss, and reverse transfer capacitance (Crss) share the following
relationships:
Ciss = Cgs + Cgd
Coss = Cds + Cgd
Crss = Cgd
Where:
Cgs = gate-source capacitance
Cds = drain-source capacitance
Cgd = gate-drain capacitance

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Cgs and Cgd are generally determined by the chip size and the thickness of the silicon gate oxide film. Cds is P-N
connection capacitance, and it is determined by the thickness of the depletion layer spread created when reverse bias
is applied to the drain region connection area and the connection. Test conditions prescribe VDS, VGS, and f, and
changes in temperature have virtually no affect on capacitance.
Input capacitance Ciss is used in the design of the Power MOS FET driver circuit to calculate the peak rush current
required for charging driver loss and input capacitance. Problems can occur, however, if the values noted on the
data sheet are used. Refer to 5 Input Dynamic Characteristics for information on such calculations. This section
includes information on input dynamic characteristics for each Renesas Power MOS FET model.
(9) Switching time td(on), tr, td(off), tf
Switching time greatly affects the test circuit’s signal source impedance RS and the drain load resistance RL. Test
conditions prescribe VDD, RL, VGS, and ID, as well as the test circuit. The signal source impedance is specified as a
50 Ω pulse generator connection. During actual use, RS can be reduced for higher speed. The effects of temperature
are negligible.
Turn-on delay time td(on) is the period from 10% of the input gate voltage waveform rise to 10% of the output
voltage waveform rise. This period is affected somewhat by the VGS(off) value, getting shorter as VGS(off) becomes
smaller.
Rise time tr is the period from 10% of the output voltage waveform to 90% of the rise. This period is affected by
VGS and VGS(off) values, getting shorter as VGS becomes greater or VGS(off) becomes smaller.
Turn-off delay time td(off) is the period from 90% of the input gate voltage waveform fall to 90% of the output
voltage waveform fall. This period is affected by VGS and VGS(off) values, getting shorter as VGS becomes smaller or
VGS(off) becomes greater. When the switching operation is accomplished through parallel connection, making VGS(off)
values uniform serves to make the current balance of the transition duration uniform.
Fall time tf is the period from 90% of the output voltage waveform to 10% of the rise. This period tends to be most
affected by load resistance RL, getting longer as RL becomes greater (light load). This is due to the time constant for
drain-source capacitance Cds charging in the off state.
(10) Diode forward voltage VDF
Diode forward voltage is the forward-direction voltage of the equivalent built-in diode between the drain and source.
Test conditions prescribe IF, and VGS = 0. When forward bias is applied to the gate, a channel is formed and the
diode forward voltage assumes the value of IF × RDS(on). Depending on the current region being used, the value for
VF is smaller than that found in standard diodes. Similarly to standard diodes, the temperature characteristic is a
negative temperature coefficient (approximately-2.4 mV/°C).
(11) Reverse recovery time trr
Reverse recovery time trr is the time it takes for reverse recovery of the equivalent built-in diode between the drain
and source. Figure 5 illustrates the reverse recovery time. Test conditions prescribe IF and di / dt, VGS = 0 and the
test circuit. In applications such as H bridge circuit output for motor control the built-in diode equivalent to a
commutation diode. trr is high speed, and loss is as low as the irr. trr and irr are affected by di / dt, and the gentler the
di / dt slope, the longer irr is. tb is the period it takes for the diode withstand voltage to recover from irr, and a smooth
dirr / dt characteristic (no detectable vibration waveform when irr recovers to 0) is called a soft waveform which
features favorable noise characteristics. The gentler the di / dt slope, the softer the tb waveform. di / dt
characteristics are determined by turn-on time (variable using gate-external resistance), floating inductance of the
circuit, and source voltage. The trr period tends to lengthen as temperature increases.
di/dt

0.1 irr
iF

irr

ta tb
dirr/dt
trr

Figure 5 Waveform of Reverse Recovery Time trr

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
2. Output Characteristics
Figure 6 shows the output characteristics of the D series 2SK413 and S series 2SK1057 which have the same
specification. Whereas in a small signal MOS FET the forward trans-conductance |yfs| is 10 to 20 ms (milli-Siemens) at
best, in a power MOS FET it is 1.0 to 15 S. Also, as is obvious from Figure 6, they have what is called pentode
characteristics and excellent linearity of |yfs| in relation to ID.
P channel MOS FETs also have similar characteristics. P channel and N channel types have complementary
characteristics.

10
10 10
15 9 8 T c =25°C
10
8 T c =25°C 8 9
Drain Current I D (A)

Drain Current I D (A)

8
7
6 6 7
Pc Pc
h= 6 h=
10 10
0W 5 0W
4 6 4
4
2 5 2 3
2
4V 1V
V GS =0 V GS =0
0 10 20 30 40 50 0 10 20 30 40 50
Drain-Source Voltage V DS (V) Drain-Source Voltage V DS (V)

(a) D Series 2SK413 (b) S Series 2SK1057

Figure 6 Typical Output Characteristics

3. Frequency Response Characteristics
One of the outstanding features of the power MOS FET is that it has excellent high speed and high frequency
characteristics. Therefore, they can be applied in high-speed switching regulators, high-output broadcasting
transmitters, etc.
The cut-off frequency of an intrinsic MOS FET is defined by the ratio of the mutual conductance and the input
capacitance, and in a typical MOS FET, it will be in the order of GHz. In fact, however, the cut-off frequency is limited
by the parasitic resistance and the input capacitance of the gate.
Figure 7, shows the equivalent circuit of MOS FET in the saturation region.
In Figure 7, the cut-off frequency (fc), at which the voltage gain falls to –3 dB of its low frequency value, is given by
the following equation.

Rg Cgd

υg Cgs RL y L R g : Gate Resistance

Cds
g m υg C gs : Gate to Source Capacitance
C ds : Drain to Source Capacitance
C gd : Gate to Drain Capacitance
R L : Load Resistance

Figure 7 Equivalent Circuit of MOS FET

1 1
fc ≅ ⋅ ················································································ (1)
2π Rg{Cgs + (1 − A 0 )Cgd}

Here, A0 is the low-frequency voltage gain, and Rg is the series resistance of the gate. Figure 8 shows the cut-off
frequencies of the vertical and the lateral structure devices, found by substituting into equation (1) the parameters
(calculated values) of a power MOS FET which has a silicon gate. In the lateral structure, Cgd is much smaller than
Cgs, and can be neglected.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
In the vertical structure, as explained in paragraph 2, Cgs is a function of the voltage gain (A0) in the low frequency
region, because Cgd is large.
We would like to summarize the above, as follows.
(1) In the case of low voltage gain, the cut-off frequencies of the vertical and the lateral structures show the same level.
The input impedance ratio at fC depends on Rg ratio, so the impedance of the vertical structure is 1.5 to 2 times
lower than that of the lateral structure.
(2) In the case of high gain amplifier circuits, the frequency characteristics of the lateral structure and better than that of
the vertical structure, because in the vertical structure the feedback capacitance (Cgd) has a great influence.

500
Condition Pg = 50 Ω/
VDS = 20 V
⏐A0⏐
Vertical
10 (⏐A0⏐ = 0, LC = 2 μm)
200

(⏐A0⏐ > 100, LC = 8 μm)

20
100 Lateral

50 50

100
Cut-off Frepuency (MHz)

20

10

1.0

0.5

0.2
0.5 1.0 2 5 10 20
Chip Size (mm)

Figure 8 Cut-off Frequency of Silicon Gate Power MOS FETs

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

0
2SK312
–1
2SK134
2SK221(H) 2SK317
–2
Response (dB)

–3

–4

–5

–6
A
–7 C off C LCH
S.G. 50 Vout
–8 100 k Vin
10
Vout
⏐yfs⏐ =
10 Vin
–9

–10
500 k 1M 2M 5M 10 M 20 M 50 M 100 M 200 M 500 M 1G
Frequency (Hz)

Figure 9 Frequency Response Characteristics of yfs (Source Common)

To further improve the frequency characteristics, the use of low resistance material such as metal is required. This will
improve the cut-off frequency by 10 to 100 times. Figure 9 shows the frequency characteristics and the test circuits of
typical kinds of MOS FETs. In 2SK317 and 2SK221 (H), the gate material is metal-gate.

Id ID

VGS
ID (max)
Rg
RL
Vds
Vi
Vgs VDD

0
VDD (sat) VDS VDD

(a) (b)

Figure 10 Switching Circuit and Typical Output Characteristics & Load Curve
4. Switching Characteristics
4.1 Switching Characteristics
When using power MOS FETs for power switching, such as in switching regulators, the load of the switching device is
usually inductive. Here, however, we would like to assume a resistance load, because it can be treated easily.
Figure 10 shows the resistance load switching circuit (a), simplified current-voltage characteristics, and the load line (b).
In this figure, we suppose that the rising curve of current vs. voltage is shown by a straight line, and gm = 0.
Therefore, in Figure 10 (b), the point of the drain voltage = VDS(sat) is included in the non-saturation region, and the
region of VDS > VDS(sat) is the saturation region.
In the lateral structure, Cgd is much smaller than Cgs and Cds, so it can be neglected. The time constants are given by
the following equations.
Ti ≅ Rg • Cin = Rg • Cgs ···················································································· (2)
To ≅ RL • Cout = Rg • Cds ·················································································· (3)
Ti : input time constant

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
To : output time constant

Then, the switching waveform is shown in Figure 11.

The quantity of charge, Qon, which is stored in the gate and shows how easily the device can be driven, is given by the
following equation.
Qon = Cgs · VG max ·························································································· (4)
The transitional charge current (irush) is given as follows.
Cgs ⋅ VGmax.
irush = ····························································································· (5)
tr

VG (max) T1 : Turn-on Delay Time ; td (on)

T2 : Rise Time ; tr
T3 : On Time
Vi
0 T4 : Turn-off Delay Time ; td (off)
T5 : Fall Time ; tf
t
VG (max) V0
VGS1–VTH
Vg VTH
0

VDD

V0 VDS (sat)
0 Vg
2SK2265
I (max) 200 ns/DIV Switching Time
VGS = 15 V, ID = 2 A td (on) : 5 ns
I0 RL = 15 Ω tr : 25 ns
0 td (off) : 60 ns
T5 tf : 60 ns
T3
T2
T1 T4

(a) (b)

Figure 11 Switching Waveform of Lateral Power MOS FETs

In the vertical structure, the feedback capacitance (Cgd) is large and depends largely on the drain voltage, so the
operation analysis will be more complicated. Figure 12 shows the Cgd-drain voltage dependency of the vertical and the
lateral structures (2SK1166, 2SK2265) under the conditions of the same chip size and the same 400 V breakdown
voltage. With a depletion layer spreading in the drain just under the gate electrode, the value of Cgd will decrease
sharply.
Considering the above, we would like to show the Cgd-and gm-drain voltage dependencies in Figure 13 at VGS > VDS,
Cgd is equal to Cgd0, the oxide film capacitance just under the drain electrode. When VGS < VDS, the depletion layer
expands to the drain region, and Cgd << Cgs. The threshold voltage, at which the drain surface is P-inverted, is
supposed to be 0. Under these conditions, we would like to look at the switching operations. When the drain voltage is
in the region of VDS > VDS(sat), the device is in the saturation region, and in the region of VDS(sat) < VDS < VGS, Cgd is
equal to Cgd0. The equivalent circuit is as shown in Figure 13 (c). The time constant of the input capacitance at
charging or discharging is given by the following equations.

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400

350 VGS = 0
f = 1MHz

300

250

Cgd (pF)
200

150

Vertical 2SK312
100

Lateral 2SK2265
50

0 10 20 30 40 50 60 70 80
V DS (V)

Figure 12 Feedback Capacitance (Cgd)-Drain Voltage Dependency

T1 ≅ Rg • Cgs (VDS > VGS)

T1’ ≅ Rg {Cgs + (1 + gm • RL)}Cgd
(VDS(sat) < VDS < VGS) ···················································································· (6)

When VDS = VDS(sat), the device is in the non-saturation region. The equivalent circuit is as shown in Figure 13 (d) and
the time constant is given as follows.

Cgd
(VGS–VTH) Rg Vg Cgd0 V0
Cgd0

RL
Vi Cgs
gmVg VDD

0 VGS VDS (VDS (sat) < VDS < VGS)

(a) (c)

gm
Rg Vg Cgd0

gm0

Vi Cgs VDS (sat)

0 (VGS–VTH) VDS
(VDS = VDS (sat))
(b) (d)

Figure 13 Drain Voltage Dependencies of Cgd and gm (a), (b), & Equivalent Circuit (c), (d)

T2 ≅ Rg (Cgs + Cgd0) ························································································ (7)

Figure 14 shows the switching waveform as a model, based on the above operations. T1, T2, T4 and T5 show the turn-on
delay time td(on), the rise time tr, the turn-off delay time td(off) and the fall time tf(ton = td(on) + tr’ t(off) = td(off) + tf)
respectively.
T6 to T9 show the charging and discharging time of Cgd. T6 and T9 indicate the region in which the mirror integration is
operated, and it is equal to the time to charge and discharge the changes, whose quantity is equivalent to the shaded part
of Figure 13 (a).
Figure 14 (b) shows the gate driving waveform Vg and the output voltage waveform V0 of the vertical structure, as
actually measured. The gate voltage waveform is similar to the basic waveform shown in (a), quantitatively.

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T1 : Turn-On Delay Time ; td (on)

T2 : Rise Time ; tr
Vi T3 : On Time
0 T4 : Turn-Off Delay Time ; td (off)
t T5 : Fall Time ; tf
VG (max)
VGS1 V0

Vg VTH
0

VDD

V0 VDS (sat)
0
Vg
T6 T7 T8 T9
ID (max) 2SK1166
200 ns/DIV Switching Time
I0 VGS = 10 V, ID = 6 A td (on) : 20 ns
0 RL = 5 Ω tr : 70 ns
T3 td (off) : 120 ns
tf : 60 ns
T1 T2 T4 T
5
(a) (b)

Figure 14 Switching Waveform of Vertical Power MOS FET

This means that we can explain the switching operation using the approximate values of the feedback capacitance and
gm shown in Figure 13 (a), and (b). The quantity of stored charges, which shows how easily the gate can be driven, is
given by the following equation.
Qon = (Cgs + Cgd0) VG max ················································································ (8)
The transitional charge current (irush) is given as follows.
(Cgs + Cgd0 )VGmax.
irush = ···················································································· (9)
t on
The following summarizes a comparison of the switching operations of the vertical and the lateral structures.
(1) The gate driving power required is determined by the ratio of the quantity of stored charges in gate capacitance. The
driving power for the vertical structure device is larger than that for the lateral structure device by
(Cgs + Cgd0) D / (Cgs)S.
(2) When the device is driven by a high speed pulse, the rise time (tr) and the fall time (tf), for both structures, are given
by the following equations.
⎛ V − Vth ⎞
t r ≅ Cin ⋅ Rg ⋅ ln ⎜ Gmax. ⎟ ············································································· (10)
−
⎝ GSmax. VGS1 ⎠
V
⎛V ⎞
t r ≅ Cin ⋅ Rg ⋅ l n ⎜ GS1 ⎟ ························································································ (11)
⎝ Vth ⎠
Here VGS1 is the gate voltage for saturation.
In the vertical structure, tr and tf are faster than those of the lateral one, because of the small value of the gate resistance.
The turn-off delay time, however, is larger, so the value of toff (=td(off) + tf) will be larger.
In an actual circuit, the output resistance (R) of the driven circuit will be added to this gate resistance (Rg).
Therefore, in high speed operation, the vertical structure device should be designed so that the output resistance of the
drive circuit will be as small as possible, by adding one or two emitter follower circuits to the driver.
Figure 15 and Figure 16 show the turn off time of the device with the drive circuit added and that of the standard
measuring circuit. Moreover, as shown in circuit (c), the operation speed will be further improved by making the gate
potential negative at cut off time.
In power MOS FETs, in contrast with bipolar transistors, the switching time is not influenced by temperature, and the
circuit design will be easier. Figure 17 shows the relation of the switching time vs. temperature characteristics,
compared to that of bipolar transistors.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

VGG VGG
P.G.
D.U.T. P.G. P.G.
D.U.T. D.U.T.
50 Ω 15 Ω 15 Ω 15 Ω
50 Ω 50 Ω
50 Ω
50 Ω 50 Ω

–VGG

(a) Standard Circuit (b) Circuit With Buffer (C) Circuit With Buffer
(Without Reverse Bias) (With Reverse Bias)

Figure 15 Drive Circuit

300

Without Buffer Circuit

100 0
400 V/5 A, S Series VGG
Turn-Off Time toff (ns)

30

400 V/5 A, D Series

10

1
0 –5 –10 –15
Reverse Gate Bias Voltage VGG (V)

Figure 16 Turn-Off Time vs. Reverse Gate Bias

2
toff
1.0 Bipolar Transistor
Switching Time ton, toff (μs)

0.5
ton

0.2
toff
0.1
ton
0.05 Power MOS FET
(400 V/5 A)

0.02
ID = 5 A
0.01
0 25 50 75 100 125
Case Temperature TC (°C)

Figure 17 Switching Time vs. Case Temperature

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
4.2 Method for Calculating Power MOS FET Switching Loss
This section explain how to calculate Power MOS FET switching loss in the case of the approximation waveform
illustrated in Figure 18.
Loss for periods t1, t2, and t3 are respectively represented by P1, P2, and P3 as noted below. P1 is turn on loss, and P3 is
turn off loss.
The following method for calculating P1 and P2 is provided as reference.
1
P1 = ⋅ f ⋅ t1(VD ⋅ Ib + 2Ib 2 ⋅ Ron) ················································································ (1)
6
1
P2 = ⋅ f ⋅ t 2 ⋅ Ron(Ip 2 + Ip ⋅ Ib + Ib 2 ) ········································································· (2)
3
1
P3 = ⋅ f ⋅ t 3 (VP ⋅ Ip + 2Ip 2 ⋅ Ron) ··············································································· (3)
6
(1) When loss P1 for period t is repeated for period T
1 t1
P1 =
T 0 ∫
(i(t) ⋅ ds(t))dt
1 t1 Ib ⎛ VD − Ib ⋅ Ron ⎞
=
∫
T 0 t1 ⎝
t⎜ −
t1
t + VD⎟ dt
⎠
1 t1 ⎛ Ib ⋅ Vb 2 Ib 2 ⋅ Ron 2 Ib ⋅ VD ⎞
=
∫
T 0 ⎜⎝
−
t12
t +
t12
t +
t1 ⎟⎠
t dt

t1
1 ⎡ Ib ⋅ VD t 3 Ib 2 ⋅ Ron t 3 Ib ⋅ VD t 2 ⎤
= ⎢ − ⋅ + ⋅ + ⋅ ⎥
T ⎢⎣ t12 3 t12 3 t1 2 ⎥⎦
0

VP
IP
VD
IP Ron

Ib
0
Ib Ron t1 t2 t3

Figure 18 Voltage and Current Approximation Waveform

VD
VP

Figure 19 L Load Switching Circuit

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
1 ⎛ Ib ⋅ VD t13 Ib 2 ⋅ Ron t13 Ib ⋅ VD t12 ⎞
P1 = − ⋅ + ⋅ + ⋅
T ⎜⎝ t12 3 t12 3 t1 2 ⎟⎠
1⎛ 1 1 2 1 ⎞
= ⎜ − ⋅ VD ⋅ Ib ⋅ t1 + Ib ⋅ Ron ⋅ t1 + V D ⋅ Ib ⋅ t1⎟
T⎝ 3 3 2 ⎠
1⎛1 1 2 ⎞
= ⎜ VD ⋅ Ib ⋅ t1 + Ib ⋅ Ron ⋅ t1⎟
T ⎝6 3 ⎠

=
1
6T
(
VD ⋅ Ib + 2Ib 2 ⋅ Ron t1 )
1
=f
T

∴ P1 =
1
6
(
⋅ f ⋅ t1 VD ⋅ Ib + 2Ib 2 ⋅ Ron )
(2) Loss P2 for Period t2
1 t 2 ⎧⎪⎛ Ip − Ib ⎞ ⎛ Ib − Ib ⎞ ⎫⎪
P2 =
∫ ⎨⎜
T 0 ⎩⎪⎝ t 2
t + Ib⎟ ⎜
⎠ ⎝ t2
Ron ⋅ t + Ib ⋅ Ron⎟ ⎬ dt
⎠ ⎭⎪
Ip − Ib
=a
t2
t2
P2 =
∫0 (a t + Ib)(a⋅ Ron ⋅ t + Ib ⋅ Ron) dt
1 t2 2
P2 =
T 0 ∫
(a ⋅ Ron ⋅ t 2 + 2 a⋅ Ib ⋅ Ron ⋅ t + Ib 2 ⋅ Ron)dt

t
1⎡ t3 t2 ⎤ 2
= ⎢a 2 Ron ⋅ + 2 a⋅ Ib ⋅ Ron + Ib 2 ⋅ Ron ⋅ t ⎥
T ⎢⎣ 3 2 ⎥⎦ 0

1 ⎪⎧ (Ip − Ib)2 t 3 Ip − Ib t 3 ⎫⎪
= ⎨ 2
⋅ Ron ⋅ 2 + 2 ⋅ Ib ⋅ Ron ⋅ 2 + Ib 2 ⋅ Ron ⋅ t 2 ⎬
T ⎪⎩ t 2 3 t2 2 ⎪⎭
1 ⎧1 2 2 ⎫
= ⎨ t 2 (Ip − Ib) Ron + (Ip − Ib)Ib ⋅ Ron ⋅ t 2 + Ib ⋅ Ron ⋅ t 2 ⎬
T ⎩3 ⎭
1 ⎧1 2 2 1 2
= ⎨ Ip ⋅ Ron ⋅ t 2 − Ip ⋅ Ib ⋅ Ron ⋅ t 2 + Ib ⋅ Ron ⋅ t 2
T ⎩3 3 3
+Ip ⋅ Ib ⋅ Ron ⋅ t 2 − Ib 2 ⋅ Ron ⋅ t 2 + Ib 2 ⋅ Ron ⋅ t 2 }
1
= ⋅ Ron ⋅ t 2 (Ip 2 + IpIb + Ib 2 )
3T
1
=f
T
1
∴ P2 = ⋅ f ⋅ Ron ⋅ t 2 (Ip 2 + Ip ⋅ Ib + Ib 2 )
3

5. Input Dynamic Characteristics

Generally, when calculating the peak-rush current necessary for charging drive loss and gate input capacity in designing
the power MOS FET drive circuit, evaluate from the following equations.
Drive loss Pd = f • Cin · VGS ·························································· (12)
Cin ⋅ VGS
Peak rush current i(rush) i(rush) = ··························································· (13)
t
Where, input capacity Cin is generally the value when the bias is fixed in the data sheet. If using this value as it is,
some problems occur. This is because in the Cin, gate drain capacity Cgd, which is mirror capacity, exists, and is
function of the drain-source voltage VDS.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Also, since the gate-source capacity, Cgs is a function of VGS, it contains complicated elements. These details are
described in 4 Switching Characteristics. It is very complicated to design the drive circuit. As a function of VGS and
VDS, gate charge load Qg should be regulated.
(1) Gate charge factor
Figure 20 shows the measurement circuit of the gate charge load, Qg. This measuring theory is that when driving
the gate with constant current, Ig, the time axis, t is multiplied by Ig and the time axis reads as the load, Qg.
Figure 21 shows Qg – VGS, VDS characteristics at Turn-on and Turn-off measured in 2SK299. The vertical axis
represents the drain-source voltage VDS, and the gate-source voltage VGS. The horizontal axis represents the gate
charge load Qg. In waveforms (a) and (b), the stage rised from zero shows the gate-source capacity Cgs charging
time, and the next flat stage shows the gate-drain capacity Cgd charging time. To the contrary, waveforms (c) and
(d) shows the discharging time. The loads necessary for charging Cgs and Cgd are different from each other.
Figure 22 shows Qg – VGS characteristics when VDD · ID of 2SK299 is a parameter. In Figure 22(b) waveform, the
charge necessary for flowing VDD = 100 V and ID = 1 A is 16 nC. At this time, necessary is about 5.2 V. (This
value changes by Vth, gm).
However, in the actual switching operation, it is generally used in the following conditions that drain-source voltage
is in “ON” (saturation) state, and a margin is added to reduce the ON resistance, and the overdrive when VGS = 10 to
15 V. Therefore, when designing the drive voltage as ID = 1 A, VGS = 10 V, the gate charge load is 28 nC. Qg is
different between VDD = 100 V and VDD = 200 V because Cgd varies with VDS.
VDD

SW3 ID Variable 500 V +

/47 μ 0.56 μ
15 V to 20 V –
Q3
47 k 1k
1S2076 0.2 μ 10 μ
0.1 μ
Q1
ID
SW1 VDS
SW2 100
D.U.T.
VGS
Q2

SW1, SW2 : ON/OFF Charge Changeover SW

Q1, Q2 : 2SK186 (IDSS = 2 mA)
Q3 : 2SK1170

N-ch Measurement Circuit

–VDD

–
500 V/47 μ 0.56 μ
–15 V to –20 V 10 μ 0.1 μ +
Q3 1 k
1S2076 0.2 μ 47 k
Q1
ID
SW3 Variable
ID VDS
SW1
SW2 100
D.U.T.
VGS
Q2

SW1, SW2 : ON/OFF Charge Changeover SW

Q1, Q2 : 2SJ68 (IDSS = 2 mA)
Q3 : 2SK1170 Unit R : Q
C: F
P-ch Measurement Circuit

Figure 20 Gate Charge Measurement Circuit

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

Turn-on Turn-off
160 16 16 160

120 12 12 120

VGS

VGS (V)
VGS (V)

VDS (V)
VDS (V)

80 8 8 VGS 80

40 4 4 40
VDS VDS
0 0
0 8 16 24 32 40 0 8 16 24 32 40
Qg (nC) Qg (nC)
(a) VDD = 100 V, ID = 5 A (c) VDD = 100 V, ID = 5 A

Turn-on Turn-off
160 16 16 160

120 12 12 120
VGS
VGS (V)

VGS (V)
VDS (V)

VDS (V)
80 VGS 8 8 80

40 4 4 40

VDS VDS
0 0
0 8 16 24 32 40 0 8 16 24 32 40
Qg (nC) Qg (nC)
(b) VDD = 100 V, ID = 1 A (d) VDD = 100 V, ID = 1 A

Figure 21 2SK299 Qg – VGS • VDS Characteristics

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

16 16

VGS (V) 12 12

VGS (V)
8 8

4 4

0 8 16 24 32 40 0 8 16 24 32 40
Qg (nC) Qg (nC)
(a) VDD = 50 V, ID = 1 A (d) VDD = 50 V, ID = 5 A

16 16

12 12

VGS (V)
VGS (V)

8 8

4 4

0 8 16 24 32 40 0 8 16 24 32 40
Qg (nC) Qg (nC)
(b) VDD = 100 V, ID = 1 A (e) VDD = 100 V, ID = 5 A

16 16

12 12
VGS (V)

VGS (V)

8 8

4 4

0 8 16 24 32 40 0 8 16 24 32 40
Qg (nC) Qg (nC)
(c) VDD = 200 V, ID = 1 A (f) VDD = 200 V, ID = 5 A

Figure 22 2SK299 Qg – VGS Characteristics

(2) Designing of driven circuit
The drive loss and necessary peak rush current of the drive circuit are evaluated by the following equations with the
gate charge load Qg.
Drive loss PD = f • Qg VGS ······································································· (14)
Q
Peak rush current i(rush) = ··············································································· (15)
t

<Example>
Using the 2SK299, when f = 100 kHz, VDD = 100 V, VGS = 15 V, switching time ton = 50 ns, and ID = 5 A, what is the
drive loss and necessary peak rush current?
<Solution>
Since Qg in the above conditions is 39 nC in Figure 22 (e).

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Pd = f ⋅ Qg ⋅ VGS
= 100 × 10 3 × 39 × 10 −9 × 15
= 58.5mW
Qg 39 × 10 −9
i(rush) = = = 0.78A
t 50 × 10 −9

As shown above, the answer can be obtained with ease.

Figure 23 shows the comparison between the drive loss measured by the Figure 24 Circuit and the drive loss
calculated using the equation (14). The horizontal axis represents frequency. As shown in this figure, calculated
value and measured value match well, which indicates that determining the gate charge Qg facilitates designing the
drive circuit accurately.
1000

500

200

VGS =15V
Drive Loss Pd (mW)

100

50
VGS =10V

20

10

5
Calculated Value
Pd (c) = f • Qg • VGS
Measured Value
Pd (m) = VDD • Iin
2
5k 10k 20k 50k 100k 200k 500k 1M
Frequency f (Hz)

Figure 23 Drive loss of Power MOS FET (2SK320)

VDD

100 Ω
A
Iin
PG 2SC1213 100 V
D.U.T.
50 Ω 2SK320
2SA673
50 Ω

VDD = 100 V
ID = 1 A

Figure 24 Test Circuit

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
(3) Gate Charge Characteristics
Figure 25 shows typical gate charge characteristics and the waveforms of VGS, VDS and ID. The characteristic curve
can be divided into three areas. Area 1 indicates a period in which the gate source capacity (Cgs) is charged until
the VGS reaches the value required to supply specific drain current ID. The FET is “off” between the threshold
voltage VGS(th) and t1 during this period.
When the VGS value exceeds VGS(th), the drain current ID begins to flow and becomes stable at t2. Area 2 is a
transition area between the VDS active and inactive areas. That is, the drain source pressure VDS varies and the gate
drain (mirror) capacity Cgd is charged. This mirror effect increases Cin, activates the FET, the VDS transition
lessens, and as a result, the effect is lost at t3. In area 3, the VDS is inactive and doesn’t very much. That is, the
VDS(on) of the FET is maintained as ID × RDS(on). Cin(3) in area 3 is larger than Cin(1), but smaller than Cin(2).
Cin(1) and Cin(3) correspond to Ciss and are equivalent to the value of Cgs + Cgd. However, Ciss and Cgs + Cgd
are not equal because the value of VDS defers between areas 1 and 3 (the Cgd value differs). That is, Cin(3) of area
3 is larger than Cin(1) because of the large Cgd caused by the thin depletion layer immediately under the gate.
(4) Calculating Method of Switching Time
Using the Gate Charged Characteristic Qg Figure 26 (c) shows a standard circuit which measures switching time,
and Figure 26 (a) shows the transient response characteristic of gate input pressure. In the figure (a), when Cin is
fixed, the VGS characteristic is;
⎧
⎪ ⎛ t ⎞⎫⎪
VGS(t) = VGS ⎨1 − exp ⎜− ⎟ ⎬ ············································································ (16)
⎪
⎩ ⎝ Cin ⋅ R ⎠
S ⎪⎭
Vg1 and Vg2 are;
⎧
⎪ ⎛ t1 ⎞ ⎫ ⎪
Vg1 = VGG ⎨1 − exp ⎜ − ⎟ ⎬ ··············································································· (17)
⎪
⎩ ⎝ Cin ⋅ R ⎠
S ⎭⎪
⎧
⎪ ⎛ t2 ⎞ ⎫ ⎪
Vg2 = VGG ⎨1 − exp ⎜− ⎟ ⎬ ·············································································· (18)
⎪
⎩ ⎝ Cin ⋅ R ⎠
S ⎪⎭

t1 and t2 – t1 can be got from formulas (17) and (18). They are as follows because Cin differs between area 1 and 2
as seen from Figure 27.
160 16

(1) (2) (3) 120 VGS 12

VDS
Cin (1) Cin (2) Cin (3)
VGS (V)
VDS (V)

80 8
Qgs Qgs Qgs
VGS

40 4

0 0
VGS (th) 16 8

12 6
t0 t1 t2 t3 t4 ID
VGS (V)

ID (A)

8 4
VDS VGS
ID
4 2
VDD
ID
0
0 0 8 16 24 32 40
t VDS (on) Qg (nC)
(= ID × RDS (on))
2SK299
Waveform
VDD = 100 V, ID = 5 A

Figure 25 Typical Gate Charge Waveform and VDS, ID Waveforms

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

VDD

VGG
RL
Vg2 Vg2
VGS (V)

Vout
RS
Vg1 Vg1

VGG Vg
t0 t1 t2 t3 t3 t2 t1 t0 RS : Signal Source Resistance
t t of Pulse Generator

(a) Turn-ON (b) Turn-OFF Switching Time Test Circuit

Figure 26 Switching Time Test Circuit and VGS Waveforms

⎛ VGG ⎞
(
t1 = Cin(1) ⋅ RS ln ⎜ ) ⎟ ················································································ (19)
⎝ GG − Vg1⎠
V

( )
t 2 − t1 = Cin(2) ⋅RS ln ⎛ VGG − Vg1 ⎞ ············································································ (20)
⎜ V − Vg2 ⎟
⎝ GG ⎠

Cin(1) and Cin(2) of area 1 and area 2 are obtained with following formulas.
ΔQ Qg1
Cin(1) = = ··························································································· (21)
ΔVg Vg1
ΔQ Qg2 − Qg1
Cin(2) = = ···················································································· (22)
ΔVg Vg2 − Vg1

In the Figure 27 waveforms, t1 is the turn-on delay time td(on), and t2 – t1 is the rise time tr. If substituting formulas
(21) and (22) for formulas (19) and (20), td(on) and tr are;

Qg1 ⎛ VGG ⎞
∴ t d(on) = ⋅ RS ln ⎜ ⎟ ············································································· (23)
Vg1 ⎝ GG
V − V g1⎠
⎛ Qg2 − Qg1⎞ ⎛ VGG − Vg1 ⎞
∴tr = ⎜ ⎟ ⋅ RS ln ⎜ ⎟ ······································································ (24)
⎝ Vg2 − Vg1 ⎠ ⎝ VGG − Vg2 ⎠

The turn-off delay time td(off) and fall time tf can be also obtained using the above method. With Figure 26 (b);

⎛ t ⎞
VGS(1) = VGG ⋅ exp ⎜− ⎟ ··············································································· (25)
⎝ Cin ⋅ RS ⎠
t2 and t1 – t2 are;
(
t 2 = Cin(1) ⋅ RS ln ) VGG
Vg2
························································································· (26)

(
t1 − t 2 = Cin(2) ⋅ RS ln ) Vg2
Vg1
···················································································· (27)

With Figure 28 Cin(1) and Cin(2) are;

ΔQ Qg3 − Qg2
Cin(1) = = ···················································································· (28)
ΔVg VGG − Vg2
ΔQ Qg2 − Qg1
Cin(2) = = ····················································································· (29)
ΔVg Vg2 − Vg1

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
In the Figure 28 waveforms, t2 is the turn-off delay time td(off), and t1 – t2 is the fall time tf.

⎛ Qg3 − Qg2 ⎞ ⎛ VGG ⎞

∴ t d(off) = ⎜ ⎟ ⋅ RS ln ⎜ Vg2 ⎟ ········································································ (30)
⎝ VGG − Vg2 ⎠ ⎝ ⎠
⎛ Qg2 − Qg1⎞ ⎛ Vg2 ⎞
∴ tf = ⎜ ⎟ ⋅ RS ln ⎜ ⎟ ·············································································· (31)
⎝ Vg2 − Vg1 ⎠ ⎝ Vg1 ⎠

td (on) tr
VGG
VDS 90%
(1) (2)
VGS (V)

VDS (V)
Vg2
Vg1

10%

Qg1 Qg2 Qg3

t1 t2 t3

Qg, t

Figure 27 Gate Charge Characteristic (Turn-on)

td (off) tf
VDS
VGG
90%
(1) (2)
VGS (V)

VDS (V)

Vg2
Vg1

10%

Qg3 Qg2 Qg1

t3 t2 t1

Qg, t

Figure 28 Gate Charge Characteristic (Turn-off)

6. Area of Safe Operation (ASO)
6.1 Forward Bias ASO
The most basic and important characteristic required for a power device is a high breakdown strength.
Since the current flowing in power MOS FETs does not concentrate locally, power MOS FETs are free from secondary
breakdown in the high voltage region.
Figure 29 shows thermal mapping of chip surfaces, under power on, for a power MOS FET and conventional bipolar
transistor.
Whereas the thermal mapping in the power MOS FET is uniform, a hot spot is generated in the bipolar transistor,
although the power applied is one-half that applied to the power MOS FET. Figure 30 shows breakdown points of

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
power MOS FETs in relation to those of bipolar transistors. ASO of bipolar transistors is limited by secondary
breakdown in the high voltage region. On the other hand, in a power MOS FET, the guaranteed area of safe operation
is equal to the range of thermal limitation. ASO design is very simple.

VDS = 60 V, ID = 2 A VCE = 30 V, IC = 4 A VCE = 60 V, IC = 1 A

(A) Power MOS FET (B) Bipolar Transistor (C) Generation of Hot Spot
(2SK135, 2SK1058) (2SC1343) Bipolar Transistor (2Sc1343)

Figure 29 Chip Surface Temperature at Power ON

5 20 50
10 0 0
W W
0
W Po
50 we
2 rM
Collector Current IC (A)

W OS
Drain Current ID (A)

BipoD753)
(2S

FE
T
20 (2
lar P

1.0 P SK
C, W 1
P 76
owe

ch )
=
0.5 10
r Tra

W
nsis
tor

0.2

DC Operation (TC = 25°C)

0.1
10 20 50 100 200 500
Drain Source Voltage VDS (V)
Collector Emitter Voltage VCE (V)

Figure 30 Area of Safe Operation

Determining Whether Power MOS FET Repeat Pulse Switching Operations Fall Within the ASO (Reference)
In order to determine whether or not Power MOS FET continuous pulse switching operations fall within the ASO, first
calculate junction temperature Tj. If the calculated value falls within the prescribed Tj max., the operation is within the
ASO. The following shows an example of such a calculation.
Example 1: For a repeat pulse switching operation with constant power loss
Junction temperature Tj is expressed by the following formula:
Tj = Tc + ΔTj
= Tc + θch–c(t) (ID2 • Ron + SW loss)

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

VDS (peak) < VDSS (max)

0
VDS = ID•Ron

(a) Voltage Waveform VDS

PW PW
ID duty =
T

0
T

(b) Current Waveform

Figure 31 Waveforms for Repeat Pulse Switching Operation with Constant Power Loss

when:
Tc: case temperature
θch–c(t): PW = t, duty n% transient thermal resistance
Ron: on-resistance max (Tj max = 150°C)
SW loss: loss caused by ton, toff during switching

Example:
When using 2SK556 (Pch = 100 W, θch-c = 1.25°C / W, Tj max = 150°C), are the switching (Power MOS FET VGS ≥
10 V) conditions within the ASO when case temperature TC = 80°C, ID = 10 A, PW = 10 μs, and duty = 20% (f = 50
kHz)? Here, note that SW loss is half of Ron loss.
(1) First, the transient thermal resistance θch-c(t) for PW = 10μs and duty = 20% is calculated using γ(t) = 0.21 from the
data sheet, giving us θch-c(t) = γs(t) • θch-c = 0.21 × 1.25 = 0.263°C / W.
Next, chi-c(t) for PW = t and duty = n% can be calculated using the following formula:

⎧ n ⎛ n ⎞ ⎫
θch − c(t) = θch − c ⎨ + ⎜1 − ⎟ * γ S(t) ⎬
⎩ 100 ⎝ 100 ⎠ ⎭
(*γs(t) is 1 shot pulse for rated transient thermal resistance.)

(2) The data sheet reveals that Ron max for 2SK556 is 0.55Ω. For a Tj max of 150°C, this value should be increased
2.2 to 2.4 times:
Ron = 2.4 × 0.55 = 1.32 Ω

(3) Consequently, junction temperature Tj is:

Tj = Tc + θch − c(t)(ID 2 ⋅ Ron + SW loss)
⎧
⎩
( 1
) ( ⎫
= 80 + 0..263⎨ 10 2 × 132 + 10 2 × 1.32 ⎬
2 ⎭
)
= 80 + 52
= 132°C

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Since Tj < Tj max, the operating conditions fall within the ASO.

Normalized Transient Thermal Impedance γS (t)

3

D=1 TC = 25°C
1.0
0.5

0.3 0.2
0.1 θch–c (t) = γS (t) • θch–c
0.1
0.05 θch–c = 1.25°C/W, TC = 25°C
PDM
0.02
0.03 0.01
lse D = PW
ho t Pu PW T
1S T
0.01
10 μ 100 μ 1m 10 m 100 m 1 10
Pulse Width PW (s)

Figure 32 2SK556 Catalog Data

Example 2: For a repeat pulse switching operation with non-constant power loss (i.e. fluctuating load, short, etc.)
Figure 33 (b) shows a method that can be effectively used for calculating an approximation (to simplify strict
conditions) for the type of waveform shown in Figure 33 (a). Figure 33 (c) shows junction temperature Tj(peak) when
loss P1 under continuous repeat operation conditions average loss P2, and peak period (ID2) loss P3 are applied.
Tj(peak) can be calculated using the following formula:
Tj(peak) ≅ Tc + P1 ⋅ θch − c(t1) + P2 ⋅ θch − c(t 2 + t 3 )
+P3 ⋅ θch − c(t 3 ) − P1 ⋅ θch − c(t 2 + t 3 ) − P2 ⋅ θch − c(t 3 )
= Tc + θch − c(t1)(ID12 ⋅ Ron1 + SW loss)
t1
+ ⋅ ID2 2 ⋅ Ron2 ⋅ θch − c(t 2 + t 3 ) + ID22 ⋅ Ron 2 ⋅ θ ch − c(t 3 )
T
t t
− 1 ⋅ ID12 ⋅ Ron1⋅ θch − c(t 2 + t 3 ) − 1 ⋅ ID2 2 ⋅ Ron2 ⋅ θ ch − c(t 3 )
T T

When:
θch–c(t1) : PW = t1, duty n% transient thermal resistance
θch–c (t2) : PW = t2 1shot pulse transient thermal resistance
θch–c (t3) : PW = t3 1shot pulse transient thermal resistance
SW loss : loss caused by ton, toff during switching
Ron : on-resistance max.(Tj max. = 150°C)

Example:
When using 2SK556, a waveform is produced such as that shown in Figure 33 (a), determine whether the following
conditions are within the ASO: case temperature TC = 50°C, ID1 = 3 A, t1 = 10 μs, duty = 50% (f = 50 kHz), t2 = 100 μs.
(1) The data sheet reveals that Ron1 for ID1 = 3 A is o.55 Ω max. For a Tj max of 150°C, this value should be increased
2.2 to 2.4 times:
Ron1 = 2.4 × 0.55 = 1.32 Ω
(2) The data sheet reveals that according to ID–Ron characteristics, Ron2 for ID2 = 30 A is Ron2 ≅ 0.8 Ω typ. For a Tj
max of 150°C, Ron max should be increased 1.3 time:
Ron2 = 2.4 × 1.3 × 0.8 = 2.5 (in actual practice, observation of the waveform is essential)
(3) For PW = t1 = 10 μs, duty 50% transient thermal resistance θch-c(t1), the data sheet provides for γs(t) = 0.5:
θch-c(t1) = γs(t) • θch-c = 0.5 × 1.25 = 0.625°C / W
(4) For PW = (t2 + t3) = 110 μs 1 shot θch-c(t2 + t3), the data sheet provides for γs(t) = 0.04:
θch-c(t2 + t3) = γs(t) • θch-c = 0.04 × 1.25 = 0.05°C / W

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

ID1 t1 ID2
Continuous
Repeat Operation
T t2
(a)

ID1 ID2

t2 t3

(b)
t3 = t1
P3

P1 P2

–P2 (t3)
–P1 (t2 + t3)
(c)

Figure 33 Sample Waveforms for Repeat Pulse Switching Operation with Non-constant Power Loss

(5) For PW = t1 = 10 μs 1 shot θch-c(t3), the data sheet provides for γs(t) = 0.015:
θch-c(t3) = γs(t) • θch-c = 0.015 × 1.25 ≅ 0.02°C / W

∴ Tj(peak) = Tc + θch − c(t1)(ID12 ⋅ Ron1 + SW loss)

t
+ 1 ⋅ ID2 2 ⋅ Ron2 ⋅ θch − c(t 2 + t 3) + ID2 2 ⋅ Ron2 ⋅ θch − c(t 3 )
T
t1 t
− ⋅ ID12 ⋅ Ron1⋅ θch − c(t 2 + t 3 ) − 1 ⋅ ID2 2 ⋅ Ron2 ⋅ θch − c(t 3 )
T T
⎧ 2 1 2 ⎫ 1
= 50 + 0.625⎨(3 × 1. 32) + (3 × 1.32)⎬ + (30 2 × 2.5) . × 0 05
⎩ 2 ⎭ 2
1 1
+30 2 × 2. 5 × 0. 02 − (3 2 × 1.32) × 0. 05 − (302 × 2.5). × 0 02
2 2
= 50 + 11. 1 + 56. 3 + 45 − 0. 3 − 22. 5
= 139. 6°C

Since Tj < Tj max, the operating conditions fall within the ASO.

6.2 Reverse Bias ASO

For power switching applications, such as switching regulators, the load of the switching device is usually inductive.
Therefore, not only the forward bias ASO, as described in the preceding section, but also the reverse bias ASO should
be considered. Generally, in a switching power supply, the emitter-base junction is reverse biased to reduce tstg and tf.
In this case, the larger the current becomes, the smaller tstg and tf will be. And, according to it, the reverse bias ASO
will be narrower, which means the operation area is more limited, as shown in Figure 34. On the other hand, in a power
MOS FET, it is possible to make toff smaller by reverse bias of the gate, without narrowering the operation area. This
gives flexibility in circuit design.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

10

Power MOS FET

8
Ta = 25°C

Collector Current IC (A)

IB1 = 1 A
6 IB2 = –1 A

Bipolar Transistor
IB1 = 1 A
4 IB1 = 1 A IB2 = –0.5 A
IB2 = –2 A

0 200 300 400 500 600

Collector-Emitter Voltage VCE (V)

Figure 34 Reverse ASO

10 1.0
VDS = 10 V

°C
VDS = 10 V T = –25°C

25
C

25
=–
8 0.8

75
C
T
Drain Current ID (A)

25
Drain Current ID (A)

6 0.6
75

4 0.4

2 0.2

0 2 4 6 8 10 0 0.4 0.8 1.2 1.6 2.0

Gate-Source Voltage VGS (V) Gate-Source Voltage VGS (V)
(a) D Series 2SK413 (b) S Series 2SK1057

Figure 35 Typical Transfer Characteristics

7. Temperature Characteristics
Figure 35 shows the transfer characteristics of power MOS FETs. In the high current area, the temperature coefficient
is negative and current concentration does not occur. A wide area of safe operation is provided and destruction by
thermal runaway is largely prevented.
Since the transfer characteristics of power MOS FETs are of the enhancement type, as in the case of bipolar transistors,
power MOS FETs don’t require a complex biasing circuit like depletion type FETs do.
The cross point at which the temperature coefficient becomes zero, is quite different between the D series device and
the S series device, owing to their structures and processes. The cross point is 2 to 6 A D series device, and about
100 mA, in S series device, although it depends on device type.
Therefore, by setting the idling current about 100 mA, the S series MOS FET, when applied to a class-B push pull audio
power amplifier, can dispense with a current temperature compensation circuit, which is required in bipolar transistor
circuits.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
8. Source-Drain Diode Characteristics
In both D series and S series Power MOS FETs, as shown in Figure 36 and Figure 37 a diode exists parasitically,
between source and drain.
The forward current and the breakdown voltage ratings of this diode have the same characteristics as those of the power
MOS FET.
Figure 38 shows the VF-IF characteristics of this diode, and Figure 39, the waveform of the backward recovery time
(trr).
Also we would like to shown in Figure 40 the trr’s on a line scale, comparing the Fast Recovery Diode with some MOS
FET’s.
As is obvious from it, this diode has excellent characteristics, much the same as a typical diode. Moreover, when this
diode is used in a bridge circuit, PWM amplifier output stage, etc, it can dispense with the external commutating diode,
resulting in a reduction of the number of components.
If a channel is produced by making VGS positive, the current flows equally in both directions.
When the current is low, VF is given by IF × Ron. The VF of this diode is smaller than that of a typical diode. Therefore,
in some cases, this diode is better than a typical one.

Channel Channel Channel

Source Source
Drain
Gate Gate

N+ N+ N+ N+

P P N

N P
N+ P+
Drain Substrate (Source)

Figure 36 Structure of D Series) Figure 37 Structure of S Series

(Vertical type) (N channel) (Lateral type) (N channel)

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

Reverse Drain Current vs. Reverse Drain Current vs.

Source to Drain Voltage Source to Drain Voltage
20 50

Reverse Drain Current IDR (A)

Reverse Drain Current IDR (A) Pulse Test
16 Pulse Test
40

10 V
12 30 15 V
5V
8 20
10 V
5V
VGS = 0, –5 V
4 10
VGS = 0, –10 V

0 0.4 0.8 1.2 1.6 2.0 0 0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage VSD (V) Source to Drain Voltage VSD (V)

2SK1517, 2SK1518 2SK1095, 2SK1622

Reverse Drain Current vs. Reverse Drain Current vs.

Source to Drain Voltage Source to Drain Voltage
50 –20

Pulse Test Pulse Test

Reverse Drain Current IDR (A)
Reverse Drain Current IDR (A)

40 –16

30 –12
–10 V

20 –8
VGS = 10 V
–5 V
10 –4
0, –5 V VGS = 0, 5 V

0 0.4 0.8 1.2 1.6 2.0 0 –0.4 –0.8 –1.2 –1.6 –2.0
Source to Drain Voltage VSD (V) Source to Drain Voltage VSD (V)

2SK1669, 2SK1670 2SJ177, 2SJ220

Figure 38 VF-IF Characteristics

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

100 μs

2SK1520, 2SK1522 2SK1520, 2SK1522 (A)

10 ms

di/dt 1 μF
Adjustment (B) 50 μs
IN (A)
VF IN (B) VR (100 V max)
trr
D.U.T. 10 Ω
IF
U19E
0

di/dt

Measuring Circuirt Scale iF = 10 A/DIV

t = 100 ns/DIV

2SK1170 2SK1518
(iF = 20 A, di/dt = 100 A/μs) (iF = 20 A, di/dt = 100 A/μs)

2SK1671 2SK1669
(iF = 30 A, di/dt = 100 A/μs) (iF = 30 A, di/dt = 100 A/μs)

Figure 39 trr Waveform of the Built-in Diode

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
2000
Power MOS FET
Usual FRD
1000
Fast FRD
2SK1170

Reverce Recovery Time t rr (ns)

(500 V/20 A)
500
2SK1623
(100 V/20 A)

2SK1947
200 (250 V/50 A)
2SK2553
(60 V/50 A)
2SK2554 2SK1518
100 (60 V/75 A) (500 V/20 A)
2SK1669
2SK2204 (250 V/30 A)
(30 V/45 A)
50

20 50 100 200 500 1000 2000

Drain-Source Voltage VDSS (V)

Figure 40 Comparison to the Built-in Diode and the FRD trr

8.1 Precautions in Handling the Built-in Diode
An built-in diode of the power MOS FET is used as a commutating diode in a motor control circuit. In this case, if the
reverse voltage is charged immediately after a high current is supplied to the diode, it may be destroyed depending on
the circuit and the operating conditions.
Figure 41 and 42 show a basic motor control circuit and the waveform of the motor control operation. These
waveforms are at Q2 and Q3 off and Q1 and Q4 on. Q4 is continuously on when Q1 is chopping.
Gate drive signal is put into G1, then Q1 is switched on and iD1 flows. When Q1 current iD1 is switched off, forward
current, iF flows through the built-in diode of Q2 by the energy accumulated at the motor inductance. If Q1 is switched
on in this condition, Q2 is into on state under the influence of reverse recovery time, trr of built-in diode on Q2, and high
level of reverse current (recovery current), iDr flows.
This excess recovery current may destroy the diode at a point in the shaded area in the figure, which indicates the period
in which the built-in diode voltage recovers. Therefore, restricting the recovery current iDr is an effective method to
prevent diode destruction. Table 2 shows the detailed circuit countermeasures.
VCC

Q1 Q3
G1 i D1 i M G3
AC 100V VDS M
and 200V i D2
Q2 Q4
G2 G4

Figure 41 Typical Motor Control Circuit

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
VLS VCC

0 VDS1 (Drain-source Voltage Waveform of Q1)

VDS (on)

i D1 (Drain Current Waveform of Q1)

0
t rr
iF
0 i D2 (Drain Current Waveform of Q1)
di Dr /dt

di F /dt i Dr

VDS (on) VS
VDS2 (Drain-source Voltage Waveform of Q2)
VCC
0
VF

<Description>

iF: Forward Current of Q2 Built-in Diode

VF : Forward Voltage Drop of Q2 Built-in Diode
VDS(on) : Drain-Source Saturation Voltage of Q2
t rr : Reverse Recovery Current Time of Q2 Built-in Diode
VLS : Voltage Drop with Current Inductance LS
i Dr : Reverse Recovery Current of Q2 Built-in Diode
(Dependes on the Drive Signal Source Impedance
diF/dt of Q1, Circuit Inductance LS, Supply Voltage
VCC, and Electric Charge Qrr (or trr) in the Built-in Diode)
VS : Spike voltage
(Dependes on the Inductance LS, iDr, and diDr/dt of the Circuit)

Figure 42 Waveform of the Motor Control Operation

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Table 2 Circuit Countermeasures against Built-in diode Destruction

Classifi- Waveforms of the built-in diode Circuit

Countermeasures Circuit Before After
cation constants, etc.
improvement improvement
(1) Delay the turn-on time, R = 330 Ω to
by inserting a resistor 820 Ω (di / dt =
and diode which are VCC IF 20 to 50 A / μs)
0 0
connected in
parallel into the gate
G1 irr I
R R G3 di/dt
of the Power MOS M
dv/dt
FET. This controls G2 VF V
R R G4 0 0
di / dt and dv / dt of the
built-in diode to restrict
the recovery current
(in this case, the turn-
off time does not have
to be delayed).
(2) Insert an L and diode VCC 0 0 L = 2 μH to 20 μH
connected in parallel I
G1 G3
into the drain of the
Power MOS FET. This M
V
controls di / dt to G2 G4
0 0
restrict the recovery
current irr.
(3) Insert a C or CR R = 10 to 47 Ω
snubber between the VCC 0 0 C = 0.01 μF to
I
drain and source of the G1 G3 0.1 μF Wiring
Power MOS FET to M CR of the snubber
restrict dv/dt and C be as short as
G2 G4 V
voltage spike of the 0 0 possible.
built-in diode.
(4) Wires between +, – Should be done
terminals of the power 0.2 to 1 μ
together with
VCC Short
supply line and the Short 0 0 countermeasures
c c I
drain / source of each G1 G3 (1) to (3).
arm (in the case of M
N/N) should be twisted. G4
G2 V
C are also connected. 0 0
Twisted Directly
By directly attaching
Wires attached
wires to the upper and
lower arms and
minimizing stray
inductance, the voltage
spike and dv/dt are
restricted.

(5) Connect the fast diode VCC 0 0

to the external of the I
G1 G3
Power MOS FET not to M
flow the current in the V
G2 G4
built-in diode. 0 0

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
9. Design of High Breakdown Voltage Application (Series Operation)
(1) Totem pole connection
Figure 43 shows a basic “totem pole” circuit, in which power MOS FETs are connected in series. This circuit has
been used extensively as a saturated logic circuit, the basic circuitry for TTL IC. Operation of this circuit will be
explained.
When no bias is applied to Q1, Q1 is cut off because power MOS FETs have enhancement type transfer
characteristics, thus the following relationships hold;
Drain
VDD

ID
Rg
Q2
VG2

VGS2 VO
Rg

Gate
Q1
Vin = VG1
VGS1

Source

Figure 43 Basic Totem Pole Circuit

VG1 = 0, ID = 0
Rg
VG2 = 1/ 2 VDD ( ∴ VG2 = VDD )
Rg + Rg
VD = VG2 − VGS2
= 1/ 2 VDD − Vth2

where Vth2 is the threshold voltage of Q2. Generally, Vth2 << VDD. Therefore VO ≅ 1/2VDD.
And the voltage applied to Q1 and Q2 will be about 1/2 VDD.
Next, let us consider a transient state. When the gate bias of Q1 is increased gradually from zero, Q1 will become
conductive and so will Q2 at the same time. If load resistance ZL is inserted between VDD and drain of Q2, drain
voltage will be VD = VDD – ZL • ID and VO (= 1/2VD – VGS2) will gradually decrease.
If VDD has much larger value than VGS2 and Q2 is driven up to the saturation region, then the characteristics of an
equivalent MOS FET would be dependent on Q1.
Generally, when devices are operated in series, voltage unbalance due to switching time difference presents a
problem. This problem is overcome in power MOS FETs because switching time can be made as short as several
tens of nanoseconds.
Figure 44 and 45 show breakdown and output characteristics where a single device is used. When this device is
used in the circuit shown in Figure 43, the breakdown and output characteristics would be as shown in Figures 46
and 47. Breakdown voltage in Figure 46 is twice as high as in Figure 44. The disadvantage is that on-resistance is
also doubled, as is obvious from Figures 45 and 47. A method of improving on-resistance is described in the
following section.

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

100

80

Drain Current ID (mA)

60

40

20

0 100 200 300 400 500

Drain to Source Voltage VDS (V)

Figure 44 Breakdown Characteristics (Single Device)

VGS = 0 to 10 V (1 V Step)
5

4
Drain Current ID (A)

0 4 8 12 16 20
Drain to Source Voltage VDS (V)

Figure 45 Output Characteristics (Single Device)

100

80
Drain Current ID (mA)

60

40

20

0 100 200 300 400 500

Drain to Source Voltage VDS (V)

Figure 46 Breakdown Characteristics

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

VGS = 0 to 10 V (1 V Step)
5

Drain Current ID (A)

3

0 4 8 12 16 20
Drain to Source Voltage VDS (V)

Figure 47 Output Characteristics

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
(2) How to reduce on-resistance in basic circuit
On-resistance (or saturation voltage) can be reduced by performing level shift of the Q2 gate potential in the positive
direction. This can be accomplished, for instance, by the methods shown in Figure 48. Figure 49 shows the output
characteristics for a case where the gate is level-shifted to the positive side. (14 V is the maximum allowable gate-
to-source voltage.)
In the circuit shown in Figure 48 as in the basic circuit, the equivalent drain to source breakdown voltage is twice as
high as when a single device is used.
G
Rg Rg

S D
Q1 Q2
(A) Level Shift by Using of Diode

G
Rg Rg

S D
Q1 Q2
(B) Level Shift by Using of Breakdown
Voltage in External Transistor

G
Rg Rg

14 V

S D
Q1 Q2

(C) Level Shift by Using of External

Power Suppy

Figure 48 How to Reduce ON-Resistance

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

VGS = 0 to 10 V (1 V Step)
5

Drain Current ID (A)

3

0 4 8 12 16 20
Drain to Source Voltage VDS (V)

Figure 49 Output Characteristics ((C) Circuit)

(3) Improvement of high frequency characteristics in totem pole connection

When the circuit shown in Figure 43 is modified for a source follower, because of the different operation of Q1 and
Q2, a phase differential occurs under the influence of the power MOS FET input capacitance (about 500 pF for
2SK1057, 600 pF for 2SJ161, f = 1 MHz). As a result, characteristics worsen, as high frequency gain droops and
phase shift increases.

Rg
Q2
Cin2
Cg Rg
VO2

RG
Q1
Signal Source Cin1

VO1 Cin1, Cin2 : Input Capacitance

RG : Signal-Source Resistance
RL Cg : Compensation Capacitance
Rg : Gate Biasing Resistance
Load

Figures 50 Improved Totem Pole Circuit

Cg
VO1 VO2

Rg Cin1 Rg

RL Cin2 Rg

Figure 51 Passive Equivalent Circuit of Totem Pole

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Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
This is expressed in Figure 50. The equivalent circuit with passive devices alone is represented in Figure 51.
It has been verified experimentally that the phase differential of VO1 and VO2 can be eliminated and driving in the
same phase can be achieved by equalizing Cg with Cin2 and that phase shift as 100 kHz can be limited within –90
degrees.

10. Analysis of Oscillation in Source Follower Circuits

<Reference>
There have been many works on analysis of oscillation in source follower circuits. The most general analysis for source
follower circuits is about the case in which the real part of the input impedance is negative and the imaginary part is
ZERO. An example is described as followers. The simplified equivalent circuit of source follower is shown in Figure
22.

i1 i2
Rg + rg Ciss

υ
vI v × gm CL v0
RL C iss : Input Resistance
gm : Transconductance
C L : CF (Capacitance Between Case and
Heatsink) + CL (Leakage Capacitance)
r g : Gate Resistance
R S : Signal-Source Resistance

Figure 52 Equivalent Circuit of Source Follower Circuit

The input impedance Zin can be obtained as follows;

Vi 1 gm
Zin = = + RL (1 + ) ··········································································· (1)
i1 jωCiss jωCiss
RL
In the case of load consisting of paralleled resistor and capacitor Substitute instead of RL in equation (1).
1 + jωC L R L

1 jωCLRL 2 jω gm RL
Zin = − −
jωCiss 1 + ω CL RL
2 2 2
(1 + ω CL 2RL 2 )ω 2Ciss
2

RL ω 2CLRL 2 gm
+ 2
− ···················································· (2)
2
1 + ω CL R L 2
(1 + ω 2CL 2RL 2 )ω 2Ciss

The condition for negative resistance is;

RL CLRL 2 gm
RS + rg + − < 0 ························································· (3)
1 + ω 2CL 2RL 2 (1 + ω 2CL 2RL 2 )Ciss

moreover, approximately,
CLRL 2 gm
RS + rg + RL − < 0 ·················································································· (4)
Ciss

Therefore, to prevent oscillation, external gate resistor RG should be inserted. Then the following equation can be
obtained.
CLRL 2 gm
R G + RS + rg + RL − ≥0
Ciss

However, the insertion of external RG makes Power MOS FETs frequency response worse. Therefore, when selecting
RG, a compromise between stability against oscillation and amplifier’s frequency response should be considered.
Voltage gain vs. frequency vs. RG is shown in Figure 53.

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

RG G rs
–1
D
υ C in
–2
S υ × gm
e i SG

eo –3
RL

Voltage Gain eo /ei (dB)

–4

RG
=0
50
100
–5

Ω
200
C iss : Input Capacitance (500pF)

300
r g : Gate Equivalent Resistance (65 Ω)

500
g m : Forward Transconductance (IS) –6

1k
R L : Load Resistance (8 Ω )
R G : Gate Series Resistance –7
e0 1
=
e1 R O + rg + 1/ ω C iss –8
1+
R L (1 + g m / ω C iss )

–9

–10
10k 100k 1M 10M 100M

Freauency f (Hz)

Figure 53 Frequency Characteristics of Source Follower (Calculated Value)

11. Thermal Design

1. Channel, Package and Surrounding Air Thermal Resistances
The total thermal resistance up to the surrounding air as seen from the channel is expressed by formula (1), which is
derived from the equivalent circuit shown in figure 54.

Rth (ch-c) Rth (i) Rth (c) Rth (ch-c) : Thermal resistance from the
channel to the package case
Rth (c-a) : Thermal resistance from the case to
the immediate exterior atmosphere
ΔTch Rth (c-a) Rth (f)
Rth (i) : Thermal resistance of insulating layer
Rth (c) : Thermal resistance of contacts
Rth (f) : Thermal resistance of heat sink
Rth : Total thermal resistance

Figure 54 Equivalent Circuit

Rth(ch − a) ⋅ (Rth(i) + Rth(c) + Rth(f))

Rth = Rth(ch − c) + ···················································· (1)
Rth(ch − a) + Rth(i) + Rth(c) + Rth(f)

Table 3 lists the thermal resistance items for each package. (Provided as reference values.)
While the thermal resistance from the case to the surrounding air (Rth(c-a)) is determined by the transistor case
materials and shape, as can been seen in table 6-3, its value is relatively large as compared to the values for Rth(i),
Rth(c), and Rth(f). As a result it is possible to approximate formula (1) by formula (2) for practical application.

Rth = Rth(ch-c) + Rth(i) + Rth(c) + Rth(f) ································································ (2)

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Table 3 Thermal Resistance
Thermal resistance term Package
DPAK TO-220AB LDPAK TO-220FM TO-3P TO-3PFM TO-3PL
Rth(ch-c) (°C/W) Tj max − Tc (The Pch (W) ratings are listed in the
Rth(ch − c) =
Pch individual product catalogues.)
(Note 1)
Rth(c-a) (°C/W) 178 80 80 62.5 55 42 45
(Rth(i) + No insulating layer Silicon grease 0.3 to 0.6 0.3 to 0.5 0.3 to 0.5 0.4 to 0.6 0.1 to 0.2 0.3 to 0.5 0.1 to 0.2
Rth(c)) used used
(°C/W) Silicon grease 2.0 to 2.5 1.5 to 2.0 1.5 to 2.0 1.5 to 2.0 0.5 to 0.9 1.0 to 1.5 0.4 to 0.5
not used
Mica sheet Silicon grease — 2.0 to 2.5 — — 0.5 to 0.8 — 0.5 to 0.7
inserted. used
(t = 50 to 100 μm) Silicon grease — 4.0 to 6.0 — — 2.0 to 3.0 — 1.2 to 1.5
not used
Notes: 1. Reference values

2. Calculating the Channel Temperature, Tch

a. When a heat sink is used and the transistor case temperature is not known
Tch = Ta + PD • (Rth(ch-c) + Rth(i) + Rth(c) + Rth(f)) ················································ (3)

b. When a heat sink is used and the transistor case temperature is known (thermal equilibrium state)
Tch = Tc + PD • Rth(ch-c) ··················································································· (4)

c. When no heat sink is used (independent device)

Tch = Ta + PD • (Rth(ch-c) + Rth(c-a)) (5)

1) Rth(ch-c) is computed using formula (6) from the allowable channel power (Pch) rating listed in the product
catalog.
Tch max − Tc
Rth(ch − c) = ··················································································· (6)
Pch

<Example>
Since the Pch from the catalog is 120 W, the Rth(ch-c) for the 2SK1170 (TO-3P) is calculated as follows.
150 − 25
Rth(ch − c) = ≅ 1.04°C / W
120

2) When the drain power dissipation is a pulse state dissipation, the historical thermal resistance, Rth(ch-c)(t), is
used. In general, the time required for Rth(ch-c) to reach steady state (the thermal equilibrium state) is 1 to
10 seconds, while that for Rth(c-a) is on the order of a few minutes. Therefore, the temperature rise for
narrow width pulse power dissipations is limited to the vicinity of the channel. Pulse widths of less than 100
ms (one shot pulses) have essentially no effect on transistor thermal states and temperature increases.

<Example>
Consider the 2SK1170 (TO-3P). Derive the transient thermal resistance Rth(ch-c)(t)1 for a one shot pulse
with a pulse width (PW) of 10 μs, and the transient thermal resistance Rth(ch-c)(t)2 for continuous operation
with a 20% duty cycle and a PW of 10 µs.

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

Normalized Transient Thermal

1.0 D=1 Tc = 25°C

Resistance γs (t)
0.5

0.3
0.2
0.1
0.1 Rth (ch-c) (t) = γs (t) • Rth (ch-c)
0.05
Rth (ch-c) = 1.04°C/W
0.02
0.03 0.01 pulse PDM
1 sh
t
o D = PW
PW T T
0.01
10μ 100μ 1m 10m 100m 1 10
Pulse Width PW (s)

Figure 55 2SK1170 Transient Thermal Resistance Characteristics (from the separate catalog)

According to the transient thermal resistance characteristics listed in the separate catalog for the 2SK1170,
these thermal resistances have the following values.
Tch(ch-c)(t)1 = γs(t) • Rth(ch-c) = 0.015 × 1.04 = 0.0156°C/W
Tch(ch-c)(t)2 = γs(t) • Rth(ch-c) = 0.034 × 1.04 = 0.035°C/W

d. Channel Temperature Tch Calculation Example

1) Mounting and operating conditions
a) The chip used in the 2SK1170 (TO-3P)
b) ID = 8 A, PW = 10 μs, duty = 50% (f = 50 kHz)
Switching power P(tf) = 500 W (tf = 0.2 μs)
(Here we only consider the power during the falling period tf. Other losses are ignored.)
c) Heat sink thermal resistance Rth(f): 1°C/W (natural air cooling)
d) Ambient temperature Ta: 50°C atmosphere
e) Mounting method: Mica sheet and silicon grease

2) Method for calculating the channel temperature Tch

a) The total thermal resistance Rth is derived as follows by substituting the thermal resistances from table 6-
3 into formula (2).
Rth = Rth(ch-c) + Rth(i) + Rth(c) + Rth(f)
= 1.04 + 0.8 + 1
= 2.84°C/W
b) The power MOS FET power dissipation PD is derived by substituting the required values into formula (9).
1
PD = (t ON ⋅ ID2 ⋅ RDS(on) max⋅ α + P(t f ) ⋅ t f )
T
1
= (10 × 82 × 0.27 × 2.41 + 500 × 0.2)
20
= 25.8W
c) The channel temperature Tch is derived by substituting the Rth and PD values calculated above into
formula (3).
Tch = Ta + PD • Rth
= 50 + 25.8 × 2.84
≅ 123°C
Assuming that a power pulse PD(t) of 500 W is applied for a time (pulse width) of PW = 50 μs (one shot
pulse) in these operating conditions, the additional temperature increase ΔTch can be derived using the
transient thermal resistance Rth(ch-c) from figure 55 as follows.
ΔTch = ΔPD • Rth(ch-c)(t)
= (500 – 25.8) × (1.04 × 0.032)
≅ 15.8°C

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Therefore, the temperature will rise an addition 15.8°C, and become about 140°C.

3. Thermal Design Technique

a. This section describes thermal design for applications using the 2SK1170 (TO-3P) power MOS FET. Here, we
design for a Tch of 120°C or less under the mounting conditions described in items (1) through (4) below.
(1) Operating conditions: ID = 8 A, 10 A, PW = 10 μs (tON), duty = 50% (f = 50 kHz)
Switching loss P(tf) = 500 W (tf = 0.2 μs)
(Here we only consider the power during the falling period tf. Other losses are ignored.)
(2) Heat sinks used: Here we investigate three different heat sinks, with thermal resistances Rth(f) of 0.5°C/W,
1.0°C/W, and 1.5°C/W.
(3) Mounting method: Mica sheet and silicon grease
(4) Ambient temperature: Ta = 50°C

b. Allowable power dissipation and power MOS FET power dissipation characteristics due to the total thermal
resistance Rth when a heat sink is used.
(1) The power MOS FET channel temperature Tch is given by formula (7).
Tch = Ta + ΔTch
= Ta + PD • Rth ·························································································· (7)
Tch − Ta
∴ PD = ································································································ (8)
Rth
Formula (8) can be used to derive the allowable power dissipation line (Tch dependency) for the total
thermal resistance Rth for the 2SK1170 under the mounting conditions specified above at Ta = 50°C for Tch
values up to a maximum of about 150°C.
(2) Next we derive the power MOS FET power dissipation characteristic (Tch dependency)
Since the on resistance RDS(on) has a positive temperature dependency, the power dissipation PD of a power
MOS FET increases with increases in the channel temperature Tch.
The power dissipation PD can be derived using formula (9).
1
PD = (ton ⋅ ID 2 ⋅ RDS(on)max ⋅ α + P(t f ) ⋅ t f ) ··································································· (9)
T
Where a is the temperature coefficient for Tch(n) with respect to 25°C.
Figure 56 shows the relationship between channel temperature (Tch) and power dissipation (PD) as derived
from formulas (8) and (9).

⎞ Rth == Rth(ch-c) + Rth(i) + Rth(c) + Rth(f) ⎞

⎞
50 ⎞ 1.04 + 0.8 + 0.5
= 2.34°C/W ( I ). Rth (f) = 0.5°C/W
(II ). Rth (f) = 1°C/W (I)
(III). Rth (f) = 1.5°C/W
40 (II )
Power MOS FET power
Power Dissipation PD (W)

dissipation (PD) characteristics The object is to design B

for Tch ≤ 120°C (III)
30 PD = On resistance loss
+ Switching loss (formula (9))
E
D
C
20
ID = 10 A

ID = 8 A
10
A The allowable power ⎞ ΔTch ⎞⎞
dissipation characteristics ⎞PD =
Rth
for three different heat sink.
0 50 100 (120) 150

Channel Temperatuer Tch (°C)

Figure 56 Channel Temperature (Tch) vs. Power Dissipation (PD) Relationship

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
Table 4 Power MOS FET Power Dissipation (PD) Calculations (for the 2SK1170)
Tch (°C)
Item
25 40 60 80 100 120 140 150
RDS(on) temperature coefficient α, with respect to
1.0 1.09 1.27 1.5 1.73 2.0 2.27 2.41
Tch = 25°C
On resistance power dissipation PON I =8A 8.64 9.4 11.0 13.0 14.9 17.3 19.6 20.8
D
t
PON = ON ⋅ ID 2 ⋅ RDS(on) max ⋅ α
T ID = 10 A 13.5 14.7 17.1 20.3 23.4 27 30.6 32.5
Switching loss tf
Ps = ⋅ P(t f ) 5 5 5 5 5 5 5 5
T
Total power dissipation ID = 8 A 13.6 14.4 16.0 18.0 19.9 22.3 24.6 25.8
PD = PON + PS ID = 10 A 18.5 19.7 22.1 25.5 28.4 32.0 35.6 37.5
Notes: 1. For simplification, the same values of PS are used for both values of ID, 8 A and 10 A.

c. The following can be said based on the relationship between the channel temperature and the power dissipation
shown in figure 6-56.
1) The point marked A is the point where the ambient temperature Ta is 50°C. That is, since the power
dissipation is “zero”, the values of Tch and Ta will be identical, i.e., 50°C.
2) The points B, C, D, and E are intersections between the total thermal resistance characteristics for the
different heat sinks and the power MOS FET power dissipation characteristics. They indicate the channel
temperature (Tch) under a state of thermal equilibrium.
Therefore, the following techniques and methods should be discussed as thermal designs and operating
conditions to fulfill the condition that Ta be less than or equal to 120°C.
(a) The heat sink used must meet either specification (I) or (II). However, the ID must be 8 A.
(b) Consider the operating conditions with an ID of 10 A. Since there is no intersection between the total
thermal resistance and the power dissipation curves for heat sinks II and III, this means that these
conditions can result in thermal runaway leading to destruction of the device. Also, since the Tch under
thermal equilibrium conditions for the type I heat sink is about 130°C, although this heat sink meets the
device rating (Tch max ≤ 150°C), it does not meet the design target of a Tch less than or equal to 120°C.
(c) Therefore, to operate at conditions up to an ID of 10 A and to fulfill the design target (Tch ≤ 120°C) either
the heat dissipation conditions must be improved, or a device with a one rank smaller on resistance must
be used.
30
PD = 1 (t ON • ID2 • RDS (on) max • α + P (tf ) át f )
T
Power Dissipation PD (W)

Rth (f) 1
30°C
⎞
⎞
Although strictly, the off time VDS and IDSS should
be added, they are ignored here since they are ⎞
⎞ Ta=
20
relatively small. D 0°C
=3
Ta 0°C
=5
Ta
Power MOS FET C
power dissipation PD Rth (f) 2
10 B
MOS A

MOS B
A Tch-Ta
PD =
MOS C Rth (ch-c) + Rth (i) + Rth (c) + Rth (f)

0 (30) 50 100 150 200

Channel Temperatuer Tch (°C)

Figure 57 Channel Temperature (Tch) vs. Power Dissipation (PD) Relationship

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics
d. This section describes examples based on figure 57.
1) When MOS A or MOS B is used with the heat sink with thermal resistance Rth(f)1:
a) Since there is no intersection between the total thermal resistance and power dissipation curves when
MOS A is used, there is no thermal equilibrium state, and thermal runaway can lead to destruction of the
device.
b) When MOS B is used, although the channel temperature rises to the thermal equilibrium point at C (about
110°C) when power is applied, there is still significant danger of thermal runaway. This is because the
influence of an unstable external environment (an unstable ambient temperature Ta or another heat source
in the vicinity) can cause the channel temperature Tch to reach point D (about 150°C), where thermal
runaway can occur.
2) Using the heat sink with thermal resistance Rth(f)2 and operating at ambient temperatures of 30 and 50°C.
a) When operating at a Ta of 30°C the system will be in thermal equilibrium at point A (Tch = 83°C) and
there will be no problems.
b) When operating at a Ta of 50°C the system will be in thermal equilibrium at point B (Tch = 154°C). This
temperature exceeds the rated allowable channel temperature (150°C). Although this will not
immediately destroy the device, it will reduce its life and make the various failure modes more likely to
occur.

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Aug 18, 2014
Power MOS FET Absolute Maximum Ratings and Electrical Characteristics

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Aug 18, 2014
Revision History
Description
Rev. Date Page Summary
1.00 Jul.18.04 ̵ First edition issued
2.00 Dec.25.08 19 Amended
21 Amended
3.00 Aug. 18, 2014 ̵ The format was changed into the newest thing.
The document number was changed.

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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES http://www.renesas.com

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Renesas Electronics America Inc.

2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Ku, Seoul, 135-920, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141

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