Lectures 2: Review of Pipelines

and Caches

Prof. David A. Patterson

Computer Science 252
Fall 1996

DAP.F96 1
 Review, #1
• Designing to Last through Trends
Capacity Speed
Logic 2x in 3 years 2x in 3 years
DRAM 4x in 3 years 1.4x in 10 years
Disk 4x in 3 years 1.4x in 10 years
• Time to run the task
– Execution time, response time, latency
• Tasks per day, hour, week, sec, ns, …
– Throughput, bandwidth
• “X is n times faster than Y” means
ExTime(Y) Performance(X)
--------- = --------------
ExTime(X) Performance(Y)

DAP.F96 2
 Review, #2
• Amdahl’s Law:
1
ExTimeold
Speedupoverall = =
(1 - Fractionenhanced) + Fractionenhanced
ExTimenew
• CPI Law: Speedupenhanced

CPU time = Seconds = Instructions x Cycles x Seconds

Program Program Instruction Cycle

• Execution time is the REAL measure of computer

performance!
• Good products created when have:
– Good benchmarks
– Good ways to summarize performance
• Die Cost goes roughly with die area4
DAP.F96 3
 Review, #3:
Price vs. Cost
100%
80% Average Discount

60% Gross Margin

40% Direct Costs

20% Component Costs

0%
Mini W/S PC

5 4.7
3.8
4 3.5 Average Discount

3 2.5 Gross Margin

2 1.8 Direct Costs

1.5
1 Component Costs

0
Mini W/S PC DAP.F96 4
 Pipelining: Its Natural!

• Laundry Example
• Ann, Brian, Cathy, Dave A B C D
each have one load of clothes
to wash, dry, and fold
• Washer takes 30 minutes

• Dryer takes 40 minutes

• “Folder” takes 20 minutes

DAP.F96 5
 Sequential Laundry
6 PM 7 8 9 10 11 Midnight
Time

30 40 20 30 40 20 30 40 20 30 40 20
T
a A
s
k
B
O
r
d C
e
r D
• Sequential laundry takes 6 hours for 4 loads
• If they learned pipelining, how long would laundry take?
DAP.F96 6
 Pipelined Laundry
Start work ASAP
6 PM 7 8 9 10 11 Midnight
Time

30 40 40 40 40 20
T
a A
s
k
B
O
r
d C
e
r D

• Pipelined laundry takes 3.5 hours for 4 loads DAP.F96 7

 Pipelining Lessons
6 PM • Pipelining doesn’t help
7 8 9 latency of single task, it
Time helps throughput of
entire workload
T
a 30 40 40 40 40 20 • Pipeline rate limited by
s slowest pipeline stage
k A • Multiple tasks operating
simultaneously
O • Potential speedup =
r B Number pipe stages
d
e • Unbalanced lengths of
r C pipe stages reduces
speedup
D • Time to “fill” pipeline and
time to “drain” it reduces
speedup DAP.F96 8
 Computer Pipelines

• Execute billions of instructions, so

throughout is what matters
• DLX desirable features: all instructions same
length, registers located in same place in
instruction format, memory operands only in
loads or stores

DAP.F96 9
 5 Steps of DLX Datapath
Figure 3.1, Page 130

Instruction Instr. Decode Execute Memory Write

Fetch Reg. Fetch Addr. Calc Access Back

IR
L
M
D

DAP.F96 10
 Pipelined DLX Datapath
Figure 3.4, page 137

Instruction
Fetch Instr. Decode Execute
Reg. Fetch Addr. Calc. Write
Back
Memory
Access

• Data stationary control

DAP.F96 11
– local decode for each instruction phase / pipeline stage
 Visualizing Pipelining
Figure 3.3, Page 133
Time (clock cycles)

I
n
s
t
r.

O
r
d
e
r

DAP.F96 12
 Its Not That Easy for
Computers
• Limits to pipelining: Hazards prevent next
instruction from executing during its designated
clock cycle
– Structural hazards: HW cannot support this combination of
instructions (single person to fold and put clothes away)
– Data hazards: Instruction depends on result of prior
instruction still in the pipeline (missing sock)
– Control hazards: Pipelining of branches & other instructions
that change the PC (football uniform analogy)
• Common solution is to stall the pipeline until the
hazard is resolved, inserting one or more
“bubbles” in the pipeline

DAP.F96 13
One Memory Port/Structural Hazards
Figure 3.6, Page 142
Time (clock cycles)

Load
I
n
s
t Instr 1
r.

O Instr 2
r
d
e Instr 3
r

Instr 4
DAP.F96 14
 One Memory Port/Structural Hazards
Figure 3.7, Page 143
Time (clock cycles)

Load
I
n
s
t Instr 1
r.

O Instr 2
r
d
e stall
r

Instr 3
DAP.F96 15
 Speed Up Equation for
Pipelining
CPIpipelined = Ideal CPI + Pipeline stall clock cycles per instr

Speedup = Ideal CPI x Pipeline depth Clock Cycleunpipelined

x
Ideal CPI + Pipeline stall CPI Clock Cyclepipelined

Speedup = Pipeline depth Clock Cycleunpipelined

x
1 + Pipeline stall CPI Clock Cyclepipelined

DAP.F96 16
 Example: Dual-port vs. Single-port
• Machine A: Dual ported memory
• Machine B: Single ported memory, but its pipelined
implementation has a 1.05 times faster clock rate
• Ideal CPI = 1 for both
• Loads are 40% of instructions executed
SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe)
= Pipeline Depth
SpeedUpB = Pipeline Depth/(1 + 0.4 x 1)
x (clockunpipe/(clockunpipe / 1.05)
= (Pipeline Depth/1.4) x 1.05
= 0.75 x Pipeline Depth
SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33
• Machine A is 1.33 times faster DAP.F96 17
 Data Hazard on R1
Figure 3.9, page 147
Time (clock cycles)
IF ID/RF EX MEM WB

I
n
add r1,r2,r3
s
t
r. sub r4,r1,r3
O
r and r6,r1,r7
d
e
r or r8,r1,r9

xor r10,r1,r11 DAP.F96 18

 Three Generic Data Hazards
InstrI followed by InstrJ

• Read After Write (RAW)

InstrJ tries to read operand before InstrI writes it

DAP.F96 19
 Three Generic Data Hazards
InstrI followed by InstrJ

• Write After Read (WAR)

InstrJ tries to write operand before InstrI reads it

• Can’t happen in DLX 5 stage pipeline because:

– All instructions take 5 stages,
– Reads are always in stage 2, and
– Writes are always in stage 5

DAP.F96 20
 Three Generic Data Hazards
InstrI followed by InstrJ

• Write After Write (WAW)

InstrJ tries to write operand before InstrI writes it
– Leaves wrong result ( InstrI not InstrJ)

• Can’t happen in DLX 5 stage pipeline because:

– All instructions take 5 stages, and
– Writes are always in stage 5

• Will see WAR and WAW in later more complicated

pipes
DAP.F96 21
 CS 252 Administrivia
• Students with too varied background?
– In past, CS grad students took written prelim exams on
undergraduate material in hardware, software, and theory
– Prelims were dropped => some unprepared for CS 252?
• In class exam on Wednesday September 3
– Bring up to 2 sheets of paper with noteson both sides
– Doesn’t affect grade, only admission into class
– 2 grades: Admitted or audit/take CS 152 1st (same time in 306)
– Improve your experience if recapture common background
• Review: Chapters 1- 3, CS 152 home page, maybe
“Computer Organization and Design (COD)”
– Chapters 1 to 8 of COD if never took prerequisite
– If did take a class, be sure COD Chapters 2, 6, 7 are familiar
– Copies in Bechtel Library on 2-hour reserve DAP.F96 22
 Forwarding to Avoid Data Hazard
Figure 3.10, Page 149
Time (clock cycles)

I
n
s
add r1,r2,r3
t
r.
sub r4,r1,r3
O
r
d and r6,r1,r7
e
r
or r8,r1,r9

xor r10,r1,r11
DAP.F96 23
HW Change for Forwarding
Figure 3.20, Page 161

DAP.F96 24
 Data Hazard Even with Forwarding
Figure 3.12, Page 153

Time (clock cycles)

I lw r1, 0(r2)
n
s
t
r. sub r4,r1,r6
O
r and r6,r1,r7
d
e
r
or r8,r1,r9
DAP.F96 25
 Data Hazard Even with Forwarding
Figure 3.13, Page 154
Time (clock cycles)
I
n
s lw r1, 0(r2)
t
r.

O
sub r4,r1,r6
r
d
e and r6,r1,r7
r

or r8,r1,r9
DAP.F96 26
 Software Scheduling to Avoid
Load Hazards
Try producing fast code for
a = b + c;
d = e – f;
assuming a, b, c, d ,e, and f in memory.
Slow code: Fast code:
LW Rb,b LW Rb,b
LW Rc,c LW Rc,c
ADD Ra,Rb,Rc LW Re,e
SW a,Ra ADD Ra,Rb,Rc
LW Re,e LW Rf,f
LW Rf,f SW a,Ra
SUB Rd,Re,Rf SUB Rd,Re,Rf
SW d,Rd SW d,Rd DAP.F96 27
Control Hazard on Branches
Three Stage Stall

DAP.F96 28
 Branch Stall Impact

• If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9!

• Two part solution:
– Determine branch taken or not sooner, AND
– Compute taken branch address earlier
• DLX branch tests if register = 0 or ≠ 0
• DLX Solution:
– Move Zero test to ID/RF stage
– Adder to calculate new PC in ID/RF stage
– 1 clock cycle penalty for branch versus 3

DAP.F96 29
 Pipelined DLX Datapath
Figure 3.22, page 163

Instruction Instr. Decode Execute Memory Write

Fetch Reg. Fetch Addr. Calc. Access Back
This is the correct 1 cycle
latency implementation!

DAP.F96 30
Four Branch Hazard Alternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken
– Execute successor instructions in sequence
– “Squash” instructions in pipeline if branch actually taken
– Advantage of late pipeline state update
– 47% DLX branches not taken on average
– PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken
– 53% DLX branches taken on average
– But haven’t calculated branch target address in DLX
» DLX still incurs 1 cycle branch penalty
» Other machines: branch target known before outcome

DAP.F96 31
Four Branch Hazard Alternatives

#4: Delayed Branch

– Define branch to take place AFTER a following instruction

branch instruction
sequential successor1
sequential successor2
........ Branch delay of length n
sequential successorn
branch target if taken

– 1 slot delay allows proper decision and branch target

address in 5 stage pipeline
– DLX uses this

DAP.F96 32
 Delayed Branch

• Where to get instructions to fill branch delay slot?

– Before branch instruction
– From the target address: only valuable when branch taken
– From fall through: only valuable when branch not taken
– Cancelling branches allow more slots to be filled

• Compiler effectiveness for single branch delay slot:

– Fills about 60% of branch delay slots
– About 80% of instructions executed in branch delay slots useful
in computation
– About 50% (60% x 80%) of slots usefully filled

DAP.F96 33
 Evaluating Branch Alternatives
Pipeline speedup = Pipeline depth
1 + Branch frequency×Branch penalty

Scheduling Branch CPI speedup v. speedup v.

scheme penalty unpipelined stall
Stall pipeline 3 1.42 3.5 1.0
Predict taken 1 1.14 4.4 1.26
Predict not taken 1 1.09 4.5 1.29
Delayed branch 0.5 1.07 4.6 1.31

Conditional & Unconditional = 14%, 65% change PC

DAP.F96 34
 Pipelining Summary

• Just overlap tasks, and easy if tasks are independent

• Speed Up ≤ Pipeline Depth; if ideal CPI is 1, then:
Pipeline Depth Clock Cycle Unpipelined
Speedup = X
1 + Pipeline stall CPI Clock Cycle Pipelined

• Hazards limit performance on computers:

– Structural: need more HW resources
– Data (RAW,WAR,WAW): need forwarding, compiler scheduling
– Control: delayed branch, prediction

DAP.F96 35
 Levels of the Memory Hierarchy
Capacity Upper Level
Access Time Staging
Cost Xfer Unit faster
CPU Registers
100s Bytes Registers
<10s ns
prog./compiler
Instr. Operands 1-8 bytes
Cache
K Bytes
10-100 ns
Cache
$.01-.001/bit cache cntl
Blocks 8-128 bytes
Main Memory
M Bytes Memory
100ns-1us
$.01-.001 OS
Pages 512-4K bytes
Disk
G Bytes
ms-3
Disk
-4
10 - 10 cents user/operator
Files Mbytes
Tape Larger
infinite
sec-min Tape Lower Level
10 -6
DAP.F96 36
 The Principle of Locality

• The Principle of Locality:

– Program access a relatively small portion of the address space at
any instant of time.
• Two Different Types of Locality:
– Temporal Locality (Locality in Time): If an item is referenced, it will
tend to be referenced again soon.
– Spatial Locality (Locality in Space): If an item is referenced, items
whose addresses are close by tend to be referenced soon.

DAP.F96 37
 Memory Hierarchy: Terminology
• Hit: data appears in some block in the upper level
(example: Block X)
– Hit Rate: the fraction of memory access found in the upper level
– Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
• Miss: data needs to be retrieve from a block in the
lower level (Block Y)
– Miss Rate = 1 - (Hit Rate)
– Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
• Hit Time << Miss Penalty Lower Level
To Processor Upper Level Memory
Memory
Blk X
From Processor Blk Y

DAP.F96 38
 Cache Measures

• Hit rate: fraction found in that level

– So high that usually talk about Miss rate
– Miss rate fallacy: as MIPS to CPU performance,
miss rate to average memory access time in memory
• Average memory-access time
= Hit time + Miss rate x Miss penalty (ns
or clocks)
• Miss penalty: time to replace a block from
lower level, including time to replace in CPU
– access time: time to lower level
= f(lower level latency)
– transfer time: time to transfer block
=f(BW upper & lower) DAP.F96 39
 Simplest Cache: Direct Mapped
Memory Address Memory
0
4 Byte Direct Mapped Cache
1
Cache Index
2
0
3
1
4
2
5
3
6
7
• Location 0 can be occupied by
8 data from:
9 – Memory location 0, 4, 8, ... etc.
A – In general: any memory location
B whose 2 LSBs of the address are 0s
C – Address<1:0> => cache index
D • Which one should we place in
E the cache?
F
• How can we tell which oneDAP.F96
is in40
the cache?
1 KB Direct Mapped Cache, 32B blocks
• For a 2 ** N byte cache:
– The uppermost (32 - N) bits are always the Cache Tag
– The lowest M bits are the Byte Select (Block Size = 2 ** M)

31 9 4 0
Cache Tag Example: 0x50 Cache Index Byte Select
Ex: 0x01 Ex: 0x00
Stored as part
of the cache “state”

Valid Bit Cache Tag Cache Data

: :
Byte 31 Byte 1 Byte 0 0
0x50 Byte 63 Byte 33 Byte 32 1
2
3

: : :

:
Byte 1023 Byte 992 31
DAP.F96 41
 Two-way Set Associative Cache
• N-way set associative: N entries for each Cache Index
– N direct mapped caches operates in parallel
• Example: Two-way set associative cache
– Cache Index selects a “set” from the cache
– The two tags in the set are compared in parallel
– Data is selected based on the tag result
Cache Index
Valid Cache Tag Cache Data Cache Data Cache Tag Valid
Cache Block 0 Cache Block 0

: : : : : :

Adr Tag
Compare Sel1 1 Mux 0 Sel0 Compare

OR
Cache Block DAP.F96 42
Hit
 Disadvantage of Set Associative Cache
• N-way Set Associative Cache v. Direct Mapped Cache:
– N comparators vs. 1
– Extra MUX delay for the data
– Data comes AFTER Hit/Miss
• In a direct mapped cache, Cache Block is available
BEFORE Hit/Miss:
– Possible to assume a hit and continue. Recover later if miss.
Cache Index
Valid Cache Tag Cache Data Cache Data Cache Tag Valid
Cache Block 0 Cache Block 0

: : : : : :

Adr Tag
Compare Sel1 1 Mux 0 Sel0 Compare

OR
DAP.F96 43
Cache Block
Hit
 4 Questions for Memory
Hierarchy
• Q1: Where can a block be placed in the upper
level? (Block placement)
• Q2: How is a block found if it is in the upper
level?
(Block identification)
• Q3: Which block should be replaced on a
miss?
(Block replacement)
• Q4: What happens on a write?
(Write strategy)

DAP.F96 44
 Q1: Where can a block be
placed in the upper level?
• Block 12 placed in 8 block cache:
– Fully associative, direct mapped, 2-way set associative
– S.A. Mapping = Block Number Modulo Number Sets

DAP.F96 45
Q2: How is a block found if it is in
the upper level?

• Tag on each block

– No need to check index or block offset
• Increasing associativity shrinks index,
expands tag

DAP.F96 46
Q3: Which block should be replaced
on a miss?
• Easy for Direct Mapped
• Set Associative or Fully Associative:
– Random
– LRU (Least Recently Used)
Associativity: 2-way 4-way 8-way
Size LRURandom LRURandom LRURandom
16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%
64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%
256 KB 1.15% 1.17%1.13% 1.13% 1.12% 1.12%

DAP.F96 47
 Q4: What happens on a write?

• Write through—The information is written to

both the block in the cache and to the block
in the lower-level memory.
• Write back—The information is written only to
the block in the cache. The modified cache
block is written to main memory only when it
is replaced.
– is block clean or dirty?
• Pros and Cons of each?
– WT: read misses cannot result in writes
– WB: no writes of repeated writes
• WT always combined with write buffers so
that don’t wait for lower level memory DAP.F96 48
 Write Buffer for Write Through
Cache
Processor DRAM

Write Buffer

• A Write Buffer is needed between the Cache and

Memory
– Processor: writes data into the cache and the write buffer
– Memory controller: write contents of the buffer to memory
• Write buffer is just a FIFO:
– Typical number of entries: 4
– Works fine if: Store frequency (w.r.t. time) << 1 / DRAM write cycle
• Memory system designer’s nightmare:
– Store frequency (w.r.t. time) -> 1 / DRAM write cycle
– Write buffer saturation
DAP.F96 49
 5 minute Class Break

• 80 minutes straight is too long for me to

lecture (12:40:00 – 2:00:00):
– ≈ 1 minute: review last time & motivate this lecture
– ≈ 20 minute lecture
– ≈ 3 minutes: discuss class manangement
– ≈ 25 minutes: lecture
– 5 minutes: break
– ≈25 minutes: lecture
– ≈1 minute: summary of today’s important topics

DAP.F96 50
 A Modern Memory Hierarchy
• By taking advantage of the principle of locality:
– Present the user with as much memory as is available in the
cheapest technology.
– Provide access at the speed offered by the fastest technology.

Processor

Control Tertiary
Secondary Storage
Storage
Second Main (Disk)
(Disk)
On-Chip
Registers

Level Memory
Cache

Datapath Cache (DRAM)

(SRAM)

Speed (ns): 1s 10s 100s 10,000,000s 10,000,000,000s

Size (bytes): 100s (10s ms) (10s sec)
Ks Ms Gs Ts
DAP.F96 51
 Basic Issues in VM System Design
size of information blocks that are transferred from
secondary to main storage (M)

block of information brought into M, and M is full, then some region

of M must be released to make room for the new block -->
replacement policy

which region of M is to hold the new block --> placement policy

missing item fetched from secondary memory only on the occurrence

of a fault --> demand load policy
mem disk
cache

reg
pages
frame

Paging Organization

virtual and physical address space partitioned into blocks of equal size

page frames

pages DAP.F96 52
 Address Map
V = {0, 1, . . . , n - 1} virtual address space n>m
M = {0, 1, . . . , m - 1} physical address space

MAP: V --> M U {0} address mapping function

MAP(a) = a' if data at virtual address a is present in physical
address a' and a' in M

= 0 if data at virtual address a is not present in M

a missing item fault

Name Space V
fault
handler
Processor
0
Addr Trans Main Secondary
a Mechanism Memory Memory
a'

physical address OS performs

this transfer
DAP.F96 53
 Paging Organization
V.A.
P.A. unit of
0 frame 0 1K 0 page 0 1K mapping
1024 1 1K Addr 1024 1 1K
Trans
MAP also unit of
7168 7 1K transfer from
virtual to
Physical physical
Memory
31744 31 1K memory
Virtual Memory
Address Mapping
10
VA page no. disp

Page Table
Page Table
Base Reg Access
V PA + actually, concatenation
index Rights
is more likely
into
page
table table located physical
in physical memory
memory DAP.F96 54
address
 Virtual Address and a Cache
VA PA miss
Trans- Main
CPU Cache
lation Memory
hit
data

It takes an extra memory access to translate VA to PA

This makes cache access very expensive, and this is the "innermost
loop" that you want to go as fast as possible

ASIDE: Why access cache with PA at all? VA caches have a problem!

synonym / alias problem: two different virtual addresses map to same
physical address => two different cache entries holding data for
the same physical address!

for update: must update all cache entries with same

physical address or memory becomes inconsistent

determining this requires significant hardware, essentially an

associative lookup on the physical address tags to see if you
have multiple hits; or

software enforced alias boundary: same lsb of VA &PA > cache size
DAP.F96 55
 TLBs
A way to speed up translation is to use a special cache of recently
used page table entries -- this has many names, but the most
frequently used is Translation Lookaside Buffer or TLB

Virtual Address Physical Address Dirty Ref Valid Access

TLB access time comparable to cache access time

(much less than main memory access time)

DAP.F96 56
 Translation Look-Aside Buffers
Just like any other cache, the TLB can be organized as fully associative,
set associative, or direct mapped

TLBs are usually small, typically not more than 128 - 256 entries even on
high end machines. This permits fully associative
lookup on these machines. Most mid-range machines use small
n-way set associative organizations.

hit
VA PA miss
TLB Main
CPU Cache
Lookup Memory

Translation miss hit

with a TLB
Trans-
lation
data
DAP.F96 57
1/2 t t 20 t
 Reducing Translation Time

Machines with TLBs go one step further to reduce #

cycles/cache access

They overlap the cache access with the TLB access

Works because high order bits of the VA are used to

look in the TLB
while low order bits are used as index into cache

DAP.F96 58
 Overlapped Cache & TLB Access

assoc index
32 TLB Cache 1K
lookup

4 bytes
10 2
00

PA Hit/ Data
20 12 PA Hit/
Miss Miss
page # disp

IF cache hit AND (cache tag = PA) then deliver data to CPU
ELSE IF cache miss and TLB hit THEN
access memory with the PA from the TLB
ELSE do standard VA translation

DAP.F96 59
Problems With Overlapped TLB Access
Overlapped access only works as long as the address bits used to
index into the cache do not change as the result of VA translation

This usually limits things to small caches, large page sizes, or high
n-way set associative caches if you want a large cache

Example: suppose everything the same except that the cache is

increased to 8 K bytes instead of 4 K:

11 2
cache
index 00
This bit is changed
by VA translation, but
20 12 is needed for cache
virt page # disp lookup
Solutions:
go to 8K byte page sizes;
go to 2 way set associative cache; or
SW guarantee VA[13]=PA[13]

1K 2 way set assoc cache

10
4 4 DAP.F96 60
 Summary #1:

• The Principle of Locality:

– Program access a relatively small portion of the address space at
any instant of time.
» Temporal Locality: Locality in Time
» Spatial Locality: Locality in Space
• Three Major Categories of Cache Misses:
– Compulsory Misses: sad facts of life. Example: cold start misses.
– Capacity Misses: increase cache size
– Conflict Misses: increase cache size and/or associativity.
Nightmare Scenario: ping pong effect!
• Write Policy:
– Write Through: need a write buffer. Nightmare: WB saturation
– Write Back: control can be complex

DAP.F96 61
 Summary #2: TLB, Virtual Memory
• Caches, TLBs, Virtual Memory all understood by
examining how they deal with 4 questions: 1) Where
can block be placed? 2) How is block found? 3) What
block is repalced on miss? 4) How are writes
handled?
• Page tables map virtual address to physical address
• TLBs are important for fast translation
• TLB misses are significant in processor
performance: (funny times, as most systems can’t
access all of 2nd level cache without TLB misses!)

DAP.F96 62
 Summary #3: Memory Hierachy
• VIrtual memory was controversial at the time:
can SW automatically manage 64KB across many
programs?
– 1000X DRAM growth removed the controversy
• Today VM allows many processes to share single
memory without having to swap all processes to
disk; VM protection is more important than memory
hierarchy
• Today CPU time is a function of (ops, cache misses)
vs. just f(ops):
What does this mean to Compilers, Data structures,
Algorithms?

DAP.F96 63