A B C D E

1 1

2
Compal Confidential 2

UMA M/B Schematics Document

Haswell with DDRIII + Lynx Point PCH

2012-10-03
3 3

LA-9642P
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 1 of 60
A B C D E
 A B C D E

Compal confidential
File Name :

1
Shark Bay 1

Intel Memory Bus 204pin DDRIII-SO-DIMM X2

　
Processor Dual Channel BANK 0, 1, 2 page 10,11

Haswell DDR3L
DDR3L 　1600MHz
1333MHz

LVDS Conn. LVDS Translator rPGA946

RTD2132S(Single)
page 28
page 27
37.5mm x 37.5mm
HDMI Conn. page 5,~9
page 30

FDI *2 DMI2 *4
2.7GT/s 5GT/s
2 2

Left USB3.0 x2 Right USB2.0 Int. Camera

USB30 x2 USB30 Port 0,1 USB20 Port 9 USB20 Port 3
page 28 page 28 page 28

USB20 x6 Touch Screen Card Reader

Realtek RTS5170
USB20 Port 2
USB20 Port 11
page 28
CRT Conn. Intel
page 29
PCH
LAN Lynx Point SATA Gen3 HDD Conn.
RJ45 Conn. Atheros PCIe x1 SATA Port 4
page 28 AR8162/QCA8172(10/100) page 28
page 28
FCBGA 695Balls
20mm x 20mm SATA ODD Conn.
SATA Port 5
page 28
3 PCIe Mini Card 3

WiMax PCIe x1
USB20 Port 10
page 28 Audio Codec
AZALIA CONEXANT
PCIe Mini Card USB20 x1 CX20757
page 28
WLAN
PCIe Port 0
page 28
Sub-borad
Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks
page 28 page 28
HP & MIC
page 28
SPI ROM EC
15" ODD/B 2MB + 4MB ENE KB9012
LSXXXP page 28 page 28
page 28
14"
Power/B LED/B
4
LSXXXP 4
LSXXXP
page 28 page 28
Thermal Sensor Touch Pad Int. KBD
page 28 page 28 page 28
USB/B CR/B
LSXXXP
LSXXXP Security Classification Compal Secret Data Compal Electronics, Inc.
page 28 page 28
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 2 of 60
A B C D E
 A B C D E

SIGNAL
Voltage Rails BOARD ID Table STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS
0 0.1 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1
power 2 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane
3
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.35V +VCC_CORE

4
5 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW
6
+1.5VS
7 Vcc 3.3V +/- 5% Board ID / SKU ID Table for AD channel
State +0.675VS
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Porject Phase
+1.05VS
G-series
0 0 0 V 0 V 0 V MP
G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
Y-series
4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
Y-series
S0
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
O O O O 6 200K +/- 5% 1.935 V 2.200 V 2.341 V Y-series
PVT
Y-series
7 NC 2.500 V 3.300 V 3.300 V MP
USB Port Table
S3
O O O X 3 External
USB 2.0 Port BOM Structure Table
2
USB Port 2

S5 S4/AC BTO Item BOM Structure

O O X X 0 Left USB3.0
UHCI0
S5 S4/ Battery only
1 Left USB3.0
O X X X 2 Touch screen
UHCI1
S5 S4/AC & Battery
3 Camera
X X X X EHCI1
don't exist 4
UHCI2 HDMI HDMI@
Address 5
EC SM Bus1 address EC SM Bus2 address 6
UHCI3
7
Device Device Address
8
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb UHCI4 Connector ME@
9 Right USB2.0
45 LEVEL 45@
10 WLAN
PCH SM Bus address EHCI2 UHCI5 10/100 LAN
11 Card reader
12
Device Address UHCI6 LAN LDO Mode LDO@
DDR DIMM0
13
1001 000Xb LAN Switch mode SWR@
DDR DIMM2 1001 010Xb Cameara CMOS@
3 3

For QIWG5 (14") 14@

NV-GPU SM Bus address For QIWG6 (15") 15@
Unpop @
Device Address

Internal thermal sensor 1001 111Xb (0x9E)

SMBUS Control Table

Thermal
WLAN Sensor
SOURCE VGA BATT KB9012 SODIMM WWAN PCH RTD2132
SMB_EC_CK1
SMB_EC_DA1
KB9012
+3VALW
X +3VALW
V X X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB9012
+3VALW
X X X X X X V
+3VS
V
+3VS
SMBCLK
X X X V V X X
4 4

SMBDATA
PCH
+3VALW +3VS +3VS X
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X
Compal Electronics, Inc.
V X V X X V X V
Compal Secret Data
SML1CLK
Security Classification
PCH Issued Date 2011/06/15 2012/07/11 Title
SML1DATA +3VS +3VS +3VS +3VS
Deciphered Date
+3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 3 of 60
A B C D E
 5 4 3 2 1

ZZZ1

+VCOMP_OUT

PEG_RCOMP 2 1
24.9_0402_1% R1
D D
PCB LA9641
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.

Haswell rPGA EDS

JCPU1A

E23 PEG_RCOMP
PEG_RCOMP M29
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28
<14> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
<14> DMI_CRX_PTX_N1 DMI_CRX_PTX_N1 C21 M31
DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30
<14> DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
<14> DMI_CRX_PTX_N3 DMI_CRX_PTX_N3 A21 M33
DMI_RXN_3 PEG_RXN_4 L32
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35
<14> DMI_CRX_PTX_P0

PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34
<14> DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
<14> DMI_CRX_PTX_P2 DMI_CRX_PTX_P2 B20 E29
DMI_CRX_PTX_P3 A20 DMI_RXP_2 PEG_RXN_8 D28
<14> DMI_CRX_PTX_P3

DMI
DMI_RXP_3 PEG_RXN_9 E31
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30
<14> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
DMI_CTX_PRX_N1 C17 E35
<14> DMI_CTX_PRX_N1 DMI_TXN_1 PEG_RXN_12
DMI_CTX_PRX_N2 B17 D34
<14> DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
DMI_CTX_PRX_N3 A17 E33
<14> DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29
<14> DMI_CTX_PRX_P0 DMI_TXP_0 PEG_RXP_0
C DMI_CTX_PRX_P1 C18 L28 C
<14> DMI_CTX_PRX_P1 DMI_TXP_1 PEG_RXP_1
DMI_CTX_PRX_P2 B18 L31
<14> DMI_CTX_PRX_P2 DMI_TXP_2 PEG_RXP_2
DMI_CTX_PRX_P3 A18 K30
<14> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33
PEG_RXP_4 K32
PEG_RXP_5 L35
PEG_RXP_6 K34
PEG_RXP_7 F29
H29 PEG_RXP_8 E28
<14> FDI_CSYNC

FDI
J29 FDI_CSYNC PEG_RXP_9 F31
<14> FDI_INT DISP_INT PEG_RXP_10 E30
PEG_RXP_11 F35
PEG_RXP_12 E34
Note: PEG_RXP_13 F33
Trace width=4 mils ,Spacing=5mil PEG_RXP_14 D32
PEG_RXP_15 H35
Max length= 10000 mils. PEG_TXN_0 H34
PEG_TXN_1 J33
PEG_TXN_2 H32
PEG_TXN_3 J31
PEG_TXN_4 G30
PEG_TXN_5 C33
PEG_TXN_6 B32
PEG_TXN_7 B31
PEG_TXN_8 A30
PEG_TXN_9 B29
PEG_TXN_10 A28
PEG_TXN_11 B27
PEG_TXN_12 A26
PEG_TXN_13 B25
B PEG_TXN_14 A24 B
PEG_TXN_15 J35
PEG_TXP_0 G34
PEG_TXP_1 H33
PEG_TXP_2 G32
PEG_TXP_3 H31
PEG_TXP_4 H30
PEG_TXP_5 B33
PEG_TXP_6 A32
PEG_TXP_7 C31
PEG_TXP_8 B30
PEG_TXP_9 C29
PEG_TXP_10 B28
PEG_TXP_11 C27
PEG_TXP_12 B26
PEG_TXP_13 C25
PEG_TXP_14 B24
PEG_TXP_15

INTEL_HASWELL_HASWELL 1 OF 9

ME@

A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

+1.35V

1
D D

R42 @
1K_0402_1%
+1.05VS +VCCST R46
Note:

2
1K_0402_5%
0 ohm Resistor should be placed H_DRAMRST# 1 2
DDR3_DRAMRST# <11,12>
R4 2 1 0_0603_5%
@ cloose to CPU

22U_0805_6.3V6M
C33

22U_0805_6.3V6M
C34
1 1
@ @
2 2

DDR3 COMPENSATION SIGNALS

+VCCIO_OUT SM_RCOMP0 R5 1 2 100_0402_1%
SM_RCOMP1 R6 1 2 75_0402_1%
SM_RCOMP2 R7 1 2 100_0402_1%
Note: Haswell rPGA EDS
1

JCPU1B Note:
R8 PECI/THERMTRIP:
62_0402_5% Trace width=4 mils ,Spacing=18mil
AP32
SKTOCC
MISC
SM_RCOMP_0
AP3 SM_RCOMP0 Trace width=12~15 mil, Spcing=20 mils
AR3 SM_RCOMP1
SM_RCOMP_1 Max trace length= 500 mils

DDR3
Zo=50 ohm AN32 AP2

THERMAL
T31 H_CATERR# SM_RCOMP2
2

AR27 CATERR SM_RCOMP_2 AN3 H_DRAMRST#

<18,32> H_PECI +VCCST AK31 PECI SM_DRAMRST

<32,37,38,44> H_PROCHOT#
H_PROCHOT# R9 1 2 H_PROCHOT#_R AM30 FC_AK31
PROCHOT PRDY
AR29 XDP_PRDY# PU/PD for JTAG signals
56_0402_5% AM35 AT29 XDP_PREQ#
<18> H_THRMTRIP# THERMTRIP PREQ AM34 XDP_TCLK
C TCK AN33 XDP_TMS +3VS C
TMS AM33 XDP_TRST#

JTAG
R10 1 2 0_0402_5% H_PM_SYNC_R AT28 TRST AM31 XDP_TDI XDP_DBRESET# R11 2 1 1K_0402_5%
<14> H_PM_SYNC

PWR
AL34 PM_SYNC TDI AL33 XDP_TDO
<18> H_CPUPWRGD PWRGOOD TDO +1.05VS
PM_SYS_PWRGD_BUF R13 1 2 0_0402_5% PM_DRAM_PWRGD_R AC10 AP33 XDP_DBRESET#
1 2 R37 BUF_CPU_RST# AT26 SM_DRAMPWROK DBR
<18> CPU_PLTRST# PLTRSTIN
2

@ 1 0_0402_5% AR30 XDP_BPM#0 XDP_TMS R14 2 @ 1 51_0402_5%

BPM_N_0

1
C536 AN31 XDP_BPM#1 @ XDP_TDI R16 2 @ 1 51_0402_5%
R15 R17 1 2 0_0402_5% CLK_CPU_DPLL#_R G28 BPM_N_1 AN29 XDP_BPM#2 C186 XDP_TDO R18 2 1 51_0402_5%
<15> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2

CLOCK
100P_0402_50V8J 10K_0402_5% <15> R19 1 2 0_0402_5% CLK_CPU_DPLL_R H28 AP31 XDP_BPM#3 0.047U_0402_16V7K
CLK_CPU_DPLL

2
2 R20 1 2 0_0402_5% CLK_CPU_SSC_DPLL#_R F27 DPLL_REF_CLKP BPM_N_3 AP30 XDP_BPM#4 XDP_TCLK R21 2 1 51_0402_5%
<15> CLK_CPU_SSC_DPLL#
1

R22 1 2 0_0402_5% CLK_CPU_SSC_DPLL_R E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 XDP_BPM#5 For EMI XDP_TRST# R23 2 1 51_0402_5%
C536 ESD reserve <15>
<15>
CLK_CPU_SSC_DPLL
CLK_CPU_DMI# R24 1 2 0_0402_5% CLK_CPU_DMI#_R D26 SSC_DPLL_REF_CLKP
BCLKN
BPM_N_5
BPM_N_6
AP29 XDP_BPM#6 Near Chip
R25 1 2 0_0402_5% CLK_CPU_DMII_R E26 AP28 XDP_BPM#7
<15> CLK_CPU_DMI BCLKP BPM_N_7
place near CPU
INTEL_HASWELL_HASWELL 2 OF 9
TMS/TDI no require pull high on Check list
+VCCIO_OUT ME@
CLK_CPU_SSC_DPLL_R 2 @ R26 1 10K_0402_5%

CLK_CPU_SSC_DPLL#_R 2 @ R27 1 10K_0402_5%

SSC CLOCK TERMINATION, IF NOT USED, stuff R26,R27

B B

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH +3V_PCH

@ +1.35V_CPU_VDDQ
1
C35
1

0.1U_0402_16V4Z
1

DS3@ DS3@
R28 R29 2 R30
100K_0402_5% 200_0402_1% 1.8K_0402_1%
U1
2

DS3@
2

DS3@ 1 R32 2 1
P

<14> SYS_PWROK B
0_0402_5% 4 PM_SYS_PWRGD_BUF
2 O
<14> PM_DRAM_PWRGD A
G

74AHC1G09GW_TSSOP5
3

@ R36
R35 3.3K_0402_1%
39_0402_5%
2

NODS3@
R133 1 2
0_0402_5%
1

D
A 2 Q1 @ A
<36> SUSP
G 2N7002H_SOT23-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

Haswell rPGA EDS

JCPU1C
Haswell rPGA EDS
<11> DDR_A_D[0..63] AR15 AC7
DDR_A_D0 T12 JCPU1D
AT14 SA_DQ_0 RSVD U4 <12> DDR_B_D[0..63]
DDR_A_D1 M_CLK_DDR#0
AM14 SA_DQ_1 SA_CK_N_0 V4 M_CLK_DDR#0 <11> AR18 AG8
DDR_A_D2 M_CLK_DDR0 DDR_B_D0 T13
AN14 SA_DQ_2 SA_CK_P_0 AD9 M_CLK_DDR0 <11> AT18 SB_DQ_0 RSVD Y4
DDR_A_D3 DDR_CKE0_DIMMA DDR_B_D1 M_CLK_DDR#2
AT15 SA_DQ_3 SA_CKE_0 U3 DDR_CKE0_DIMMA <11> AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 <12>
DDR_A_D4 M_CLK_DDR#1 DDR_B_D2
AR14 SA_DQ_4 SA_CK_N_1 V3 M_CLK_DDR#1 <11> AM18 SB_DQ_2 SB_CK0 AF10 DDR_CKE2_DIMMB M_CLK_DDR2 <12>
DDR_A_D5 M_CLK_DDR1 DDR_B_D3
AN15 SA_DQ_5 SA_CK_P_1 AC9 M_CLK_DDR1 <11> AR17 SB_DQ_3 SB_CKE_0 Y3 DDR_CKE2_DIMMB <12>
DDR_A_D6 DDR_CKE1_DIMMA DDR_B_D4 M_CLK_DDR#3
AM15 SA_DQ_6 SA_CKE_1 U2 DDR_CKE1_DIMMA <11> AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 <12>
DDR_A_D7 DDR_B_D5
AM9 SA_DQ_7 SA_CK_N_2 V2 AN17 SB_DQ_5 SB_CK1 AG10 DDR_CKE3_DIMMB M_CLK_DDR3 <12>
DDR_A_D8 DDR_B_D6
AN9 SA_DQ_8 SA_CK_P_2 AD8 AN18 SB_DQ_6 SB_CKE_1 Y2 DDR_CKE3_DIMMB <12>
DDR_A_D9 DDR_B_D7
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
DDR_A_D11 AN8 SA_DQ_10 SA_CK_N_3 V1 DDR_B_D9 AR12 SB_DQ_8 SB_CK2 AG9
DDR_A_D12 AR9 SA_DQ_11 SA_CK_P_3 AC8 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D12 AT11 SB_DQ_11 SB_CK3 AF9
D SA_DQ_14 SA_CS_N_0 DDR_CS0_DIMMA# <11> SB_DQ_12 SB_CKE_3 D
DDR_A_D15 AT8 L9 DDR_CS1_DIMMA# DDR_B_D13 AR11
AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS1_DIMMA# <11> AM12 SB_DQ_13 P4
DDR_A_D16 DDR_B_D14 DDR_CS2_DIMMB#
AK9 SA_DQ_16 SA_CS_N_2 M10 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS2_DIMMB# <12>
DDR_A_D17 DDR_B_D15 DDR_CS3_DIMMB#
AJ6 SA_DQ_17 SA_CS_N_3 M8 AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMMB# <12>
DDR_A_D18 M_ODT0 DDR_B_D16
AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT0 <11> AR6 SB_DQ_16 SB_CS_N_2 P1
DDR_A_D19 M_ODT1 DDR_B_D17
AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT1 <11> AM5 SB_DQ_17 SB_CS_N_3
DDR_A_D20 DDR_B_D18
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
AJ7 SA_DQ_21 SA_ODT_3 V5 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 <12>
DDR_A_D22 DDR_A_BS0 DDR_B_D20
AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS0 <11> AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT3 <12>
DDR_A_D23 DDR_A_BS1 DDR_B_D21
AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS1 <11> AN5 SB_DQ_21 SB_ODT_2 P2
DDR_A_D24 DDR_A_BS2 DDR_B_D22
AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 <11> AN6 SB_DQ_22 SB_ODT_3 R7
DDR_A_D25 DDR_B_D23 DDR_B_BS0
AF1 SA_DQ_25 V10 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS0 <12>
DDR_A_D26 DDR_B_D24 DDR_B_BS1
AF2 SA_DQ_26 VSS U6 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS2 DDR_B_BS1 <12>
DDR_A_D27 DDR_A_RAS# DDR_B_D25
AG4 SA_DQ_27 SA_RAS U7 DDR_A_RAS# <11> AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 <12>
DDR_A_D28 DDR_A_WE# DDR_B_D26
AG5 SA_DQ_28 SA_WE U8 DDR_A_WE# <11> AJ2 SB_DQ_26 R10
DDR_A_D29 DDR_A_CAS# DDR_B_D27
AG1 SA_DQ_29 SA_CAS DDR_A_CAS# <11> AM1 SB_DQ_27 VSS R6 DDR_B_RAS#
DDR_A_D30 DDR_B_D28
AG2 SA_DQ_30 V8 DDR_A_MA[0..15] <11> AN1 SB_DQ_28 SB_RAS P6 DDR_B_RAS# <12>
DDR_A_D31 DDR_A_MA0 DDR_B_D29 DDR_B_WE#
J1 SA_DQ_31 SA_MA_0 AC6 AK2 SB_DQ_29 SB_WE P7 DDR_B_WE# <12>
DDR_A_D32 DDR_A_MA1 DDR_B_D30 DDR_B_CAS#
J2 SA_DQ_32 SA_MA_1 V9 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# <12>
DDR_A_D33 DDR_A_MA2 DDR_B_D31
J5 SA_DQ_33 SA_MA_2 U9 L2 SB_DQ_31 R8 DDR_B_MA[0..15] <12>
DDR_A_D34 DDR_A_MA3 DDR_B_D32 DDR_B_MA0
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D48 B5 SA_DQ_47 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
E6 SA_DQ_48 AP15 DDR_A_DQS#[0..7] <11> J10 SB_DQ_46 SB_MA_14 AG7
DDR_A_D49 DDR_A_DQS#0 DDR_B_D47 DDR_B_MA15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D49 B8 SB_DQ_48
C SA_DQ_51 SA_DQS_N_2 SB_DQ_49 DDR_B_DQS#[0..7] <12> C
DDR_A_D52 D5 AF3 DDR_A_DQS#3 DDR_B_D50 A9 AP18 DDR_B_DQS#0
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS[0..7] <11> E9 SB_DQ_54 SB_DQS_N_4 H9
DDR_A_D57 DDR_A_DQS0 DDR_B_D55 DDR_B_DQS#5
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
E11 SA_DQ_59 SA_DQS_P_2 AG3 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS[0..7] <12>
DDR_A_D60 DDR_A_DQS3 DDR_B_D58 DDR_B_DQS0
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
+VREF_CA_R AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
+VREF_CA_R SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
+VREF_DQ_DIMMA_R +VREF_DQ_DIMMA_R F16 DDR_B_D63 B14 H8 DDR_B_DQS5
+VREF_DQ_DIMMB_R F13 SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5 C9 DDR_B_DQS6
+VREF_DQ_DIMMB_R SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDR_B_DQS7
SB_DQS_P_7

INTEL_HASWELL_HASWELL 3 OF 9 INTEL_HASWELL_HASWELL 4 OF 9
ME@ ME@

CPI DRIVER VREF PATH IS DEFAULT

*M3+M1:Default Recommendation
B
M1:VREF_DQ driven by a voltage Divider Network during B
Processor power-off state.
M3:VREF_DQ driven by Processor.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9641P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

D D

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP 2 1
24.9_0402_1% R60

Note:
Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
Haswell rPGA EDS
JCPU1H

HDMI@ C48 1 2 0.1U_0402_10V6K TMDS_B_DATA2#_PCH T28 M27 EDP_CPU_AUX#

<25> HDMI_TX2-_CK 1 2 U28 DDIB_TXBN_0 EDP_AUXN N27 EDP_CPU_AUX# <22>
HDMI D2 HDMI@ C41 0.1U_0402_10V6K TMDS_B_DATA2_PCH EDP_CPU_AUX
<25> HDMI_TX2+_CK 1 2 TMDS_B_DATA1#_PCH T30 DDIB_TXBP_0 EDP_AUXP P27 EDP_HPD# EDP_CPU_AUX <22>
HDMI@ C42 0.1U_0402_10V6K
<25> HDMI_TX1-_CK 1 2 TMDS_B_DATA1_PCH U30 DDIB_TXBN_1 EDP_HPD E24 EDP_COMP
HDMI D1 HDMI@ C43 0.1U_0402_10V6K eDP
<25> HDMI_TX1+_CK 1 2 TMDS_B_DATA0#_PCH U29 DDIB_TXBP_1 EDP_RCOMP R27
HDMI <25> HDMI_TX0-_CK
HDMI@ C44 0.1U_0402_10V6K
DDIB_TXBN_2 EDP_DISP_UT IL
T14
HDMI D0 HDMI@ C45 1 2 0.1U_0402_10V6K TMDS_B_DATA0_PCH V29
<25> HDMI_TX0+_CK 1 2 U31 DDIB_TXBP_2
HDMI@ C46 0.1U_0402_10V6K TMDS_B_CLK#_PCH
<25> HDMI_CLK-_CK 1 2 TMDS_B_CLK_PCH V31 DDIB_TXBN_3
HDMI CLK HDMI@ C47 0.1U_0402_10V6K
C <25> HDMI_CLK+_CK DDIB_TXBP_3 P35 EDP_CPU_LANE_N0 C
T34 EDP_TXN_0 R35 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <22>
U34 DDIC_TXCN_0 EDP_TXP_0 N34 EDP_CPU_LANE_P0 <22>
EDP_CPU_LANE_N1
U35 DDIC_TXCP_0 EDP_TXN_1 P34 EDP_CPU_LANE_P1
V35 DDIC_TXCN_1 EDP_TXP_1 P33 FDI_CTX_PRX_N0
U32 DDIC_TXCP_1 FDI_TXN_0 R33 FDI_CTX_PRX_P0 FDI_CTX_PRX_N0 <14>
T32 DDIC_TXCN_2 FDI_TXP_0 N32 FDI_CTX_PRX_N1 FDI_CTX_PRX_P0 <14>
U33 DDIC_TXCP_2 FDI_TXN_1 P32 FDI_CTX_PRX_N1 <14>
FDI_CTX_PRX_P1
Place on connector side V33 DDIC_TXCN_3 FDI_TXP_1 FDI_CTX_PRX_P1 <14>
DDIC_TXCP_3
P29
R29 DDID_TXDN_0
N28 DDID_TXDP_0
P28 DDID_TXDN_1 DDI

P31 DDID_TXDP_1
R31 DDID_TXDN_2
N30 DDID_TXDP_2
P30 DDID_TXDN_3
DDID_TXDP_3

INTEL_HASWELL_HASWELL 8 OF 9

+VCCIO_OUT
ME@
HPD INVERSION FOR EDP

10K_0402_5%
2
RC1
1
B EDP_HPD# B

1
R458
1 2 1K_0402_5%

OUT
<22> TL_HPD

100K_0402_5%
2
IN

GND
R61
@ Q6
DTC124EKAT146_SC59-3

3
2
HPD is a active high signal from device. The HPD processor input is a low voltage
active signal.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R62
1K_0402_1%
@

2
D D

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2 socket pin map definition

0:Lane Reversed
Haswell rPGA EDS *
JCPU1I CFG4

1
AT1
AT2 RSVD_TP C23 R63
AD10 RSVD_TP RSVD_TP B23 1K_0402_1%
RSVD RSVD_TP D24

2
A34 RSVD_TP D23
A35 RSVD_TP RSVD_TP
RSVD_TP PCH_PWROK <14,32>
W29
W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16 T19
W33 TESTLO_G26 CFG_16 AR23
RSVD CFG_18 Embedded Display Port Presence Strap

1
AL30 AP21
AL29 RSVD CFG_17 AP23
C F25 RSVD CFG_19 C
+CPU_CORE VCC
@ R51 1 : Disabled; No Physical Display Port
1 2 H_CPU_TESTLO 2K_0402_1% CFG4
R64 49.9_0402_1% C35 AR33 attached to Embedded Display Port

2
1 2 CFG_RCOMP B35 RSVD_TP RSVD G6
RSVD_TP FC_G6 AM27
R309 49.9_0402_1% 0 : Enabled; An external Display Port device is
RSVD
*

2
1 2 H_CPU_RSVD AL25 AM26
R66 49.9_0402_1% RSVD_TP RSVD F5 @ R52
connected to the Embedded Display Port
W30 RSVD AM2 1K_0402_1%
W31 RSVD_TP RSVD K6
H_CPU_TESTLO W34 RSVD_TP RSVD

1
TESTLO E18 CFG6
T16 CFG0 AT20 RSVD
T17 CFG1 AR20 CFG_0 U10 CFG5
CFG2 AP20 CFG_1 RSVD P10
CFG_2 RSVD

1
T18 CFG3 AP22
CFG4 AT22 CFG_3 B1 @ R67 @ R68
CFG5 AN22 CFG_4 NC A2 1K_0402_1% 1K_0402_1%
CFG6 AT25 CFG_5 RSVD AR1
CFG7 AN23 CFG_6 RSVD_TP

2
AR24 CFG_7 E21
AT23 CFG_8 RSVD_TP E20
AN20 CFG_9 RSVD_TP
AP24 CFG_10 AP27
AP26 CFG_11 RSVD AR26
AN25 CFG_12 RSVD
AN26 CFG_13 AL31
AP25 CFG_14 VSS AL32
CFG_15 VSS
PCIE Port Bifurcation Straps

INTEL_HASWELL_HASWELL 9 OF 9 11: (Default) x16 - Device 1 functions 1 and 2 disabled

B B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
ME@
* disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
@R69
@ R69
1K_0402_1%

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

Haswell rPGA EDS +CPU_CORE

JCPU1E

AA26
VCC AA28
+1.35V_CPU_VDDQ Source K27
RSVD
VCC
VCC
AA34
L27 AA30
T27 RSVD VCC AA32
V27 RSVD VCC AB26
+1.35V +1.35V_CPU_VDDQ RSVD VCC AB29
D
VCC AB25 D
C51 @ VCC AB27
+1.35V +1.35V_CPU_VDDQ 0.1U_0402_10V6K VCC AB28
@J1
@ J1 1 2 AB11 VCC AB30
1 2 AB2 VDDQ VCC AB31
C49 AB5 VDDQ VCC AB33
PAD-OPEN 4x4m 0.1U_0402_10V6K AB8 VDDQ VCC AB34
1 2 AE11 VDDQ VCC AB32
AE2 VDDQ VCC AC26
@ AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
N26 VCC AD35
K26 RSVD VCC AE26
+CPU_CORE VCC VCC
AL27 AE32
VCC_SENSE +CPU_CORE
+1.05VS +VCCIO_OUT
AK27 RSVD
RSVD
VCC
VCC
AE28
AE30
VCC AG28
VCC
100_0402_1%

AG34
Note: VCC
1

R78 2 @ 1 0_0603_5% AE34

0 ohm Resistor should be placed VCC

4.7U_0402_6.3V6M
R79

AF25
VCC AF26
cloose to CPU VCCSENSE AL35 VCC AF27
C 1 VCC_SENSE VCC C

C53
RESISTOR STUFFING OPTIONS ARE @ E17 AF28
2

+VCCIO_OUT AN35 RSVD VCC AF29

PROVIDED FOR TESTING PURPOSES +VCCIO_OUT VCCIO_OUT VCC
A23 AF30
VCCSENSE 2 Note: F22 RSVD VCC AF31
<44> VCCSENSE +VCOMP_OUT VCOMP_OUT VCC
Place the UP resistor close to CPU W32
RSVD VCC
AF32

1
AL16 AF33
R81 J27 RSVD VCC AF34
VSSSENSE 75_0402_1% AL13 RSVD VCC AF35
<10,44> VSSSENSE RSVD VCC AG26
VCC AH26

2
VCC
1
100_0402_1%

R83 1 2 43_0402_5% H_CPU_SVIDALRT# AM28 AH29

<44> VR_SVID_ALRT# VIDALERT VCC
AM29 AG30
<44> VR_SVID_CLK VIDSCLK VCC
R84

AL28 AG32
<44> VR_SVID_DAT VIDSOUT VCC AH32
AP35 VCC AH35
2

VSS VCC

1
2 R88 1 H27 AH25
Note: R87
+1.05VS
150_0402_1% AP34 PWR_DEBUG VCC AH27
VSS VCC

2
Place the UP resistor close to CPU 130_0402_1% AT35
RSVD_TP VCC
AH28
AR35 AH30
R89 T23 AR32 RSVD_TP VCC AH31

2
10K_0402_5% AL26 RSVD_TP VCC AH33
@ AT34 RSVD_TP VCC AH34

1
+VCCIO_OUT AL22 VSS VCC AJ25
AT33 VSS VCC AJ26
VDDQ DECOUPLING AM21 VSS
VSS
VCC
VCC
AJ27
AM25 AJ28
+1.35V_CPU_VDDQ AM22 VSS VCC AJ29
AM20 VSS VCC AJ30
AM24 VSS VCC AJ31
AL19 VSS VCC AJ32
AM23 VSS VCC AJ33
VSS VCC
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

AT32 AJ34
VSS VCC AJ35
1 1 1 1 1 1 VCC
C54

C55

C56

C57

C58

G25
+ C59 VCC H25
B B
330U_2.5V_M VCC J25
2 2 2 2 2 VCC K25
2 +CPU_CORE VCC L25
VCC M25
Y25 VCC N25
Y26 VCC VCC P25
Y27 VCC VCC R25
Y28 VCC VCC T25
Y29 VCC VCC
Y30 VCC U25
Y31 VCC VCC U26
VCC VCC
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

Y32 V25
Y33 VCC VCC V26
1 1 1 1 1 VCC VCC
C60

C61

C62

C63

C64

Y34
Y35 VCC W26
VCC VCC W27
2 2 2 2 2 VCC
INTEL_HASWELL_HASWELL 5 OF 9

ME@

A A

Security Classification Compal Secret Data

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

Haswell rPGA EDS Haswell rPGA EDS

JCPU1F JCPU1G
D A10 AK34 B34 K10 D
A13 VSS VSS AK5 B4 VSS VSS K2
A16 VSS VSS AL1 B7 VSS VSS K29
A19 VSS VSS AL10 C1 VSS VSS K3
A22 VSS VSS AL11 C10 VSS VSS K31
A25 VSS VSS AL12 C13 VSS VSS K33
A27 VSS VSS AL14 C16 VSS VSS K35
A29 VSS VSS AL15 C19 VSS VSS K4
A3 VSS VSS AL17 C2 VSS VSS K5
A31 VSS VSS AL18 C22 VSS VSS K7
A33 VSS VSS AL2 C24 VSS VSS K8
A4 VSS VSS AL20 C26 VSS VSS K9
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AA31 VSS VSS AL4 C4 VSS VSS M26
AA29 VSS VSS AL5 C7 VSS VSS M28
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AC27 VSS VSS AM16 D27 VSS VSS N2
AB4 VSS VSS AM19 D29 VSS VSS N29
AB6 VSS VSS E25 D31 VSS VSS N3
AB7 VSS VSS AM32 D33 VSS VSS N31
AB9 VSS VSS AM4 D35 VSS VSS N33
AC11 VSS VSS AM7 D4 VSS VSS N35
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
C AC31 VSS VSS AN16 E10 VSS VSS N6 C
AC33 VSS VSS AN19 E13 VSS VSS N7
AC35 VSS VSS AN2 E16 VSS VSS N9
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE29 VSS VSS AN34 F12 VSS VSS R26
AE3 VSS VSS AN4 F14 VSS VSS R28
AE27 VSS VSS AN7 F15 VSS VSS R30
AE35 VSS VSS AP1 F17 VSS VSS R32
AE4 VSS VSS AP10 F18 VSS VSS R34
AE6 VSS VSS AP13 F20 VSS VSS R5
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AG25 VSS VSS AR13 F32 VSS VSS T35
AE31 VSS VSS AR16 F34 VSS VSS T4
AG31 VSS VSS AR19 F4 VSS VSS T6
AE33 VSS VSS AR2 F6 VSS VSS T7
AG6 VSS VSS AR22 F7 VSS VSS T9
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
B AH4 VSS VSS AT16 G31 VSS VSS W10 B
AH5 VSS VSS AT19 G33 VSS VSS W3
AH6 VSS VSS AT21 G35 VSS VSS W35
AH7 VSS VSS AT24 G4 VSS VSS W4
AH8 VSS VSS AT27 G5 VSS VSS W6
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE <44,9>
AK32 VSS VSS B22 J34 VSS RSVD T15
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS

INTEL_HASWELL_HASWELL 6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9

ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

+1.35V +1.35V
[email protected]
<6> DDR_A_D[0..63] +VREF_DQ_DIMMA_R
DDR3 SO-DIMM A <6> DDR_A_DQS[0..7]
+1.35V

JDIMM1
<6> DDR_A_DQS#[0..7]

1
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <6> DDR_A_MA[0..15]

2.2U_0603_6.3V4Z

0.1U_0402_10V6K
DDR_A_D0 5 6 DDR_A_D5 R50
DQ0 DQ5

C65

C66
1 1 DDR_A_D1 7 8 1K_0402_1%
9 DQ1 VSS3 10 DDR_A_DQS#0

2
@ DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0 R48 1 2 2_0402_5% +VREF_DQ_DIMMA
13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 D
DQ2 DQ6 1
DDR_A_D3 17 18 DDR_A_D7 C39
DQ3 DQ7

1
19 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 0.022U_0402_16V7K
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 2 R53
DQ9 DQ13

1
25 26 1K_0402_1%
DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1 R54
Note:

2
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST# VREF trace width:20 mils at least
DQS1 RESET# DDR3_DRAMRST# <12,5> 24.9_0402_1%
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14 Spacing:20mils to other signal/planes

2
DQ10 DQ14
DDR_A_D11 35
DQ11 DQ15
36 DDR_A_D15 Place near DIMM scoket
37 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22 +1.35V +VREF_CA_R
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
DQ19 VSS19

1
55 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
Note:
DDR_A_D25 59 DQ24 DQ29 60 R40 VREF trace width:20 mils at least
61 DQ25 VSS21 62 DDR_A_DQS#3 1K_0402_1%
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3 Spacing:20mils to other signal/planes

2
DM3 DQS3
65
VSS23 VSS24
66 Place near DIMM scoket
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 +VREF_CA 2_0402_5% 2 1 R47
71 DQ27 DQ31 72
VSS25 VSS26 1
C37

1
0.022U_0402_16V7K
C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA 2 C
<6> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6>

1
75 76 R44
77 VDD1 VDD2 78 DDR_A_MA15 1K_0402_1% R45
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<6> DDR_A_BS2 24.9_0402_1%

2
81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11

2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
Layout Note: (10uF_0603_6.3V)*8
99 A1 A0 100 Place near DIMM
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<6>
<6>
M_CLK_DDR0
M_CLK_DDR#0 M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1
M_CLK_DDR1 <6> (0.1uF_402_10V)*4
CK0# CK1# M_CLK_DDR#1 <6>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <6>
<6> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <6>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# +1.35V
<6> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6>
<6> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <6>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
DDR_CS1_DIMMA# 121 A13 ODT1 122
M_ODT1 <6> EVT Check
<6> DDR_CS1_DIMMA# S1# NC2 1

10U_0603_6.3V6M
C69

10U_0603_6.3V6M
C70

10U_0603_6.3V6M
C71

10U_0603_6.3V6M
C72

10U_0603_6.3V6M
C73

10U_0603_6.3V6M
C74

10U_0603_6.3V6M
C75

10U_0603_6.3V6M
C76

0.1U_0402_10V6K
C77

0.1U_0402_10V6K
C78

0.1U_0402_10V6K
C79

0.1U_0402_10V6K
C80
123 124 1 1 1 1 1 1 1 1 1 1 1 1
125 VDD17 VDD18 126 +VREF_CA + C81 @
NCTEST VREF_CA +VREF_CA <12> 220U_6.3V_M
127 128
VSS27 VSS28

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36 @ @
DQ32 DQ36 2 2 2 2 2 2 2 2 2 2 2 2 2

C67

C68
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 @
B DDR_A_DQS4 137 DQS#4 DM4 138 B
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
Layout Note:
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
@ DDR_A_DQS6 171 DQS#6 DM6 172
1 2 173 DQS6 VSS43 174 DDR_A_D54
+3VALW VSS44 DQ54
R141 DDR_A_D50 175 176 DDR_A_D55
0_0402_5% DDR_A_D51 177 DQ50 DQ55 178 +0.675VS
179 DQ51 VSS45 180 DDR_A_D60 DDR_A_DM0
1 2 +3V_DIMM DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 DDR_A_DM1
+3VS DQ56 DQ61
R137 DDR_A_D57 183 184 DDR_A_DM2
0_0402_5% 185 DQ57 VSS47 186 DDR_A_DQS#7 @ @ DDR_A_DM3
VSS48 DQS#7

1U_0402_6.3V6K
C82

1U_0402_6.3V6K
C83

1U_0402_6.3V6K
C84

1U_0402_6.3V6K
C85
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1 1 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2 2 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3V_DIMM VDDSPD SDA SMB_DATA_S3 <12,16,26> Layout Note:
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <12,16,26>
Place near DIMM
C86

C87

1 1 203 204 +0.675VS

VTT1 VTT2
205 206 [email protected]
@ G1 G2
2 2 FOX_AS0A626-U8SN-7F
ME@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, October 03, 2012 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

[email protected]
<6> DDR_B_D[0..63]
+1.35V +1.35V
<6> DDR_B_DQS[0..7]
JDIMM2
<6> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 <6> DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3

2.2U_0603_6.3V4Z

0.1U_0402_10V6K
@ 9 10 DDR_B_DQS#0
DDR_B_DM0 11 VSS4 DQS#0 12 DDR_B_DQS0
1 1 DM0 DQS0
13 14
VSS5 VSS6

C88

C89
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <11,5>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15 +1.35V
37 DQ11 DQ15 38 +VREF_DQ_DIMMB_R
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DQ16 DQ20 Note:

1
DDR_B_D17 41 42 DDR_B_D21
43 DQ17 DQ21 44 VREF trace width:20 mils at least
DDR_B_DQS#2 45 VSS15 VSS16 46 DDR_B_DM2 R56
DDR_B_DQS2 47 DQS#2 DM2 48 Spacing:20mils to other signal/planes 1K_0402_1%
49 DQS2 VSS17 50 DDR_B_D22

2
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23 R49 1 2 2_0402_5% +VREF_DQ_DIMMB
DDR_B_D19 53 DQ18 DQ23 54
DQ19 VSS19 1
55 56 DDR_B_D28 C40
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DQ24 DQ29

1
DDR_B_D25 59 60 0.022U_0402_16V7K
61 DQ25 VSS21 62 DDR_B_DQS#3 2
VSS22 DQS#3

1
DDR_B_DM3 63 64 DDR_B_DQS3 R58
65 DM3 DQS3 66 R59 1K_0402_1%
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30 24.9_0402_1%

2
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72

2
VSS25 VSS26

<6> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <6>
75 76
C 77 VDD1 VDD2 78 DDR_B_MA15 C
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<6> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<6> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <6>
<6> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <6>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <6>
DDR_B_BS0 109 110 DDR_B_RAS#
<6> DDR_B_BS0
111 BA0 RAS# 112
DDR_B_RAS# <6> Layout Note: (10uF_0603_6.3V)*8
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB# Place near DIMM
<6> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <6>
DDR_B_CAS# 115 116 M_ODT2
<6> DDR_B_CAS#
117 CAS# ODT0 118
M_ODT2 <6> (0.1uF_402_10V)*4
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <6>
<6> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA <11> +1.35V

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
127 128
DDR_B_D32 129 VSS27 VSS28 130 DDR_B_D36
DQ32 DQ36

C90

C91
DDR_B_D33 131 132 DDR_B_D37 1 1
133 DQ33 DQ37 134
VSS29 VSS30

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4 @
DQS#4 DM4

C92

C185

C94

C95

C96

C97

C98

C99

C100

C101

C102

C103
DDR_B_DQS4 137 138 1 1 1 1 1 1 1 1 1 1 1 1
139 DQS4 VSS31 140 DDR_B_D38 2 2
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B
DDR_B_D35 143 DQ34 DQ39 144 @ @
145 DQ35 VSS33 146 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
DDR_B_DM5 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
Layout Note:
DDR_B_DQS#6 169 VSS41 VSS42 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60 +0.675VS
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184 DDR_B_DM0
185 DQ57 VSS47 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 187 VSS48 DQS#7 188 DDR_B_DQS7 @ @ DDR_B_DM2
DM7 DQS7

1U_0402_6.3V6K
C104

1U_0402_6.3V6K
C105

1U_0402_6.3V6K
C106

1U_0402_6.3V6K
C107
189 190 DDR_B_DM3
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 DDR_B_DM4
DQ58 DQ62 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
195 DQ59 DQ63 196 DDR_B_DM6
197 VSS51 VSS52 198 DDR_B_DM7
199 SA0 EVENT# 200 SMB_DATA_S3 2 2 2 2
+3V_DIMM VDDSPD SDA SMB_DATA_S3 <11,16,26>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <11,16,26>
2.2U_0603_6.3V4Z

0.1U_0402_10V6K
C109

1 R93 10K_0402_5% 203 204 +0.675VS

VTT1 VTT2 [email protected]
C108

A A
@
1
205 206
Layout Note:
G1 G2 Place near DIMM
2 FOX_AS0A626-U4SN-7F
2
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, October 03, 2012 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

Note:
W=20mils W=20mils
PCH_RTCX1/PCHRTCX2
+RTCVCC +RTCBATT
Trace length <1000 mils @
R94 PCH_RTCX1 R196 1 2 GCLK_32K
GCLK_32K <34>
1K_0402_5% 0_0402_5%
1 2 1 2 PCH_RTCX2
R95 10M_0402_5%
1 NOGCLK@

1
C110 Y1
1U_0603_10V4Z CLRP1 1 2
2 SHORT PADS 32.768KHZ_12.5PF_CM31532768DZFT
D 2 NOGCLK@ D
1 1
C112
C111 18P_0402_50V8J
18P_0402_50V8J NOGCLK@
NOGCLK@ 2 2
+RTCVCC

R96 1 2 1M_0402_5% SM_INTRUDER#

R97 1 2 330K_0402_5% PCH_INTVRMEN U4A LPT_PCH_M_EDS

+RTCVCC CLRP2

SHORT PADS
CLRP2
OPEN SAVE ME RTC REGISTER BC8
INTVRMEN C113 1 PCH_RTCX1 B5 SATA_RXN_0 BE8
RTCX1 SATA_RXP_0

1
：：
(INTEGRATED SUS 1.05V VR) 1U_0603_10V4Z SHORT CLEAR ME RTC REGISTER
* H Integrated VRM enable PCH_RTCX2 B4 AW8
RTCX2 SATA_TXN_0 AY8
L Integrated VRM disable

RTC
2
1 2 2 PCH_SRTCRST# B9 SATA_TXP_0
(INTVRMEN should always be pull high.) SRTCRST#
R98 20K_0402_5% BC10
1 2 PCH_RTCRST# SM_INTRUDER# A8 SATA_RXN_1 BE10
R99 20K_0402_5% INTRUDER# SATA_RXP_1
1

1
+3V_PCH

SHORT PADS
CLRP3
CLRP3 PCH_INTVRMEN G10 AV10
C115 INTVRMEN SATA_TXN_1 AW10
OPEN SAVE CMOS SATA_TXP_1
R100 2 1 1K_0402_5% HDA_SYNC 1U_0603_10V4Z D9

2
2 RTCRST# BB9
SHORT CLEAR CMOS SATA_RXN_2
+3VS BD9
HDA_BIT_CLK B25 SATA_RXP_2
R101 1 @ 2 1K_0402_5% PCH_GPIO33 HDA_BCLK AY13
HDA_SYNC A22 SATA_TXN_2 AW13
HDA_SYNC SATA_TXP_2
C HDA_SPKR AL10 BC12 C
<31> HDA_SPKR SPKR SATA_RXN_3 BE12
+3VS HDA_RST# C24 SATA_RXP_3
HDA_RST# AR13
1 2 1K_0402_5% L22 SATA_TXN_3

AZALIA
R102 @ HDA_SPKR HDA_SDIN0 AT13

SATA
<31> HDA_SDIN0 HDA_SDI0 SATA_TXP_3
K22
HIGH= Enable ( No Reboot )
* LOW= Disable (Default)
ME FALSH HDA_SDI1 BD13 SATA_DTX_C_PRX_N4
SATA_RXN4/PERN1 SATA_DTX_C_PRX_N4 <30>
G22 BB13 SATA_DTX_C_PRX_P4
HDA_SDI2 SATA_RXP4/PERP1 SATA_DTX_C_PRX_P4 <30>
HDD
F22 AV15 SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_N4 <30>
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_PTX_C_DRX_P4
SATA_TXP4/PETP1 SATA_PTX_C_DRX_P4 <30>
HDA_SDOUT A24 SATA 6G
+3V_PCH <32> HDA_SDOUT HDA_SDO BC14 SATA_DTX_C_PRX_N5
SATA_RXN5/PERN2 SATA_DTX_C_PRX_N5 <30>
R104 1 @ 2 1K_0402_1% PCH_GPIO33 B17 BE14 SATA_DTX_C_PRX_P5 SATA_DTX_C_PRX_P5 <30> ODD
R105 2 @ 1 1K_0402_5% HDA_SDOUT DOCKEN#/GPIO33 SATA_RXP5/PERP2

+3V_PCH R106 1 @ 2 10K_0402_5% PCH_GPIO13 C22 AP15 SATA_PTX_C_DRX_N5

HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_PTX_C_DRX_N5 <30>
* Low = Disabled (Default) AR15 SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_P5 <30>
SATA_TXP5/PETP2
High = Enabled [Flash Descriptor Security Override]
AY5 SATA_COMP +3VS
SATA_RCOMP
+5VS AP3 SATA_ACT# 2 R108 1 10K_0402_5%
SATALED#
2 R110 1 PCH_JTAG_TCK AB3 AT1 HDD_DET#
JTAG_TCK SATA0GP/GPIO21 HDD_DET# <18>
2
G

RP12 Q10 51_0402_5% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R HDD_DET# and BBS_BIT0_R pull high by 10P8R
JTAG_TMS SATA1GP/GPIO19 BBS_BIT0_R <18>
<31> HDA_BITCLK_AUDIO 8 1 HDA_BIT_CLK LBSS138LT1G_SOT-23-3
7 2 HDA_SYNC_R 3 1 HDA_SYNC PCH_JTAG_TDI AE2 BD4

JTAG
<31> HDA_SYNC_AUDIO JTAG_TDI SATA_IREF +1.5VS
6 3 HDA_RST#
S

<31> HDA_RST_AUDIO#
2

B B
<31> HDA_SDOUT_AUDIO 5 4 HDA_SDOUT @ PCH_JTAG_TDO AD3 BA2
R115 JTAG_TDO TP9
33_0804_8P4R_5% @ 1M_0402_5% F8 BB2
TP25 TP8
1 2 C26
SATA Impedance Compensation
1

TP22
R118 AB6
0_0402_5% TP20 +1.5VS
+3V_PCH +3V_PCH +3V_PCH
DG remove Q10 on Version 1.5 1 OF 11 SATA_COMP 1 2
DH82LPMS-QC4C-A1_FCBGA695~D 7.5K_0402_1% R107
1

Note:
R119 R311 R121
@ @ @
Trace width:4mils
200_0402_1% 200_0402_1% 200_0402_1%
Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid
routing next to clock pins.
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1

R122 R123 R124

100_0402_1% 100_0402_1% 100_0402_1%
@ @ @
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
RP23
4 5 DAC_BLU
3 6 DAC_GRN

1
2 7 DAC_RED
R125 R126 1 8
2.2K_0402_5% 2.2K_0402_5%
150_0804_8P4R_5%

2
CRT_DDC_CLK
Change PN
CRT_DDC_DATA
LPT_PCH_M_EDS LPT_PCH_M_EDS
U4B U4E
D D
<4> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 AW22 DAC_BLU T45 R40 HDMICLK_NB HDMICLK_NB <25>
DMI_RXN_0 <24> DAC_BLU VGA_BLUE DDPB_CTRLCLK
<4> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 AR20
DMI_RXN_1 AJ35 FDI_CTX_PRX_N0 DAC_GRN U44 R39 HDMIDAT_NB
FDI_RXN_0 FDI_CTX_PRX_N0 <7> <24> DAC_GRN VGA_GREEN DDPB_CTRLDATA HDMIDAT_NB <25>
<4> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 AP17
DMI_CTX_PRX_N3 AV20 DMI_RXN_2 AL35 FDI_CTX_PRX_N1 DAC_RED V45 R35
<4> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <7> <24> DAC_RED VGA_RED DDPC_CTRLCLK
<4> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 AY22 AJ36 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <7> CRT_DDC_CLK M43 R36
DMI_RXP_0 FDI_RXP_0 <24> CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA
<4> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 AP20
DMI_RXP_1 AL36 FDI_CTX_PRX_P1 CRT_DDC_DATA M45 N40

CRT
FDI_RXP_1 FDI_CTX_PRX_P1 <7> <24> CRT_DDC_DATA VGA_DDC_DATA DDPD_CTRLCLK
<4> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 AR17
DMI_CTX_PRX_P3 AW20 DMI_RXP_2 AV43 N42 N38
<4> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 <24> CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA
DMI_CRX_PTX_N0 BD21 AY45 N44
<4> DMI_CRX_PTX_N0 BE20 DMI_TXN_0 TP5 <24> CRT_VSYNC VGA_VSYNC H45
DMI_CRX_PTX_N1
<4> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 1 2 U40 DDPB_AUXN
CRT_IREF

DISPLAY
DMI_CRX_PTX_N2 BD17 TP15 R132 649_0402_1% DAC_IREF K43
<4> DMI_CRX_PTX_N2 DMI_TXN_2 DDPC_AUXN
DMI_CRX_PTX_N3 BE18 AW44 U39
<4> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 VGA_IRTN J42
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC DDPD_AUXN
<4> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <4>
DMI_CRX_PTX_P1 BC20 PCH_PWM N36 H43
<4> DMI_CRX_PTX_P1 DMI_TXP_1 <22> PCH_PWM EDP_BKLTCTL DDPB_AUXP
AL40 FDI_INT

LVDS
FDI_INT FDI_INT <4>
DMI_CRX_PTX_P2 BB17 PCH_ENBKL K36 K45
<4> DMI_CRX_PTX_P2 DMI_TXP_2 EDP_BKLTEN DDPC_AUXP
DMI_CRX_PTX_P3 BC18 AT45 +1.5VS
<4> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF G36 J44
PCH_ENVDD
BE16 AU42 EDP_VDDEN DDPD_AUXP
+1.5VS DMI_IREF TP17 K40
DDPB_HPD TMDS_B_HPD# <25>
AW17 AU44 PCI_PIRQA# H20
SUSACK# is only used on platform TP12 TP13 PIRQA# K38
AV17 AR44 FDI_RCOMP 1 2 PCI_PIRQB# L20 DDPC_HPD
that support the Deep Sx state. TP7 FDI_RCOMP +1.5VS PIRQB#
R145 7.5K_0402_1% H39
1 2 DMI_RCOMP AY17 PCI_PIRQC# K17 DDPD_HPD
+1.5VS DMI_RCOMP PIRQC#
R135 7.5K_0402_1%
PCI_PIRQD# M20
PIRQD# G17 PCH_GPIO2
R136 1 DS3@ 2 0_0402_5% SUSACK#_R R6 C8 DSWODVREN DGPU_HOLD_RST# A12 PIRQE#/GPIO2 R140@
<32> SUSACK# SUSACK# DSWVRMEN GPIO50
NODS3@ F17 ODD_DA#_R 1 2
PCI PIRQF#/GPIO3 ODD_DA# <30,32>
C +3VS 10K_0402_5%2 R138 1 SYS_RST# AM1 L13 PCH_DPWROK 1 R139 2 0_0402_5% EC_RSMRST# PCH_GPIO52 B13 0_0402_5% C
SYS_RESET# DPWROK GPIO52 L15 PCH_GPIO4
SYS_PWROK AD7 K3 DGPU_PWR_EN C12 PIRQG#/GPIO4
SYS_PWROK WAKE# PCIE_WAKE# <26,27> GPIO54 M15 PCH_GPIO5
PCH_PWROK F10 AN7 PM_CLKRUN# BBS_BIT1 C10 PIRQH#/GPIO5
<32,8> PCH_PWROK PWROK System Power CLKRUN# GPIO51 AD10 PCI_PME#
AB7 Management U7 SUS_STAT# T20 T21 PCH_GPIO53 A10 PME#
APWROK SUS_STAT#/GPIO61 GPIO53 Y11 PCH_PLTRST#
PM_DRAM_PWRGD H3 Y6 PCH_GPIO55 AL6 PLTRST#
<5> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK <32> GPIO55
J2 Y7
<32> EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# <32>
DH82LPMS-QC4C-A1_FCBGA695~D 5 OF 11
R148 1 DS3@ 2 0_0402_5% SUSWARN#_R J4 C6 PCH_DPWROK R149 1 DS3@ 2 0_0402_5% DPWROK_EC <32>
<32> SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <32>
K1 H1 +3VS
<32> PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# <32>
1 2 AC_PRESENT_R E6 F3 SLP_A# T22 SLP_A# can be left NC when IAMT is 1 R151 2
<32,37,39> ACIN ACPRESENT/GPIO31 SLP_A#
D1 CH751H-40PT_SOD323-2 not support on the platfrom BBS_BIT1 1 R182 2 10K_0402_5% 0_0402_5%
PCH_GPIO72 K7 F1 SLP_SUS#
BATLOW#/GPIO72 SLP_SUS# SLP_SUS# <32,36>
BBS_BIT1 R153 1 @ 2 1K_0402_5%
RI# N4 AY3 H_PM_SYNC
RI# PMSYNCH H_PM_SYNC <5>
AEPWROK can be connect to

3
PWROK if iAMT disable AB10 G5
TP21 SLP_LAN# 1 PCH_PLTRST#
Boot BIOS Strap (GPIO51)

G
D2 SLP_LAN# can be left NC if no use 4 A
SLP_WLAN#/GPIO29 <26,27,32> PLT_RST# Y
integrated LAN. 2
B

P
SATA_SLPD

1
DH82LPMS-QC4C-A1_FCBGA695~D 4 OF 11 BBS_BIT1 Boot BIOS Location 1 U5@

5
(BBS_BIT0) MC74VHC1G08DFT2G SC70 5P
C117 @
0 0 LPC 1U_0402_6.3V4Z
2 +3VS

2
R156
0 1 Reserved (NAND) 100K_0402_5%

1 0 PCI +3VS
B B
RP1
PCI_PIRQA# 8 1
1 1 * SPI PCI_PIRQB# 7 2
GPIO51 has internal pull up. PCI_PIRQC# 6 3
U6 PCI_PIRQD# 5 4
MC74VHC1G08DFT2G SC70 5P
3

GPIO55 8.2K_0804_8P4R_5%
1
G

<44> VGATE A 4SYS_PWROK PCH_GPIO55 R158 1 @ 2 1K_0402_5% DGPU_HOLD_RST# 2 R167 1 10K_0402_5%

Y SYS_PWROK <5>
PCH_PWROK 2
B
P

DGPU_HOLD_RST# 2 R168 1 10K_0402_5%

5

A16 swap overide Strap/Top-Block @

R157 @ Swap Override jumper
100K_0402_1% +3V_PCH
+3VS Low=A16 swap
+RTCVCC override/Top-Block
2

+3VALW PCI_GNT3# Swap Override enabled

4 5 SUSWARN#_R High=Default *
1

3 6 PCIE_WAKE#
2 7 PCH_GPIO72 R134
1 8 RI# 330K_0402_5%
SUSACK# and SUSWARN# can be tied together if +3VS
EC does not want to involve in the handshake RP10
2

mechanism for the Deep Sleep state entry and exit. 10K_0804_8P4R_5%
DSWODVREN PCH_GPIO55 1 R176 2 10K_0402_5%
1

SUSWARN#_R 1 2 SUSACK#_R
R169 @ 0_0402_5% R143
330K_0402_5%
CLKRUN#: @
External pull up to core well is required.
2

+3V_PCH RP13
6 5 +3VS
+3VS PCH_GPIO2 7 4 PCH_GPIO4
A A
DGPU_PWR_EN 8 3 PCH_GPIO5

：：
DSWODVREN - On Die DSW VR Enable ODD_DA#_R 9 2 PCH_GPIO52
1 R172 2 8.2K_0402_5% PM_CLKRUN# 10 1
* H Enable (DEFAULT)
L Disable
+3VS
1 R173 2 200K_0402_5% AC_PRESENT_R
2 R174 1 10K_0402_5% 10K_1206_10P8R_5%

2 R312 1 10K_0402_5% EC_RSMRST#

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

D D

+3V_PCH

R177 2 1 10K_0402_5%

PEG_CLKREQ#_R R179 1 2 10K_0402_5%

@
LPT_PCH_M_EDS
U4C

R185 1 2 0_0402_5% CLK_PCIE_LAN#_R Y43 AB35 CLK_PCIE_VGA#_R

<27> CLK_PCIE_LAN# CLKOUT_PCIE_N_0 CLKOUT_PEG_A
LAN R187 1 2 0_0402_5% CLK_PCIE_LAN_R Y45 AB36 CLK_PCIE_VGA_R
<27> CLK_PCIE_LAN CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P
AB1 AF6 PEG_CLKREQ#_R
<27> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47
+3V_PCH R181
R313 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AA44 Y39
<26> CLK_PCIE_WLAN1# CLKOUT_PCIE_N_1 CLKOUT_PEG_B
R189 1 2 0_0402_5% CLK_PCIE_WLAN1_R AA42
<26> CLK_PCIE_WLAN1 CLKOUT_PCIE_P_1 Y38
WLAN CLKOUT_PEG_B_P
AF1 CLK_BUF_DMI# R183 2 1 10K_0402_5%
<26> CLKREQ_WLAN# PCIECLKRQ1#/GPIO18
+3VS R184 2 1 10K_0402_5% U4 PCH_GPIO56 R191 2 1 10K_0402_5%
+3V_PCH CLK_BUF_DMI R192 2 1 10K_0402_5%
AB43 PEGB_CLKRQ#/GPIO56
CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
AB45 CLKOUT_DMI CLK_CPU_DMI# <5> CLK_BUF_BCLK# R193 2 1 10K_0402_5%
CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI CLK_BUF_BCLK R194 2 1 10K_0402_5%
2 1 10K_0402_5% AF3 CLKOUT_DMI_P CLK_CPU_DMI <5>
+3VS R195 PCH_GPIO20
PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
C AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL# <5> C
CLK_CPU_SSC_DPLL CLK_BUF_DOT96# R197 2 1 10K_0402_5%
AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <5> CLK_BUF_DOT96 R199 2 1 10K_0402_5%
R201 2 1 10K_0402_5% PCH_GPIO25 T3 CLKOUT_PCIE_P_3 AF35 CLK_CPU_DPLL#
+3V_PCH PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLK_CPU_DPLL# <5>
AF36 CLK_CPU_DPLL
AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <5> CLK_BUF_CKSSCD# R202 2 1 10K_0402_5%
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# CLK_BUF_CKSSCD R203 2 1 10K_0402_5%
PCH_GPIO26 V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P
+3V_PCH AE44 AR24 CLK_BUF_BCLK# CLK_PCH_14M R205 2 1 10K_0402_5%
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
PCH_GPIO44 AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
4 5 PCH_GPIO26 PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
3 6 PCH_GPIO44 AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
2 7 PCH_GPIO45 AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
1 8 PCH_GPIO46 PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
RP9 AJ44 CLKIN_SATA_P CLOCK TERMINATION for FCIM and need close to PCH
10K_0804_8P4R_5% CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
PCH_GPIO46 Y3 AM43 XTAL25_IN R198 1 2 GCLK_PCH_25MHZ
PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 GCLK_PCH_25MHZ <34>
XTAL25_OUT 0_0402_5%
AH43 XTAL25_OUT GCLK@
CLKOUT_ITPXDP C40
AH45 CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P F38
CLK_PCI_LPBACK 22_0402_5% 1 2 R209 CLK_PCI_LPBACK_R D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36
22_0402_5% 1 2 R211 CLK_PCI_EC_R E44 CLKOUTFLEX2/GPIO66
<32> CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67
CLK_PCI_DB_R B42 CLKOUTFLEX3/GPIO67 PCH_GPIO67 <18>
CLKOUT_33MHZ2 AM45 ICLK_IREF 1 R213 2
B ICLK_IREF +1.5VS B
F41 0_0402_5%
CLKOUT_33MHZ3 AD39
A40 TP19 AD38
CLKOUT_33MHZ4 TP18
AN44 PCH_CLK_BIASREF 1 R214 2
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
7.5K_0402_1%

DH82LPMS-QC4C-A1_FCBGA695~D 2 OF 11

XTAL25_IN

XTAL25_OUT 1 2
R215 1M_0402_5%

3 4
OSC NC
2 1
NC OSC
Y2
1 25MHZ_10PF_7V25000014 1
C118 C119
12P_0402_50V8J R02 12P_0402_50V8J
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

PCH_SMBCLK R190 1 @ 2 0_0402_5% SMB_CLK_S3

PCH_SMBDATA R200 1 @ 2 0_0402_5% SMB_DATA_S3

LPT_PCH_M_EDS
U4D
D Q11A D
2N7002DW-T/R7_SOT363-6 6 1 SMB_CLK_S3
N7 PCH_GPI011 2 R216 1 SMB_CLK_S3 <11,12,26>
SMBALERT#/GPIO11 +3V_PCH
LPC_AD0 A20 10K_0402_5%
<32> LPC_AD0 LAD_0
SMBus R10 PCH_SMBCLK DIMM1

2
LPC_AD1 C20 SMBCLK
<32> LPC_AD1 LAD_1
SMBDATA
U11 PCH_SMBDATA
+3VS DIMM2

5
LPC_AD2 A18
<32> LPC_AD2
MINI CARD

LPC
LAD_2 N8 PCH_GPIO60 2 R221 1
SML0ALERT#/GPIO60 +3V_PCH
<32> LPC_AD3 LPC_AD3 C18 1K_0402_5% 3 4 SMB_DATA_S3
LAD_3 U8 PCH_SML0CLK SMB_DATA_S3 <11,12,26>
2N7002DW-T/R7_SOT363-6
LPC_FRAME# B21 SML0CLK Q11B
<32> LPC_FRAME# LFRAME# R7 PCH_SML0DATA Q130A
+3VS D21 SML0DATA 2 R222 1 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2
LDRQ0# +3V_PCH EC_SMB_CK2 <22,29,32>
H6 PCH_HOT# 10K_0402_5%
2 1 10K_0402_5% G20 SML1ALERT#/PCHHOT#/GPIO74 PCH_HOT# <32>
R223
LDRQ1#/GPIO23 K6 SML1CLK VGA
Translator

2
SERIRQ AL11 SML1CLK/GPIO58
<32> SERIRQ SERIRQ
SML1DATA/GPIO75
N11 SML1DATA
+3VS EC

5
thermal sensor
AF11 3 4 EC_SMB_DA2
SPI_CLK_PCH_RAJ11 CL_CLK EC_SMB_DA2 <22,29,32>
2N7002DW-T/R7_SOT363-6
SPI_CLK AF10 Q130B
SPI_SB_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7 +3V_PCH
SPI_SB_CS1# AL7 CL_RST#
SPI_CS1#
AJ10
SPI_CS2#

2
SPI
BA45
SPI_SI AH1 TP1 R226 R227
SPI_MOSI BC45 2.2K_0402_5%
Thermal TP2 2.2K_0402_5%
C SPI_SO_R AH3 C
SPI_MISO BE43

1
SPI_IO2 AJ4 TP4 PCH_SML0CLK
SPI_IO2 BE44
SPI_IO3 AJ2 TP3 PCH_SML0DATA
SPI_IO3 AY43 PCH_TD_IREF 1 2
TD_IREF R228 8.2K_0402_1% +3VS

DH82LPMS-QC4C-A1_FCBGA695~D 3 OF 11 RP16
PCH_SMBDATA 8 1
SMB_CLK_S3 7 2

8MB SPI ROM FOR ME

+3V_PCH
SMB_DATA_S3 6 3
PCH_SMBCLK 5 4

+3VS
& Non-share ROM. +3VS
2.2K_0804_8P4R_5%

+3VS
R229 1 2 SPI_IO2
3.3K_0402_5% RP17
EC_SMB_CK2 8 1
R230 1 2 SPI_IO3 U7 EC_SMB_DA2 7 2
3.3K_0402_5% SPI_SB_CS1# 1 8 SML1DATA 6 3
CS# VCC +3V_PCH
SPI_SO_R 33_0402_5% 1 R233 2 SPI_SO1 2 7 SPI_HOLD#1 R239 1 2 33_0402_5% SPI_IO3 SML1CLK 5 4
SPI_IO2 33_0402_5% 1 R236 2 SPI_WP#1 3 SO HOLD# 6 SPI_CLK1 R234 1 2 33_0402_5% SPI_CLK_PCH_R
4 WP# SCLK 5 SPI_SI1 R235 1 2 33_0402_5% SPI_SI 2.2K_0804_8P4R_5%
GND SI
16M W25Q16DVSSIG SOIC 8P

B SPI_CLK_PCH_R B
U7 Rersver 4M+2M Solution
1

R237
33_0402_5%
@ +3VS
2

C121
1 2
C120
22P_0402_50V8J U8 0.1U_0402_16V4Z
@ SPI_SB_CS0# 1 8
SPI_SO_R 33_0402_5% 1 R238 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R245 1 2 33_0402_5% SPI_IO3
SPI_IO2 33_0402_5% 1 R246 2 SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH R240 1 2 33_0402_5% SPI_CLK_PCH_R
4 WP# SCLK 5 SPI_SI_R R241 1 2 33_0402_5% SPI_SI
R124;c190 close GND SI
to U4.T3 pin 32M W25Q32FVSSIQ SOIC 8P

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

D D

U4I LPT_PCH_M_EDS
USB DEBUG=PORT1 AND PORT9
AW31 B37 USB20_N0
AY31 PERN1/USB3RN3 USB2N0 D37 USB20_P0 USB20_N0 <35>
PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 <35> LEFT USB
BE32 USB2N1 C38 USB20_P1 USB20_N1 <35> (USB 3.0)
BC32 PETN1/USB3TN3 USB2P1 A36 USB20_N2 USB20_P1 <35> LEFT USB
PETP1/USB3TP3 USB2N2 C36 USB20_P2 USB20_N2 <35>
AT31 USB2P2 A34 USB20_N3 USB20_P2 <35> Touch panel
AR31 PERN2/USB3RN4 USB2N3 C34 USB20_P3 USB20_N3 <23>
PERP2/USB3RP4 USB2P3 B33 USB20_P3 <23> USB Camera
BD33
PETN2/USB3TN4
USB2N4
USB2P4
D33 EHCI1
BB33 F31
PETP2/USB3TP4 USB2N5 G31
USB2P5 K31
PCIE_PRX_DTX_N3 AW33 USB2N6 L31
<27> PCIE_PRX_DTX_N3 PERN_3 USB2P6
<27> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 AY33 G29
PERP_3 USB2N7 H29
LAN USB2P7
C122 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 BE34 A32
<27> PCIE_PTX_C_DRX_N3 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 BC34 PETN_3 USB2N8 C32
C124
<27> PCIE_PTX_C_DRX_P3 PETP_3 USB2P8 A30 USB20_N9
PCIE_PRX_DTX_N4 AT33 USB2N9 C30 USB20_P9 USB20_N9 <35>
<26> PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4 AR33 PERN_4 USB2P9 B29 USB20_N10 USB20_P9 <35> RIGHT USB
<26> PCIE_PRX_DTX_P4 PERP_4 USB2N10 USB20_N10 <26>
WLAN D29 USB20_P10 WLAN
1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 BE36 USB2P10 A28 USB20_N11 USB20_P10 <26>
C125
C <26> PCIE_PTX_C_DRX_N4 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BC36 PETN_4 USB2N11 C28 USB20_P11 USB20_N11 <33> C
C123 CARD READER
<26> PCIE_PTX_C_DRX_P4 PETP_4 USB2P11
USB2N12
G26 USB20_P11 <33> EHCI2

PCIe
AW36 F26

USB
AV36 PERN_5 USB2P12 F24
PERP_5 USB2N13 G24
BD37 USB2P13
BB37 PETN_5
PETP_5 AR26 USB3_RX1_N
AY38 USB3RN1 AP26 USB3_RX1_P USB3_RX1_N <35>
AW38 PERN_6 USB3RP1 BE24 USB3_TX1_N USB3_RX1_P <35>
PERP_6 USB3TN1 BD23 USB3_TX1_P USB3_TX1_N <35>
BC38 USB3TP1 AW26 USB3_TX1_P <35>
USB3_RX2_N
BE38 PETN_6 USB3RN2 AV26 USB3_RX2_N <35>
USB3_RX2_P
PETP_6 USB3RP2 BD25 USB3_RX2_P <35>
USB3_TX2_N
AT40 USB3TN2 BC24 USB3_TX2_P USB3_TX2_N <35>
AT39 PERN_7 USB3TP2 AW29 USB3_TX2_P <35>
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26
BC40 PETN_7 USB3TN5 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29
AN39 PERN_8 USB3RP6 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
PETN_8 CAD NOTE:
BD41 K24 USBRBIAS 1 R242 2
PETP_8 USBRBIAS# K26 22.6_0402_1%
Route single-end 50-ohms and max 500-mils length.
USBRBIAS Avoid routing next to clock pins or under stitching capacitors.
1 2 PCH_PCIE_IREF BE30 M33 Recommended minimum spacing to other signal traces is 15 mils.
+1.5VS PCIE_IREF TP24
R243 0_0402_5% L33
TP23
BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC1# USB_OC0# <35>
B OC1#/GPIO40 U2 USB_OC2# B
BB29 OC2#/GPIO41 P1 USB_OC3#
TP6 OC3#/GPIO42 M3 USB_OC4#
OC4#/GPIO43 T1 USB_OC5# USB_OC4# <35>
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6#
+1.5VS PCIE_RCOMP OC6#/GPIO10
R244 7.5K_0402_1% M1 USB_OC7#
OC7#/GPIO14

DH82LPMS-QC4C-A1_FCBGA695~D 9 OF 11

+3V_PCH
RP14
USB_OC1# 6 5
USB_OC2# 7 4 USB_OC4#
USB_OC5# 8 3 USB_OC7#
USB_OC3# 9 2 USB_OC6#
10 1 USB_OC0#
+3V_PCH

10K_1206_10P8R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
Weak internal pull-high
1 R247 2 10K_0402_5% EC_SMI#

1 R273 2 10K_0402_5% PCH_GPIO24 U4F LPT_PCH_M_EDS

D PCH_GPIO0 AT8 D
BMBUSY#/GPIO0
1 R248 2 10K_0402_5% PCH_GPIO1 F13
TACH1/GPIO1
+3VS 1 R249 2 10K_0402_5% PCH_GPIO6 A14
TACH2/GPIO6
G15 CPU/Misc
GPIO28 <32> EC_SCI# EC_SCI#
TACH3/GPIO7
On-Die PLL Voltage Regulator
EC_SMI# Y1

：
This signal has a weak internal pull up <32> EC_SMI# GPIO8 +1.05VS

* H
L ：On-Die voltage regulator enable (Default)
On-Die PLL Voltage Regulator disable
+3V_PCH
R02 1
1 R252@ 2 10K_0402_5%

R253 2 1K_0402_5%
PCH_GPIO12 K13

AB11
LAN_PHY_PWR_CTRL/GPIO12
TP14
AN10 GATEA20
GATEA20 <32> Check list requir 1K pull high, CRB 100 ohm@
GPIO15

2
+3V_PCH AY1 PCH_PECI_R 1 @ 2
<32> EC_LID_OUT# PECI H_PECI <32,5>
R256 PCH_GPIO16 AN2 0_0402_5% R255 R258
1 2 10K_0402_5% SATA4GP/GPIO16 AT6 KBRST#
RCIN# KBRST# <32> 100_0402_1%
GPIO
+3VS 1 R259 2 10K_0402_1% DGPU_PWROK C14
TACH0/GPIO17 @
R260 1 @ 2 1K_0402_5% PCH_GPIO28 AV3
H_CPUPWRGD <5>

1
PCH_GPIO22 BB4 PROCPWRGD
SCLOCK/GPIO22 AV1 PCH_THRMTRIP#_R 1 2
THRMTRIP# H_THRMTRIP# <5>
PCH_GPIO24 Y10 R262 390_0402_5%
GPIO24 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <5>
PCH_GPIO27 (Have internal Pull-High) PCH_GPIO27 R11
* High: VCCVRM VR Enable
GPIO27
VSS
N10
PCH_GPIO28 AD11
Low: VCCVRM VR Disable GPIO28
PCH_GPIO34 AN6
+3VALW GPIO34
1 R265 2 10K_0402_5% PCH_GPIO35 AP1
GPIO35/NMI#
R266 1 @ 2 10K_0402_5% PCH_GPIO36 AT3
SATA2GP/GPIO36
R267 1 @ 2 10K_0402_5% PCH_GPIO27 PCH_GPIO37 AK1
SATA3GP/GPIO37
PCH_GPIO38 AT7
C SLOAD/GPIO38 C

+3VS R268 1 2 10K_0402_5% PCH_GPIO39 AM3 A2

SDATAOUT0/GPIO39 VSS A41
+3VS +3VS PCH_GPIO48 AN4 VSS A43
SDATAOUT1/GPIO48 VSS A44
PCH_GPIO49 AK3 VSS B1
SATA5GP/GPIO49 VSS
1

R270 R271 B2
R272 1 2 10K_0402_5% PCH_GPIO57 U12 VSS B44
200K_0402_5% 200K_0402_5% +3V_PCH GPIO57 VSS B45
Need Update
@ @ ODD_EN C16 VSS BA1
<30> ODD_EN TACH4/GPIO68 VSS BC1
2

PCH_GPIO37 PCH_GPIO36 PCH_GPIO69 D13 VSS BD1

TACH5/GPIO69 VSS BD2
VSS
1

PCH_GPIO70 G13 BD44

TACH6/GPIO70 VSS BD45
Check Behavior VSS
R274 R275 PCH_GPIO71 H15 BE2
10K_0402_5% TACH7/GPIO71 VSS BE3
10K_0402_5%
VSS D1
2

BE41 VSS E1
BE5 VSS NCTF VSS E45
C45 VSS VSS A4
A5 VSS VSS
VSS
BIOS Request SKU ID
DH82LPMS-QC4C-A1_FCBGA695~D 6 OF 11
+3VS +3VS

10K_0402_5%
PCH_GPIO69 Function
@ R276
0
2

1
10K_0402_5%

10K_0402_5%

1
PCH_GPIO69
B R277 R278 B

10K_0402_5%
@ @ +3VS
1

@ R279
PCH_GPIO38 2 @ 1 PCH_GPIO16
R280 10K_0402_5%
PCH_GPIO67 2 1 PCH_GPIO49
Config GPIO16 & 49
PCH_GPIO67 <15>

1
R281 10K_0402_5%
USB3.0 x4, PCIE x8, SATA x6 11
2

1
10K_0402_5%

10K_0402_5%

2 1 PCH_GPIO16
PCH_GPIO38 PCH_GPIO67 Function R284 10K_0402_5%
R282 R283 2 @ 1 PCH_GPIO49
R285 10K_0402_5%
* USB3.0 x6, PCIE x8, SATA x4 01
+3VS +3VS
1

0 0 Optimus

2
10K_0402_5%

10K_0402_5%
PCH_GPIO70 Function
0 1 Reserved
0 @ R286 @ R287

1 0 DIS 1

1
PCH_GPIO71 PCH_GPIO70
PCH_GPIO71

2
1 1 UMA R288 R289
0 200K_0402_5% 200K_0402_5%
1 @ @

1
RP15
A A
PCH_GPIO48 6 5 +3VS
PCH_GPIO34 7 4 HDD_DET# HDD_DET# <13>
GATEA20 8 3 BBS_BIT0_R BBS_BIT0_R <13>
KBRST# 9 2 PCH_GPIO0
+3VS 10 1 PCH_GPIO22

10K_1206_10P8R_5%

Security Classification
2011/06/15
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

LH1
1_0603_1%

LH1
D +VCCADAC 2 1 D
+1.5VS
BLM18PG181SN1_0603
@

0.01U_0402_16V7K

0.1U_0402_10V7K

10U_0603_6.3V6M
1 1 1

C128
C126

C127
2 2 2

PCH Power Rail Table

U4G LPT_PCH_M_EDS

+1.05VS P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5 +1.05V_+1.5V_RUN
AA24 P43
AA26 VCC CRT DAC VSS
VCC VCC 1.05V 1.29 A
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 AD20 M31
VCC VCCADACBG3_3 +3VS +1.05VS
C129

C130

C131

C132
AD22
AD24 VCC
VCC VCCIO 1.05V 3.629 A
AD26 BB44
2 2 2 2 VCC VCCVRM

1U_0402_6.3V6K
AD28 1
VCC FDI

C134
AE18 AN34 VCCADAC1_5 1.5V 0.070 A
AE20 VCC VCCIO +3VS
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
AG18 VCC HVCMOS VCC3_3_R30 R32
VCC VCC3_3_R32

0.1U_0402_10V7K
AG20 1 VCCCLK 1.05V 0.306 A
AG22 VCC Y12 +PCH_USB_DCPSUS1 +3V_PCH
VCC DCPSUS1

0.1U_0402_10V7K

C135
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A

Core

C136
C AJ32 C
VCCSUS3_3 1
+1.05VS AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN VCCVRM 1.5V 0.179 A
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20 2
VCCASW VCCIO +1.05VS
U18 AK26 VCC3_3 3.3V 0.133 A
U20 VCCASW VCCVRM AK28 +1.05V_+1.5V_RUN
VCCASW VCCVRM
22U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 U22
VCCASW
C137

C138

C139

U24 BE22 VCCASW 1.05V 0.67 A

V18 VCCASW VCCVRM
PCIe/DMI
V20 VCCASW AK18 +1.05V_+1.5V_RUN
2 2 2 VCCASW VCCIO +1.05VS
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
Y18 VCCASW VCCVRM
Y20 VCCASW SATA AK22
VCCASW VCCIO VCCSPI 3.3V 0.022 A
Y22 +1.05VS
VCCASW AM18
VCCIO AM20
VCCIO VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
VCCIO

C143

C144

C145

C146

C147
AT22
VCCIO

2 2 2 2 2
V_PROC_IO 1.05V 0.004 A
DH82LPMS-QC4C-A1_FCBGA695~D 7 OF 11

1 2 +PCH_VCCDSW +1.5VS +1.05V_+1.5V_RUN

R290 5.1_0402_1% +1.05VS
+PCH_VCCDSW_R

B B
R291 2 1 0_0603_5% +PCH_USB_DCPSUS1 1 R292 2
0_0402_5%
+1.05VS @

10U_0603_6.3V6M
1

C148
R293 2 @ 1 0_0603_5% @

2
1U_0402_6.3V6K

1
C149

+1.05VS
2
+PCH_USB_DCPSUS3 2 R294 1
0_0603_5%
@

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1

C150

C151
2 @ 2 @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
+PCH_VCCDSW3_3

1 R307 2 +3VALW
LPT_PCH_M_EDS
U4H 0_0402_5%

0.1U_0402_10V7K
1
D +3V_PCH D

C154

0.1U_0402_10V7K
1
R24 R20
VCCSUS3_3 VCCSUS3_3 2

C155
R26 R22
R28 VCCSUS3_3 VCCSUS3_3
+1.05VS VCCSUS3_3 GPIO/LPC 2
0.1U_0402_10V7K

1 U26
VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3 +3VS PCH Power Rail Table
C152

M24
VSS AA14 +PCH_VCCSST 1 2
2 +3VS U35 DCPSST C156 0.1U_0402_10V7K
VCCUSBPLL
0.1U_0402_10V7K

1 AE14 Voltage Rail Voltage S0 Iccmax Current (A)

USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
C153

AG14
VCC3_3 +3V_PCH

0.1U_0402_10V7K
U30 1 VCC 1.05V 1.29 A
2 0.1U_0402_10V7K +1.05VS V28 VCCIO
1 VCCIO

C158
V30 U36
VCCIO VCCIO +1.05VS
C157
Y30 VCCIO 1.05V 3.629 A
VCCIO +3V_PCH 2
2 +1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2
1U_0402_6.3V6K

0.1U_0402_10V7K
1 A26 1 VCCADAC1_5 1.5V 0.070 A
VCCSUSHDA
C159
AF34
VCCVRM

C160
+RTCVCC

10U_0603_6.3V6M

1U_0402_6.3V6K
1 +PCH_VCC AP45 K8 1 VCCADAC3_3 3.3V 0.0133 A
2 VCC VCCSUS3_3 2

C140

C162
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC C163
2 RTC 2
VCCCLK 1.05V 0.306 A
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC 0.1U_0402_10V7K
VCCCLK3_3 DCPRTC

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
P16 1 2 1 1 1
DCPRTC

C166
L29 VCCCLK3_3 3.3V 0.055 A
VCCCLK3_3

C164

C165
L26 AJ12 +PCH_VPROC
M26 VCCCLK3_3 V_PROC_IO AJ14 +3VS 2 2 2
VCCCLK3_3
CPU
V_PROC_IO VCCVRM 1.5V 0.179 A
+1.05VS U32
VCCCLK3_3

ICC
V32 AD12 VCC3_3 3.3V 0.133 A
C
1 R314 2 +PCH_USB_DCPSUS2 VCCCLK3_3 SPI VCCSPI C

1U_0402_6.3V6K
0_0402_5% +PCH_VCCCLK AD34 1
VCCCLK

C167
@ P18 +PCH_VCCCFUSE VCCASW 1.05V 0.67 A
VCC
1U_0402_6.3V6K

1 AA30 P20
VCCCLK VCC
C168

AA32
@ VCCCLK L17 2
VCCASW +1.05VS VCCSUSHDA 3.3V 0.01 A
AD35
2 VCCCLK R18
AG30 VCCASW R297 +1.05VS
VCCCLK VCCSPI 3.3V 0.022 A
AG32 0_0805_5%
VCCCLK AW40 +PCH_VPROC 1 2
VCCVRM +1.05V_+1.5V_RUN
AD36 VCCSUS3_3 3.3V 0.261 A
+1.05VS VCCCLK AK30 +3VS
VCC3_3

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
AE30 Thermal 1 1 1
VCCCLK

C171
LH2 AE32 AK32 VCCDSW3_3 3.3V 0.015 A
VCCCLK VCC3_3

C169

C170
1 2 +PCH_VCC

0.1U_0402_10V7K
4.7UH_LQM18FN4R7M00D_20% 1 2 2 2
V_PROC_IO 1.05V 0.004 A
10U_0603_6.3V6M

1U_0402_6.3V6K

C173
1 1 DH82LPMS-QC4C-A1_FCBGA695~D 8 OF 11
C172

C174

@ 2

2 2

Place near pin AP45

0_0805_5%
+PCH_VCCCFUSE R299 1 2 +1.05VS
+1.05VS R300 +PCH_VCCCLK @
0_0805_5%

1U_0402_6.3V6K
1 2 1 0_0805_5%

C175
R301 1 2 +3VS
B B

2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1
C176

C177

C178

C179

C180
@
2 2 2 2 2

Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32

+3VS +PCH_VCCCLK3_3
R302
0_0805_5%
1 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
C181

C182

C183

C184
2 2 2 2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

D D

U4J LPT_PCH_M_EDS

AL34 K39 U4K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
C AN8 VSS VSS P30 AD14 VSS VSS AY36 C
AP13 VSS VSS P32 AD16 VSS VSS AT43
AP24 VSS VSS R12 AD18 VSS VSS BD31
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
AV31 VSS VSS V16 AJ20 VSS VSS H13
AV33 VSS VSS V26 AJ22 VSS VSS H17
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B B11 VSS VSS BC22 VSS VSS K33 B
B15 VSS BB42 VSS VSS BC28
VSS VSS VSS

DH82LPMS-QC4C-A1_FCBGA695~D DH82LPMS-QC4C-A1_FCBGA695~D
10 OF 11 11 OF 11

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_PS
RT1
RTD2132R LDO MODE
80mil 0_0805_5% 80mil @
1 2 +SWR_V12 1 R551 2 +SWR_LX
0_0805_5%
+3VS_PS
Close to Pin3 UT2
19
TXEC+ LVDS_ACLK <23>
+DP_V33 LT1 2 1 +DP_V33 40mil 3 20
LVDS_ACLK# <23>
FBMA-L11-201209-221LMA30T_0805 DP_V33 TXEC-
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z 60mil 13 21
SWR_VDD TXE2+ LVDS_A2 <23>

Power
D LT2 2 1 +SWR_VDD 18 22 D
1 1 1

LVDS
PVCC TXE2- LVDS_A2# <23>
FBMA-L11-201209-221LMA30T_0805
CT1

CT2

CT3
+SWR_V12 LT3 1 2 +SWR_LX 20mil 12 23
LVDS_A1 <23>
SWR_LX TXE1+
2 2 2
4.7UH_PG031B-4R7MS_1.1A_20% 60mil 11 SWR_VCCK TXE1-
24
LVDS_A1# <23>
27
7 VCCK 25
DP_V12 TXE0+ LVDS_A0 <23>
26
TXE0- LVDS_A0# <23>

RTD2132S TL_ENVDD need 40 mil if use for LVDS power on R version

C190 1 2 0.1U_0402_10V6K EDP_CPU_AUX_R 2
<7> EDP_CPU_AUX AUX_P

DP-IN
C191 1 2 0.1U_0402_10V6K EDP_CPU_AUX#_R 1 14

GPIO
<7> EDP_CPU_AUX# AUX_N GPIO(PWM OUT) TL_INVT_PWM <23>
Close to L87 Close to Pin18 15
GPIO(Panel_VCC) TL_ENVDD <23>
C192 1 2 0.1U_0402_10V6K EDP_CPU_LANE_P0_R 5 16
<7> EDP_CPU_LANE_P0 LANE0P GPIO(PWM IN) PCH_PWM <14>
+SWR_VDD C193 1 2 0.1U_0402_10V6K EDP_CPU_LANE_N0_R 6 17 ENBKL <32>
<7> EDP_CPU_LANE_N0 LANE0N GPIO(BL_EN)
10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 9 LVDS 29
<16,29,32> EC_SMB_CK2 CIICSCL1 MIICSCL1 EDID_CLK <23>
10 28
<16,29,32> EC_SMB_DA2 CIICSDA1 EDID MIICDA1 EDID_DATA <23>
CT4

CT5

CT6

CT7

CT8

Other
2 2 2 2 2 32 ROM 31 MIIC_SCL
<7> TL_HPD HPD MIICSCL0 30 MIIC_SDA
8 MIICSDA0 ADD TP on trace or via
4 DP_REXT 33
DP_GND GND

2
Close to Pin13
RT8 RTD2132R-VE-CG_QFN32_5X5
12K_0402_1%

1
Close to L29 +3VS_PS
C C
+SWR_V12 EDID_DATA RT9 1 2 4.7K_0402_5%
22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

EDID_CLK RT10 1 2 4.7K_0402_5%

1 1 1 1
CT9

CT10

CT11

CT12

2 2 2 2

Close to
Pin27
Close to Pin7

+3VS_PS +3VS_PS
ENBKL

2
RT4 RT11
4.7K_0402_5% @ 4.7K_0402_5%

2
R438

1
100K_0402_1% MIIC_SCL MIIC_SDA

2
RT5 RT12
@ 4.7K_0402_5% 4.7K_0402_5%
B B

1
MIIC_SDA
MIIC_SCL
0 1

0 X EC CODE

1 Internal ROM EEPROM

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

W=60mils W=60mils @
+3VS +LCDVDD_CONN +3VS 2 1
U72 R686 0_0402_5%
1 +LCDVDD_CONN (20 MIL)
5 VOUT +3VS_CMOS

4.7U_0603_6.3V6K
VIN Q83
1
PMV65XP_SOT23-3~D

C516
D @ 2 1 1 D
C538 2 1 4 GND @
SS (20 MIL)

D
0.1U_0402_16V4Z R685 0_0402_5% C517 3 1 10U
2 3 0.1U_0402_16V4Z
@ 1 EN 2 2 1 1
CMOS@ CMOS@
C4 APL3512ABI-TRG_SOT23-5 C518 C519 @

G
2
1500P_0402_50V7K 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
2 CMOS@ 2 2
<22> TL_ENVDD 150K_0402_5%
<32> CMOS_ON#
R435
1
R296 for CMOS shake issue reserve
C520 CMOS@
+LCDVDD_CONN 0.1U_0402_16V4Z

1
2
W=60mils
@ R408
100K_0402_5%
TL_ENVDD @ R553
@1 2

2
0_0805_5%

VGA LCD/PANEL BD. Conn.

Vendor suggest reserve
C C
RTD2132R Internal load switch for +LCD_VCC +LEDVDD B+
R813
0_0805_5%
1 2
1 1
C539 @
680P_0402_50V7K C541
@ 4.7U_0805_25V6-K
BKOFF# 2 2
1

JLVDS1
R716 1
2 1 31
10K_0402_5% 2 G1
3 32
R441 1 2 0_0402_5% 4 3 G2 33
<22> TL_INVT_PWM
2

5 4 G3 34
6 5 G4
<32> BKOFF# 6
BKOFF# 7
INVT_PWM 8 7
9 8
10 9
<22> LVDS_ACLK 10
<32> EC_INVT_PWM R431 1 @ 2 0_0402_5% 11
<22> LVDS_ACLK# 11
12
13 12
B B
<22> LVDS_A2 13
14
<22> LVDS_A2# 14
15
<22> LVDS_A1 15
16
<22> LVDS_A1# 16
17
<22> LVDS_A0 18 17
<22> LVDS_A0# 18
<22> EDID_DATA 19
20 19
<22> EDID_CLK 20
+3VS 21
22 21
1 +LCDVDD_CONN 22
(60 MIL) 23
680P_0402_50V7K 24 23
+3VS 24
C540@ 25
2 26 25
+3VS_CMOS 26
USB20_P3 R688 2 1 0_0402_5% USB20_P3_R 27
USB20_N3 R684 2 1 0_0402_5% USB20_N3_R 28 27
29 28
30 29
30
CMOS 4 3 USB20_P3_R
4 3 ACES_88341-3001 ME@
<17> USB20_P3
<17> USB20_N3
1 2 USB20_N3_R
1 2
L58 WCM-2012-900T_4P
A A
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 23 of 60
5 4 3 2 1
 A B C D E

CRT Connector
1 1

FCM1608CF-121T03 0603
1 2 RED
<14> DAC_RED
L30
FCM1608CF-121T03 0603 +5V_Display
1 2 GREEN
<14> DAC_GRN
L31
FCM1608CF-121T03 0603 CONTE_80431-5K1-152
1 2 BLUE
<14> DAC_BLU

C522

C523

C524

C525

C526

C527
L32 JCRT1 ME@

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1 1 1 1 1 1 6
RP22 PAD T66 NC11 11
4 5 DAC_BLU RED 1
3 6 DAC_GRN 7
2 7 DAC_RED 2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
1 8 GREEN 2
8 G 16
150_0804_8P4R_5% JVGA_HS 13 17
BLUE 3 G
9
JVGA_VS 14
4
2 10 2
CRT_DDC_CLK_CONN 15
5
1
C528

100P_0402_50V8J
2

+5VS

1 1
C529 C531
U10
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_Display

2 3 RED
+3VS VCC_VIDEO VIDEO1

1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<14> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3

2
3 3
0.1U_0402_16V4Z
2 11 9 CRT_DDC_DAT_CONN
<14> CRT_DDC_CLK DDC_IN2 DDC_OUT1

13 12 CRT_DDC_CLK_CONN
<14> CRT_VSYNC SYNC_IN1 DDC_OUT2

15 14 JVGA_VS
<14> CRT_HSYNC SYNC_IN2 SYNC_OUT1

6 16 JVGA_HS
GND SYNC_OUT2

TPD7S019-15DBQR_SSOP16

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: W ednesday, October 03, 2012 Sheet 24 of 60
A B C D E
 5 4 3 2 1

+5V_Display
U73

+5VS 3
W=40mils
L35 HDMI@ OUT
1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN 1
1 2 IN C543
1
2
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN C544 GND 0.1U_0402_16V4Z 2
D 4 3 D
WCM-2012HS-900T 0.1U_0402_16V4Z 2 AP2330W-7_SC59-3
+3VS
L36 HDMI@
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN
1 2

2
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN R485
4 3 1M_0402_5% Q93
WCM-2012HS-900T HDMI@ HDMI@

2
G
2N7002H_SOT23-3

1
L37 HDMI@
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN TMDS_B_HPD# 3 1
1 2 <14> TMDS_B_HPD#

D
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN
4 3

2
WCM-2012HS-900T R488
20K_0402_5%
L38 HDMI@ HDMI@
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN JHDMI1 ME@

1
1 2 HDMI_DET 19
18 HP_DET
+5V_Display +5V_Display +5V
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 17
C 4 3 DDC/CEC_GND C
HDMIDAT_R 16
WCM-2012HS-900T +3VS RP21 HDMICLK_R 15 SDA
8 1 HDMIDAT_R 14 SCL
7 2 HDMICLK_R 13 Reserved
6 3 HDMIDAT_NB HDMI_CLK-_CK R465 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
<7> HDMI_CLK-_CK CK- G1
5 4 HDMICLK_NB 11 21
+3VS <7> HDMI_CLK+_CK CK_shield G2
HDMI_CLK+_CKR464 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 22
2.2K_0804_8P4R_5% HDMI_TX0-_CK R467 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 CK+ G3 23
<7> HDMI_TX0-_CK D0- G4
HDMI@ 8
<7> HDMI_TX0+_CK D0_shield
HDMI_TX0+_CK R466 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7
HDMI_TX1-_CK R469 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6 D0+
<7> HDMI_TX1-_CK D1-
Q63A <7> HDMI_TX1+_CK 5
HDMI@ HDMI_TX1+_CK R468 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
D1+
2

2N7002DW-T/R7_SOT363-6 <7> HDMI_TX2-_CK HDMI_TX2-_CK R471 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3

2 D2-
<7> HDMI_TX2+_CK D2_shield
1 6 HDMICLK_R HDMI_TX2+_CK R470 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
<14> HDMICLK_NB D2+
5

SUYIN_100042GR019M23DZL

<14> HDMIDAT_NB 4 3 HDMIDAT_R

RP19
Q63B HDMI_CLK-_CONN 1 10
HDMI@ HDMI_CLK+_CONN 2 9 HDMI_TX0+_CONN
B 2N7002DW-T/R7_SOT363-6 HDMI_TX1-_CONN 3 8 HDMI_TX0-_CONN B
HDMI_TX1+_CONN 4 7 HDMI_TX2+_CONN
5 6 HDMI_TX2-_CONN

680_1206_10P8R_5%
HDMI@

@ D32 @ D28 @ D29

HDMICLK_R 9 10 1 1 HDMICLK_R HDMI_TX1+_CONN 9 10 1 1 HDMI_TX1+_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN

HDMIDAT_R 8 9 2 2 HDMIDAT_R HDMI_TX1-_CONN 8 9 2 2 HDMI_TX1-_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN

+3VS
HDMI_DET 7 7 4 4 HDMI_DET HDMI_CLK+_CONN 7 7 4 4 HDMI_CLK+_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN

1
D
6 6 5 5 HDMI_CLK-_CONN 6 6 5 5 HDMI_CLK-_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN 2
G
3 3 3 3 3 3 S Q95

3
HDMI@
8 8 8 2N7002H_SOT23-3

YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 25 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

1 1

+3VS_WLAN

+3VS 80mil +3VS_WLAN

J6 1 1

@
C548@ C547@
Mini-Express Card(WLAN/WiMAX) 1
1 2
2
+1.5VS
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2 2
JUMP_43X79
EMI reserve
JWLN1
PCIE_WAKE# 1 2
<14,27> PCIE_WAKE# 1 2
3 4
5 3 4 6
<32> EC_BT_ON# 5 6
<15> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<15> CLK_PCIE_WLAN1# 11 12
13 14
<15> CLK_PCIE_WLAN1 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 EC_WL_OFF# <32>
21 22 PLT_RST# <14,27,32>
23 24 +3VS_WLAN
2 <17> PCIE_PRX_DTX_N4 25 23 24 26
2
<17> PCIE_PRX_DTX_P4 25 26
27 28 R02
Need check module behavior 29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <11,12,16>
31 32 1 R502 2 @ 0_0402_5%
<17> PCIE_PTX_C_DRX_N4 31 32 SMB_DATA_S3 <11,12,16>
33 34
<17> PCIE_PTX_C_DRX_P4 35 33 34 36
+3VS_WLAN 35 36 USB20_N10 <17>
37 38
39 37 38 40 USB20_P10 <17>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<32,33> EC_TX 1 2 51 49 50 52
<32,33> EC_RX 51 52
R506
100_0402_1% 53 54
GND1 GND2

<32> INTEL_BT_OFF#
BELLW_80003-8041

2
ME@
R507
100K_0402_5%

3 For EC to detect 3

1 debug card insert.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 26 of 60
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN
+LX
Layout Notice : Place as close Close together
chip as possible. J10

@
LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +1.1_DVDDL 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P

1000P_0402_50V7K
1 2 1 2

10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +1.1_DVDDL

0.1U_0402_16V4Z
JUMP_43X79

CL1

CL2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
D 1 1 D

CL4

CL5

CL6
Note: Place Close to LAN chip 1 1 1
3 1

D
2 2 LL1 DCR< 0.15 ohm

CL3
GCLK@
GCLK@ Rate current > 1A
RL3 2 2 2
QL1

G
2
LAN_PWR_ON# 2 1 PMV65XP_SOT23-3~D
<32> LAN_PWR_ON# 10U
2
GCLK@
10K_0402_5% CL7 SWR@SWR@SWR@
1
0.1U_0402_16V7K Place close to Pin34
Close to
Pin40

Vendor recommand reseve the UL1 8162@

PU resistor close LAN chip

RL4 1 2 4.7K_0402_5%
+3V_LAN
AR8162-AL3A-R
@
PLT_RST#
<14,26,32> PLT_RST#
SA000065400 S IC QCA8172-AL3A-R QFN 40P E-LAN CTRL
SA000052J10 S IC AR8162-AL3A-R QFN 40P E-LAN CTRL
C C

UL1
Place Close to Chip
CL9 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N3 29 38 RL12 10K_0402_5%
<17> PCIE_PRX_DTX_N3 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P3 30
Atheros LED_1 23
<17> PCIE_PRX_DTX_P3 TX_P LED_2
AR8151/AR8161
36
<17> PCIE_PTX_C_DRX_N3 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <28>
MDI0+
<17> PCIE_PTX_C_DRX_P3 RX_P TRXP0 15 MDI1- MDI0+ <28>
TRXN1 MDI1- <28>
32 14 MDI1+
<15> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <28>
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17
RL6 1 @ 2 0_0402_5% PLT_RST# 2 TRXP2 21
<14,26> PCIE_WAKE# PERST# TRXN3 20
RL7 1 2 0_0402_5% 3 TRXP3 Place Close to PIN1
<32> LAN_WAKE# W AKE#
25 10 LAN_RBIAS 1 2 +3V_LAN
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33

CL12

CL13

CL14

CL15

CL16
27

1000P_0402_50V7K

10U_0603_6.3V6M

10U_0603_6.3V6M
Vendor recommand reseve the

0.1U_0402_16V4Z

1U_0402_6.3V4Z
TESTMODE 1 1 1 1

2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7

1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
@
B B
4
<15> CLKREQ_LAN# CLKREQ# 24 @ @
DVDDL/PPS 37 +1.1_DVDDL 10U +3V_LAN
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16
AVDDL AVDDH/AVDD33 +3V_LAN
+1.1_AVDDL_L 34 22 +2.7_AVDDH EMI reserve
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
CL17

CL18

CL19

CL20

CL21
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 CL22

CL23

CL24

CL25

CL26

CL10

CL8
@ 41 1 1 1 1 1 1 1
GND

QCA8172-AL3A-R_QFN40_5X5 @ @
2 2 2 2 2
Near 2 2 2 2 2
@
2 2
Pin6 8172@

Place close to Pin16

@ Near
Near Near Near RL13 1 2 0_0402_5% Near Near
<34> GCLK_LAN_25MHZ Pin9
Pin13 Pin19 Pin31 Pin22 Pin37
1
CL27
value shoud be discuss 5P_0402_50V8C
2 @
ORB 5P LAN_XTALI

A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 1
CL28 25MHZ_10PF_7V25000014CL29 NOGCLK@
15P_0402_50V8J 15P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
NOGCLK@ 2011/06/15 2012/07/11 Title
2 NOGCLK@ 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8162/8172
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7982P
Date: Wednesday, October 03, 2012 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3

DL1 2
GND VDD
5

1'S PN:SC300001G00
D D
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-

RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V

2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<27> MDI0+ TD+ TX+
MDI0- 2 15 MDO0- GAS@
<27> MDI0- 3 TD- TX- 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
1 6 11 MCT
MDI1+ 7 CT CT 10 MDO1+
<27> MDI1+ 8 RD+ RX+ 9
CL31 MDI1- MDO1-
<27> MDI1- RD- RX-
0.01U_0402_16V7K
2
MHPC_NS681612A
C C

CL63 1 2 0.1U_0603_50V7K

CL61 1 2 0.1U_0603_50V7K

Need check Symbol CHASSIS1_GND

JLAN1
MDO0+ 1
PR1+
MDO0- 2
PR1-
MDO1+ 3
PR2+
MCT 4
PR3+
5
PR3-
B B
MDO1- 6
PR2-
MCT 7 9
PR4+ GND 10
8 GND
PR4-
SANTA_130456-121

ME@

CHASSIS1_GND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7982P
Date: Wednesday, October 03, 2012 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

D +3VS D

2
C329
0.1U_0402_16V4Z
@
1
U9 THERMAL@
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <16,22,32>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <16,22,32>
C587 @
2200P_0402_50V7K REMOTE1- 3 6
2 D- ALERT#

+3VS 1 R335 2 4 5
THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P

EMC1412-A (SA00003YA00)
Address 1111_100xb
S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
REMOTE1,2+/-:
C C
Trace width/space:10/10 mil
Trace length:<8"

CPU
H1 H2 H3
HOLEA HOLEA HOLEA

B FD1 FD2 FD3 FD4 B

1
H_3P8 H_3P8 H_3P8

A
B M/B 橢橢橢 M/B 橢橢
FAN1 Conn H7
HOLEA
H8
HOLEA
H9
HOLEA
H10
HOLEA
H11
HOLEA
H12
HOLEA
H18
HOLEA H16
H17
HOLEA
HOLEA
+5VS

1
1
R581 JFAN1
2 1 0_0603_5% 1
2 1 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P5X3P5N H_3P0N
<32> EC_TACH 3 2
<32> EC_FAN_PWM 3
4
A 2 5 4
G5 2P8 * 7 pcd D A
6
C591 G6 E
10U_0603_6.3V6M ACES_85205-04001
1 ME@ Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
10U Fintek-Thermal IC/FAN/screw
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 29 of 60
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

JHDD1
1
0.01U_0402_25V7K 2 1 C116 SATA_PTX_DRX_P4 2 GND
<13> SATA_PTX_C_DRX_P4 RX+
<13> SATA_PTX_C_DRX_N4 0.01U_0402_25V7K 2 1 C114 SATA_PTX_DRX_N4 3
4 RX-
SATA_DTX_C_IRX_N4 C596 1 2 0.01U_0402_25V7K SATA_DTX_PRX_N4 5 GND
<13> SATA_DTX_C_PRX_N4 SATA_DTX_C_IRX_P4 C597 1 2 0.01U_0402_25V7K SATA_DTX_PRX_P4 6 TX-
<13> SATA_DTX_C_PRX_P4 7 TX+
GND

1 1

8
9 3.3V
10 3.3V
11 3.3V
12 GND
R550 13 GND
0_0805_5% 14 GND
1 2 +5V_HDD 15 5V
+5VS 5V
16
17 5V
18 GND
19 Reserved
+5V_HDD 10U +3VS 20 GND 23
R02 21 12V GND 24
22 12V GND
12V
1 1 1 1 1
@ SUYIN_127043FB022G278ZR
C598 C599 C600 @ C602 C603
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z
2 2 2 2 2

2
ODD Power Control 2

@ J9
1 2
1 2 +5V_ODD FOR 15"
EMI reserve
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
S

3 1 JODD2
1 1
1
1

Q99 @ <13> SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_P5 15@ C605 1 2 0.01U_0402_25V7K SATA_PTX_DRX_P5_15 2

R552 @ PMV65XP_SOT23-3~D C604 SATA_PTX_C_DRX_N5 15@ C606 1 2 0.01U_0402_25V7K SATA_PTX_DRX_N5_15 3 2
G

<13> SATA_PTX_C_DRX_N5
2

@ R568 10K_0402_5% @ 0.1U_0402_16V4Z 4 3

10K_0402_5% R675 @ 2 SATA_DTX_C_PRX_N5 15@ C618 1 2 0.01U_0402_25V7K SATA_DTX_PRX_N5_15 5 4
100K_0402_5% <13> SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5 15@ C617 1 2 0.01U_0402_25V7K SATA_DTX_PRX_P5_15 6 5
1
2

1 2 <13> SATA_DTX_C_PRX_P5 1 2 ODD_DETECT# 7 6

C608 R710 @ 0_0402_5% +5V_ODD 8 7
8
1

1 10U_0603_6.3V6M 9
2 ODD_DA# 10 9
OUT

C607 @ <14,32> ODD_DA# R02 10 11

GND 12
0.01U_0402_25V7K GND
2 2 1 R555 2
<18> ODD_EN IN +3VS
10K_0402_5%
GND

Q100 @ HB_A051020-SAHR21
DTC124EKAT146_SC59-3
3

ME@

3 Co-lay 3

FOR 14"
SATA ODD Conn.
JODD1

1
SATA_PTX_C_DRX_P5 14@ C616 1 2 0.01U_0402_25V7K SATA_PTX_DRX_P5_14 2 GND
SATA_PTX_C_DRX_N5 14@ C615 1 2 0.01U_0402_25V7K SATA_PTX_DRX_N5_14 3 A+
4 A-
SATA_DTX_C_PRX_N5 14@ C614 1 2 0.01U_0402_25V7K SATA_DTX_PRX_N5_14 5 GND
SATA_DTX_C_PRX_P5 14@ C613 1 2 0.01U_0402_25V7K SATA_DTX_PRX_P5_14 6 B-
7 B+
GND

ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V
ODD_DA# 11 +5V
12 MD 15
13 GND GND 14
GND GND

4 SANTA_205504-1 4

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 30 of 60
A B C D E F G H
 5 4 3 2 1

CX20751 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1%
Amplifier. +3VS

An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%

mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.

An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1% Don't support LINE_IN function
voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
RA7 could be @
+VREF_1V65 CA3 vendor suggest
D D
change to 2.2U
+LDO_OUT_3.3V

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS

2.2U_0603_6.3V4Z
1 1 2 1 AVDD_3.3 pinis output of

CA1

CA2

CA4
internal LDO. NOT connect

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

CA3
1 1 to external supply.

CA5

CA6
2 2 1 2

2 @ 2

+3VS
+3VS

1U_0603_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1

CA8

CA9
1 1
Should be same supply rail as used for

CA15

CA10
PCH HDA bus controller section @
For EMI @ 2 2
2 2
Layout Note:Path from +5VS to LPWR_5.0
Near Audio Chip
RPWR_5.0 must be very low
+3VS resistance (<0.01 ohms)
RA3
+3VS
1 @ 2 0_0402_5%
1

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
+5VS
RA15 +3V_PCH
1 2 1 1
4.7K_0402_5% +LDO_1.8V

CA16

CA17

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+5VS
RA4 0_0402_5% 1 1

CA18

CA19
10 mils

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

@ 2 2
1 1 1 1
HDA_RST_AUDIO#

CA20

CA21

CA22

CA23
@

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 2
1 1 1

CA24

CA25
@ @
CA11 2 2 2 2 Check footprint
C 0.1U_0402_16V4Z C

0.1U_0402_16V4Z
2 2 2

18

29

27
28
24
1

3
7
2
UA1

CA26
FILT_1.8

VDDO_3.3
DVDD_3.3

AVDD_3.3
VDD_IO

VREF_1.65V

AVDD_5V
AVDD_HP
2
Please bypass caps very close to device. HGNDA, HGNDB 80mils
13
LPWR_5.0 16
HDA_RST_AUDIO# 9 RPWR_5.0 11
<13> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5
<13> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE CA28
<13> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% 6 APPLE_MIC RA16 1 2 100_0402_1% 1 2 HGNDB
<13> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 34 +MICBIASB 1U_0402_6.3V4Z
<13> HDA_SDOUT_AUDIO SDATA_OUT MICBIASB 35 +MICBIASC JHP1
MICBIASC CA27 4
PC_BEEP 10 32 MICB_L NOKIA_MIC RA12 1 2 100_0402_1%1 2 1U_0402_6.3V4Z HGNDA 3
39 PC_BEEP PORTB_L_LINE 33 MICB_R HP_L RA13 1 2 15_0402_5% HPOUT_L 1
<32> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack RA14 1 2 15_0402_5% 2
using wide copper bridge HP_R HPOUT_R
under codec (100 mils or more) 30 APPLE_MIC External MIC
PORTD_A_MIC 31 NOKIA_MIC PLUG_IN 5
1 2 1 PORTD_B_MIC 25 HGNDA
<32> EAPD DMIC_DAT/GPIO1 HGNDA
RA11 0_0402_5% 40 26 HGNDB 6
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB CA36
MICB_L RA17 1 2 100_0402_1% 1 2 HP_L SINGA_2SJ2352-000131F
Internal analog MIC MIC_IN 36 22 HP_L 1U_0402_6.3V4Z
37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R CA46
GPIO1/PORTC_R_MIC PORTA_R Headphone MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
ME@
CA64 1 2 @ 0.1U_0402_16V4Z 1U_0402_6.3V4Z
RA20 1 2 3K_0402_5%
SPK_L2+ 12
CA65 1 2 @ 0.1U_0402_16V4Z SPK_L1- 14 LEFT+ RA19 1 2 3K_0402_5% Pin Ref
LEFT- +MICBIASB

Internal SPEAKER 21 1:L

CA66 1 2 @ 0.1U_0402_16V4Z SPK_R2+ 17 AVEE 19 2:R
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 3:GND/MIC

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V4Z 4:MIC/GND
1 2 for Universal jack

CA35

CA30
5:normal open
GND

CA7
B
6:GND B
1 2 HDA_BITCLK_AUDIO
2 1
41

@ RA21 CX20757-11Z_QFN40
22P_0402_50V8J 33_0402_5% HPOUT_L
@
EMI request reserve RA21 & CA7 HPOUT_L
HPOUT_R
HPOUT_R
CA30 vendor suggest HGNDB
follow vendor suggest change to 2.2U HGNDB
& reserver default design HGNDA
Place colose to Codec chip HGNDA

2
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3
+MICBIASC

1
CA31

CA32

CA33

CA34
@ @
1

DA1 DA2
PC Beep

2
RA23
2.2K_0402_5% @ @ @ @
EC Beep 1 2 RA492
<32> BEEP#
2

1
CA37 0.1U_0402_16V4Z 1 2 PC_BEEP MIC1 CA41 1U_0603_10V4Z LA1 LA2
<13> HDA_SPKR
1 2 33_0402_5% 1 EXT_MIC 1 2 MIC_IN 0_0603_5% 0_0603_5%
CA45 0.1U_0402_16V4Z 2 GNDA
ICH Beep LA3 LA4 LA1~LA4 vendor suggest mount 0 ohm first~
1 1
WM-64PCY_2P 0_0603_5% 0_0603_5% Bead reserve for EMI if needed
0.1U_0402_16V4Z

0.1U_0402_16V4Z

JSPK1
1

45@ CA41 vendor suggest

change to 1U SPK_R1- LA1 @1 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1
RA22 2 2 SPK_R2+ LA2 @1 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 2 1
LA3 @1 2 3 2
CA42

CA44

10K_0402_5% SPK_L1- FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN

SPK_L2+ LA4 @1 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 4 3
2

5 4
@ @ 6 G5
wide 20MIL

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
G6
1 1 1 1
vendor suggest

CA38

CA39

CA40

CA43
+5VS ME@
A change to 1000p A
@
DA3 2 @ 2 @ 2 @ 2 ACES_85205-04001
SPK_R1-_CONN 6 3 SPK_L1-_CONN
I/O4 I/O2

5 2
VDD GND

SPK_R2+_CONN 4
I/O3 I/O1
1 SPK_L2+_CONN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
AZC099-04S.R7G_SOT23-6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CX20751 Codec
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7982P
Date: Wednesday, October 03, 2012 Sheet 31 of 60
5 4 3 2 1
 +3VLP Vcc 3.3V +/- 5%
+3VALW R694 100K +/- 5%
1
R304 C535 Board ID min typ
2 1 +3VALW_EC 100P_0402_50V8J
R695 VAD_BID V AD_BID VAD_BID max
0_0603_5%
2 0 0 0 V 0 V 0 V MP
L44 8.2K +/- 5% 0.216
FBM-11-160808-601-T_0603 +3VALW 1 V 0.250 V 0.289 V PVT
1 1 1 1 1 1
+EC_VCCA

0.1U_0402_16V4Z
C653

0.1U_0402_16V4Z
C654

0.1U_0402_16V4Z
C662

0.1U_0402_16V4Z
C655

1000P_0402_50V7K
C657

1000P_0402_50V7K
C658
1 2 18K +/- 5%
+3VALW
1 1
+EC_VCCA 2 0.436 V 0.503 V 0.538 V DVT
C659 33K +/- 5%
C656 2 2 2 2 2 2 3 0.712 V 0.819 V 0.875 V EVT

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U31

22
33
96

67
9
1 2 2 ECAGND 2
L45

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
FBM-11-160808-601-T_0603

1 21
<18> GATEA20 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
<18> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <31>
3 26 NOVO#
<16> SERIRQ SERIRQ GPIO12 NOVO# <33>
4 27 ACOFF
<16> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <39>
LPC_AD3 5 +3VS
<16> LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
<16> LPC_AD2 LPC_AD2

1
LPC_AD1 8 63 BATT_TEMP +3VALW +3VALW
<16> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <37,38>
LPC_AD0 10 LPC & MISC 64
<16> LPC_AD0 LPC_AD0 GPIO39

2
2 1 2 1 65 R588
ADP_I/GPIO3A ADP_I <38,39>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 BRDID_1 @ @ 10K_0402_5%
<15> CLK_PCI_EC CLK_PCI_EC GPIO3B
13 75 BRDID_0 R694 R697 @
<14,26,27> PLT_RST#

2
1 2 EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 100K_0402_1% 100K_0402_1% EC_FAN_PWM
+3VALW EC_RST# IMON/GPIO43 IMVP_IMON <44>
R590 47K_0402_5% EC_SCI# 20
<18> EC_SCI#

1
BATT_LEN# 38 EC_SCII#/GPIO0E BRDID_0 BRDID_1
2 <38> BATT_LEN# GPIO1D 68
EC_WL_OFF# <26>

2
C661 DAC_BRIG/GPIO3C 70 R04 @ +5VALW
EN_DFAN1/GPIO3D EC_BT_ON# <26>
0.1U_0402_16V4Z DA Output 71 R695 R696
1 IREF/GPIO3E DPWROK_EC <14>
KSI0 55 72 +3VALW 8.2K_0402_5% 8.2K_0402_5%
KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# <14>
KSI1 56
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%

1
KSO[0..15] KSI3 58 KSI2/GPIO32 83 R594
<33> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <31>
KSI4 59 84 USB_ON# USB_ON# 1 2
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <35>
KSI5 60 85
<33> KSI[0..7] KSI5/GPIO35 CAP_INT#/GPIO4C EC_TS_ON# <35>
KSI6 61 PS2 Interface 86 10K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D EAPD <31>
KSI7 62 87 TP_CLK
+3VALW KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <33>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <33>
R600 KSO1 40 +3VALW
1 2 EC_SMB_CK1 KSO2 41 KSO1/GPIO21
2.2K_0402_5% KSO3 42 KSO2/GPIO22 97
R604 KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98
1 2 EC_SMB_DA1 KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99
2.2K_0402_5% KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
HDA_SDOUT <13>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00
SPI Device Interface
NTC_V <38> HDA_SDOUT: For ME FALSH
KSO8 47 KSO7/GPIO27
KSO9 48 KSO8/GPIO28 119
KSO9/GPIO29 SPIDI/GPIO5B VSB_PWR_EN <38>
KSO10 49 120 VSB_PWR_EN 2 R599 @1 100K_0402_1%
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
KSO12 51 128 SUSACK#
KSO12/GPIO2C SPICS#/GPIO5A SUSACK# <14>
KSO13 52
KSO14 53 KSO13/GPIO2D +5VS
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <22>
KSO16 81 74
<33> KSO16 KSO16/GPIO48 PECI_KB930/GPIO41 INTEL_BT_OFF# <26>
KSO17 82 89
<33> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <27>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <33>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <33>
EC_SMB_CK1 77 GPIO 92 TP_CLK R603 1 2 4.7K_0402_5%
<38,39> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <33> +3VLP
EC_SMB_DA1 78 93 BATT_LOW_LED#
<38,39> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <33>
EC_SMB_CK2 79 SM Bus 95 SYSON
<16,22,29> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <36,41>
EC_SMB_DA2 80 121 @ TP_DATA R598 1 2 4.7K_0402_5%
<16,22,29> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <44>

1
127 PM_SLP_S4# <14> KB9012A2 work around
PM_SLP_S4#/GPIO59 R4945
+3VS 47K_0402_5%
6 100
<14> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <14>
14 101 EC_LID_OUT# BATT_TEMP 1 2
<14> PM_SLP_S5# EC_LID_OUT# <18>

2
EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 Turbo_V C663 100P_0402_50V8J
<18> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <38>
1 2 EC_TACH 16 103 PROCHOT ACIN 1 2
<23> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <38>
R605 10K_0402_5% 17 104 MAINPWON_R R738 1 @ 2 0_0402_5% C664 100P_0402_50V8J
<14,36> SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <40>
18 GPO 105 BKOFF# 1 2
GPIO0C BKOFF#/GPXIOA08 BKOFF# <23>
ODD_DA# 19 GPIO 106 PBTN_OUT# R522 @ 4.7K_0402_5%
<14,30> ODD_DA# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <14>
EC_INVT_PWM 25 107
<23> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
EC_TACH 28 108
<29> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
29
<27> LAN_WAKE# EC_TX 30 EC_PME#/GPIO15 +3VALW
<26,33> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<26,33> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <14,37,39>
PCH_PWROK 32 112 EC_ON
<14,8> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <40>
EC_FAN_PWM 34 114 ON/OFF <33>
<29> EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <33>
2 1 NUM_LED#: NC 116 SUSP#
SUSP#/GPXIOD05 SUSP# <36,41,42,43>
@ R608 117 PCH_HOT#_R R792 2 @ 1 0_0402_5%
GPXIOD06 PCH_HOT# <16>
10K_0402_5% 118
PECI_KB9012/GPXIOD07
AGND/AGND

122 PECI_KB9012 1 2
XCLKI/GPIO5D H_PECI <18,5>
GND/GND
GND/GND
GND/GND
GND/GND

123 124 +V18R R669 43_0402_1% LID_SW# 2 R601 1 100K_0402_1%

<14> SUSCLK XCLKO/GPIO5E V18R
1
GND0

C667
1

4.7U_0603_6.3V6K
1

R740 C93 2
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8
2
2

KB9012QF A3 LQFP 128P_14X14

ECAGND

@ @

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER

+3VALW
H_PROCHOT# <37,38,44,5>
ECAGND
2

1
D
R606 PROCHOT 2 1
10K_0402_5% EMC Request G
Q37 S C493
1

3
SYSON 2N7002H_SOT23-3 47P_0402_50V8J
2
C492
0.1U_0402_10V6K

1
@
LAN_WAKE#
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 32 of 60
 KSI[0..7]
KSI[0..7] <32>
JKB1 ME@
KSO[0..17] KSI1 1 JKB2 ME@
KSO[0..17] <32> 2 1 26
KSI7
KSI6 3 2 25 GND2
KSO9 4 3 GND1
KSI4 5 4 KSI1 24
KSI5 6 5 KSI7 23 24
KSO0 7 6 KSI6 22 23
KSI2 8 7 KSO9 21 22
KSI3 9 8 KSI4 20 21
KSO5 10 9 KSI5 19 20
KSO1 11 10 KSO0 18 19
KSI0 12 11 KSI2 17 18
KSO2 13 12 KSI3 16 17
KSO4 14 13 KSO5 15 16
KSO7 15 14 KSO1 14 15
KSO8 16 15 KSI0 13 14
KSO6 17 16 KSO2 12 13
KSO3 18 17 KSO4 11 12
KSO12 19 18 KSO7 10 11
KSO13 20 19 KSO8 9 10
KSO14 21 20 KSO6 8 9
KSO11 22 21 KSO3 7 8
KSO10 23 22 KSO12 6 7
KSO15 24 23 KSO13 5 6
KSO16 25 24 KSO14 4 5
KSO17 26 25 KSO11 3 4
27 26 KSO10 2 3
28 27 KSO15 1 2
29 28 31 1
30 29 GND 32 ACES_88514-2401
JP3 30 GND
1 ACES_88514-3001
+3VALW 1
2
<26,32> EC_TX 2
3
<26,32> EC_RX 4 3
4
ACES_85205-0400
ME@

L67 WCM-2012-900T_4P
USB20_N11 1 2 USB20_N11_R
+3VALW 1 2

USB20_P11 4 3 USB20_P11_R
4 3

2
@ +3VS
R642
100K_0402_5%
ME@
CVILU_CF06041H0RB-NH

1
D26 1
+3VLP NOVO# 2 USB20_N11 R687 2 1 0_0402_5% USB20_N11_R 2 1
<32> NOVO# <17> USB20_N11 2
1 NOVO_BTN# USB20_P11 R683 2 1 0_0402_5% USB20_P11_R 3
3 <17> USB20_P11 4 3
ON/OFF
4
2

SMT1-05_4P SW3
1 3 5
R701 DAN202UT106_SC70-3 GND 6
2 4 100K_0402_5% GND
1

JCR1
6
5

J11
1 2 ON/OFF
ON/OFF <32>
SHORT PADS LED1

PWR_LED# 1 2 2 R623 1
<32> PWR_LED# +5VALW
300_0402_5%

19-213A-T1D-CP2Q2HY-3T_WHITE

+3VALW
+5VS

EMI reserve JPWRB1

1
JTP1 ME@ 2 1
<32> LID_SW# 2
@ C696 LED2 NOVO_BTN# 3
8 ON/OFF 4 3
0.1U_0402_16V4Z 7 GND BATT_LOW_LED# 1 2 2 R764 1 5 4
GND <32> BATT_LOW_LED# +3VALW 5
470_0402_5% 6
6

2
6
TP_CLK 5 6 HT-191UD5_AMBER @ 7
<32> TP_CLK 4 5 8 GND
TP_DATA
<32> TP_DATA 4 GND
1 1 TP_3 3 D24
TP_2 2 3 ACES_88058-060N
@ C697 C698 @ TP_1 1 2 PJSOT24C 3P C/A SOT-23

1
100P_0402_50V8J 100P_0402_50V8J 1
2 2 ACES_88058-060N ME@
3

C490

C491
0.1U_0402_10V6K

0.1U_0402_10V6K

1 1
15@
@ D15 2 R627 1 TP_3 LED5
PSOT24C_SOT23-3 0_0402_5% @ @
2 2 BATT_CHG_LED# 1 2 2 R765 1
<32> BATT_CHG_LED# +5VALW
1

2 R619 1 14@ TP_1 300_0402_5%

0_0402_5%
19-213A-T1D-CP2Q2HY-3T_WHITE

15" 14"
L R +5VALW 1
JLED1
1
2
1 VCC 1 VCC +3VALW
3 2
+5VS 3
LID_SW# 4
SW4 SW5 5 4
SMT1-05_4P SMT1-05_4P
2 CLK 2 CLK LED6 PWR_LED# 6 5
6
5
6

5
6

BATT_LOW_LED# 7
4 2 4 2 14@ CAPS_LED# 1 2 2 R303 1 BATT_CHG_LED# 8 7
14@ TP_3 TP_2
3 DAT 3 DAT <32> CAPS_LED#
300_0402_5%
+5VS
CAPS_LED# 9 8
3 1 3 1 10 9
19-213A-T1D-CP2Q2HY-3T_WHITE 10
4 GND 4 L 11
12 GND
GND
5 L 5 R HB_A091020-SAHR21
ME@
SW6 15@ SW7 15@
SMT1-05_4P SMT1-05_4P
GND
6 R 6
5
6

5
6

4 2 4 2
TP_2 TP_1
3 1 3 1

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 33 of 60
 A B C D E

Green Clock

1 RG12 1
GCLK@ 1 2 +GCLK_VBAT
+CHGRTC_R

390_0402_5%

+RTCBATT

+1.05VS

2
+3V_LAN
+3VLP RG10 @
0_0402_5%
+3VLP +3V_LAN
1

1
CG3 GCLK@
GCLK@ 1 22U_0805_6.3V6M

1
0_0402_5%
CG2 1
2

RG8
0.1U_0402_16V7K

1 CG4
2 RG11 2.2U_0402_6.3V6M
U71 2 GCLK@
0_0402_5%

2
GCLK@
GCLK@
10 14
2

2 VBAT VDD_RTC_OUT 2

GCLK@ 1 15
CG5 +V3.3A

0.1U_0402_16V7K
2 1 +3V_LAN 2
GCLK@ 1 CG1 GCLK@ VDD 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K
CG7 2
0.1U_0402_16V7K
32kHz GCLK@
GCLK_32K <13> PCH_32.768K
0.1U_0402_16V7K

2
11
VDDIO_27M 27MHz
12 GCLK_27MHZ_R AMD_GPU
<27> LAN
8 6 GCLK_LAN_25MHZ_R RG3 1 2 33_0402_5%GCLK_LAN_25MHZ
VDDIO_25M_A 25MHz_A GCLK_LAN_25MHZ
GCLK@
<15> PCH_25M
PCH_GCLK 3 5 GCLK_PCH_25MHZ_R RG4 1 2 0_0402_5% GCLK_PCH_25MHZ
VDDIO_25M_B 25MHz_B GCLK_PCH_25MHZ
GCLK@
GreenCLK_XTALI 1
Y8 GreenCLK_XTALO 16 XTAL_IN
XTAL_OUT
Close to GCLK

GND1
GND2
GND3

GND4
4 3
NC OSC
1 2
OSC NC
SLG3NB244VTR_TQFN16_2X3

4
7
13

17
1 GCLK@ 1
GCLK@ CG8 25MHZ_10PF_7V25000014 GCLK@ CG9 GCLK@
15P_0402_50V8J 15P_0402_50V8J
2 2
3 3

Reserved for Swing Level adjustment

( Close GCLK side )
*
@
GCLK_LAN_25MHZ RG6 *1 2 0_0402_5%

@
GCLK_PCH_25MHZ RG7 * 1 2 0_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ext. ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 34 of 60
A B C D E
 5 4 3 2 1

+3VS +3VS_TS
ME@
1 TS@ 2
R5583 0_0402_5% 8
Right Ext.USB Conn. 7
6
GND
GND
+3VS_TS 6

D
3 1 R20 5
D +5VALW 4 5 D
+USB_VCCB <17> USB20_N2 3 4
<17> USB20_P2 3
R5581 @ Q156 2

G
2
100K_0402_5% PMV65XP_SOT23-3~D EC_TS_ON# R722 1 @ 2 0_0402_5% TS_RST# 1 2
R02 1 2 @ 1

0.1U_0402_16V7K
<32> EC_TS_ON#
U36 RIGHT USB PORT X1

C1322
1 2 JTS1
1 8
C713 0.1U_0402_16V4Z 2 GND VOUT 7 C1331
2 1 3 VIN VOUT 6 0.1U_0402_16V7K TS@
4 VIN VOUT 5 2 1
<32> USB_ON# EN FLG USB_OC4# <17> @
G547I2P81U_MSOP8
Touch Screen

JUSB3 ME@

8
+USB_VCCB 7 GND
W=80mils GND
6
+USB_VCCB 5 6
4 5
1 4
C714 1 USB20_N9 R868 2 @ 1 0_0402_5% USB20_N9_C 3
+ <17> USB20_N9 3
USB20_P9 R869 2 @ 1 0_0402_5% USB20_P9_C 2
<17> USB20_P9 2
220U_6.3V_M C715 1
1

2
470P_0402_50V7K
6.3Φ * 5.9 2 2 ACES_88058-060N
SF000001500

USB20_N9 4 3 USB20_N9_C
4 3

USB20_P9 1 2 USB20_P9_C
C 1 2 D25 @ C

1
L66 WCM-2012-900T_4P PJDLC05_SOT23-3

@ D27 1 R728@ 2
U3RXDN1 9 10 1 1 U3RXDN1 0_0402_5% Intel_PCH_USB2.0
1 R563@ 2
U3RXDP1 8 9 2 2 U3RXDP1 WCM-2012-900T_4P 0_0402_5%
1 2 U2DN2
B <17> USB20_N1 1 2 WCM-2012-900T_4P B
U3TXDN1 7 7 4 4 U3TXDN1
1 2 U2DN1
<17> USB20_N0 1 2
U3TXDP1 6 6 5 5 U3TXDP1 4 3 U2DP2
<17> USB20_P1 4 3
2A/Active Low L55
3 3 4 3 U2DP1
+5VALW +USB3_VCCA <17> USB20_P0 4 3
1 R721@ 2
8 0_0402_5% L51
C704 U35 R02 W=80mils 1 R562@ 2
.1U_0402_16V7K 1 8 0_0402_5%
1 2 2 GND VOUT 7 YSCLAMP0524P_SLP2510P8-10-9 1 R742@ 2
3 VIN VOUT 6 0_0402_5% 1 R564@ 2
USB_ON# 4 VIN VOUT 5 @ D30 0_0402_5%
EN FLG USB_OC0# <17> WCM-2012-900T_4P +USB3_VCCA
Intel_PCH_USB3.0
U3RXDN2 9 10 1 1 U3RXDN2
G547I2P81U_MSOP8 1 2 U3RXDN2 WCM-2012-900T_4P +USB3_VCCA
<17> USB3_RX2_N 1 2
U3RXDP2 8 9 2 2 U3RXDP2 W=80mils 1 2 U3RXDN1

U3TXDN2 7 4 U3TXDN2 4 3 U3RXDP2 JUSB1

LP2 <17> USB3_RX1_N 1 2
W=80mils
LP1
7 4 <17> USB3_RX2_P 4 3 U3TXDP2 9 4 3 U3RXDP1 JUSB2
L54 SSTX+ <17> USB3_RX1_P 4 3
U3TXDP2 6 6 5 5 U3TXDP2 1 U3TXDP1 9
1 R743@ 2 U3TXDN2 8 VBUS L50 SSTX+
1
3 0_0402_5% U2DP2 3 SSTX- 1 R561@ 2 U3TXDN1 VBUS
8
3
7 D+ 0_0402_5% U2DP1 SSTX-
3
+USB3_VCCA 8 1 R636@ 2 U2DN2 2 GND 10 D+
7
0_0402_5% U3RXDP2 6 D- GND 11 1 R565@ 2 U2DN1 GND
2 10
C850 USB30@ 4 SSRX+ GND 12 0_0402_5% U3RXDP1 D-
6 GND 11
YSCLAMP0524P_SLP2510P8-10-9 .1U_0402_16V7K WCM-2012-900T_4P U3RXDN2 5 GND GND 13 C849 USB30@ SSRX+
4 GND 12
1 2 U3TXDN2_L 1 2 U3TXDN2 SSRX- GND .1U_0402_16V7K WCM-2012-900T_4P U3RXDN1 GND
5 GND 13
<17> USB3_TX2_N 1 2 SSRX- GND
TAITW_PUBAU1-09FNLSCNN4H0 1 2 U3TXDN1_L 1 2 U3TXDN1
<17> USB3_TX1_N 1 2
ME@ TAITW_PUBAU1-09FNLSCNN4H0
1 2 U3TXDP2_L 4 3 U3TXDP2 ME@
D22 D31 <17> USB3_TX2_P 4 3
1 @ @ 1 2 U3TXDP1_L 4 3 U3TXDP1
L53 <17> USB3_TX1_P 4 3
1 C735 U2DN1 3 6 U2DP2 3 6 C848 USB30@
A + I/O2 I/O4 I/O2 I/O4 .1U_0402_16V7K C847 USB30@ L49 A
C736 470P_0402_50V7K 1 R638 @2 .1U_0402_16V7K 1 R546@ 2
220U_6.3V_M 0_0402_5% 0_0402_5%
SF000002Y00 2 2 2 5 +5VALW
2 5 +5VALW
GND VDD GND VDD

1 4 U2DP1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3 Security Classification Compal Secret Data Compal Electronics, Inc.
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/Left USB Ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 35 of 60
5 4 3 2 1
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS

+3VALW +3VS
+5VALW +5VS
U38 U39
DMN3030LSS-13_SOP8L-8 +3VALW TO +3VALW(PCH AUX Power)
DMN3030LSS-13_SOP8L-8 8 1
8 1 1 7 2 1 1

1
1 7 2 1 1 C723 6 3 C724 +3VALW +3V_PCH

1
C720 6 3 C721 4.7U_0603_6.3V6K @ 5 @ 4.7U_0603_6.3V6K C725
4.7U_0603_6.3V6K @ 5 @ 4.7U_0603_6.3V6K C722 @ 1U_0603_10V4Z R645
R644 2 2 2 PJ1

@
1 @ 1U_0603_10V4Z 470_0603_5% 1

4
2 2 2 470_0603_5% @ 2 1

1 2
@ 2 1

1 2
+VSB +VSB D
D 2 SUSP JUMP_43X79

1
2 SUSP G 3 1 4.7U_0603_6.3V6K 1U_0603_10V6K
1

G S Q108 1 1

1
R646 S Q107 R647 2N7002_SOT23 C782 DS3@ DS3@ DS3@ 1

3
150K_0402_5% 2N7002_SOT23 470K_0402_1% @ 4.7U_0603_6.3V6K Q121 C780 @
@ LP2301ALT1G_SOT23-3 R777

2
2 2 C783 @ 470_0603_5%
2

2
5VS_GATE 2 R649 15VS_GATE_R 2
1

2
1
D R650 +5VALW
1
1

D SUSP 2 Q111 C727

82K_0402_5% 0_0402_5%

1
SUSP 2 Q110 C726 G 2N7002_SOT23 0.01U_0402_25V6 D
G 2N7002_SOT23 0.01U_0402_25V6 S @ 2 2
R778

1
S 2 G
3

1 2 S @

3
Q118
2N7002K_SOT23-3
47K_0402_5%
DS3@ 1 DS3@

1
D DS3@ SLP_SUS
SLP_SUS# 2 Q120 C781
2N7002K_SOT23-3 0.1U_0402_16V4Z
G
2
S

3
+RTCVCC +5VALW

1
+5VALW
+5VALW R652 @
2 R653 2
220K_0402_5%

1
100K_0402_5%
1

2
@ R780 @ SUSP
<5> SUSP
R654 100K_0402_5%
100K_0402_5% Q117
2

1
DTC124EKAT146_SC59-3
2

SYSON# SLP_SUS

OUT
1

Q124
1

@ Q119 2
OUT

<32,41,42,43> SUSP# IN
DTC124EKAT146_SC59-3

GND
OUT

SYSON 2
<32,41> SYSON IN

1
2
GND

<14,32> SLP_SUS#

3
IN @
GND

R1110 @
1

100K_0402_5%
3

DTC124EKAT146_SC59-3
3

2
R781 DS3@
100K_0402_5%
2

+1.5VS +1.35V +1.05VS +0.675VS

1

3 3
R655 R656 R659 @ R658
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5%
@ @ @
1 2

1 2

1 2

1 2

D D D D
2 SUSP 2 SYSON# 2 SUSP 2 SUSP
G G G G
S Q113 S Q114 S Q116 @S Q115
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

@ @ @

For Intel S3 Power Reduction.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Wednesday, October 03, 2012 Sheet 36 of 60
A B C D E
 5 4 3 2 1

DC030006J00 PL101
FBMA-L11-453215800LMA90T_2P
VIN
1 2

PF101 PL102
12A_65V_451012MRL FBMA-L11-453215800LMA90T_2P
4 APDIN 1 2 APDIN1 1 2
4
D 3 D
3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2
2

1
PC101

PC102

PC103

PC104
1
1

2
@ 4602-Q04C-09R 4P P2.5
JDCIN101

+CHGRTC
PR101
1K_0603_1%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
3 PR102
1K_0603_1% JRTC101 @
1 2 1
2 1
3 2
C 4 GND C
GND

ACES_50271-0020N-001

RTC Battery
+5VS

+3VALW

47K_0402_1%
<32,38,44,5> H_PROCHOT#

PR106

10K_0402_1%
2N7002KDW-2N_SOT363-6

PU101A
6

PR108
AS393MTR-E1 SO 8P OP

8
PC105 3 BATT_TEMP <32,38>

P
+
PQ101A

2 2 1 1
1N4148WS-7-F_SOD323-2

1
O 2
-

G
1.5M_0402_5%
0.022U_0402_16V7K
1

100K_0402_1%
100P_0402_50V8J
4

1
PR104
PD105

PR109
PC107

2
2

1
B +5VS B

H_PROCHOT#
2

47K_0402_1%
PR107
2N7002KDW-2N_SOT363-6
3

8
PC106 5
P
+
PQ101B

5 2 1 7
O 6 ACIN <14,32,39>
1N4148WS-7-F_SOD323-2

-
G
0.022U_0402_16V7K
4

1.5M_0402_5%

PU101B
4

AS393MTR-E1 SO 8P OP
PD104

PR105
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 37 of 47
5 4 3 2 1
 5 4 3 2 1

@ VMB2 VMB
JBATT201 PF201 PL201
SUYIN_200082GR007M229ZR

1 12A_65V_451012MRL SMB3025500YA_2P
1 2 1 2 1 2
2 3 EC_SMCA BATT+
3 4 EC_SMDA
4 5
5 6
6 7

1
D D
7 8

1
PC201 PC203
GND 9

100_0402_1%

100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K

2
GND
PR201

PR204
2

2
JBATT202 @
1
SUYIN_200082GR007M229ZR

1 2
2 3
3 4
4 5
5 6 90W(DIS) : 6.65K 100W active 90W recovery
6 7 PH201 under CPU botten side :
7 8 65W(UMA): 1.65K 70W active 65W recovery
GND 9 EC_SMB_CK1 <32,39> CPU thermal protection at 93 +-3 degree C 20120314
GND
Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
EC_SMB_DA1 <32,39>

1 2
+3VALW
PR206
6.49K_0402_1%
+EC_VCCA
<32,39> ADP_I

12.7K_0402_1%
1
1 2
BATT_TEMP <32,37,38> A/D

PR226
6.65K_0402_1%
PR207
10K_0402_5%
90W(DIS) : 27.4K

PR221
+3VS
65W(UMA) : 5.11K

2
<32> NTC_V

100K_0402_1%_TSM0B104F4251RZ
2

100K_0402_1%
C C

PR215 @
<32,37,44,5> H_PROCHOT#

1
<32> Turbo_V

1
1
D

PQ201 @

PH201
2

10K_0402_1%
2 ADP_OCP_1

<BOM Structure>

2
PR222
G
S 2N7002KW_SOT323-3

3
PR216 @

1
0_0402_5%

1
<32> PROCHOT 1 2
PR228
0_0402_5%

2
ECAGND
+3VALW +3VALW

ECAGND

100K_0402_1%
2
100K_0402_1%
2

PR214
PR211

1
VL
1

BATT_OUT <39>
PJ202
B @ JUMP_43X39 B
6

VL
0.01U_0402_25V7K

1 2
1 2 +VSB
PQ202A
1

47K_0402_1%
PC202

2 2N7002KDW-2N_SOT363-6 PQ204 @
PR210

TP0610K-T1-GE3_SOT23-3
PR202
2

1
2

75K_0402_1%
3 1
B+ +VSBP
1

100K_0402_1%

0.22U_0603_25V7K
8

1
PR224 @

PC205 @
PC208
1

1
3 0.022U_0402_16V7K PQ202B
P

<32,37,38> BATT_TEMP + 1 2 1 5 2N7002KDW-2N_SOT363-6 PC206 @

2 O 0.1U_0603_25V7K

2
-
G

1N4148WS-7-F_SOD323-2

PU201A
4

2
100P_0402_25V8K

PR223 @
4

1
100K_0402_1%

+3VLP VL
1.5M_0402_5%

AS393MTR-E1 SO 8P OP 22K_0402_1%
2

2
PD201

1 2
1
PR213

PC207

PR205

2
100K_0402_1%

PR217
2

@ 100K_0402_1%
1

PR220

PR218 @

1
1K_0402_5% D
1 2 2 PQ203 @
<40> SPOK
1

G 2N7002KW_SOT323-3
1

PC204 @
1U_0402_6.3V6K
S

3
1
2 PQ205 PR219 @
<32> BATT_LEN#
G 2N7002KW_SOT323-3 1K_0402_5%
S 1 2
<32> VSB_PWR_EN
3

2
A A
PJ201
@ JUMP_43X39
1 2
+VSBP 1 2 +VSB

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8

4
2 7
3 6

@ 10U_0805_25V6K

@ 10U_0805_25V6K

2200P_0402_50V7K
PQ304 1 2 5

10U_0805_25V6K

10U_0805_25V6K
D D
47K_0402_5%
1

2
PC301

200K_0402_1%
0.1U_0603_25V7K

PC319

4
1
PR302

PC310

PC313

PC315

PC316
DTA144EUA_SC70-3 5600P_0402_25V7K DISCHG_G

PC302

PR304

1
PR322
200K_0402_1%
2

2
2 1 2

2
ACN VIN

1SS355_SOD323-2
2

2ACOFF
1

ACP PR321

1DISCHG_G-1
47K_0402_1%
1

2
PD302
P2-1 PR325

1
2 200K_0402_1%
PQ303 PQ311

1
PC307 PC311 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3
PR306 <39> ACPRN 1 2 2 1
3

20K_0402_1%
1 2 0.1U_0402_25V6 0.1U_0402_25V6 2 1 2
6

PQ306
1

D 2N7002KW _SOT323-3 PC308 PD303 PQ313

150K_0402_1%
PR305

PQ307A 2 1SS355_SOD323-2
2 2N7002KDW -2N_SOT363-6 G BATT_OUT <38> 0.1U_0402_25V6 P2 2N7002KW _SOT323-3

0.1U_0402_25V6
3

1
D
S
3

1
2 1

PC324
2 PACIN
1

VIN G
S

3
392K_0402_1%
1
P2-2

10_1206_5%

TPC8065-H 1N SOP-8
2

5
6
7
8
C C
PR309
2N7002KDW-2N_SOT363-6

PQ309
PR319
3
PQ307B

ACOK

CMPIN

CMPOUT

ACP

ACN
PR303 <32,38> ADP_I
2

47K_0402_1% PR308 21

1
PACIN 1 2 5 1 2 6 TP 4
PACIN ACDET PC314
64.9K_0402_1% PC304 20 BQ24737VCC 1 2
4

PC303 1 2 7 VCC
1 2 IOUT PL302 PR324

3
2
1
1U_0603_25V6K
1

PQ305 100P_0402_50V8J 19 10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 0.1U_0402_25V6
<32,38> EC_SMB_DA1
8
SDA
PU301
1 2
BATT+
BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG CHG1 4
18 DH_CHG
HIDRV

5
6
7
8
ACOFF 2 9 2 3
<32> ACOFF SCL

1
<32,38> EC_SMB_CK1

PQ310
PR315 PR320 PC317

4.7_1206_5%
TPC8A03-H 1N SO8

PR323
200K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
124737_SN
ILIM BTST
1

+3VALW PD301
3

PR316 4 @

LODRV

1
16 2 1

PC322

PC323
100K_0402_1%

GND
SRN

SRP
REGN

BM
2

2
RB751V-40_SOD323-2

680P_0603_50V7K
11

12

13

14

15

3
2
1
1
BQ24737VDD

PC320
2
PC312
6.8_0402_5%
1

10_0402_5%
1U_0603_25V6K

2
PR317

PR318
@

PC306 DL_CHG
2

2
B 0.1U_0402_25V6 B
2 1
1

PC305 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2

BQ24737VDD

PR314
10K_0402_1%
1

1 2
ACIN <14,32,37>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2

1 2

ACPRN <39> PR312

2
12K_0402_1%
2

PQ308

A DTC115EUA_SC70-3 A
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER-BQ24737
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: W ednesday, October 03, 2012 Sheet 39 of 47

5 4 3 2 1
 A B C D E

1 1

B+ PL401
HCB2012KF-121T50_0805 PU401
1 2 3V_VIN 8 1 3V5V_EN PR402
IN EN1 PD401
499K_0402_1%
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

11 3 ENLDO_3V5V 2 1 2 1
IN EN2 PC402 B+

1
150K_0402_1%

1U_0603_25V6K
PC403

14 6 BST_3V 1 2
IN BS RLZ5.1B_LL34
1

1
PC404

PC405

PC406

PR403
7 12 0.1U_0603_25V7K
GND LX

PC407
PL402
2

2
10 9 LX_3V 1 2
+3VALWP

2
GND LX
13 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC412 @

PC413 @
4.7_1206_5%
2 5
<38> SPOK PG LDO +3VLP

PC408

PC409

PC410

PC411
1

PR404

2
SY8208BQKC_QFN14_3X3 PC414

13V_SN
4.7U_0603_6.3V6M

680P_0603_50V7K
PC415 @
2 2

2
B+ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402
11 1 3V5V_EN
IN EN1
1

1
PC420

PC416

PC417

PC418

14 3 ENLDO_3V5V PC421
IN EN2 0.1U_0603_25V7K
7 6 BST_5V 1 2
2

GND BS
10 12
GND LX PL404 @PJ401
@ PJ401
13 9 LX_5V 1 2 +5VALWP +3VALWP 1 2 +3VALW
GND LX 1 2
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
VCC OUT
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%

1
PR406 @

PC427 @

PC428 @
2 8
PG LDO VL
1

PC422

PC423

PC424

PC425

PC426
4.7U_0603_6.3V6M

SY8208CQKC_QFN14_3X3

2
1 5V_SN

@PJ402
@ PJ402
2

2
1

PC430
4.7U_0603_6.3V6M

+5VALWP 1 2 +5VALW
3 1 2 3
PC429 @

JUMP_43X118
2

2 1
<32> EC_ON
PR407 2.2K_0402_5%
2 1
<32> MAINPWON
PR408 0_0402_5%

3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

PC431 @
1
PR409

2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 03, 2012 Sheet 40 of 47
A B C D E
 A B C D

PL502
1.35V_B+ 1 2 B+
HCB2012KF-121T50_0805
STATE S3 S5 1.5VP VTT_REFP 0.75VSP

2200P_0402_50V7K
10U_0805_25V6K

0.1U_0402_25V6
4.7U_0805_25V6-K
PC520 @

PC509 @
1

1
PC501

PC513
S0 Hi Hi On On On

5
Off

2
S3 Lo Hi On On (Hi-Z) +1.35VP PQ501
TPCA8065-H_PPAK56-8-5
UG_1.35V 4
S4/S5 Lo Lo Off Off Off
1 1
LX_1.35V

3
2
1
Note: S3 - sleep ; S5 - power off

0_0603_5%
PR503
PR501 PC512 PL501
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.35V 1 2 BST_1.35V-1 1 2 2 1
+0.675VSP

1
+1.35VP

10U_0805_25V6K

10U_0805_25V6K

4.7_1206_5%
1

PR515 @
PC504

20

19

18

17

16

TPCA8057-H_PPAK56-8-5
1

PQ502
PC505
PU501

VTT

VLDOIN

BOOT

UGATE

PHASE
2

11.35V_SN
21 1

2
PAD

330U_2.5V_M
1 15 4 +

PC522
LG_1.35V
VTTGND LGATE

PC517 @

680P_0603_50V7K
2 14 2
VTTSNS PGND PR511

3
2
1

2
6.65K_0402_1%
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS

4 12
+1.35VP
+VTT_REFP VTTREF VDDP
OCP min 20A
5 11 2 1 OVP min 1.485V
+1.35VP VDDQ VDD
+5VALW

PGOOD
PR514
1

5.1_0603_5%

1U_0603_10V6K
TON
PC506

1U_0603_10V6K
FB

S3

S5
2 0.033U_0402_16V7K 2
2

1
PC510

PC511
6

S3_1.35V 7

10

2
S5_1.35V
PR502
49.9K_0402_5%
<32,36,42,43> SUSP# 1 2

PR505 PR509
0_0402_5% 887K_0402_1%
<32,36> SYSON 1 2 2 1 1.35V_B+

PR507
1

PC503 PC508 @ 8.2K_0402_1%

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1
2

PJ504
+1.35VP 2 1 +1.35V
PR506 2 1
10K_0402_1% @ JUMP_43X118
2

PJ506
2 1
+0.675VSP 2 1 +0.675VS

JUMP_43X79
@
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.35V_DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: W ednesday, October 03, 2012 Sheet 41 of 47
A B C D
 5 4 3 2 1

PR601
0_0402_5%
2 1
SUSP# <32,36,41,42,43>

2
PR602
1M_0402_1%

1
@ PR603 @ PC601
4.7_1206_5% 680P_0603_50V7K
PL603 PU601 1 2SNB_1.5V 1 2
D D
HCB2012KF-121T50_0805
B+ 1 2 B+_1.5V 11
IN EN
1 PC602
0.1U_0603_25V7K

10U_0805_25V6K
14 6 1
BST_1.5V 2 PL601

0.1U_0402_25V6
2200P_0402_50V7K
IN BS

1
1UH_PCMB063T-1R0MS_12A_20%

PC604
+3VS
+1.5VSP

PC603 @
7 12 1 2

PC617
GND LX

2
10 9 LX_1.5V

30.1K_0402_1%

47U_0805_6.3V6M

47U_0805_6.3V6M

22U_0805_6.3VAM

22U_0805_6.3VAM
GND LX
1

330P_0402_50V7K
1

1
13 4

PR607
@ PR604 GND FB

PC607

PC608

PC609

PC610

@ PC611
0_0402_5% ILMT_1.5V 3 8
+3VALW

2
ILMT BYP
2

2
4.7U_0603_6.3V6K
ILMT_1.5V 2 5

4.7U_0603_6.3V6K
PG LDO

PC606
1

1
+1.5VSP PJ602

PC605
SY8208DQKC_QFN14_3X3 2 1
+1.5VS

2
2 1

1
PR605

2
0_0402_5% PR608 @ JUMP_43X118
2

20K_0402_1%

2
@ PU602 PL602
PJ604 1UH_PHT32251B-1R0MS_2.34A_20%
C
+3VALW 1 2 8032_VIN 4
IN LX
3 8032_LX 1 2 +1.5VSP C

5 2
PAD-OPEN 3x3m PG GND

4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M
1

PR613 @
6 1
FB EN
1

1
PC623

PC615

PC616
22U_0805_6.3V6M
SY8032ABC_SOT23-6
2

2
2
8032_FB

8032_SNUB
PC624
22P_0402_50V8J PR627
2 1 0_0402_5%
2
8032_1.5V_EN 1

1000P_0603_50V7K
PC612 @
1
0.1U_0402_25V6

SUSP# <32,36,41,42,43>
2

PR619
47K_0402_1%

15K_0402_1%
PR622

PC614

1 2 2
2
1
2

PR620
10K_0402_1%
1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: Wednesday, October 03, 2012 Sheet 42 of 47
5 4 3 2 1
 5 4 3 2 1

D D

PR701
<32,36,41,42> SUSP# 60.4K_0402_1%
1 2 1.05V_EN
+1.05VSP PJ701 +1.05VS

@ 10K_0402_1%
2
2 1

.1U_0402_16V7K
2 1

1
PR706
@ JUMP_43X118

PC701
2
1 PL702
C HCB2012KF-121T50_0805 C

100K_0402_1%
<BOM Structure>
1.05VSP_B+ 1 2

2200P_0402_50V7K

10U_0805_25V6K

0.1U_0402_25V6
4.7U_0805_25V6-K
B+

PC713 @

PC715 @
PR712

1
PC712
5
6
7
8

TPC8065-H 1N SOP-8
PR713 PC707

PC711
PQ701
2.2_0603_5% 0.1U_0603_25V7K

2
BST_1.05VSP1 2 BST_1.05VSP_1
1 2

1
17

16

15

14

13
10.7K_0402_1%

PU701 4
PR704

PAD

PGOOD

EN
MODE

BST
1 12 LX_1.05VSP
0.1U_0402_25V6

3
2
1
VREF SW PL701
+1.05VSP
1

1 2
12K_0402_1%
PC702

2 11 DH_1.05VSP 1UH_PCMB063T-1R0MS_12A_20%
2

REFIN DH
2

1
PR705

1000P_0603_50V7K 4.7_1206_5%
TPC8A03-H 1N SO8
5
6
7
8
PC703

PQ702
TPS51219RTER_QFN16_3X3

PR714
0.01UF_0402_25V7K
1

3 10 DL_1.05VSP 1
GSNS DL

220U_6.3V_M
1

2
@ +

PC714
4
4 9
VSNS V5 +5VALW 2
+1.05VP
COMP

1
PGND
TRIP

GND

B B
OCP min 8A

3
2
1
1

PC709
2
PC706 PC708 OVP min 1.24V
5

8
2

1U_0603_10V6K
1000P_0402_50V7K

2
2

PR707 1 2 @
PC704

45.3K_0402_1%
1

10_0402_5%
0.01UF_0402_25V7K
1

PR711

PR709
1 2

10_0402_1%
2

PC705
1000P_0402_50V7K
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: W ednesday, October 03, 2012 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

D D

PR918
121K +-1% 0603
1 2 SWN3

PR911 PR919 @37W 37W: @

220K_0402_5%_ERTJ0EV224J
165K_0402_1% 121K +-1% 0603
1 2 1 2 SWN2 47W: INSTALL

1000P_0402_50V7K

0.047U_0402_16V7K
CSREF

220P_0402_50V7K
75K_0402_1%

@20K_0402_1%
PR920

2
121K +-1% 0603

1
PH901

PR901

PC901

PC910

PC916

PR926
1 2 SWN1

PR929

2
5.76K_0402_1%

1
CSP3 2 1
SWN3 <45>

Place close to

1000P_0402_50V7K

0.047U_0402_16V7K
CSREF
phase 1 inductir

@20K_0402_1%
PC917 @37W

PR927
37W: @

2
PC911
47W: INSTALL

1
1
PR930

2
5.76K_0402_1%
CSREF <45>

1
CSP2 2 1
SWN2 <45>
CSP3

0.047U_0402_16V7K
CSREF

@20K_0402_1%
CSP2

2
1

PC918

PR928
CSP1

CSSUM
C CPU_B+ C
PR931
DRON <45>

2
5.76K_0402_1%

1
PR922 CSP1 2 1
SWN1 <45>
66.5K_0402_1%
2 CSCOMP 1 2 37W=43K
PR907
1K_0402_1% 37W=10K 47W=66.5K
+5VS
<32> IMVP_IMON 47W=15.4K 81103_PWM <45>
1

2
0.01U_0402_25V7K

PR932 @47W
PC902 PC904 BST_CPU_Phase3

2K_0402_1%
390P_0402_50V7K 10P_0402_25V8K PR913
1 2 1 2 1 2 PR912 15.4K_0402_1%
1
PC905

PR902 37W=10K 24.3K_0402_1% PU901 PR924 PC913

27
26
25
24
23
22
21
20
19
49.9_0402_1% 1 2 NCP81103MNTWG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6K
47W=7.5K

1
1 2BST_CPU_Phase3-2
1 2

CSSUM
CSREF
CSCOMP

PWM2/IMAX
DRON
CSP3
CSP2
CSP1

BST3
2

2
PC908
.1U_0402_16V7K CSP2 37W: INSTALL
1 2 1 2 2 1 28 18
ILIM HG3 HG3 <45> 47W: @
PR903 PR904 29 17
IOUT SW3 SW3 <45>
1K_0402_1% 7.5K_0402_1% 30 16 PC914
VRMP LG3 LG3 <45>
31 15 1 2
32 COMP PVCC 14
33 FB PGND 13 2.2U_0603_10V7K
1 2 34 DIFFOUT LG1 12
LG1 <45> +5VS
VSN SW1 SW1 <45>
PR909 35 11
VSP HG1 HG1 <45>
1K_0402_5% 36 10
<10,9> VSSSENSE VCC BST1
1

VR_RDY
VRHOT#

INT_SEL
TSENSE
1 2

ALERT#
PC903 PR925 PC915

ROSC
1000P_0402_50V7K 37 2.2_0603_5% 0.22U_0402_10V6K

SCLK
SDIO
<9> VCCSENSE GND
PC906 1
BST_CPU_Phase1 2BST_CPU_Phase1-1
1 2

EN
2

2200P_0402_50V7K

1
2
3
4
5
6
7
8
9
PR921
B 1 2 45.3K_0402_1% B
+5VS 1 2

TSENSE
2.2U_0603_10V7K

PR908 PR914
2_0603_5% 0_0402_5%
ALERT#
2
PC907

1 2

VR_RDY
SCLK
SDIO
<32> VR_ON

2
PR915
1

0_0402_5% PC912
1 2 .1U_0402_16V7K
<32,37,38,5> H_PROCHOT#

1
0.1U_0402_25V6K

TSENSE
2
PC987 @
1

PR917

1
34.8K_0402_1%
PR942
2

0_0402_5%
1

+VCCIO_OUT
PR934

100K_0402_1%_TSM0B104F4251RZ
0_0402_5%
1 2
1.91K +-1% 0402
1
130_0402_1%

54.9_0402_1%

VRHOT Assert Threshold : 472 mV

2

61.9K_0402_1%
PR916

TSENSE Bias Current : 120 uA

2
PR906

PR910

ALER# pull high at HW side

PR923

PH902
need to confirm HW circuit PRZ146=61.9K, 110C active
2

PC909
1

.1U_0402_16V7K
1

1
1 2 SDIO
<9> VR_SVID_DAT
+3VS

PR905
0_0402_5% Close VR side
VGATE
<14>

ALERT#
<9> VR_SVID_ALRT#

A Place close to A
SCLK
<9> VR_SVID_CLK phase 1 MOSFET

Security Classification
2011/12/14
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: Wednesday, October 03, 2012 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

B+
PL901
D D
FBMA-L11-453215800LMA90T_2P
1 2
CPU_B+

2200P_0402_50V7K
0.1U_0402_25V6K
1 1

PC941 @
220U_25V_M

100U_25V_M

1
+ +

PC985

PC986

PC942
CPU_B+

2
2 2

10U_0805_25V6K

10U_0805_25V6K
5
PQ901

1
PC920

PC925
2

2
4
<44> HG1

MDU1516URH_POWERDFN56-8-5
3
2
1

PL902
0.22UH +-20% PCMB104T-R22MS 35A +CPU_CORE
1 4
<44> SW1
2 3
5

<44> LG1

1
PQ902
R22

4.7_1206_5%
PR937 @
V1N_CPU
CPU_B+
0.82mohm

10U_0805_25V6K

10U_0805_25V6K
5
4 2 1
CSREF <44>
2
1SNUB_CPU1
PQ905

1
PR939

PC938

PC939
10_0402_1%

680P_0603_50V7K
MDU1511RH_POWERDFN56-8-5 SWN1 <44>
3
2
1

2
PC922 @
4
<44> HG3
C C
2

MDU1516URH_POWERDFN56-8-5
+CPU_CORE

3
2
1
PL904
0.22UH +-20% PCMB104T-R22MS 35A
1 4
<44> SW3

1
2 3

4.7_1206_5%
5

PR943 @
<44> LG3
PQ906

2
PR944
4 V3N_CPU 2 1 CSREF

SNUB_CPU3
10_0402_1%

MDU1511RH_POWERDFN56-8-5 SWN3 <44>

3
2
1

680P_0603_50V7K
PC940 @
1
2
CPU_B+

10U_0805_25V6K

10U_0805_25V6K
PC932 @37W

PC933 @37W
PR936 @37W

1
2.2_0603_5%
B B
BSTA2 1 2 BSTA2_1
@37W
0.22U_0402_10V6K

2
5

PQ903
PC923 @37W
1
2

4
PU902 @37W
NCP81151MNTBG_DFN8_2X2
1 9
BST FLAG
MDU1516URH_POWERDFN56-8-5 PL903 @37W +CPU_CORE
3
2
1

2 8 HG2 0.22UH +-20% PCMB104T-R22MS 35A

<44> 81103_PWM PWM DRVH
PR935 @37W
2 1EN_VCORE2 3 7 SW2 1 4
<44> DRON EN SW
2K_0402_1%
+5VS 2 1 VCC_VCORE2 4 6 2 3
VCC GND
5

PR933 @37W 5 LG2 PQ904

4.7_1206_5%
2.2U_0603_10V7K

DRVL
PR940 @

0_0402_5% @37W
PC919 @37W
1

4
2

SNUB_CPU2 2

PR941 @37W
10_0402_1%
MDU1511RH_POWERDFN56-8-5 V2N_CPU 2 1 CSREF
3
2
1

680P_0603_50V7K
PC930 @
1

SWN2 <44>
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: Wednesday, October 03, 2012 Sheet 45 of 47
5 4 3 2 1
 A
B
C
D
+CPU_CORE

2 1 2 1

PC947 PC946

5
5

22U_0805_6.3V6M 22U_0805_6.3V6M
+

2
1
2
1
2
1

PC950 PC949 PC948

+CPU_CORE

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2V_Y

+

2
1
2
1
2
1

PC953 PC952 PC951

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2V_Y
+

2
1
2
1
2
1

PC956 PC955 PC954

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2V_Y
34 X 22u/0805

2
1
2
1
2
1
3 X 330u/9m(47W)

PC959 PC958 PC957

22U_0805_6.3V6M 22U_0805_6.3V6M @330U_D2_2V_Y
+

2 1 2 1
2
1

PC962 PC961 PC960

22U_0805_6.3V6M 22U_0805_6.3V6M @330U_D2_2V_Y

2 1 2 1 2 1

PC965 PC964 PC963

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

4
4

34 X 22u/0805

2 1 2 1
2X330u/9m(37W)

2
1

PC968 PC967 PC966

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1
2
1

PC971 PC970 PC969

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1
2
1

PC974 PC973 PC972

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1
2
1

PC977 PC976 PC975

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1

PC979 PC978
22U_0805_6.3V6M 22U_0805_6.3V6M

Issued Date
2 1 2 1

Security Classification
PC981 PC980
22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1

3
3

PC983 PC982
22U_0805_6.3V6M 22U_0805_6.3V6M

2 1

PC984
22U_0805_6.3V6M

2012/04/03
Compal Secret Data
Deciphered Date

2
2

2014/12/31

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title

Date:
Gx00
Document Number

W ednesday, October 03, 2012

1
1

PROCESSOR DECOUPLING

Sheet
Compal Electronics, Inc.

of 46
47
0.1
Rev
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

D
2 D

7
C C

10

11

12
B B

13

14

15

A 16 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Gx00
Date: W ednesday, October 03, 2012 Sheet 47 of 47
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