Robert Jason D.
Ramos
4-BSECE
Computer System Organization
Intel Microprocessor
8086
Introduced June 8, 1978
Clock rates:
5 MHz, 0.33 MIPS
8 MHz, 0.66 MIPS
10 MHz, 0.75 MIPS
The memory is divided into odd and even banks. It accesses both banks concurrently to
read 16 bits of data in one clock cycle
Data bus width: 16 bits, address bus: 20 bits
29000 transistors at 3 μm
Addressable memory 1 megabyte
Up to 10× the performance of 8080
First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable
computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300
/ Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line)
Used segment registers to access more than 64 KB of data at once, which many
programmers complained made their work excessively difficult.[citation needed]
The first x86 CPU
Later renamed the iAPX 86
8088
Introduced June 1, 1979
Clock rates:
4.77 MHz, 0.33 MIPS
8 MHz, 0.66 MIPS
16-bit internal architecture
External data bus width: 8 bits, address bus: 20 bits
29000 transistors 29,000 at 3 μm
Addressable memory 1 megabyte
Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end);
identical Execution Unit (EU), different Bus Interface Unit (BIU)
Used in IBM PC and PC-XT and compatibles
Later renamed the iAPX 88
80186
Introduced 1982
Clock rates
6 MHz, > 1 MIPS
55000 transistors
Included two timers, a DMA controller, and an interrupt controller on the chip in
addition to the processor (these were at fixed addresses which differed from the IBM
PC, although it was used by several PC compatible vendors such as Australian company
Cleveland)
Added a few opcodes and exceptions to the 8086 design, otherwise identical instruction
set to 8086 and 8088
BOUND, ENTER, LEAVE
INS, OUTS
IMUL imm, PUSH imm, PUSHA, POPA
RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg,imm
Address calculation and shift operations are faster than 8086
Used mostly in embedded applications – controllers, point-of-sale systems, terminals,
and the like
Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000,
and CP/M 86 Televideo PM16 server
Later renamed to iAPX 186
80188
A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188
80286
Introduced February 2, 1982
Clock rates:
6 MHz, 0.9 MIPS
8 MHz, 10 MHz, 1.5 MIPS
12.5 MHz, 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available.
Data bus width: 16 bits, address bus: 24 bits
Included memory protection hardware to support multitasking operating systems with
per-process address space.
134,000 transistors at 1.5 μm
Addressable memory 16 MB
Added protected-mode features to 8086 with essentially the same instruction set
3–6× the performance of the 8086
Widely used in IBM PC AT and AT clones contemporary to it
80386SX
Introduced June 16, 1988
Clock rates:
16 MHz, 2.5 MIPS
20 MHz, 3.1 MIPS, introduced January 25, 1989
25 MHz, 3.9 MIPS, introduced January 25, 1989
33 MHz, 5.1 MIPS, introduced October 26, 1992
32-bit internal architecture
External data bus width: 16 bits
External address bus width: 24 bits
275,000 transistors at 1 μm
Addressable memory 16 MB
Virtual memory 64 TB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No math co-processor
No commercial software used protected mode or virtual storage for many years
Later renamed Intel386 SX
80486DX
Introduced April 10, 1989
Clock rates:
25 MHz, 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
33 MHz, 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
50 MHz, 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2),
introduced June 24, 1991
Bus width: 32 bits
1.2 million transistors at 1 μm; the 50 MHz was at 0.8 μm
Addressable memory 4 GB
Virtual memory 64 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50× performance of the 8088
Officially named Intel486 DX
Used in Desktop computing and servers
Family 4 model 1
80486SX
Introduced April 22, 1991
Clock rates:
16 MHz, 13 MIPS
20 MHz, 16.5 MIPS, introduced September 16, 1991
25 MHz, 20 MIPS (12 SPECint92), introduced September 16, 1991
33 MHz, 27 MIPS (15.86 SPECint92), introduced September 21, 1992
Bus width: 32 bits
1.185 million transistors at 1 μm and 900,000 at 0.8 μm
Addressable memory 4 GB
Virtual memory 64 TB
Identical in design to 486DX but without a math coprocessor. The first version was an
80486DX with disabled math coprocessor in the chip and different pin configuration. If
the user needed math coprocessor capabilities, he must add 487SX which was actually
an 486DX with different pin configuration to prevent the user from installing a 486DX
instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with
only 1 effectively turned on
Officially named Intel486 SX
Used in low-cost entry to 486 CPU desktop computing, as well as extensively in low cost
mobile computing
Upgradable with the Intel OverDrive processor
Family 4 model 2
80486DX2
Introduced March 3, 1992
Runs at twice the speed of the external bus (FSB)
Fits in Socket 3
Clock rates:
40 MHz
50 MHz
66 MHz
Officially named Intel486 DX2
Family 4 model 3
80486SL
Introduced November 9, 1992
Clock rates:
20 MHz, 15.4 MIPS
25 MHz, 19 MIPS
33 MHz, 25 MIPS
Bus width: 32 bits
1.4 million transistors at 0.8 μm
Addressable memory 4 GB
Virtual memory 64 TB
Officially named Intel486 SL
Used in notebook computers
Family 4 model 4
80486DX4
Introduced March 7, 1994
Clock rates:
75 MHz, 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
100 MHz, 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
1.6 million transistors at 0.6 μm
Bus width: 32 bits
Addressable memory 4 GB
Virtual memory 64 TB
Pin count 168 PGA Package, 208 sq. ftP Package
Officially named Intel486 DX4
Used in high performance entry-level desktops and value notebooks
Family 4 model 8
