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Assignment 1

This document provides instructions for Assignment 1 for the course SKEL4743 Basic Digital VLSI Design. The assignment involves using transistor-level simulation to: 1) Plot ID-VDS and ID-VGS curves for NMOS transistors with different W/L ratios and channel lengths to analyze the impact of these parameters. 2) Design a CMOS inverter and pseudo-NMOS inverter to operate at mid-supply voltage and simulate their voltage transfer characteristics and transient response. 3) Compare and discuss the results of the CMOS and pseudo-NMOS inverter designs.

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214 views2 pages

Assignment 1

This document provides instructions for Assignment 1 for the course SKEL4743 Basic Digital VLSI Design. The assignment involves using transistor-level simulation to: 1) Plot ID-VDS and ID-VGS curves for NMOS transistors with different W/L ratios and channel lengths to analyze the impact of these parameters. 2) Design a CMOS inverter and pseudo-NMOS inverter to operate at mid-supply voltage and simulate their voltage transfer characteristics and transient response. 3) Compare and discuss the results of the CMOS and pseudo-NMOS inverter designs.

Uploaded by

mid_cyclone
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SCHOOL OF ELECTRICAL ENGINEERING

FACULTY OF ENGINEERING
UNIVERSITI TEKNOLOGI MALAYSIA
2019/2020-I

SKEL4743 Basic Digital VLSI Design


ASSIGNMENT 1

Instruction: Work individually. Write a report to show the results and the discussion and
submit to elearning.

Assignment 1a: -

Using transistor model level 49, perform the tasks below: -

1) For an NMOS transistor with W/L=1.5 and L=0.25um: -


a. Plot an ID-VDS curves with simulation setting as below:-
i. VGS=2.5V.
ii. Vary VDS from 0V to 2.5V with an increment of 0.01V.
b. Plot an ID-VGS curve with simulation setting as below:-
i. VDS=2.5V
ii. Vary VGS from 0V to 2.5V with an increment of 0.01V.
2) Repeat task (1) but for NMOS with W/L=1.5 and L=40 times larger than L in task (1).
3) Compare the simulation results from task (1) and task (2), and discuss the comparison results.
To ease the comparison process, draw the circuit for task (1) and (2) in the same schematic
page so that you can plot the results on the same axes.
4) Repeat task (1) to (3) but for PMOS transistor.

Assignment 1b: -

Using transistor model level 49, perform the tasks below: -

1) Design a CMOS Inverter for VM = VDD/2.


a. Determine and calculate W and L for NMOS and PMOS (use transistor parameters as
given in class).
b. Simulate and plot the VTC for the inverter and check whether VM is as expected.
c. From the VTC, find VIL, VIH, VOL, VOH, NMH and NML.
d. Apply a square wave signal to the inverter input, then plot Vin and Vout for two cycle
only and measure tPHL, tPLH, tr and tf.
2) Design a Pseudo NMOS Inverter for VM = VDD/2.
a. Determine and calculate W and L for NMOS and PMOS (use transistor parameters as
given in class).
b. Using the answer in (6a), calculate VOL.
SCHOOL OF ELECTRICAL ENGINEERING
FACULTY OF ENGINEERING
UNIVERSITI TEKNOLOGI MALAYSIA
2019/2020-I

c. Simulate and plot the VTC for the inverter and check whether VM and VOL are as
expected.
d. From the VTC, find VIL, VIH, VOH, NMH and NML.
e. Apply the same square wave signal as in task (1)d to the inverter input, then plot Vin
and Vout for two cycle only and measure tPHL, tPLH, tr and tf.
3) Compare and discuss the results in task (1) and (2). To ease the comparison process, draw the
circuit for task (1) and (2) in the same schematic page so that you can plot the results on the
same axes.

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