Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)

IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

Parallel Implementation of Cryptographic Algorithm:

AES Using OpenCL on GPUs
Govardhana Rao Inampudi Prof. Shyamala K Prof.S.Ramachandram
Department of Computer Science and engineering Department of Computer Science and engineering Department of Computer Science and engineering
Osmania University, Hyderabade Osmania University, Hyderabade Osmania University, Hyderabade
igrao10@gmail.com prkshyamala@gmail.com Schandram@gmail.com

Abstract—The importance of protecting the information has GPU implementation of the AES algorithm. Experimental
increased rapidly during the last decades. This motivates the results followed by conclusions are presented in section IV
need for cryptographic algorithms. The Acceleration of the and V respectively.
symmetric key cryptography algorithm is enhanced using
parallel implementation on GPGPUs with Open Computing II. LITERATURE SURVEY
Language (OpenCL). The General Purpose Graphics
Processing Units (GPGPU) enables high level of parallelism Details of AES algorithm [5], hardware and software
with Compute Unified Device Architecture (CUDA)/Open employed are briefly discussed in this section. The software
Computing Language (OpenCL) programming environments constructs and terms used in the implementation are also
using (Single Instruction Multiple Data) SIMD architecture. In elucidated. The program flow of OpenCL [2] is explained in
this paper, the parallel implementation of Advanced detail.
Encryption Standard (AES) Algorithm using OpenCL is
A. Advanced Encryption Standard Algorithm
presented. The experimental results show that, the parallel
implementation of encryption algorithm tested on GPUs
accelerates the speed when compared to sequential The Advanced Encryption Standard (AES) is a specification
implementation of encryption algorithm. The experimental for the encryption of electronic data established by the
result shows that, the percentage 99.8% is improved compared National Institute of Standards (NIST) [3] in 2001 based on
to sequential implementation of Encryption algorithm. Rijndael cipher, where input is a plain text and encryption
produces cipher text.
Keywords: Advanced Encryption Standard (AES), Graphics
Processing Unit (GPU), Image Restoration, OpenCL, SIMD The algorithm has four rounds based on Rijndael cipher [6] as
shown in Fig 2:
I. INTRODUCTION
The Graphics Processing Unit (GPU) [1] plays a vital role in 1. Key Expansion: Round keys are derived from the
various types of image and video processing applications. The cipher key using Rijndael’s key schedule. 128-bit
invention of these many core GPUs provides the scope to round key block for each round is required for AES.
accelerate speed in case of massive parallel applications. The
GPU ported applications improves the performance by 2. Initial Round: Each byte of the state is combined
offloading the compute intensive part onto GPU and with a block of the round key using bitwise XOR.
remaining code onto Central Processing Unit (CPU). The
multi core GPUs provide high performance for data parallel 3. Rounds:
tasks using SIMD architectures [2] [3]. In [4], the author i) Sub Bytes: A non-linear substitution step where
shows that, the usage of GPGPUs accelerates the each byte is replaced with another based on lookup
cryptographic solution to crack the UNIX password cipher in table.
100 MHz. ii) Shift Rows: In this step, the last three rows of the
states are shifted cyclically.
The focus of this paper is to accelerate the implementation of iii) Mix Columns: In this step, the four bytes in each
AES algorithm. The proposed work is implemented using columns are combined.
OpenCL and tested on Nvidia GPUs. The experimental results iv) AddRoundKey: In this step, the sub key is added
are compared with sequential implementation on different set by combining each byte of the state with the
of inputs. corresponding byte of the sub key using bit wise
The rest of the paper is organized as follows: section II XOR.
discusses the existing parallel formulation of AES algorithm 4. Last Round: In this round, Sub Bytes, Shift Rows
and introduction to GPU computing. Section III describes the and an AddRoundKey operation takes place.

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 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

B. Introduction to Graphics Processing Unit D. Introduction to OpenCL

The Graphics Processing Unit (GPU) is a specialized
electronic circuit designed to accelerate the creation of images Open CL is a framework for parallel programming of
in a frame buffer intended for output to display. A typical heterogeneous systems. OpenCL provides an effective way to
GPU is characterized by the presence of hundreds of cores program for heterogeneous systems, homogeneous, multi-core
compared to any conventional CPU, which has limited number processors. The OpenCL execution model comprises of two
of cores, such as 2 to 16 cores. GPUs are used in embedded components, such as kernels and host programs. kernels are
systems, mobile phones, personal computers, workstations, the basic unit of executable code that runs on one or more
and game consoles. Modern GPUs are very efficient at OpenCL devices. Similar to C functions, kernels can be
manipulating computer graphics and image processing, and invoked using data or task parallelism. The host program
their highly parallel structure makes them more effective than executes on the host system called as device context, and
general-purpose CPUs for algorithms where, the large blocks queues kernel execution instances using command queues.
of data is processed in parallel. Kernels are queued in in-order, but can be executed in either
in-order or out-of-order. OpenCL allows the kernel to access
Global memory, Constant memory, Local memory and private
memory.
A profiler is used to analyze the various constraints, and
aspects of a program. AMD APP Profiler is a performance
analysis tool that gathers data from the OpenCL run-time and
AMD Radeon GPUs during the execution of an OpenCL
application. Similarly, CodeXL also gives comparative
analysis of kernel executions. In this paper, these profilers are
used to analyze the kernels execution for AMD Radeon
8550M GPU.

In [8], the author proposed two schemes for parallel AES

encryption implementation with off-line key expansion on
shared-memory multi core architecture. The tasks are equally
partitioned and grouped into cluster. High efficient inter-core
communication is obtained based on the shared memory. This
Figure 1 Basic Unified GPU Architecture kind of implementation reduces the latency for a single AES
encryption, compared with pipelining schemes.
C. Implementation of AES using GPUs The author [6] describes both traditional style approaches
based on the OpenGL graphics API and presents an efficient
This section presents the details of sequential implementation
implementation of the AES algorithm in the CUDA platform
of AES algorithm and GPU implementation of AES algorithm.
by NVIDIA Graphics card. The performance of the new
The various steps in AES algorithm is shown in Fig 2. The
fastest GPU solution is compared with those of the reference
time taken to execute all the rounds increases linearly as the
input size increases. sequential implementations running on an Intel Pentium IV
3.0 GHz CPU.

III. PARALLEL IMPLEMENTATION OF AES ALGORITHM

In this section, the parallel implementation of AES algorithm

is discussed in detail. The various steps involved in parallel
Implementation are as follows:

1. The kernel functions are programmed based on data

decomposition technique, data input is divided into 256 work-
items which is maximum possible for the GPU hardware used
in this paper.
2. Data Parallelism is achieved by utilizing the maximum
available work-items, which in turn assigns these elements to
multiple threads and simultaneously to GPU cores for
execution. For the AMD 8550M and AMD 8570M GPU’s, a
Fig. 2. Steps in AES Algorithm maximum of 16777216 elements can be invoked at a time.

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 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

3. OpenCL constructs, such as BARRIER construct Code Snippet for Parallel Formulation of shift row
allows results to be copied back to the host program function:
only after complete execution of a work-group // Rotate first row 1 columns to right
4. The AES algorithm employed is of 14 rounds (i.e,
256-AES). if ( k==4)
5. The size of each work item is 24 bits, which {
represent the RGB pixels in hexadecimal. emp=P [ i + 3 ] ;
P [ i +3]=P [ i + 2 ] ;
P [ i +2]=P [ i + 1 ] ;
P [ i +1]=P [ i ] ;
P [ i ]= temp ;
}
// Rotate second row 2 columns to right

i f ( k==8)
{
emp=P [ i ] ;
P [ i ]=P [ i + 2 ] ;
P [ i +2]= temp ;
temp=P [ i + 1 ] ;
P [ i +1]=P [ i + 3 ] ;
P [ i +3]= temp ;
}
// Rotate third row 3 columns to right
Fig 3: Flow diagram of Parallel implementation of AES i f ( k==12)
algorithm {
emp=P [ i ] ;
As shown in Fig 3, the Encrypt() function executed P [ i ]=P [ i + 1 ] ;
concurrently, where as key expansion is executed P [ i +1]=P [ i + 2 ] ;
sequentially. Based on the prefix computation technique, the P [ i +2]=P [ i + 3 ] ;
encrypt function is executed concurrently by utilizing the P [ i +3]= temp ; }
supported GPUs. The parallel formulation of the shiftrow()
function is illustrated with the example is as follows:

Code Snippet for Sequential Execution of shift row IV. EXPERIMENTAL RESULTS
function:

/ / Rotate first row 1 columns t o l e f t The parallel implementation of the proposed work is
Temp= s t a t e [ 1 ] [ 0 ] ; implemented using OpenCL and tested on GPUs. The GPU
state[1][0]=state[1][1]; implementation of AES algorithm is tested on AMD Radeon
state[1][1]=state[1][2]; 8550M GPU and 8570G GPU. AMD APP Profiler is used for
state[1][2]=state[1][3]; performance analysis, to evaluate the proposed work from the
s t a t e [ 1 ] [ 3 ] = temp ; OpenCL run-time and AMD Radeon GPUs during the
/ / Rotate second row 2 columns t o l e f t execution of an Open CL application. The figure 4 shows the
Temp= s t a t e [ 2 ] [ 0 ] ; screen-shots of GPU implementation of the proposed work.
state[2][0]=state[2][2]; Various parameters like the GPU platform being executed
s t a t e [ 2 ] [ 2 ] = temp ; currently, the global and local item sizes processed by the
Temp= s t a t e [ 2 ] [ 1 ] ; GPU, kernel occupancy of OpenCL application are considered
state[2][1]=state[2][3]; to evaluate the proposed work.
s t a t e [ 2 ] [ 3 ] = temp ;
/ / Rotate third row 3 columns t o l e f t Table I shows the execution time in milliseconds for the
Temp= s t a t e [ 3 ] [ 0 ] ; encryption and decryption functions. As shown in the Table I,
state[3][0]=state[3][3]; First column represents the number of work items, column 2
state[3][3]=state[3][2]; and 3 lists the time taken for parallel implementation of the
state[3][2]=state[3][1]; proposed work and column 4 and 5 represents the time taken
s t a t e [ 3 ] [ 1 ] = temp ; for sequential implementation of AES algorithm. As the

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 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

number of work items increases from 256 to 1024, the

execution time for GPU implementation of AES algorithm is
Table II: Execution Time of GPU Implementation of AES
rapidly decreasing when compared to sequential Algorithm on 8550M and 8570G
implementation. The best speedup achieved for GPU
implementation is 98.8% when compared to sequential Work-items Encrypt Decrypt Encrypt Encrypt
implementation for 1024 work items. When the number of 8550G(ms) 8550G(ms) 8570M(ms) 8570M(m)
work items are more than 1024, the execution time is
256 0.131 0.098 0.093 0.09
increasing due to the communication and task interactions
between the nodes. Due the communication latency and task 1024 0.129 0.104 0.093 0.09
interactions, the execution time for GPU implementation is
2560 0.136 0.108 0.095 0.089
increasing , but when compared to sequential implementation
for 10240000 work items, the percentage of speedup is 99.6%. 10240 0.27 0.27 0.122 0.111

25600 0.62 0.65 0.263 0.241

Figure 4 shows the execution time for GPU implementation
for two different GPU devices, such as 8550M and 8570G, 102400 2.3 2.3 0.759 0.721
where X-axis represents the work item sizes and Y-axis
256000 5.08 4.884 1.74 1.597
represents the time taken to execute the encryption and
decryption function. This shows that, the same implementation 1024000 18.95 15.94 4.885 4.532
has given different results of time based on the execution
2560000 46.36 37.85 12.119 11.223
depending on the configuration of the devices indicating scope
for further efficient results. The graph shows the improvement 10240000 183.6 147 48.4 44.7
in execution time for two different devices, indicates that,
there is a scope for further improvement to enhance speedup.

Table I: Sequential and Parallel Execution Time of AES

algorithm.
Work Execution Execution Execution Execution
Items time for time for time for time for
Parallel Parallel Sequential Sequential
Encryption Decryption Encryption Decryption
(ms) (ms) (ms) (ms)
256 0.131 0.098 2 3

1024 0.129 0.104 10 10

Fig. 4. Parallel Implementation 8550M vs 8570G
2560 0.136 0.108 10 10

102400 2.3 2.3 460 710

25600 5.08 4.884 1246 1685

1024000 18.95 15.94 4488 7066 V. CONCLUSION

In this paper, the Acceleration of the symmetric key
2560000 46.36 37.85 11589 17351
cryptography algorithm is enhanced using parallel
10240000 183.6 147 `44256 70823 implementation on GPGPUs with Open Computing Language
(OpenCL). The Advanced Encryption Standard (AES)
Algorithm is implemented using OpenCL and tested on GPU
devices, such as 8550M and 8570G. The experimental results
Table II shows the execution time in milliseconds for the
shows that, the parallel implementation of encryption
encryption and decryption functions on two different GPU
algorithm tested on GPUs accelerates the speed when
devices. As shown in the Table II, First column represents the
compared to sequential implementation of encryption
number of work items, column 2 and 3 lists the time taken for
algorithm. The percentage of speedup achieved on 1024 work
GPU implementation of the proposed work on 8550M device
items is 99.8%. compared to sequential implementation of
and column 4 and 5 represents the time taken GPU
AES algorithm
implementation of the proposed work on 8570G device.

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 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

VI. REFERENCES

[1] D. Kirk, “Nvidia CUDA software and GPU parallel

computing architecture,” in ISMM, vol. 7, 2007,
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[2] Y. Boykov and V. Kolmogorov, “An experimental

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[3] A. Brunton, C. Shu, and G. Roth, “Belief propagation on

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[4] G. Kedem and Y. Ishihara, “Brute force attack on Unix

passwords with simd computer,” in Proceedings of the 8th
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[5] http://www.nvidia.com/object/cuda opencl.html.

[6] Svetlin A. Manavski, “CUDA compatible GPU as an

efficient hardware accelerator for AES cryptography”, In
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[7] J. Daemen, V. Rijmen, “AES Proposal: Rijndael”, Original

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[8] Jielin Wang, Weizhen Wang, Jianw ei Yang, Zhiyi Yu, Jun
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