GROUP 6

VLSI SYSTEM DESIGN

(ELE 556)

TITLE :
ICC LAB REPORT

PREPARE BY :
NAME STUDENT NO GROUP
MUHAMMAD AMIR LUQMAN BIN 2016348665 PEE2007D2
SUJANA
MUHAMMAD NUR HADI BIN AB SAMAT 2016343615 PEE2007D2
OBJECTIVES
PnR 1
1. To familiarize you with the IC Compiler GUI
2. To learn how to get help with command and variables
PnR 2
1. Explore additional features of the IC Compiler GUI
2. Perform GUI based analysis
PnR 3
1. Walk through the data setup process of creating and maintaining a Milkyway database
to hold your design
2. Run a complete basic flow, from loading a floorplan through routing
PnR 4
1. To create power/ground rings and straps using Power Network Synthesis
2. To able analyse IR drop using Power Network Analysis

PROCEDURE
PnR 1 IC Compiler GUI
Task 1 Start IC Compiler
1. Log in to the UNIX environment with the assigned user id and password
2. Before invoking IC Compiler, we want to remove a GUI window configuration file, if
it exists. This file exists if you have previously invoked IC Compiler in this login
account – its purpose is to remember the last GUI window configuration you had
before exiting the tool, so that the configuration will look the same the next time you
invoke the tool. For this lab we need you to start with a default window configuration.
If the following file exists in your home directory, delete it.
rm ~/.config/Synopsys/icc_shell.conf
3. Form the lab’s installation directory, change to the following working directory and
install the lab
UNIX% cd ~lab_work/icc/lab0/ORCA_TOP/rm_icc.tmp
UNIX% make restore_lab0
4. Start IC Compiler and load a routed design using the provided make script
UNIX% make load
5. Have a look in current directory. In the IC Compiler shell type
icc_shell> ls
6. Start the GUI
7. Bring the LayoutWindow to the foreground, enlarge or maximize the LayoutWindow
Task 2 Navigating the Layout View
1. Spend few minutes to familiar with the zoom and pan buttons in the LayoutWindow
 2. Hot keys are also available when the LayoutWindow is active
3. You can find out about other hot key definitions in two ways: Hover with the mouse
over a button and a “balloon help” will appear showing the name of the function and
the keyboard shortcut. You can also select the pull down menu Help  Report
Hotkey Bindings. A new view appears, listing the hot key definitions. To close this
view select Window  Close View or [Ctrl W].
4. Some people like to use mouse “strokes” to pan and zoom, instead of using GUI
buttons or keyboard “hot keys”. Zoom in on an area of interest: Lower-case [Z] and
[Esc].
5. The keyboard arrow keys can also be used to pan the display North/South/East/West.
6. If your mouse has a scroll wheel, it can be used to zoom in/out (2X or ½X) around the
area of the mouse’s pointer.
Task 3 Controlling Object and Layer Visibility
1. In the Vis. Column (Visible), uncheck everything except Cell. The fastest way to do
this is to right-click on the Vis. label and select Hide All, then check the Cell box.
2. Now check PIN
3. Check Labels
4. In selection mode, draw a box to fully enclose one of the standard cells. This selects
all selectable objects inside the box, which highlighted in white
5. Make pins un-selectable by unchecking the box under the Sel. column (Selectable).
Draw the same box again to see that only the standard cell is selected
6. Check Route. All routes are displayed. Expand Route and Net Type under it, turn off
Power and Ground
7. Save the view setting.
8. Select Default from the pull down list to restore the default settings.
9. Select Layers tab, which can be used to “fine tune” the routing visibility further on a
layer by layer basis
10. Zoom into the middle of the block
11. This design uses a total of seven metal routing layer.
12. Observe the routes as you turn on one layer at a time.
13. The individual object type can be turned on/off by clicking the patterned colour
squares.
14. The check marks control layer selectability
Task 4 Querying and Selecting Objects
1. To be able tp query or select objects, the mouse cursor must be an arrow.
2. Hover the cursor arrow over an object without clicking the mouse. The object is
highlighted with dashed white lines, and an “InfoTip” box appears in the bottom left,
displaying some key attributes of the object.
3. Now select a single object with a left mouse click. The selected object is highlighted
with solid white lines, and remains highlighted until un-selected, or a different object
is selected. Keep the object selected.
4. While one object is selected, hover the mouse cursor over a different object. Notice
that the “InfoTip” box displays information about the “dashed white line” object, not
the selected (solid white line) object.
 5. To obtain a “full query” of a selected object press lower-case [Q] or use the menu:
Select Query Selection. A query panel opens and lists all the attribute values of the
selected object.
6. Close the query panel by clicking the “Hide” minus sign in its upper right corner, or
by right-clicking in the top or bottom banner area of the panel and selecting “Hide”.
7. Unselect all objects by either clicking on an empty area in the layout, by using the
menu Select Clear, or by typing [Ctrl D].
8. Select multiple objects in the same area with a left button “drag-and-draw”. All
selectable objects within the drawn rectangle are selected.
9. Keep what is selected and select additional objects by holding down the [Ctrl] key
while selecting with the left mouse click.
10. Click on an area with multiple objects stacked on top of each other (for example, a via
connecting a horizontal and a vertical metal route). Notice that one object will be
selected (solid white), while a different object will be queried (dashed white). The
“InfoTip” box goes with the “dashed” object.
11. Cycle through the “stacked” objects by repeatedly clicking the left mouse button.
Notice that both the solid and dashed line objects cycle.
12. Select the Objects tab at the top of the View Settings panel and turn off Route
visibility.
13. Select a handful of standard cells by dragging a selection box around them.
14. If it is difficult to notice the highlighted objects among other bright objects, it is
possible to reduce the “brightness” of the unselected objects, thereby increasing the
contrast. A “Brightness” control is located at the top of the View Settings panel.
15. Reduce the brightness to 50% to see the improved contrast.
16. From the MainWindow or LayoutWindow use File Close Design to remove the
current design from the tool’s memory. If the Close Design dialog box appears, click
on Discard All to close the design without saving it.
17. You are done using the GUI. To close the GUI, while keeping the IC Compiler
session active, type:
stop_gui
Task 5 Getting Help with Command and Variables
1. IC Compiler supports command name, variable name, file name and command option
“completion” through the [Tab] key. Try the following in the IC Compiler command
shell window:
h[Tab]e[Tab] –v[Tab] help[Enter]
2. To view the man page on a command or variable you need to enter the exact
command or variable name. Alternatively, you can enter the starting characters of the
command/variable and use command completion to find the rest. If you are not sure
what the exact name is, use help for commands, and printvar for variables, along with
the * wildcard. Here are some examples:
Let’s say you are looking for more information about a certain optimization command.
You do not remember the exact command name, but you know it contains the string
“syn” (for “synthesis”). To list all commands that contain this string enter:
help *syn*
3. To list the available options for psynopt:
 help –verbose psynopt
4. To get a full help manual page – a detailed description of the command and all of its
options, type:
man psynopt
5. Now let’s say you need help on a specific variable, but again, you don’t remember its
exact name, but it contains “library”. To list all variables containing this string, enter:
printvar *library*
6. To get a full help manual page of the variable, type:
man target_library
7. Lastly, get additional help with an error or warning message, using the unique
message code
man PSYN-025
8. Quit the IC Compiler shell

PnR 2 More ICC GUI

Task 1 Window Configuration
1. Before invoking IC Compiler, remove the GUI window configuration file, which was
created during Lab 1. The file’s purpose is to remember the last GUI window
configuration you had before exiting the tool, so that the configuration will look the
same the next time you invoke the tool. For this lab we need you to start with a
default window configuration.
rm ~/.config/Synopsys/icc_shell.conf
2. From the lab’s installation directory, change to the following working directory and
install the lab
cd ~/lab_work/icc/lab0/ORCA_TOP/rm_icc/tmp
make restore_lab0
3. Start IC Compiler and load a routed design using the provided make script
make load
4. Start the GUI
5. If the Overview window and/or the View Setting panel are missing, perform Step10 to
bring them back, then return to continue the next step.
6. Undock the View Settings panel by right clicking over the top edge of the panel (over
the two horizontal lines), and selecting “Float”. The view is now stand-alone (floating
or undocked) in its own window. Left-click at the top of the floating panel and drag to
move it wherever you like.
7. Dock the panel by right clicking its top edge and selecting Dock Left.
8. Move the position of the Overview window down, below the View Settings panel, by
left-clicking its top banner to “grab and drag” the window down. Release the mouse
button when the window is below the View Settings panel. You can also use this
method to undock and re-dock a window.
9. Close both the Overview and the View Settings windows by clicking their “Hide”
icon in the top right corner or by right-clicking the top edge and selecting “Hide”.
The windows are hidden. This gives you maximum viewing area for your layout.
 10. Re-open the Overview and View Settings windows as follows: Right-click anywhere
in the grey tool bar areas at the top or the left of the LayoutWindow (where the pull-
down menu selections are listed). A menu appears listing the available tool-bar views,
followed by the four window views. Select “Overview”. The Overview window
appears on the left. Open the View Settings panel by either pressing the [F8] hot key
or repeating the above step and selecting View Settings.
11. From the top tool bar select the “Window” pull-down menu. Near the bottom is a list
of all open windows. Selecting one brings that window to the foreground. You can do
the same thing with [Ctrl `] - Control plus “back-tick” (usually below the “tilde” ~).
12. You can have multiple “layout views” displayed in one LayoutWindow. Open a new
layout view by selecting View New Layout View. The new view is displayed,
along with two “tabs” at the bottom, labeled Layout.1 and Layout.2. You can display
the different views by selecting the tab, or by setting up “cascaded” or “tiled” views
(Window Tile Views or Cascade Views).
13. Maximize one of the two layout views. Optionally, close the other.
Task 2 Pan and Zoom History
1. If the “history buttons” shown here do not already appear in the LayoutWindow tool
bar, right-click in the tool bar and select “Zoom and Pan History”. Three additional
“history” buttons are added to the tool bar.
2. Tool-bar button “groups” can be “collapsed” to take up less room, or the relative
location of the groups can be moved to the left or right by left-clicking over the
double-vertical bars and dragging and dropping in the desired area.
3. Zoom in on an area of interest: lower-case [Z], then [Esc].
4. Click on the right-most “history” button shown above or select the menu entry View
Zoom Named Zoom and Pan Settings.
5. In the dialog box enter the name “myzoom”, click Add and then Close.
6. Return to a full view, by typing lower-case [F] key.
7. To retrieve the saved view, bring up the same dialog box, select “myzoom” and click
on Zoom To. Close the dialog box.
8. Pan or zoom to several different areas of interest on the layout and then try the “Go
Back” and “Go Forward” buttons to cycle through the view history.
Task 3 Selection Lists, Highlighting and Querying
1. Selection lists. Turn Route visibility off.
2. Zoom into core area of the layout and select four or five standard cells.
3. Reduce the brightness to 50% to improve the contrast. The “Brightness” control is
located at the top of the View Settings panel.
4. Show the selected objects in a list format: Use the Select Selection List menu entry.
5. The list can be further filtered by using the Select/Deselect buttons: Using the [Shift]
or [Ctrl] key, select all except the first two objects from the selection list and click the
Deselect button to remove them from the list. Notice that only those two standard
cells remain selected in the LayoutWindow.
6. Keep the selection list open, and the standard cells selected.In the tool bar locate the
solid yellow “color” rectangle. Click on the pull-down menu and select the color red,
then click on the “pen” button to apply the highlight to the selected cells. If the
 selection list disappeared bring it back with [Ctrl L]. To see the colored highlights you
must unselect the cells ([Ctrl D] or click an area with no objects). The objects remain
highlighted in red.Select one other cell that is not currently highlighted.
7. By default, when the cursor arrow hovers over an object, the object is lightly
highlighted, and an “InfoTip” box appears, displaying some key attributes of the
object. To obtain a “full query”, select a single standard cell, and query it by typing
lower-case [Q] or by using the menu entry: Select Query Selection. A window opens
and lists all the cell’s attributes and attribute values. You may need to expand the
window to the left to see the values of each attribute.
8. Close the query window by clicking Hide minus sign
9. If you do not want to change the current set of selected items, or you want to query
many objects, there is an alternative method.
10. Select a few standard cells again. A final way to look for information in a list of
selected cells is with the menu entry.
11. Click the right and left blue arrow buttons to cycle through the properties of each item
in the selection one at a time. Check the “All” box to see the properties that are
identical for all the selection items.
 12. 12. Cancel the Properties dialog box, unselect all objects [Ctrl D], and fit the
layout view to the window [F]. Return the “brightness” to 100%.

Task 4 Analyze Voltage Areas and Timing Paths

1. From the “Visual Mode” pull down shown on the right, which is set to “Draw
Snapshot data on layout” by default, select Voltage Areas.
2. In the Visual Mode panel that appears to the right of the layout window, click on
Reload. You should now see color coded objects for different VA object types such as
Level Shifters, Always-On cells, Isolation cells ete. This is a useful analysis tool for a
multi-voltage design. For example, in the list of checked objects that appear in the
Voltage Areas panel, if you un-check “Cells of PD_RISC_CORE”, you can clearly
see the light-blue dotted outline of the PD_RISC_CORE voltage area in the lower
right corner of the block.
3. At the top of the “Visual Mode” panel on the right there is field which shows the
current visual mode “Voltage Areas”. Select the pull-down menu to the right of this
field and select “Hierarchy”. Click “Reload”, then press OK. This displays the color
coded logical hierarchy of the first level of hierarchy from the top, by default. You
can look at lower levels of hierarchy by changing the “Color hierarchical cells at
level” number in the “Color By Hierarchy” dialog that appears after clicking “Reload”.
Close the “Visual Mode” panel.
4. Examine the overall timing quality of the design by displaying a list of path slacks for
analysis. Select Window New Timing Analysis Window… and click OK in the
Warning dialog.
5. A TimingWindow opens with Select Paths dialog box. Click OK to accept the default
options. This might take some time.
6. Expand the slack list window to the right by placing your cursor arrow over the right
border of the window. The cursor changes shape (shown above). Click the left mouse
button and drag the boundary to the right. You can left click and drag the gray column
header boundaries to resize the column widths if the field values are not fully
displayed. You can re-arrange the order of the columns by left-clicking a column
header and dragging it to the desired location. Click inside a gray column header and
a sort arrow appears allowing you to sort the column’s data.
7. Select the path with the most negative Slack in the list by left-clicking it. The line
should highlight to a blue color. Observe that the selected path is highlighted in white
in the LayoutWindow.
8. There are controls for generating Histograms, Inspector and Schematics at the bottom
of the TimingWindow. Click the Schematic button and a schematic of the highlighted
path appears in the gray area of the TimingWindow, or in a new tab. You can select
and open multiple schematic windows (two are open in the example on the next page
and have been re-arranged to fit next to each other).
Click the Histogram button and “OK” the dialog box. A set of timing slack histogram
bars appears. Select one of the histogram bars and the list window populates with all
the paths in that bar. Select one of these paths and the LayoutWindow updates
accordingly. Click the Inspector button to start the path inspector. This feature shows
additional, as well as more detailed, information about a timing path. This also opens
 a schematic window, along with another window that can display details about the
path (by selecting the appropriate tab): The Clock tab lists details about the launching
and capturing clock of the path; Data Path lists timing and additional details along the
entire path; Crosstalk lists related delay and parasitic information.
Task 5 Window Management
1. A final note on window management: It is possible to have multiple MainWindows,
LayoutWindows and TimingWindows open at the same time. You can also open
multiple designs at the same time, and switch between them. If you have not already
done so, try the [Ctrl ` ] (control back-tic) sequence to cycle through these windows,
similar to an ALT-TAB in other Windows interfaces. If you have multiple tabs (or
views) within a window, you can cycle through them using [Ctrl Tab]. If you have
problems with windows disappearing, e.g. a Properties window that vanishes under a
LayoutWindow, check the controls in your Linux/Unix window manager. Find a
control to keep “Secondary windows” on top.
2. From the MainWindow or LayoutWindow use File Exit Discard All to exit IC
Compiler.

PnR 3 DATA SETUP & BASIC FLOW

Task 1 Create a Milkyway Library and Load TLU-Plus
1. Change current directory to lab_data_setup and look at the contents of the directory
cd ~/lab_work/icc/lab1_data_setup
ls -a
2. Use gedit to look at the contents of the .synopsys_dc.setup file
3. At the bottom of the file, we have created the following user-defined variables to help
document and simplify the data setup process.
4. The section above the user-defined variables contains the logic library setting which
were discussed on the lecture.
5. 5. Above that we associate the power/ground net names VDD/VSS with tie-
high/low logic levels “1” and “0”, respectively. VDD and VSS are used by default, so
these settings are not explicitly required, but are only included for “documentation”
purposes. If other net names are used for power/ground then these variables must be
defined using the non-default P/G net names (e.g. PWR/GND):
Set mw_logic0_net “VSS”
Set mw_logic1_net “VDD”
6. Exit the text editor or viewer.
7. Start IC Compiler from the Linux prompt.
8. Verify that the .synopsys_dc.setup file was indeed read in, by querying one of the
user-defined variables and ensure it matches the .synopsys_dc.setup settings:
printvar sdc_file
9. Start the GUI
10. Create the design library
a. Use the MainWindow menu
File  Create Library … to bring up the Create Library dialog box.
 b. Use the variables already defined for the library and tech file names.
c. Attach reference libraries to your design library:
Click the Add… button.
Double-click to move up one level, then double-click ref followed by
mw_lib.
Select the standard cell library “sc” and click OK to add it to the list
d. Add the “io” and “ram16x128” libraries as well.
e. Select the “Open library” check box to open the design library after it is
created.
f. Click OK.
11. Type the following in the IC Compiler shell, and note the contents of the newly
created UNIX directory risc_chip.mw (the design library).
icc_shell> ls risc_chip.mw
12. From the MainWindow use the menu File  Set TLU+ … to bring up the Set
TLU+ dialog box.

Click the browse button, then double-clock as needed to locate the ref
directory. Enter paths to the files shown below. Click OK to load the TLU Plus
parasitic files.

Task 2 Load the Netlist, Constraints and Control

1. Before reading in the Verilog netlist make sure the design library is open: An easy
way to do so is by checking if the File  Open Library … entry is grayed out. If it
is, this confirms that a design library is currently open.
2. Select File  Import Designs … to bring up the Import Design dialog box.
3. Under Input format select verilog.
4. Click Add … then browse to select the file design_data/RISC_CHIP.v
and Open.
Under Top design name enter $top_design (or RISC_CHIP).
Click OK.
The following command is the equivalent of the GUI operation above:
Import_design $verilog_file –format Verilog \ -top $top_design
5. Check the physical and logical libraries for consistency, from the ICC shell, type:
check_library
6. Check that TLU+ files are attached and that they pass three sanity checks:
check_tlu_plus_files
7. Verify that the specified link libraries have been loaded
list_libs
8. Define the logical connections between power/ground pins and nets
Source $derive_pg_file
Check_mv_design –power_nets
9. Apply the top level design constraints. The next several command are reconnected to
verify key constraints, or to get specific information about key constraints.
Read_sdc $sdc_file
10. Check if any key timing constraint
 check_timing
11. Check to see what “timing exception” constraints are applied to your design. These
include false and multicycle paths, as well as asynchronous min- and max-delay
constraints. These constraints are an “exception” to the default “single-cycle” timing
behavior – it is useful to know if your design contains any of these timing exceptions,
and where they are being applied:
report_timiing_requirements
12. Check to see if timing analysis was disabled along any paths. If disabled timing arcs
exist, you would probably want to check with the synthesis group if they are still
required during the physical design phase:
report_disable_timing
13. Check to see if the design has been configured for a specific “mode” or “case”, for
example “functional” versus “test” mode. This is done by constraining a control pin or
port to a constant logic 0 or 1 during timing analysis and optimization only, not “hard-
wired”. This is helpful to confirm if your design is in the correct “mode” for physical
design optimizations:
report_case_analysis
14. Verify that the clocks are appropriately modeled:
report_clock
report_clock -skew
15. Apply some timing and optimization controls which are specified
in ./scripts/opt_ctrl.tcl:
source $ctrl_file
16. Run a “zero-interconnect” (zic) timing report. ZIC mode sets the capacitive load of
wires to zero
source scripts/zic_timing.tcl
17. The scripts displays the timing report on the screen and saves it to a file. You can look
at the contents of the timing report file by executing a UNIX “cat”at the icc_shell
prompt:
exec cat zic.timing
18. The “scan enable” signal (scan_en) was defined as an ideal network (see $sdc_file) to
prevent synthesis from buffering this signal. Remove the ideal network definition so
that it will be buffered during physcial design:
remove_ideal_network [get_ports scan_en]
19. Enable Zroute mode routing technology
set_routes_mode_option –zroute true
20. Save the cell and notice the new binary files under risc_chip.mw/CEL:
Save_mw_cel –as RISC_CHIP_data_setup

Task 3 Basic Flow: Design Planning

1. Read in the provide DEF file
read_def $def_file
2. Press [F] in the LayoutWindow to refresh the view. You should now see the
floorplanned design.
 3. Ensure that standard cells will not be placed under the power and ground metal routes
(this constraint is not part of DEF):
Set_pnet_options –complete {METAL3 METAL4}
4. Save the design cell and notice the new binary files under risc_chip.mw/CEL:
Save_mw_cel –as RISC_CHIP_floorplanned

Task 4 Basic Flow: Placement

1. Place and optimize the design for timing, and generate a timing report:
place_opt
redirect –tee place_opt.timing {report_timing}
2. In the LayoutWindow, zoom in and take a look at the standard cell placement
3. Close the congestion map by clicking on the small “x” in the upper right corner of the
congestion dialog box.
4. Save the design cell:
save_mw_cel –as RISC_CHIP_placed

Task 5 Basic Flow: CTS

1. You will be using default settings to generate the clock tree. However, in order to
allow IC Compiler to calculate the actual clock skews during clock tree synthesis,
instead of incorporating the estimated skew from the constraints, remove the “clock
uncertainty” first. Also, enable hold-time fixing
remoce_clock_uncertainty [all_clock]
set_fix_hold [all clocks]
clock_opt
redirect –tee clock_opt.timing {report_timing}
2. Display the clock tree: Use the LayoutWindow menu Clock Color By Clock Trees
to bring up the “visual mode” dialog box.
Click “Reload”.
In the dialog box that appears, make sure the Source Pin Name “clk” is selected
(highlighted in blue).
At the bottom of the dialog box select the box “All Levels, Types”.
Click OK.
The clock tree metal interconnects (or routes), as well as the standard cells, IO pad
and macro cells connected to the clock tree, are highlighted. Notice how the clock tree
starts at the IO pad cell “clk_iopad” (top edge of the periphery, on the right), then
connects to all the registers (“sdnrq#” or “sdcrq#”) and macro cells (zoom in, or hover
your cursor over a cell to see its name).
3. Remove the clock tree highlight by closing (“x”) the visual mode window.
4. Save the design cell:
Save_mw_cel –sel RISC_CHIP_cts
5. We still need to route the design, but first:
Exit IC Compiler by clicking File  Exit  Discard All, or typing exit or quit and
OK at the ic_shell prompt. We’ll explain why we did this next…
Task 6 Basic Flow: Routing
1. Invoke IC Compiler’s GUI:
icc_shell -gui
2. Since the design library has already been created, and you saved the layout cell after
CTS, all you have to do is load the RISC_CHIP_cts cell from the risc_chip.mw
design library, as follows:
a. In the MainWindow click on the little yellow “open design” icon on the
top left, or use the menu command: File  Open Design …
b. In the Open Design dialog panel, click the yellow folder icon . The Select
Library dialog box opens. Select the library folder risc_chip.mw and click
Choose.
c. Select RISC_CHIP_cts and click OK to open it.
3. Re-apply the timing and optimization controls, which were applied during data setup.
This is required because some of the settings are applied using variables. In general,
variable settings are not saved with the design cell – they remain set during the
current IC Compiler session. After exiting and re-invoking IC Compiler, the variables
are reset to their original default values:
source $ctrl_file
4. Re-enable Zroute mode routing technology – this setting is also not saved with the
design cell, and must be re-applied whenever re-invoking IC Compiler:
set_source_mode_options –zroute true
5. Now we are ready to continue to route the design. This will take care of all the signal
nets (the clock nets were already detail-routed by clock_opt):
route_opt
6. Generate a timing report. You should see positive slacks:
7. By default timing reports show maximum delay or setup timing. Generate a min-delay
or hold timing report. You should also see that there are no hold violations:
8. Generate physical design statistics:
report_design -physical
9. Save the design
save_mw_cel –as RISC_CHIP_routed
10. Quit the IC Compiler shell

PnR 4 DESIGN PLANNING

Task 1 Load the Design
1. Change to the lab2_dp directory, invoke IC Compiler and start the GUI:
cd ~/lab_work/icc/lab2_dp
icc_shell -gui
2. Open the orca_setup cell from the orca_lib.mw design library.
3. Take a look at the LayoutWindow. The large greenish-blue rectangles are the macro
and IO pad cells, and the small purple rectangles in the lower left corner (zoom in if
 you want to see them more clearly), are the standard cells. All of these cells are
instantiated cells in the netlist. They are all stacked on top of each other at the origin
(0,0).
4. Re-apply the TLUplus files:
source –echo scripts/tluplus.tcl
5. Apply timing and optimization controls which are specified in ./scripts/opt_ctrl.tcl:
source scripts/opt_ctrl.tcl
6. Switch to the Design Planning task menu in the LayoutWindow by selecting:
File  Task  Design Planning

Task 2 Initialize the Floorplan

1. The logical netlist from synthesis does not contain physical-only cells such as power
and ground pad cells or corner pad cells. You have to therefore create these extra cells
before being able to physically place them in the periphery area of your chip. Create
the corner and P/G cells and define all pad cell positions using a provided script:
source –echo scripts/pad_cell_cons.tcl
Look at the log output to verify that these cells have been created and constrained
without any error or warning messages. The layout has been updated to include these
cells. The corner cells are easily visible – look at the large blue square that takes up
the full layout view (labeled pfrelr). There are actually four corner cells on top of each
other. If you select one of the corner cells you will see a small information window
pop up in the lower left corner displaying the name of the cell. If you select again,
different cells are alternately selected.
2. Create the floorplan: In Layout window:
Select FloorplanCreate Floorplan…
Change the Core utilization to 0.8 (80%).
Change the Core to left/right/bottom/top spacing to 30.
Click OK.
3. Fit [F] the LayoutWindow and have a look at the chip’s core and periphery areas. The
blue hash-marked rectangles outside the chip along the top edge are the unplaced
macro cells. The purple objects along the right edge are all the standard cells.
4. Zoom into the periphery area of the chip and notice that the spacing between all the
pads is about equal.
5. Insert the pad fillers to fill the gaps between the pads. Depending on the technology
and library being used, this may be needed for N- or P-well and/or for power/ground
pad ring continuity. To keep the number of pad filler cells required to a minimum,
specify the larger filler cells first in the list. Otherwise, a 1,000 um space will get
filled with 200 x 5 um width cells, instead of one 1,000 um width cell. Enter the
command in the box below or source the provided script scripts/insert_pad_filler.tcl:
insert_pad_filler –cell “pfeed10000 pfeed05000\
pfeed02000 pfeed01000 pfeed00500 pfeed00200\
pfeed00100 pfeed00050 pfeed00010 pfeed00005”
6. Zoom into the space between two pad cells and notice the filler cells that have been
inserted. You may have to zoom in several times to see the filler cells.
 7. Make the “logical” connection (no physical routing) between the power/ground
signals and all power/ground pins of the I/O pads, macros and standard cells, by
executing the following script:
Source –echo scripts/connect_pg.tcl
8. Build the PAD area power supply ring
create_pad_rings
9. Save the design.

Task 3 Preplace the Macros Connected to I/O Pads

1. Zoom in to see the top periphery area shown in Figure 1 below.
2. Identify macros that connect to I/O pads, as follows:
Choose Select  Cells  By Types…
Click the Uncheck All button in the top (Cell Type) section of the dialog box.
Select the Macro cell type check box.
Click the Select All button in lower left corner of the dialog box.
Click OK.
Notice that all the macros are now selected – highlighted in white.

Select the Flylines button from the top banner section of the
LayoutWindow.
In the “Show flylines” panel that appears on the right side of the window click on the
pull-down menu and choose Selected to IO and Apply.
Reduce the “brightness” to 50% or less to better see the three flylines. The lower left
three macros show connections to IO pads near the top.
3. Keep the “Show flylines” panel open and, if needed, adjust the viewing area
(pan/zoom) to see the picture below. If you accidentally unselect the macros and the
flylines disappear, use the [Ctrl] key to re-select the three circled macros shown here,
and the flylines will re-appear.
4. The three macros with a direct connection to IO pad cells are called
I_CLOCK_GEN/I_PLL_PCI, I_CLOCK_GEN/I_PLL_SD and
I_CLOCK_GEN/I_CLKMUL. Hover your mouse arrow over a cell to see its
information window in the lower-left area. The two PLLs in this design should be
placed towards the top left and right corners of the chip so they are closer to their
respective clock pads.
5. Now you will manually move the I_PLL_PCI macro, which is connected to the left
pad, into the core area. Keep in mind that you can use the undo button to back
track your steps.
a. Select just the I_PLL_PCI macro using Selection Tool button.
b. Select the Start edit Tool button (may be in the left banner of the
window) to begin the moving process.
Drag the I_PLL_PCI macro to approximately the top-left corner of the core
area. Leave some room to the edges of the core.
 c. With the PLL still selected, use the align functions to align the PLL to the top
and left edges of the core:
Click the Align Objects to Left button to align it to
the core’s left edge
From the pull-down menu select the Align Objects to Top
button to align it to the core’s top edge
The PLL is now aligned with the edges of the core.
d. To make sure that the cell is not moved by virtual flat
placement, click on the “padlock” button to lock it
down. You should see an X through the cell now.

6. Try to move the “fixed” I_PLL_PCI macro. You should not be able to do so. If you
are able to move it, use the undo button to put it back and “fix” it in place. Don’t
worry if you make a mistake since you will be provided with a script to place these
macros at the expected coordinates in a later step.
Use the [ESC] key as needed to return the cursor to the “select” mode.
7. In the next steps you will repeat the steps above to move the other two macros into the
core area and near their respective IO pad cells. DO NOT spend too much time on this
step to get them perfectly placed. A script in the next step will ensure correct
placement:
Click on I_PLL_SD to select it.
Select and drag it to the top-right corner of the core area.
Align it to the top and right edges.
Rotate 180o  to reduce its wirelength.
Click the “padlock” button to lock it down.

Select and drag I_CLKMUL to the left side of I_PLL_SD.

Align it to the top edge.
From the”Rotate” pull-down menu select Y-axis to mirror along the Y-direction (=
flip in the X-direction) to reduce the wirelength.

To space I_CLKMUL 10 microns from I_PLL_SD:

Hold down the Ctrl key and select both I_CLKMUL and I_PLL_SD.
Specify a distribute offset of 10 .

Select the Distribute Objects to Right button  .

Lock down the I_CLKMUL macro.

Close the flylines panel on the right by clicking on the small “x” .
8. To ensure that the three macros are placed as expected, you can source the following
script:
Source –echo scripts/preplace_macros.tcl

Task 4 Perform Virtual Flat Placement

 1. Verify that the current VF placement strategy options have default settings
2. Apply a sliver size of 10 to prevent standard cells from being placed in narrow
channels (< 10 um) between macros:
set_fp_placement_strategy –silver_size 10
3. Execute a timing-driven VF placement with “no hierarchy gravity” (to ensure that the
“logical hierarchy” does not affect placement of this non-hierarchical or flat layout):
create_fp_placement –timing_driven –no_hierarchy_gravity
4. Examine the global route congestion map:
Click on the Global Route Congestion button .
Click the Reload button on the pop-up panel.
5. A dialog box appears which contains the command to be executed for congestion
analysis, type in the following
Route_zrt_global –congestion_map_only true
6. Close the Global Route Congestion panel on the right by clicking on the small “x” in
its upper right corner.
7. Routing of power and ground straps and macro rings for this design can be made
easier if we turn some of the macros into arrays. Source the script below to change the
placement strategy to accomplish the following goals:
a. Place macros as close to the edges of the chip as possible
b. Group macros together as much as possible
c. Turn on virtual IPO to mimic timing optimization (and prevent unnecessary
placement optimization)
8. Double check your settings.
9. Source the following script to set a hard keepout margin of 10 microns around all
macros. This will make it easier to create P/G rings around the macros and avoid
congestion as well as signal routing DRCs around the macros
10. Take one last look at the macro placement before running the VF placer again
11. Notice that the macro placement is very different – a lot of ‘grouping’ of similar
macros, except for the manually placed ones, which are “fixed” in place.
12. Analyze the global route congestion map again. If the Global Route Congestion panel
is still open you can Reload OK to update the map.
There should not be any congestion issues.
Close the analysis panel on the right by clicking on the small “x”.
13. Lock down all macros
14. Save the cell

Task 5 Power Network Synthesis

1. Setup the layers to be used for the power network:
PreroutePower Network ConstraintsStrap Layers Constraints...
Select the METAL5 Layer and set the Direction to Horizontal.
Set the “By strap number” Max to 24 and Min to 2.
Set the metal width Max to 4 and Min to 2
Set “PG spacing: Microns” as 0.6
Click the Set button.
Repeat the same steps for METAL4 except set the Direction to Vertical.
 Set then Close the dialog.
2. Define the core ring layers:
PreroutePower Network ConstraintsRing Constraints...
Make sure METAL3 (Horizontal) and METAL2 (Vertical) are selected for the core
ring.
Select the Ring width option and choose Variable.
Set the Max to 12 and the Min to 10.
Extend straps to: Core ring
Click the Set button.
Close the dialog.
3. Define the macro rings:
PreroutePower Network Constraints Block Rings Constraints…
Select the Cell masters option and click its browse button.
From the selection dialog highlight all macro masters (use shift select) – there should
be 6.
Click OK to choose them.
For Power Ground nets enter VDD VSS.
Set the vertical and horizontal layers to METAL4 and METAL5 respectively, and
change the width to 3 for both.
Click on Set, then Close.
4. Apply global constraints:
PreroutePower Network ConstraintsGlobal Constraints...
Keep the existing options selected.
Select the option “No routing over hard macros”.
Click on Set, then Close.
5. Open the PNS dialog using PrerouteSynthesize Power Network…
In the Synthesize power network by nets filed enter: VDD VSS.
Change the Supply voltage (V) to 1.32 .
(The nominal voltage is 1.2 V; Use the maximum voltage of 1.32V)
Leave the Target IR Drop at 10% of supply voltage.
Change the Power budget (mW) to 350 (the power spec for this chip).
Under the Pads info section, select “Specified pad masters”.
Enter pv0i pvdi into the adjacent field.
VDD:pvdi.FRAM VSS:pv0i.FRAM
Press Apply, and after some calculations you should see an IR drop map.
VDD:pvdi.FRAM VSS:pv0i.FRAM
6. Play with the “Target IR Drop” field to see its affect on the number and width of the
straps: Set it to “Lowest”, or set the Specified field to 100, then Apply again.
Observe how the network changes, and along with it the IR drop.
7. When done experimenting, set the Target IR Drop back to 10%, then Apply.
8. Build the suggested power plan clicking on the Commit button, or by typing:
9. Zoom into your chip to see how all PG straps and rings were created.
Notice that there are no connections between the macros and the surrounding power
rings.
Notice also that there are no P/G rails along the standard cell placement rows.
 10. To complete power plan we need to hook up the power pins on all macros, and create
the standard cell power rails. Execute the following commands to accomplish this
11. Now analyze the completed power plan using Preroute Analyze Power Network…
Enter the same values used previously for Power Network Synthesis,
In the power ground nets filed enter: VDD VSS.
Change the Supply voltage (V) to 1.32 .
Change the Power budget (mW) to 350.
Under the Pads info section, select “Specified pad masters”.
Enter pv0i pvdi into the adjacent field.
12. Close the PNA Voltage Drop on the right by clicking on its small “x”.
13. Save the cell

Task 6 Check the Timing

1. You have created many straps on METAL2 and METAL3. By default the VF placer
placed standard cells under these straps, but no DRC checking is done. To make sure
that no shorts were caused enter the following commands to turn on short checking
under METAL2 and METAL3, then legalize placement to move violating standard
cells away from the power straps
2. Perform actual global routing by running the following command
3. Bring up the global route congestion map (no need to “Reload). There should be
negligible congestion. Close the panel (click on small “x”).
4. Generate a maximum-delay (setup) timing report. You should see the words slack
(MET) followed by a positive number at the end of each of the 8 clock group paths.
This design meets setup timing.
5. To fix any timing violations (and design rule violations), if there were any, you would
invoke the following command and repeat global route. Feel free to do so, if you have
the time, otherwise skip to the “Save the cell” step
6. Repeat global routing, congestion analysis and timing analysis one last time. The
design should not have any congestion issues or timing violations.
7. Save the cell as floorplan_complete.
8. This completes floorplanning process.

Task 7 Write Out the DEF Floorplan File

1. Remove all the placed standard cells then write out the floorplan file in DEF format.
The DEF floorplan file will be used by Design Compiler Topographical to re-
synthesize the design using the floorplan you just designed, and will again be used by
IC Compiler to re-create the floorplan when reading in the re-synthesized netlist (next
Task)
2. Verify that the DEF file has been created in the design_data directory.
3. Close the design library without saving the design in memory:
File  Close Library  Discard All
Task 8 Create 2nd Pass Design Ready for Placement
1. Perform data setup using the new ORCA netlist and constraints
2. Read the DEF file that was written out in the previous task
3. Re-apply the pnet options that you applied after Power Network Synthesis in Task 6,
step 1. These settings are not captured in the DEF file
4. Save the cell as ready_for_placement.
5. Exit IC Compiler.

RESULTS
PnR 2

PnR 3
Report timing

Report clock skew

Task 3

Task 4
Report timing
Task 5
Report timing

Task 6
Design route

Report timing
Hold time (no violation)

Physical design report

PnR 4
Macros and IO pad cell
Task 2

Metal route

Task 3
Task 5
IR drop map

Task 6
Report timing
Setup timing
Task 8

Floorplan
DISCUSSION
In PnR 3, the congestion heat map shown in the layout, as well as an overflow
distribution graph. Zero overflow are highlighted because those areas could become
congested if any additional routing resources will be needed after optimization, CTS, etc. in
order to allow IC Compiler to calculate the actual clock skews during clock tree synthesis,
instead of incorporating the estimated skew from the constraints, remove the clock
uncertainty first and enable hold time fixing. The logical netlist from the synthesis does not
contain physical only cells such as power and ground pad cell or corner pad cells. It have to
create the extra cell before being able to physically place them in the periphery area in the
chip. To make sure that no shorts were caused enter the following commands to turn on short
checking under Metal 2 and Metal 3. To complete power plan, it need to hook up the power
pins on all macros and create the standard cell power rails. The DEF floorplan file will be
used by Design Compiler Topographical to re-synthesis the design using the floorplan.

CONCLUSION
As a conclusion, in PnR 1 lab have all the steps needed to learn about the IC Compiler
GUI. It is consist of basic steps to learn how to get help with the commands and variables.
After that, it continues to the PnR 2 which is deep explore in the additional features of the IC
Compiler GUI. It also the show the steps to perform GUI based analysis. In the PnR 3 which
is about the data setup and basic flow. It show step through the data setup process of creating
and maintaining a Milkyway database to hold design data. It will run a complete basic flow,
from loading a floorplan through routing. Lastly on PnR 4 is about the basic flow of design
flow. The logical netlist from synthesis does not contain physical-only cell such as power and
ground pad cell.