Digital Design Flow

In Desktop Create a folder to do the digital design flow. Right click in the
Desktop and select Create Folder

It will create a folder like below

Name it Asic_Counter

Note : Give folder name without any space

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Inside Asic_Counter folder paste your HDL files or Right click in the desktop and
select create document -> empty file

It will create a text file like below

Name the file Counter.v

Note : File name should be with HDL Extension

Double click the counter.v text file

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Inside this text file you can type your HDL Coding

Do the same for the Counter test bench

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save it and it will look like below window

Right click in the same folder and give open in terminal

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Invoke the cadence environment by type the below commands

csh
Source /cad/cshrc (mention the path of the tools)

After this you can see the window like below

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Functional Simulation :

Use the following command to invoke user friendly GUI : nclaunch -new

It will invoke the nclaunch window for functional simulation we can

compile,elaborate and simulate it using Multistep

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we can simulate a design using the Incisive simulator.

For that we have to Create the cds.lib and hdl.var files for to Compile, elaborate
and simulate the design and test bench

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Click the cds.lib file

save the file

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choose any of the option listed above

After that give ok

You can see the below window after giving ok

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Left side you can see the HDL files.Right side of the window has worklib and
snapshots directories listed.

Worklib is the directory where all the compiled codes are stored while Snapshot
will have output of elaboration which in turn goes for simulation

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Compilation:

left side select the file and in Tools : launch verilog compiler with current
selection will get enable.

Click it to compile the code

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After compilation it will come under worklib you can see in right side window.

Select the test bench and compile it. It will come under worklib. Under Worklib
you can see the module and testbench. Next is to elaborate the design.

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Elaboration:

select the file under worklib and in Tools : launch elaborator with current
selection will get enable. select the elaborator to elaborate the design.

Choose the module and test bench and elaborate the design.

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After elaboration the file will come under snapshot. Select the test bench and
elaborate it.

Simulation:
Select the testbench file under snapshot and in Tools : Launch simulator with
current selection will get enable.

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select simulator to simulate the design. After simulation you will get the two
windows like below image.

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you will get the two windows Design Browser and Simvision .In design browser
you can see the test bench in left side window.

select the test bench for the counter and Right click it. Select the send to
waveform window or select the waveform icon

you can see the waveform window after that click the run tool to see the functional
simulation for the counter

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The equivalent command terminal output can be observed in the Simvision console
window and also in the nclaunch console terminal.

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Synthesis :
Synthesis will be done using RTL Compiler. It is a script language called Tool
Command Language( TCL)

Inside the run.tcl file we have to mention the commands like below image.

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Script file explained below

 Give the path of the library w.r.t to the directory you are in using the
command: set_attribute lib_search_path

 Give the path of the RTL files with respect to the directory you are in using
the below command: set_attribute hdl_search_path

 Read the library from the directory specified in giving the path for the
library files in First line using the command: set_attribute library
(slow.lib) is the name of the library file in the directory --library.

 Read the RTL files from the directory specified in the second line. The RTL
files are in the directory name : read_hdl Counter.v

 Now Elaborate the design using : elaborate command.

Constraint File : Not Mandatory

*If you are having constraint file then you can include the constraint file like this

[Give the standard delay constraints using: read_sdc./constraints_top.sdc]

 Synthesize the circuit using the command: synthesize -to_mapped -effort

medium.
 Write the delay file using below commands

write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge >

delays.sdf

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Used to mention the time unit : timescale
Used to ignore the negative timing checks : nonegchecks
Used to split out the recrem(recovery-removal) timing check to separate
checks for recovery and removal : recrem
Specifies the edges values : edges
Keeps edge specifiers on timing check arcs but does not add edge specifiers on
combinational arcs : check_edge

 Timing could be check using : report timing.

 Similarly for Gates : report gates.
 Check area using : report area.
 Check Power dissipation using : report power.
 It will generate the reports
 Write the hdl code in terms of library components for the synthesized circuit
using the command: write_hdl > counter_netlist.v
(counter_netlist.v) is the name of file in which the code gets write.

 Similarly write the constraint file using : write_sdc > counter_const.sdc.

Constraint File :

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Invoke RTL Compiler by typing below command on your terminal window. The
below picture can be seen after typing the above command

rc -f run.tcl -gui
The window will appear like the below image

Gui - Graphical User Interface

You will get the gui and the generated reports like below images

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It will generate the Area,Power,gate and Timing Reports for the counter.

Timing :

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Power:

Cells:

Gate Report:

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GUI:

Double click the file from left side of the window and you can see the RTL
Structure of the design

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Drag the RTL Structure to view the standard cells

Generated Files after Synthesis:

Above highlighted files are generated by run.tcl.

Use ‘exit’ command to close RC.

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Post Synthesis Simulation:

Post synthesis simulation using nclaunch. Using the netlist we can do the
simulation so that we can see the delay for that we have to include the library file
slow.v.

You can get the Verilog extension library files from

/cad/FOUNDRY/digital/90nm/dig/vlog

Copy that file and paste inside the Asic_counter folder

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Right click and open in terminal invoke the nclaunch. Compile the codes and
elaborate it

Note : In Test bench and Netlist files we have to mention the Timescale

After compile the technology library you will get the window like above and then
Simulate the test bench

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You can see the waveform like below window with Delay

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Encounter ( Physical Design):
After Synthesis Physical Design can be done by invoking the tool - Encounter
Digital implementation. Invoke the tool using encounter or velocity.

The tool starts as below image:

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Go to the Tool window and click on the File and select Import Design.

You will get the new window like below

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choose the verilog and choose the Netlist file by browsing the file from the
Asic_Counter folder

It will ask for the NETLIST Files give the double arrow >>

It will show the location of the netlist.

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Right side window you can choose the netlist file Counter_netlist.v which is
generated by synthesis

Click on Auto assign in Top cell

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Note: WE Have to include two Template files for the Backend Design while
import the design in encounter.

They are Default Global and Default View

Default Global :

We have to mention the netlist file name which we have mentioned in

the run.tcl file and also mention the LEF file path and Save the file

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Default View :

Mention the Library path and constraint file name which we have mentioned in
the run.tcl file and Save the file

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Have to include the Default global and default view file for that select the load

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Include the Default Global file

Give ok. You can get a window like below with a blue color vertical line.

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It is imported our design in the Encounter. press F (F - Fit into the Screen)

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Floorplan :

Click on Floorplan and select Specify Floorplan.

Below image window will appear

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Select the Aspect Ratio and Core utilization as per the requirement. Give some
dimension in Core to left, Core to right, Core to top, Core to bottom. e.g. give 10 to
each.

This is to create the space for Power rings which will be created in power planning.
Click OK and the Tool window will be look like as below.

The core dimensions are changed.

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Power Planning: Click on power, select power planning and click on Add Rings.

The below image will appear

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choose the nets by clicking the browse button

Select the nets VDD and VSS and ADD it

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Select the top and bottom layer as top most metal Metal 9, Left and Right as
Metal 8. Set the width as per the requirement and taking the space between core
boundary and I/O pad considerations. Select the option for offset as center in
channel and click OK.

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The power ring will get created in between the channel. The image on the next is
showing the power ring created.

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Power Stripe : The next step in power planning is to create power strips. Select
Power, click Power Planning and click Add Stripe.

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The below window will appear

choose the nets VDD and VSS in set Configurtaion.

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For adding the stripes, select metal layer as Metal 8 and choose direction as
vertical (if direction chosen is horizontal, chose metal layer as Metal 9). Click OK
and the design will get the vertical thin strips of type Metal 8.
choose Number of sets : 3

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Special Route: After the power planning, go to Route and click Special Route.

A New Window Sroute will appear. You will get a window like below

choose the nets VDD and VSS and give ok

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Give ok

This is done to provide power to standard cells. The horizontal blue coloured metal
stripes created as a result of Special Route.

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Placement: For placement, click on place and Place Standard Cell.

You will get the below window

Click OK on Place window and in physical view the coloured standard cells can be
seen as a result of placement of standard cells.

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Before CTS, timing analysis has to be done for any setup violations.
Click on Timing, and select Report Timing. A Timing analysis window will get
open.

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In the window select the Pre-CTS as Design Stage and select the Setup as
Analysis Type.

Click OK to complete the Timing analysis. The timing information will get display
on terminal in tabular form.
In the table displayed on the terminal under Time Design Summary, check for
any negative value under WNS(Worst Negative Slack) and TNS(Total Negative
Slack).

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If there is any of the negative slack value under WNS or TNS, click Optimize in
Tool window and Select Optimize Design. A new window ―Optimization will
get open.

Select Pre-CTS as Design Stage and Setup as optimization type and click OK.

The tool will optimize the design and the optimized timing results will be
displayed over terminal again.

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Clock Tree Synthesis : Go to Clock, click Synthesize Clock Tree, a new
window Synthesize Clock Tree will get open.

Click on Gen Spec and a new window Generate Clock Spec will open.

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From Cells List, Select all clocks starting with ―CLK and click on Add button to
add them to the Selected Cells. Select a name for Output specification.

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Click OK. Then specify a name for Results Directory. and click OK. The tool
window looks like the image below.

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Again Perform the Timing by clicking on Timing and selecting Report Timing.

Select Post-CTS under Design Stage and do the select Set-up as Analysis Type.

Click Ok to perform the timing. The timing information will be displayed over the
terminal window. Again check for any negative slacks under WNS or TNS.

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If there is any negative value found for either of WNS or TNS then perform the
Optimization Technique to reduce the negative slack..

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Timing Analysis for Setup as Analysis Type is done. Repeat Step for performing
timing for Post CTS as Design Stage and Hold as Analysis Type.

The tool will show the timing results in the terminal window.

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Optimize the design

Click OK to perform the Optimization and Tool will perform the optimization and
displays the optimized results in the terminal window under time Design
Summary. The results of Optimization can be seen on the next page in tabular form
for both Setup and Hold mode.

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As compare to the Timing Results performed for Hold mode the design has been
optimized and tabular results shows that all slack values are now positive values
and no more negative values for slack.

Routing : Perform Routing by clicking Route, and select NanoRoute and then
click Route. A window NanoRoute will open.

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Below window will appear

Click Ok to Perform Routing. The tool will Perform the Routing and the Routing
statistics can be seen on terminal window including DRC violations.

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Perform the timing again. Go to Timing, select Report Timing and a Timing
Analysis window will get open. Select Post-Route as the Design Stage and Setup
as Analysis Type. Click Ok. The timing results will be displayed in terminal
window for Set up mode.

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Since there is no negative value of slack so design does not require optimization
for Set-up mode in Post-Route stage. If negative values are there optimize the
design

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Repeat the Step Post-Route as Design Stage and Hold as the Analysis Type. Click
OK. The timing results can be seen in the terminal window for hold mode.

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Since there is no negative value of slack so design does not require optimization
for Hold mode in Post-Route stage. If negative values are there optimize the design

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Write the SDF:

In Encounter window Timing -> Write SDF

you will get the below window

Give the name for the Output file. It will generate the sdf file for the counter

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Layout Netlist :

In Encounter Window choose File->save-> Netlist

Give ok. It will generate the Netlist file of the Layout

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Post Layout Simulation:

For simulation invoke the nclaunch and compile the netlist file generated
after layout and elaborate it.

Simulate the test bench and see the wave form.

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You can see the delay using this layout netlist

GDSII: File -> Save -> GDS/OASIS

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Give name to the Output File like Countergds and give ok. It will genearte the
GDSII file

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