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3T XOR Gate Design

This paper presents a new XOR gate design. it has used only 3T and is design3d using pmos only. IT resulted in low power consumption.

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Shiwani Singh
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152 views

3T XOR Gate Design

This paper presents a new XOR gate design. it has used only 3T and is design3d using pmos only. IT resulted in low power consumption.

Uploaded by

Shiwani Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Multi Phase Adiabatic Logic Modelling using VHDL

Shiwani Singh
1
Electronics and Communication Department
SRMS CET, Bareilly

E-mail: [email protected]

Abstract—In comparison to conventional CMOS (nonadiabatic logic), the verification


of the functionality and the low energy traits of adiabatic logic techniques are generally
performed using transient simulations at the transistor level. However, as the size and
complexity of the adiabatic system increases, the amount of time required to design
and simulate also increases. Moreover, due to the complexity of synchronizing the
power-clock phases, debugging of errors becomes difficult too thus, increasing the
overall verification time. This paper proposes a VHSIC Hardware Descriptive
Language (VHDL) based modelling approach for developing models representing the
different phase adiabatic logic designs. Using the proposed approach, the functional
errors can be detected and corrected at an early design stage so that when designing
adiabatic circuits at the transistor level, the circuit performs correctly and the time for
debugging the error scan substantially be reduced. The function defining the four
periods of the trapezoidal AC power-clock is defined in a package which is followed by
designing a library containing the behavioral VHDL models of adiabatic logic gates
namely; AND/NAND, OR/NOR and XOR/XNOR.
Keywords— Adiabatic logic, low power and VHDL.
I. Introduction
The XOR gate forms the basic building blocks of various digital VLSI circuits like full
adder, multiplier, comparator and parity checker. Enhancing the performance of the
XOR gates can significantly improve the performance of the system as whole. The
design of this gate has been undergoing a considerable improvement in terms of power
consumption. Many design architectures and techniques have been developed to reduce
power consumption and has become one of the primary focuses of digital design [1].
This paper proposes a 3T XOR circuit which reduces the threshold-loss problem
significantly as exists in previous designs and improves the power consumption too.
The paper is organized as follows: Section II describes an existing 3T XOR cell as
reported in the literature. Section III introduces the proposed 3T XOR cell. Simulation
results and their comparisons are included in Section IV and finally Section V
concluded the paper.
II. Prior Work
Figure 1. Existing XOR Gate

The design shown in Fig.1 [2]-[6] is based on a modified version of a CMOS inverter
and a pMOS pass transistor. When the input B is at logic high, the inverter functions
like a normal CMOS inverter. When the input B is at logic low, the CMOS inverter
output is at high impedance. However, the pass transistor M3 is enabled and the output
Y gets the same logic value as input A. However, when A=1 and B=0, voltage
degradation due to threshold drop occurs across transistor M3 and consequently the
output Y is degraded with respect to the input. The voltage degradation due to
threshold drop can be considerably minimized by increasing the W/L ratio of transistor
M3 [7]. Table I illustrates the performance in terms of obtained output at various input
combinations.

III. Proposed 3T XOR Gate

Figure 2. Proposed XOR Gate

The design of proposed XOR gate is shown in Fig. 2. It consists of three pMOS
transistors and an input voltage of (-440)mV is given to M3. Due to this input voltage,
M3 remains ON. The substrate terminals of all the transistors are connected to
respective source terminal in order to nullify the substrate bias effect.
When AB=00, all transistors are ON and as pMOS is weak ‘0’ device, it will pass low
logic signal with threshold loss. When AB=01, M1 is ON and pMOS being strong ‘1’
device will pass complete logic high at the output but as M3 is always ON, so due to
parallel resistance of both the devices the output will be slightly degraded than logic ‘1’
and similar case will happen with AB =10. The W/L ratios of transistors M1and M2
are increased up to 3/1 in order to minimize the threshold loss of M3[7].
For AB=11, only M3 is ON and it will pass incomplete logic ‘0’ signal at the output
port.
Table I. Performance Table of Existing and Proposed 3T XOR Cell
Expected Output Obtained Output (Volt)
A (Volt) B (Volt)
(Volt) Existing Proposed
0 0 0 -0.13 0.09
0 1 1 0.99 0.83
1 0 1 0.76 0.83
1 1 0 0 0.09
The performance table shown in Table I illustrates that the small degradation in the
output voltage with respect to the full scale input voltage value which can be easily
interpreted as logic ‘1’. This proposed design for XOR gate gives better performance
than existing one.

IV. Simulations and Comparison


All schematic simulations are performed on Tanner EDA tool version 13.0 using 45nm
technology with input voltage ranges from 0.5 to 1.0 V in steps of 0.1 V.

Figure 3. Power Consumption with increasing input voltage and temperature


In order to prove that proposed design is consuming low power and have better
performance, simulations are carried out for power consumption at varying supply
voltages and input voltages, temperature and operating frequency respectively.
Fig.3 and Fig.4 reveal that the power consumption of the proposed cell is less than that
of existing one and thus proposed cell proves its superiority over existing one and
hence ensuring the better performance for low power systems.
Figure 4. Power Consumption with increasing operating frequency

V. Conclusion
The pre layout simulations of both the designs have been done and studied using 45nm
technology. The proposed design shows improved logic levels at certain input
combinations. The proposed XOR gate also has improved power consumption with
respect to various parameters. Hence, the proposed gate can be used for various
applications like adder, multiplier and other complex designs.

References
1. Y. Leblebici, S.M. Kang (1999), “CMOS Digital Integrated Circuits,” Singapore:
McGraw Hill, 2nd edition, Ch. 7.
2. T.Sharma, et. al. (2010), “High Speed, Low Power 8T Full Adder Cell with 45%
Improvement in Threshold Loss Problem,” Proceedings of the 12th International
Conference on Networking, VLSI and Signal Processing, pp. 272-276, Coimbatore
and University of Cambridge, UK.
3. Tripti Sharma, et. al. (2010),, “A Novel CMOS 1-bit 8T Full Adder Cell,” World
Scientific and Engineering Academy and Society (WSEAS) Transactions on Systems,
Vol. 9, No.3, pp.317-32.
4. Tripti Sharma, et. al.(2010), “High Performance Full Adder Cell: A Comparative
Analysis,” Proceedings of the 2010 IEEE Student’s Technology Symposium, 3-4
April, IIT Kharagpur.
5. S. R. Chowdhury, et. al.(2008), “ A high speed 8-transistor full adder design using
novel 3 transistor XOR gates,” International Journal of Electronics, Circuits and
Systems, vol. 2, No. 4, pp. 217-223.
6. J. Wang, et. al.(1994), “New efficient designs for XOR and XNOR functions on the
transistor level,” IEEE J. Solid-State Circuits, vol. 29, no. 7, pp. 780–786.
7. Y.Tsividis, (1996), “Mixed Analog-Digital VLSI Devices and Technology,”
Singapore: McGraw Hill, 1st edition.

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