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CMOS Logic Family

CMOS logic circuits use complementary pairs of NMOS and PMOS transistors to achieve very low power consumption. CMOS transistors use either electrons or holes as current carriers, depending on whether they are N-type or P-type. Common CMOS gates like inverters, NAND gates, and NOR gates can be constructed by combining NMOS and PMOS transistors. CMOS logic has high noise immunity and only draws significant current during signal transitions, resulting in very low power usage.

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Aditya Sahare
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76 views

CMOS Logic Family

CMOS logic circuits use complementary pairs of NMOS and PMOS transistors to achieve very low power consumption. CMOS transistors use either electrons or holes as current carriers, depending on whether they are N-type or P-type. Common CMOS gates like inverters, NAND gates, and NOR gates can be constructed by combining NMOS and PMOS transistors. CMOS logic has high noise immunity and only draws significant current during signal transitions, resulting in very low power usage.

Uploaded by

Aditya Sahare
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to CMOS Logic Circuits

CMOS stands for Complementary Metal Oxide Semiconductor


Complementary: there are N-type and P-type transistors. N-type
transistors use electrons as the current carriers. P-type transistors use holes
as the current carriers.
Electrons are free carriers in the conduction band with energy of Ec or
just above the conduction band edge. Free electrons are generated by
doping the silicon with an N-type impurity such as phosphorous or
arsenic.
A hole is a current carrier due to the absence of an electron in a covalent
bond state, i.e. a missing electron which would otherwise be part of a
silicon-to-silicon bond. Holes are free carriers in the valence band with
energy of Ev or just below the valence band edge. Holes are generated
by doping the silicon with a P-type impurity such as boron.
Metal: the gate of the transistor was made of aluminum metal in the early
days, but is made of polysilicon today (for the past 25 years or more).
Oxide: silicon dioxide is the material between the gate and the channel
Semiconductor: the semiconductor material is silicon, a type IV element in
the periodic chart. Each silicon atom bonds to four other silicon atoms in a
tetrahedral crystal structure.
CMOS NFET and PFET Transistors

oxide oxide
gate gate
N+

N N+
P+ P+
source P substrate drain source N well drain
N channel device P channel device
N channel device: built directly in the P substrate with N-doped source and
drain junctions and normally N-doped gate conductor
Requires positive voltage applied to gate and drain (with respect to source)
for electrons to flow from source to drain (thought of as positive drain
current)
P channel device: built in an N-well (a deep N-type junction diffused into the P
substrate) with P-doped source and drain junctions and N or P-doped gate
Requires negative voltage applied to gate and drain (with respect to source)
for electrons to flow from drain to source (thought of as negative drain
current)
CMOS
MOSFETs as an inverter
5V
5V 5V

input output
0V 5V 5V 0V

0V 0V
0V
• 0 V input turns OFF lower (n-channel) FET, turns ON upper (p-channel), so
output is connected to +5 V
• 5 V input turns ON lower (n-channel) FET, turns OFF upper (p-channel), so
output is connected to 0 V
– Net effect is logic inversion: 0  5; 5  0
• Complementary MOSFET pairs  CMOS

2
NAND gate from MOSFETs
Lower two FETs are NMOS and Upper two FETS are PMOS.
5V

INA

OUT C

NAND
AB C 0V 0V
0 0 1
0 1 1
A C
1 0 1
1 1 0 B
3
NOR gate from MOSFETs

• Both inputs at zero:


just a NAND flipped
upside-down…
5V 5V – lower two FETs OFF, upper two ON
– result is output HI
• Both inputs at 5 V:
– lower two FETs ON, upper two OFF
– result is output LOW
IN A
• IN A at 5V, IN B at 0 V:
– lower left OFF, lower right ON
OUT C – upper ON, middle OFF
– result is output LOW
• IN A at 0 V, IN B at 5 V: NOR
IN B
– opposite of previous entry AB C
– result is output LOW 0 0 1
0 1 0
0V A C 1 0 0
B 1 1 0
4
Input/Output Voltage of MOS logic family
•VOHmin : The minimum output voltage in HIGH state (logic '1') = 4.7V for CMOS

•VOLmax : The maximum output voltage in LOW state (logic '0') = 0.2V for CMOS

•VIHmin : The minimum input voltage in HIGH state (logic '1') = 3.7 V for CMOS

VILmax : The maximum input voltage in LOW state (logic '0') = 1.3 V for CMOS

Low noise margin (LNM):

LNM=VILmax-VOLmax = 1.3-0.2 = 1.1V

High noise margin(HNM):

HNM=VOHmin-VIHmin = 4.7-3.7 = 1.0V


Input/Output Current of MOS logic family / Fan-out
When a CMOS driver output is LOW, the maximum input current to the
CMOS load is only 1uA. This means CMOS driver has to sink only 1uA.
( IIL, max = -1uA)

Similarly when CMOS driver output is high, the CMOS driver is sourcing
1uA. (IIH, max = 1uA)

To determine fan-out, one must know how much input current gate load
draws (Iin) and how much output current the driving gate can supply (Io).

For 74C00 series, output current for CMOS driving CMOS:


IOL, max = 10uA and IOH, max = - 10uA

Fan-out under HIGH & LOW condition is same and equal to 10.
Evolution of CMOS Logic Family
Comparison between CMOS & TTL Logic Family
TTL: transistor-transistor logic: BJT based
chips have L, LS, F, AS, ALS, or H designation
output: logic high has VOH > 3.3 V; logic low has VOL < 0.35
V
input: logic high has VIH > 2.0 V; logic low has VIL < 0.8 V
dead zone between 0.8V and 2.0 V
nominal threshold: VT = 1.5 V

CMOS: complimentary MOSFET


chips have HC or AC designation
output: logic high has VOH > 4.7 V; logic low has VOL < 0.2 V
input: logic high has VIH > 3.7 V; logic low has VIL < 1.3 V
dead zone between 1.3V and 3.7 V
nominal threshold: VT = 2.5 V

Chips with HCT are CMOS with TTL-compatible


thresholds

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