Quad-Channel, 2.

5 kV Isolators with
Integrated DC-to-DC Converter
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
FEATURES FUNCTIONAL BLOCK DIAGRAMS
isoPower integrated, isolated dc-to-dc converter
Regulated 3.3 V or 5.0 V output
VDD1 1 OSC RECT REG 16 VISO
Up to 500 mW output power
GND1 2 15 GNDISO
Quad dc-to-25 Mbps (NRZ) signal isolation channels
VIA/VOA 3 14 VOA/VIA
16-lead SOIC package with 7.6 mm creepage 4 CHANNEL iCOUPLER CORE
VIB/VOB 4 13 VOB/VIB
High temperature operation: 105°C maximum ADuM5401/ADuM5402/
VIC/VOC 5 12 VOC/VIC
High common-mode transient immunity: >25 kV/μs ADuM5403/ADuM5404
VOD 6 11 VID
Safety and regulatory approvals
UL recognition RCOUT 7 10 VSEL

06577-001
2500 V rms for 1 minute per UL 1577 GND1 8 9 GNDISO

CSA Component Acceptance Notice #5A

Figure 1.
VDE certificate of conformity (pending)
IEC 60747-5-2 (VDE 0884, Part 2)
VIORM = 560 V peak VIA VOA
3 14
VIB ADuM5401 VOB
APPLICATIONS 4 13
VIC VOC
5 12
RS-232/RS-422/RS-485 transceivers

06577-100
VOD VID
Industrial field bus isolation 6 11

Power supply start-up bias and gate drives Figure 2. ADuM5401

Isolated sensor interfaces VIA VOA
Industrial PLCs 3 14
VIB ADuM5402 VOB
4 13
GENERAL DESCRIPTION VOC
5 12
VIC

06577-101
1 VOD VID
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are 6 11

quad-channel digital isolators with isoPower®, an integrated,

Figure 3. ADuM5402
isolated dc-to-dc converter. Based on the Analog Devices, Inc.,
VIA VOA
iCoupler® technology, the dc-to-dc converter provides up to 3 14
VOB ADuM5403 VIB
500 mW of regulated, isolated power at either 5.0 V or 3.3 V 4 13
VOC VIC
from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the 5 12
06577-102
VOD VID
power levels shown in Table 1. These devices eliminate the need 6 11
for a separate, isolated dc-to-dc converter in low power, isolated
Figure 4. ADuM5403
designs. The iCoupler chip scale transformer technology is used
VOA VIA
to isolate the logic signals and for the power and feedback paths 3 14
in the dc-to-dc converter. The result is a small form factor, total VOB ADuM5404 VIB
4 13
isolation solution. VOC VIC
5 12
06577-103

VOD VID
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators 6 11

provide four independent isolation channels in a variety of

Figure 5. ADuM5404
channel configurations and data rates (see the Ordering Guide
for more information). Table 1. Power Levels
isoPower uses high frequency switching elements to transfer Input Voltage (V) Output Voltage (V) Output Power (mW)
power through its transformer. Special care must be taken 5.0 5.0 500
during printed circuit board (PCB) layout to meet emissions 5.0 3.3 330
standards. See the AN-0971 Application Note for board layout 3.3 3.3 200
recommendations.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Pin Configurations and Function Descriptions ......................... 13 
Applications ....................................................................................... 1  Truth Table .................................................................................. 16 
General Description ......................................................................... 1  Typical Performance Characteristics ........................................... 17 
Functional Block Diagrams ............................................................. 1  Terminology .................................................................................... 20 
Revision History ............................................................................... 3  Applications Information .............................................................. 21 
Specifications..................................................................................... 4  PCB Layout ................................................................................. 21 
Electrical Characteristics—5 V Primary Input Supply/ Thermal Analysis ....................................................................... 21 
5 V Secondary Isolated Supply ................................................... 4  Propagation Delay-Related Parameters ................................... 22 
Electrical Characteristics—3.3 V Primary Input Supply/ Start-Up Behavior....................................................................... 22 
3.3 V Secondary Isolated Supply ................................................ 6 
EMI Considerations ................................................................... 22 
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 8  DC Correctness and Magnetic Field Immunity.......................... 22 

Package Characteristics ............................................................. 10  Power Consumption .................................................................. 23 

Regulatory Information ............................................................. 10  Power Considerations ................................................................ 24 

Insulation and Safety-Related Specifications .......................... 10  Increasing Available Power ....................................................... 24 

IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation Insulation Lifetime ..................................................................... 25 
Characteristics ............................................................................ 11  Outline Dimensions ....................................................................... 26 
Recommended Operating Conditions .................................... 11  Ordering Guide .......................................................................... 26
Absolute Maximum Ratings.......................................................... 12 
ESD Caution ................................................................................ 12 

Rev. C | Page 2 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
REVISION HISTORY
6/12—Rev. B to Rev. C Changes to DC Correctness and Magnetic Field Immunity
Created Hyperlink for Safety and Regulatory Approvals Section .............................................................................................. 21
Entry in Features Section ................................................................. 1 Changes to Power Consumption Section and Figure 29 ........... 22
Updated Outline Dimensions ........................................................26 Changes to Power Considerations ................................................ 23
Added Increasing Available Power Section and Table 26 .......... 23
9/11—Rev. A to Rev. B Added Table 27 ................................................................................ 24
Changes to Product Title, Features Section, and General Changes to Insulation Lifetime Section ....................................... 24
Description Section ........................................................................... 1
Added Table 1; Renumbered Sequentially ..................................... 1 11/08—Rev. 0 to Rev. A
Changes to Specifications Section................................................... 3 Changes to Figure 1 and General Description Section ................ 1
Changes to Table 19 and Table 20 .................................................11 Changes to Table 1 ............................................................................ 3
Changes to Table 21 ........................................................................12 Changes to Table 2 ............................................................................ 5
Changes to Table 22 ........................................................................13 Changes to Table 4 ............................................................................ 7
Changes to Table 23 ........................................................................14 Changes to Table 6 and Table 7 ....................................................... 8
Changes to Table 24 and Table 25 .................................................15 Changes to Table 8 and Table 9 ....................................................... 9
Changes to Figure 11 to Figure 13 ................................................16 Changes to Figure 7 and Table 10 ................................................. 10
Changes to Figure 11, Figure 12 Caption, Figure 14 Caption, Changes to Figure 8 and Table 11 ................................................. 11
and Figure 16 Caption ....................................................................16 Changes to Figure 9 and Table 12 ................................................. 12
Added Figure 19 and Figure 20; Renumbered Sequentially ......17 Changes to Figure 10 and Table 13 ............................................... 13
Changes to Figure 21 and Figure 22 .............................................17 Moved Truth Table Section ............................................................ 13
Changes to Terminology Section ..................................................19 Changes to Applications Information Section and PCB Layout
Changes to Applications Information Section ............................20 Section .............................................................................................. 17
Deleted Increasing Available Power, Figure 15, and Figure 16; Changes to DC Correctness and Magnetic Field Immunity
Renumbered Sequentially ..............................................................20 Section .............................................................................................. 18
Changes to PCB Layout Section ....................................................20 Changes to Power Considerations Section .................................. 20
Added Start-Up Behavior Section .................................................21 Added Increasing Available Power Section, Table 15,
Moved and Changes to EMI Considerations Section ................21 and Table 16 ..................................................................................... 20

5/08—Revision 0: Initial Version

Rev. C | Page 3 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.

Table 2. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1 5 % IISO = 10 mA to 90 mA
Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 µF||10 µF, IISO = 90 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 100 mA VISO > 4.5 V
Efficiency at IISO (MAX) 34 % IISO = 100 mA
IDD1, No VISO Load IDD1 (Q) 19 30 mA
IDD1, Full VISO Load IDD1 (MAX) 290 mA

Table 3. DC-to-DC Converter Dynamic Specifications

1 Mbps—A Grade, C Grade 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
Input IDD1
ADuM5401 19 68 mA No VISO load
ADuM5402 19 71 mA No VISO load
ADuM5403 19 75 mA No VISO load
ADuM5404 19 78 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 100 87 mA
ADuM5402 100 85 mA
ADuM5403 100 83 mA
ADuM5404 100 81 mA

Table 4. Switching Specifications

A Grade C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 55 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional 1 tPSKCD 50 6 ns
Opposing Directional 2 tPSKOD 50 15 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
7

barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.

Rev. C | Page 4 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Table 5. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 × V
VDD1
Logic High Output Voltages VOH VDD1 − 0.3 or VISO − 0.3 5.0 V IOx = −20 μA, VIx = VIxH
VDD1 − 0.5 or VISO − 0.5 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient |CM| 25 35 kV/μs VIx = VDD1 or VISO, VCM = 1000 V,
Immunity1 transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. C | Page 5 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.

Table 6. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1 5 % IISO = 6 mA to 54 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 54 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF||10 µF, IISO = 54 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 60 mA VISO > 3 V
Efficiency at IISO (MAX) 33 % IISO = 60 mA
IDD1, No VISO Load IDD1 (Q) 14 20 mA
IDD1, Full VISO Load IDD1 (MAX) 175 mA

Table 7. DC-to-DC Converter Dynamic Specifications

1 Mbps—A or C Grade 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
Input IDD1
ADuM5401 14 44 mA No VISO load
ADuM5402 14 46 mA No VISO load
ADuM5403 14 47 mA No VISO load
ADuM5404 14 51 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 60 52 mA
ADuM5402 60 51 mA
ADuM5403 60 49 mA
ADuM5404 60 48 mA

Table 8. Switching Specifications

A Grade C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 45 ns Between any two units
Channel Matching
Codirectional 1 tPSKCD 50 6 ns
Opposing Directional 2 tPSKOD 50 15 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
7

barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.

Rev. C | Page 6 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Table 9. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 × V
VDD1
Logic High Output Voltages VOH VDD1 − 0.3 or VISO − 0.3 3.3 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5 or VISO − 0.5 3.1 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient |CM| 25 35 kV/µs VIx = VDD1 or VISO, VCM = 1000 V,
Immunity 1 transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. C | Page 7 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.

Table 10. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1 5 % IISO = 6 mA to 54 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF||10 µF, IISO = 90 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 100 mA VISO > 3 V
Efficiency at IISO (MAX) 30 % IISO = 90 mA
IDD1, No VISO Load IDD1 (Q) 14 20 mA
IDD1, Full VISO Load IDD1 (MAX) 230 mA

Table 11. DC-to-DC Converter Dynamic Specifications

1 Mbps—A or C Grade 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
Input IDD1
ADuM5401 9 44 mA No VISO load
ADuM5402 9 45 mA No VISO load
ADuM5403 9 46 mA No VISO load
ADuM5404 9 47 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 100 92 mA
ADuM5402 100 91 mA
ADuM5403 100 89 mA
ADuM5404 100 88 mA

Table 12. Switching Specifications

A Grade C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional 1 tPSKCD 50 6 ns
Opposing Directional 2 tPSKOD 50 15 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.

Rev. C | Page 8 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Table 13. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × V
VDD1
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 × V
VDD1
Logic High Output Voltages VOH VDD1 − 0.2, VISO − 0.2 VDD1 or VISO V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5 or VDD1 − 0.2 or V IOx = −4 mA, VIx = VIxH
VISO − 0.5 VISO − 0.2
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient |CM| 25 35 kV/µs VIx = VDD1 or VISO, VCM = 1000 V,
Immunity 1 transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. C | Page 9 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
PACKAGE CHARACTERISTICS
Table 14.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output) 1 RI-O 1012 Ω
Capacitance (Input-to-Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance 2 CI 4.0 pF
IC Junction-to-Ambient Thermal θJA 45 °C/W Thermocouple located at center of package underside,
Resistance test conducted on 4-layer board with thin traces 3
1
This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.

REGULATORY INFORMATION
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are approved by the organizations listed in Table 15. Refer to Table 20 and the
Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.

Table 15.
UL 1 CSA VDE (Pending)2
Recognized under 1577 component Approved under CSA Component Certified according to IEC 60747-5-2
recognition program1 Acceptance Notice #5A (VDE 0884 Part 2):2003-01 2
Single protection, 2500 V rms Testing was conducted per CSA 60950-1-07 Basic insulation, 560 V peak
isolation voltage and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage
Basic insulation at 600 V rms (848 V peak)
working voltage
Reinforced insulation at 250 V rms (353 V peak)
working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(current leakage detection limit = 10 µA).
2
In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥
1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01
approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Distance L(I01) 8.0 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1
Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. C | Page 10 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking branded on the package denotes IEC 60747-5-2 (VDE 0884, Part 2) approval.

Table 17. VDE Characteristics

Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, VPR 1050 V peak
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a VPR
After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 896 V peak
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 6)
Case Temperature TS 150 °C
Side 1 IDD1 Current IS1 555 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω

600
SAFE OPERATING VDD1 CURRENT (mA)

500

400

300

200

100
06577-002

0
0 50 100 150 200
AMBIENT TEMPERATURE (°C)

Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 18.
Parameter Symbol Min Max Unit
Operating Temperature 1 TA −40 +105 °C
Supply Voltages 2
VDD1 @ VSEL = 0 V VDD 3.0 5.5 V
VDD1 @ VSEL = VISO VDD 4.5 5.5 V
1
Operation at 105°C requires reduction of the maximum load current as specified in Table 19.
2
Each voltage is relative to its respective ground.

Rev. C | Page 11 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 19. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
Storage Temperature Range (TST) −55°C to +150°C
section of this specification is not implied. Exposure to absolute
Ambient Operating Temperature −40°C to +105°C
Range (TA) maximum rating conditions for extended periods may affect
Supply Voltages (VDD1, VISO)1 −0.5 V to +7.0 V device reliability.
Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 2 −0.5 V to VDDO + 0.5 V
ESD CAUTION
Average Output Current per Pin3 −10 mA to +10 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
1
Each voltage is relative to its respective ground.
2
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
3
See Figure 6 for maximum rated current values for various temperatures.
4
Common-mode transients exceeding the absolute maximum slew rate may
cause latch-up or permanent damage.

Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter Max Unit Applicable Certification
AC Voltage, Bipolar Waveform 424 V peak All certifications, 50-year operation
AC Voltage, Unipolar Waveform
Basic Insulation 600 V peak Working voltage per IEC 60950-1
Reinforced Insulation 353 V peak Working voltage per IEC 60950-1
DC Voltage
Basic Insulation 600 V peak Working voltage per IEC 60950-1
Reinforced Insulation 353 V peak Working voltage per IEC 60950-1
1
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Rev. C | Page 12 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD1 1 16 VISO
GND1 2 15 GNDISO
VIA 3 14 VOA
ADuM5401
VIB 4 TOP VIEW 13 VOB

VIC 5 (Not to Scale) 12 VOC

VOD 6 11 VID
RCOUT 7 10 VSEL

06577-004
GND1 8 9 GNDISO

Figure 7. ADuM5401 Pin Configuration

Table 21. ADuM5401 Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5401 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).

Rev. C | Page 13 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
VDD1 1 16 VISO

GND1 2 15 GNDISO

VIA 3 14 VOA
ADuM5402
VIB 4 TOP VIEW 13 VOB

VOC 5 (Not to Scale) 12 VIC

VOD 6 11 VID

RCOUT 7 10 VSEL

06577-005
GND1 8 9 GNDISO

Figure 8. ADuM5402 Pin Configuration

Table 22. ADuM5402 Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5402 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).

Rev. C | Page 14 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
VDD1 1 16 VISO

GND1 2 15 GNDISO

VIA 3 14 VOA
ADuM5403
VOB 4 TOP VIEW 13 VIB

VOC 5 (Not to Scale) 12 VIC

VOD 6 11 VID

RCOUT 7 10 VSEL

06577-006
GND1 8 9 GNDISO

Figure 9. ADuM5403 Pin Configuration

Table 23. ADuM5403 Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5403 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).

Rev. C | Page 15 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
VDD1 1 16 VISO

GND1 2 15 GNDISO

VOA 3 14 VIA
ADuM5404
VOB 4 TOP VIEW 13 VIB

VOC 5 (Not to Scale) 12 VIC

VOD 6 11 VID

RCOUT 7 10 VSEL

06577-007
GND1 8 9 GNDISO

Figure 10. ADuM5404 Pin Configuration

Table 24. ADuM5404 Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended
that both pins be connected to a common ground.
3 VOA Logic Output A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5404
to control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both
pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VIA Logic Input A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).

TRUTH TABLE
Table 25. Truth Table (Positive Logic)
VSEL 1 RCOUT 2 VDD1 (V) VISO (V) Notes
H PWM 5 5 Master mode, normal operation
L PWM 5 3.3 Master mode, normal operation
L PWM 3.3 3.3 Master mode, normal operation
H PWM 3.3 5 This supply configuration is not recommended due to extremely poor efficiency
1
H refers to a high logic, and L refers to a low logic.
2
PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices.

Rev. C | Page 16 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

TYPICAL PERFORMANCE CHARACTERISTICS

40 4.0 4.0

35 3.5 3.5
POWER

30 3.0 3.0

INPUT CURRENT (A)

EFFICIENCY (%)

25 2.5 2.5

POWER (W)
20 2.0 2.0

15 1.5 1.5

10 1.0 1.0
IDD
3.3V INPUT/3.3V OUTPUT 0.5 0.5
5
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0 0

06577-033
0

06577-011
0 0.02 0.04 0.06 0.08 0.10 0.12 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
OUTPUT CURRENT (A)
INPUT SUPPLY VOLTAGE (V)

Figure 11. Typical Power Supply Efficiency at 5 V Input/5 V Output Figure 14. Typical Short-Circuit Input Current and Power
and 3.3 V Input/3.3 V Output vs. VDD1 Supply Voltage

1.0

OUTPUT VOLTAGE
0.9

(500mV/DIV)
0.8
POWER DISSIPATION (W)

0.7

0.6

0.5
10% LOAD 90% LOAD
DYNAMIC LOAD

0.4

0.3

0.2

06577-012
VDD1 = 5V, V ISO = 5V
0.1 VDD1 = 5V, V ISO = 3.3V
VDD1 = 3.3V, V ISO = 3.3V
0 (100µs/DIV)
06577-026

0 0.02 0.04 0.06 0.08 0.10 0.12

IISO (A)

Figure 12. Typical Total Power Dissipation vs. Isolated Output Supply Current Figure 15. Typical VISO Transient Load Response, 5 V Output,
in All Supported Power Configurations 10% to 90% Load Step

0.12
OUTPUT VOLTAGE
(500mV/DIV)

0.10
OUTPUT CURRENT (A)

0.08

0.06
DYNAMIC LOAD

0.04 10% LOAD 90% LOAD

0.02
06577-013

3.3V INPUT/3.3V OUTPUT

5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0 (100µs/DIV)
06577-027

0 0.05 0.10 0.15 0.20 0.25 0.30 0.35

INPUT CURRENT (A)

Figure 13. Typical Isolated Output Supply Current vs. Input Current Figure 16. Typical VISO Transient Load Response, 3.3 V Output,
in All Supported Power Configurations 10% to 90% Load Step

Rev. C | Page 17 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
5
5V OUTPUT RIPPLE (10mV/DIV)

4 10% LOAD

VISO (V)
90% LOAD

06577-014

06577-031
BW = 20MHz (400ns/DIV) 0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
TIME (ms)

Figure 17. Typical VISO = 5 V Output Voltage Ripple at 90% Load Figure 20. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V

20
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
16
3.3V OUTPUT RIPPLE (10mV/DIV)

SUPPLY CURRENT (mA)

12

4
06577-015

06577-028
BW = 20MHz (400ns/DIV) 0 5 10 15 20 25
DATA RATE (Mbps)

Figure 18. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load Figure 21. Typical ICH Supply Current per Forward Data Channel
(15 pF Output Load)

7 20
10% LOAD 5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
6 5V INPUT/3.3V OUTPUT
16
SUPPLY CURRENT (mA)

12
4
VISO (V)

90% LOAD

3
8

4
1
06577-030

0 0
06577-029

–1 0 1 2 3 0 5 10 15 20 25
TIME (ms) DATA RATE (Mbps)

Figure 19. Typical Output Voltage Start-Up Transient Figure 22. Typical ICH Supply Current per Reverse Data Channel
at 10% and 90% Load, VISO = 5 V (15 pF Output Load)

Rev. C | Page 18 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
5 3.0

2.5
4

SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

2.0
3

1.5
5V 5V
2
1.0
3.3V
3.3V
1 0.5

06577-118
0

06577-119
0 5 10 15 20 25 0 5 10 15 20 25
DATA RATE (Mbps) DATA RATE (Mbps)

Figure 23. Typical IISO (D) Dynamic Supply Current per Input Figure 24. Typical IISO (D) Dynamic Supply Current per Output
(15 pF Output Load)

Rev. C | Page 19 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

TERMINOLOGY
IDD1 (Q) tPLH Propagation Delay
IDD1 (Q) is the minimum operating current drawn at the VDD1 tPLH propagation delay is measured from the 50% level of the
pin when there is no external load at VISO and the I/O pins are rising edge of the VIx signal to the 50% level of the rising edge
operating below 2 Mbps, requiring no additional dynamic supply of the VOx signal.
current. IDD1 (Q) reflects the minimum current operating condition.
Propagation Delay Skew, tPSK
IDD1 (D) tPSK is the magnitude of the worst-case difference in tPHL and/or
IDD1 (D) is the typical input supply current with all channels tPLH that is measured between units at the same operating temper-
simultaneously driven at a maximum data rate of 25 Mbps ature, supply voltages, and output load within the recommended
with full capacitive load representing the maximum dynamic operating conditions.
load conditions. Resistive loads on the outputs should be
Channel-to-Channel Matching, (tPSKCD/tPSKOD)
treated separately from the dynamic load.
Channel-to-channel matching is the absolute value of the
IDD1 (MAX) difference in propagation delays between two channels when
IDD1 (MAX) is the input current under full dynamic and VISO load operated with identical loads.
conditions.
Minimum Pulse Width
ISO (LOAD) The minimum pulse width is the shortest pulse width at which
ISO (LOAD) is the current available to the load. the specified pulse width distortion is guaranteed.
tPHL Propagation Delay Maximum Data Rate
The tPHL propagation delay is measured from the 50% level of The maximum data rate is the fastest data rate at which the
the falling edge of the VIx signal to the 50% level of the falling specified pulse width distortion is guaranteed.
edge of the VOx signal.

Rev. C | Page 20 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

APPLICATIONS INFORMATION
BYPASS < 2mm
The dc-to-dc converter section of the ADuM5401/ADuM5402/
VDD1 VISO
ADuM5403/ADuM5404 works on principles that are common to GND1 GNDISO
most switching power supplies. It has a secondary side controller VIA/VOA VOA/VIA
architecture with isolated pulse-width modulation (PWM) VIB/VOB VOB/VIB

feedback. VDD1 power is supplied to an oscillating circuit that VIC/VOC VOC/VIC

VOD VID
switches current into a chip scale air core transformer. Power
RCOUT VSEL

06577-120
transferred to the secondary side is rectified and regulated to GND1 GNDISO
either 3.3 V or 5 V. The secondary (VISO) side controller regulates
the output by creating a PWM control signal that is sent to the Figure 25. Recommended PCB Layout
primary (VDD1) side by a dedicated iCoupler data channel. The In applications involving high common-mode transients, ensure
PWM modulates the oscillator circuit to control the power being that board coupling across the isolation barrier is minimized.
sent to the secondary side. Feedback allows for significantly higher Furthermore, design the board layout such that any coupling that
power and efficiency. does occur affects all pins equally on a given component side.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement Failure to ensure this can cause voltage differentials between
undervoltage lockout (UVLO) with hysteresis on the VDD1 power pins exceeding the absolute maximum ratings for the device
input. This feature ensures that the converter does not enter as specified in Table 19, thereby leading to latch-up and/or
oscillation due to noisy input power or slow power-on ramp rates. permanent damage.
PCB LAYOUT The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital devices that dissipate approximately 1 W of power when fully
isolators with 0.5 W isoPower integrated dc-to-dc converter loaded and running at maximum speed. Because it is not possible
require no external interface circuitry for the logic interfaces. to apply a heat sink to an isolation device, the devices primarily
Power supply bypassing is required at the input and output depend on heat dissipation into the PCB through the GND
supply pins (see Figure 25). Note that low ESR bypass capacitors pins. If the devices are used at high ambient temperatures, provide
are required between Pin 1 and Pin 2 and between Pin 15 and a thermal path from the GND pins to the PCB ground plane.
Pin 16, as close to the chip pads as possible. The board layout in Figure 25 shows enlarged pads for Pin 8 and
Pin 9. Large diameter vias should be implemented from the pad to
The power supply section of the ADuM5401/ADuM5402/ the ground, and power planes should be used to reduce inductance.
ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency Multiple vias should be implemented from the pad to the ground
to pass power efficiently through its chip scale transformers. In plane to significantly reduce the temperature inside the chip.
addition, the normal operation of the data section of the iCoupler The dimensions of the expanded pads are at the discretion of
introduces switching transients on the power supply pins. Bypass the designer and depend on the available board space.
capacitors are required for several operating frequencies. Noise
suppression requires a low inductance, high frequency capacitor; THERMAL ANALYSIS
ripple suppression and proper regulation require a large value The ADuM5401/ADuM5402/ADuM5403/ADuM5404 parts
capacitor. These are most conveniently connected between Pin 1 consist of four internal die attached to a split lead frame with two
and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO. die attach paddles. For the purposes of thermal analysis, the die
To suppress noise and reduce ripple, a parallel combination of is treated as a thermal unit, with the highest junction temperature
at least two capacitors is required. The recommended capacitor reflected in the θJA from Table 14. The value of θJA is based on
values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller measurements taken with the parts mounted on a JEDEC standard,
capacitor must have a low ESR; for example, use of a ceramic 4-layer board with fine width traces and still air. Under normal
capacitor is advised. operating conditions, the ADuM5401/ADuM5402/ADuM5403/
ADuM5404 devices operate at full load across the full temperature
The total lead length between the ends of the low ESR capacitor range without derating the output current. However, following the
and the input power supply pin must not exceed 2 mm. Installing recommendations in the PCB Layout section decreases thermal
the bypass capacitor with traces more than 2 mm in length may resistance to the PCB, allowing increased thermal margins in
result in data corruption. Consider bypassing between Pin 1 and high ambient temperatures.
Pin 8 and between Pin 9 and Pin 16 unless both common ground
pins are connected together close to the package.

Rev. C | Page 21 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
PROPAGATION DELAY-RELATED PARAMETERS As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404
Propagation delay is a parameter that describes the time it takes devices can draw large amounts of current at low voltage for
a logic signal to propagate through a component (see Figure 26). extended periods of time.
The propagation delay to a logic low output may differ from the The output voltage of the ADuM5401/ADuM5402/ADuM5403/
propagation delay to a logic high. ADuM5404 devices exhibits VISO overshoot during startup. If
this overshoot could potentially damage components attached
INPUT (VIx) 50%
to VISO, a voltage-limiting device such as a Zener diode can be
tPLH tPHL used to clamp the voltage. Typical behavior is shown in Figure 19
and Figure 20.

06577-018
OUTPUT (VOx) 50%

Figure 26. Propagation Delay Parameters

EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5401/ADuM5402/
Pulse width distortion is the maximum difference between
ADuM5403/ADuM5404 devices must operate at 180 MHz to
these two propagation delay values and is an indication of
allow efficient power transfer through the small transformers.
how accurately the input signal timing is preserved.
This creates high frequency currents that can propagate in circuit
Channel-to-channel matching refers to the maximum amount board ground and power planes, causing edge emissions and
the propagation delay differs between channels within a single dipole radiation between the primary and secondary ground
ADuM5401/ADuM5402/ADuM5403/ADuM5404 component. planes. Grounded enclosures are recommended for applications
Propagation delay skew refers to the maximum amount the that use these devices. If grounded enclosures are not possible,
propagation delay differs between multiple ADuM5401/ follow good RF design practices in the layout of the PCB. See the
ADuM5402/ADuM5403/ADuM5404 components operating AN-0971 Application Note for board layout recommendations
under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
START-UP BEHAVIOR Positive and negative logic transitions at the isolator input cause
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not narrow (~1 ns) pulses to be sent to the decoder via the transformer.
contain a soft start circuit. Therefore, the start-up current and The decoder is bistable and is, therefore, either set or reset by the
voltage behavior must be taken into account when designing pulses, indicating input logic transitions. In the absence of logic
with this device. transitions at the input for more than 1 µs, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
When power is applied to VDD1, the input switching circuit begins
correctness at the output. If the decoder receives no internal pulses
to operate and draw current when the UVLO minimum voltage
for more than approximately 5 µs, the input side is assumed to
is reached. The switching circuit drives the maximum available
be unpowered or nonfunctional, and the isolator output is forced to
power to the output until it reaches the regulation voltage where
a default low state by the watchdog timer circuit. This situation
PWM control begins. The amount of current and the time
should occur in the ADuM5401/ADuM5402/ADuM5403/
required to reach regulation voltage depends on the load and
ADuM5404 during power-up and power-down operations.
the VDD1 slew rate.
The limitation on the magnetic field immunity of the
With a fast VDD1 slew rate (200 µs or less), the peak current draws
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is set by the
up to 100 mA/V of VDD1. The input voltage goes high faster than
condition in which induced voltage in the receiving coil of the
the output can turn on, so the peak current is proportional to
transformer is sufficiently large to either falsely set or reset the
the maximum input voltage.
decoder. The following analysis defines the conditions under
With a slow VDD1 slew rate (in the millisecond range), the input which this may occur. The 3.3 V operating condition of the
voltage is not changing quickly when VDD1 reaches the UVLO ADuM5401/ADuM5402/ADuM5403/ADuM5404 is examined
minimum voltage. The current surge is approximately 300 mA because it represents the most susceptible mode of operation.
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
The pulses at the transformer output have an amplitude greater
behavior during startup is similar to when the device load is a
than 1.0 V. The decoder has a sensing threshold at approximately
short circuit; these values are consistent with the short-circuit
0.5 V, thus establishing a 0.5 V margin in which induced voltages
current shown in Figure 14.
can be tolerated. The voltage induced across the receiving coil is
When starting the device for VISO = 5 V operation, do not limit given by
the current available to the VDD1 power pin to less than 300 mA.
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices
may not be able to drive the output to the regulation point if a where:
current-limiting device clamps the VDD1 voltage during startup. β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.

Rev. C | Page 22 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Given the geometry of the receiving coil in the ADuM5401/ Note that, at combinations of strong magnetic field and high
ADuM5402/ADuM5403/ADuM5404, and an imposed frequency, any loops formed by PCB traces can induce error
requirement that the induced voltage be, at most, 50% of the voltages sufficiently large to trigger the thresholds of succeeding
0.5 V margin at the decoder, a maximum allowable magnetic circuitry. Exercise care in the layout of such traces to avoid this
field is calculated as shown in Figure 27. possibility.
100
POWER CONSUMPTION
MAXIMUM ALLOWABLE MAGNETIC FLUX

The VDD1 power supply input provides power to the iCoupler data
10
channels, as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
DENSITY (kgauss)

1 and secondary input/output channels cannot be determined sepa-

rately. All of these quiescent power demands have been combined
into the IDD1 (Q) current, as shown in Figure 29. The total IDD1 supply
0.1
current is the sum of the quiescent operating current; the dynamic
current, IDD1 (D), demanded by the I/O channels; and any external
0.01 IISO load.
IDD1(Q) IISO
0.001 CONVERTER CONVERTER
06577-019

1k 10k 100k 1M 10M 100M IDD1(D) PRIMARY SECONDARY

MAGNETIC FIELD FREQUENCY (Hz)

Figure 27. Maximum Allowable External Magnetic Flux Density

IDDP(D) IISO(D)

For example, at a magnetic field frequency of 1 MHz, the maximum

allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at
PRIMARY SECONDARY
the receiving coil. This voltage is approximately 50% of the sensing DATA DATA
INPUT/OUTPUT INPUT/OUTPUT
threshold and does not cause a faulty output transition. Similarly, if 4-CHANNEL 4-CHANNEL
such an event occurs during a transmitted pulse (and is of the

06577-024
worst-case polarity), it reduces the received pulse from >1.0 V to
0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 29. Power Consumption Within the
ADuM5401/ADuM5402/ADuM5403/ADuM5404
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5401/ Both dynamic input and output current is consumed only
ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28 when operating at channel speeds higher than the refresh rate,
expresses these allowable current magnitudes as a function of fr. Each channel has a dynamic current determined by its data
frequency for selected distances. As shown in Figure 28, the rate. Figure 21 shows the current for a channel in the forward
ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely direction, which means that the input is on the primary side of
immune and can be affected only by extremely large currents the part. Figure 22 shows the current for a channel in the reverse
operated at high frequency very close to the component. For the direction, which means that the input is on the secondary side of
1 MHz example, a 0.5 kA current placed 5 mm away from the the part. Both figures assume a typical 15 pF load. The follow-
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is required ing relationship allows the total IDD1 current to be calculated:
to affect the operation of the device. IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 (1)
1k
where:
DISTANCE = 1m
IDD1 is the total supply input current.
MAXIMUM ALLOWABLE CURRENT (kA)

100
ICHn is the current drawn by a single channel determined from
Figure 21 or Figure 22, depending on channel direction.
10 IISO is the current drawn by the secondary side external load.
DISTANCE = 100mm E is the power supply efficiency at 100 mA load from Figure 11
at the VISO and VDD1 condition of interest.
1
DISTANCE = 5mm

0.1

0.01
06577-020

1k 10k 100k 1M 10M 100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 28. Maximum Allowable Current for Various Current-to-

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Spacings
Rev. C | Page 23 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
The maximum external load can be calculated by subtracting As the secondary side converter begins to accept power from the
the dynamic output load from the maximum allowable load. primary, the VISO voltage starts to rise. When the secondary side
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4 (2) UVLO is reached, the secondary side outputs are initialized to
their default low state until data is received from the corresponding
where: primary side input. It can take up to 1 μs after the secondary
IISO (LOAD) is the current available to supply an external secondary side is initialized for the state of the output to correlate to the
side load. primary side input.
IISO (MAX) is the maximum external secondary side load current
available at VISO. Secondary side inputs sample their state and transmit it to the
IISO (D)n is the dynamic load current drawn from VISO by an input primary side. Outputs are valid about 1 μs after the secondary
or output channel, as shown in Figure 23 and Figure 24. side becomes active.

The preceding analysis assumes a 15 pF capacitive load on each Because the rate of charge of the secondary side power supply is
data output. If the capacitive load is larger than 15 pF, the additional dependent on loading conditions, the input voltage, and the output
current must be included in the analysis of IDD1 and IISO (LOAD). voltage level selected, take care that the design allows the converter
sufficient time to stabilize before valid data is required.
POWER CONSIDERATIONS
When power is removed from VDD1, the primary side converter
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power and coupler shut down when the UVLO level is reached. The
input, data input channels on the primary side, and data channels secondary side stops receiving power and starts to discharge.
on the secondary side are all protected from premature operation
by undervoltage lockout (UVLO) circuitry. Below the minimum The outputs on the secondary side hold the last state that they
operating voltage, the power converter holds its oscillator inactive received from the primary side. Either the UVLO level is reached
and all input channel drivers and refresh circuits are idle. Outputs and the outputs are placed in their high impedance state, or the
remain in a high impedance state to prevent transmission of outputs detect a lack of activity from the primary side inputs and
undefined states during power-up and power-down operations. the outputs are set to their default low value before the secondary
power reaches UVLO.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that INCREASING AVAILABLE POWER
time, the data channels initialize to their default low output The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are
state until they receive data pulses from the secondary side. designed with the capability of running in combination with
When the primary side is above the UVLO threshold, the data other compatible isoPower devices. The RCOUT pin allows the
input channels sample their inputs and begin sending encoded ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its
pulses to the inactive secondary output channels. The outputs PWM signal to another device acting as a master to regulate its
on the primary side remain in their default low state because no self and slave devices. Power outputs are combined in parallel
data comes from the secondary side inputs until secondary side while sharing output power equally.
power is established. The primary side oscillator also begins to The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only
operate, transferring power to the secondary power circuits. be a master/standalone, and the ADuM5200 can only be a slave/
The secondary VISO voltage is below its UVLO limit at this standalone device. The ADuM5000 can operate as either a master
point; the regulation control signal from the secondary side or slave. This means that the ADuM5000, ADuM520x, and
is not being generated. The primary side power oscillator is ADuM540x can only be used in the master/slave combinations
allowed to free run under these conditions, supplying the listed in Table 26.
maximum amount of power to the secondary side. Table 26. Allowed Combinations of isoPower Parts
As the secondary side voltage rises to its regulation setpoint, Slave
a large inrush current transient is present at VDD1. When the Master ADuM5000 ADuM520x ADuM540x
regulation point is reached, the regulation control circuit produces ADuM5000 Yes Yes No
the regulation control signal that modulates the oscillator on the ADuM520x No No No
primary side. The VDD1 current is then reduced and is propor-
ADuM540x Yes Yes No
tional to the load current. The inrush current is less than the
short-circuit current shown in Figure 14. The duration of the The allowed combinations of master and slave configured parts
inrush current depends on the VISO loading conditions and on listed in Table 26 is sufficient to make any combination of power
the current and voltage available at the VDD1 pin. and channel count.

Rev. C | Page 24 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Table 27 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power.

Table 27. Configurations for Power and Data Channels

Number of Data Channels
Power Unit 0 Channels 2 Channels 4 Channels 6 Channels
1-Unit Power ADuM5000 master ADuM520x master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM121x
2-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave
3-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave
ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave

INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insulation
All insulation structures eventually break down when subjected to is significantly lower. This allows operation at higher working
voltage stress over a sufficiently long period. The rate of insulation voltages while still achieving a 50-year service life. The working
degradation is dependent on the characteristics of the voltage voltages listed in Table 20 can be applied while maintaining the
waveform applied across the insulation. In addition to the testing 50-year minimum lifetime, provided that the voltage conforms
performed by the regulatory agencies, Analog Devices carries to either the unipolar ac or dc voltage cases.
out an extensive set of evaluations to determine the lifetime Any cross-insulation voltage waveform that does not conform
of the insulation structure within the ADuM5401/ADuM5402/ to Figure 31 or Figure 32 should be treated as a bipolar ac wave-
ADuM5403/ADuM5404 devices. form and its peak voltage limited to the 50-year lifetime voltage
Analog Devices performs accelerated life testing using voltage levels value listed in Table 20. The voltage presented in Figure 32 is
higher than the rated continuous working voltage. Acceleration shown as sinusoidal for illustration purposes only. It is meant to
factors for several operating conditions are determined. These represent any voltage waveform varying between 0 V and some
factors allow calculation of the time to failure at the actual working limiting value. The limiting value can be positive or negative,
voltage. The values shown in Table 20 summarize the peak voltage but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE
for 50 years of service life for a bipolar ac operating condition
and the maximum CSA/VDE approved working voltages. In

06577-021
0V
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working Figure 30. Bipolar AC Waveform
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM5401/ADuM5402/ RATED PEAK VOLTAGE

ADuM5403/ADuM5404 devices depends on the voltage wave-

06577-023
form type imposed across the isolation barrier. The iCoupler
0V
insulation structure degrades at different rates depending on
Figure 31. DC Waveform
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30,
Figure 31, and Figure 32 illustrate these different isolation
voltage waveforms. RATED PEAK VOLTAGE

Bipolar ac voltage is the most stringent environment. The goal

of a 50-year operating lifetime under the bipolar ac condition 0V
determines the maximum working voltage recommended by
NOTES:
Analog Devices. 1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
06577-022

WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.

THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE
VOLTAGE CANNOT CROSS 0V.

Figure 32. Unipolar AC Waveform

Rev. C | Page 25 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Number Number Maximum Maximum Maximum
of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package
Model 1, 2 VDD1 Side VISO Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range (°C) Description Option
ADuM5401ARWZ 3 1 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5401CRWZ 3 1 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5402ARWZ 2 2 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5402CRWZ 2 2 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5403ARWZ 1 3 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5403CRWZ 1 3 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5404ARWZ 0 4 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5404CRWZ 0 4 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
1
Z = RoHS Compliant Part.
2
Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.

Rev. C | Page 26 of 28
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

NOTES

Rev. C | Page 27 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

NOTES

©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06577-0-6/12(C)

Rev. C | Page 28 of 28