LOGIC DESIGN LAB MANUAL 3rd Semester

LIST OF EXPERIMENTS
Logic Design Lab (11EC208)

1. Simplification, realization of Boolean expressions using logic gates/Universal gates.

2. Realization of Half/Full adder and Half/Full Subtractors using logic gates.
3. (i) Realization of parallel adder/Subtractors using 7483 chip
(ii) BCD to Excess-3 code conversion and vice versa.
4. Realization of Binary to Gray code conversion and vice versa
5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code converter.
6. Realization of One/Two bit comparator and study of 7485 magnitude comparator.
7. Use of a) Decoder chip to drive LED display and b) Priority encoder.
8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type.
9. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476, 7490,
74192, 74193).
10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.
11. Wiring and testing Ring counter/Johnson counter.
12. Wiring and testing of Sequence generator.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-1
Aim : Simplification, realization of Boolean expression using logic gates/universal
gates
a)Verification of Logic gates.
b) Realize the following expressions Using Logic gates and universal gates in
i)SOP form ii) POS form
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EXOR gate 7486
5 NAND gate 7400
6 NOR gate 7402
7 EX-NOR gate 74266
8 Patch chords
9 Trainer Kit

NOT GATE

TRUTH TABLE SYMBOL IC7404

OR
GATE

TRUTH TABLE SYMBOL IC7432

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LOGIC DESIGN LAB MANUAL 3rd Semester

AND GATE

TRUTH TABLE SYMBOL IC7408

NAND GATE

TRUTH TABLE SYMBOL IC7400

NOR GATE

TRUTH TABLE SYMBOL IC7402

XOR GATE

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LOGIC DESIGN LAB MANUAL 3rd Semester
TRUTH TABLE SYMBOL IC7486

EX-NOR GATE

TRUTH TABLE SYMBOL IC74266

Procedure:
1.Place the Ic in the socket of the trainer kit.
2. Make the connections for the gate as shown in the circuit diagram.
3. Verify the Truth Table.
4.Repeat the above steps for other gates in the different Ic chips.

1a. Realize the following expression in

(1) SOP form (sum of product)
(2) POS form (product of sum)
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LOGIC DESIGN LAB MANUAL 3rd Semester
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EXOR gate 7486
5 NAND gate 7400
6 NOR gate 7402
7 Patch chords
8 Trainer Kit

THEORY : To minimise a boolean expression we can emplay any one of the following techniques: i)
Boolean Algebra ii) Karnaugh maps.
Before we proced to simplification techniques, two forms of the Boolean expression must be noted

1) Sum of product (SOP): Ex: ABC+AB+AC

2) Product of Sum (POS) : Ex: (A+B+C)(A+B)+(A+C)

SUM OF PRODUCT (SOP):

F(A,B,C,D) = ∑(5,7,9,11,13,15)

Simplification- SOP form using basic gates

Using NAND gates using NOR gates

PRODUCT OF SUM : F(A,B,C,D) = ∏(0,1,2,3,4,6,8,10,12,14)

Simplification- POS form Using basic gates

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LOGIC DESIGN LAB MANUAL 3rd Semester

Using NAND gates Using NOR gates

Truth Table

A B C D Y=(A+B)D
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

Procedure:
1.Place the Ic in the socket of the trainer kit.
*complex boolean Expression s are simplified by using K maps.
2. make the connections as shown in the circuit diagram.
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LOGIC DESIGN LAB MANUAL 3rd Semester
3.Apply diff combinations of i/ps according to the truth table . verify the o/p.
4 repeat the above procedure for all the circuit diagrams.

*NOTE: The Truth Table is common for Both SOP and POS form.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-2
HALF ADDER & FULL ADDER

Aim: (a) Realization of half /full adder and

(b)half/full subtractor using logic gates
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EXOR gate 7486
5 NAND gate 7400
6 NOR gate 7402
7 Patch chords
8 Trainer Kit

THEORY: The basic rules of binary addition are

0+0 = 0
0+1 = 1
1+0 = 1
1+1 = (10)2
Column by column addition, similar to decimal addition is performed a logic circuit known as half adder
adds two 1 bit signals. In octual addition there is often a thiral bit, the carry bit that must be added.
Hence to add 3 bits at a time a logic circuit known as a Full adder is used.

(a)HALF ADDER USING BASIC GATES :

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LOGIC DESIGN LAB MANUAL 3rd Semester
HALF ADDER USING NAND GATES

FULL ADDER USING NAND GATES :

Truth table (Full adder)

USING NAND GATES

Circuit Diagram

USING NOR GATES

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LOGIC DESIGN LAB MANUAL 3rd Semester

Procedure:
Verify the truth table for half adder and full adder circuits using basic and universal gates.

HALF SUBTRACTOR
Truth Table Circuit Diagram
A B Diff Barrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Using NAND gates

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LOGIC DESIGN LAB MANUAL 3rd Semester
FULL SUBTRACTOR:
Truth Table
A B Bin Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Logic Diagram

USING NAND GATES

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LOGIC DESIGN LAB MANUAL 3rd Semester

USING NOR GATES

Procedure:
verify the truth table for half subtractor and full subtractor circuits using
basic and universal gates.

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LOGIC DESIGN LAB MANUAL 3rd Semester

EXPERIMENT-3
AIM: (1) REALISATION of Parallel adder/subtractor using 7483chip
(2) BCD to XS3 code conversion and vice versa
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 EXOR gate 7486
2 Patch chords
3 Trainer Kit
4 4 bit parallel
adder/subtractor 7483

THEORY:
The IC 7483 is a 4- bit parallel adder IC that contains four inter connected FAs
high speed operation.the inputs to this IC are two 4-bit numbers A3,A2,A1,A0 & B3,B2,B1,B0
and the carry Cin in to the LSB position.The outputs are the sum bits ∑3, ∑2,∑1,∑0. and the
Cout of the b position.

Pin diagram:

1) REALISATION of Parallel adder/subtractor using 7483chip

LOGIC diagram

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LOGIC DESIGN LAB MANUAL 3rd Semester

Block Diagram

Procedure:
1. Make the connections as shown .
2. For addition ,make Cin=0 and apply the 4 bits as i/p for A and apply another set of 4 bits
to B. Observe the o/p at S3, S2 S1 S0 and carry generated at Cout.
Repeat the above steps for different inputs and tabulate the result.
3.For subtration Cin is made equal to 1 and A-B format is used.
A- First no
B- second no.
By Xor –ing the i/p bits of ‘B’ by 1 , complement of ‘B’ is obtained. Further Cin ,which is 1
is added to the LSB of the Xor –ed bits. This generates 2’s complement of B.
3. Verify the difference and polarity of differences at S0, S1, S2, S3.and Cout.
If Cout is 0 , diff is –ve and diff is 2’s complement form.
If Cout is 1, diff is +ve and result is in true form.
Repeate the above steps for different inputs. And tabulate the result.

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LOGIC DESIGN LAB MANUAL 3rd Semester

Readings:-
Cin A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0
0 1 0 0 1 1 0 0 1 1 0 0 1 0
0 0 1 1 1 0 0 0 1 0 1 0 0 0
1 1 0 0 1 1 0 0 0 1 0 0 0 1
1 0 0 0 1 0 0 1 1 0 1 1 1 0

BCD to Ex-3 and Ex-3 to BCD

Truth Table

BCD XS3
B4 B3 B2 B1 X4 X3 X2 X1
Circuit Diagram 0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
BCD to XS-3 0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester
XS3 BCD
X4 X3 X2 X1 B4 B3 B2 B1
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 0 0 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

code conversion and vice-versa can be implemented using Ic 7483 along with 7486 Xor gates. The four

i/p bits of ‘B’ ie B3, B2, B1, B0, are fixed as 0011. cin =0, performs addition and Cin =1 performs

subtraction.

For BCD to xs –3 code conversion 3 has to be added to i/p bits of A there for Cin =0.

For Xs-3 to BCD code conversion ‘3’ has to be subtarcated from the i/p of A therefor Cin =1.

Verify the truth table.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-4

REALISATION OF BINARY TO GRAY CODE CONVERSION VICE

&VERSA

AIM: To Design and set up (i) 4-bit Binary to Gray code converter circuit and
(ii) 4-bit Gray to binary code circuit using gates.
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 EXOR gate 7486
2 NAND gate 7400
3 Patch chords
4 Trainer Kit

1)7486(XOR) 2)7400(NAND)

Binary to Gray code converter

BINARY GRAY CODE
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester
G3 = ∑(8,9,10,11,12,13,14,15)

G3=B3

G2 = ∑(4,5,6,7,8,9,10,11)

G2 =

G1= ∑(2,3,4,5,10.,11,12,13) G0 = ∑(1,2,3,5,6,9,10,13,14)

USING XOR GATES ONLY

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LOGIC DESIGN LAB MANUAL 3rd Semester

Using NAND Gates only

GRAY TO BINARY

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LOGIC DESIGN LAB MANUAL 3rd Semester
GRAY CODE BINARY CODE
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

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LOGIC DESIGN LAB MANUAL 3rd Semester

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester
USING NAND GATE

Procedure:
1. Place the Ic’s in the socket of the trainer kit.

2. Make connections for the gate as shown in the circuit diagram.

3.Apply different combinations of the input according to the truth table and verify the

corresponding o/ps shown on the truth table.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-5

REALISATIION OF 1-BIT AND 2-BIT COMPARATOR AND STUDY OF 7485

MAGNITUDE COMPARATOR
AIM: (i) To Realise 1-bit digital comparater & 2-bit digital compatater with the following outputs
(i) a>b
(ii) a=b
(iii) a < b
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EXOR gate 7486
5 Magnitude
comparator 7485
6 Patch chords
7 Trainer Kit

THEORY:

A Magnatitude comparater is a combinational circuit that compares two numbers, A and B , and
determines their relative magnitudes. The out come of the comparision is specified by three binary
variables that indicates wheather
A>B
A=B
A<B IC 7485 PIN DETAILS

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LOGIC DESIGN LAB MANUAL 3rd Semester
1-BIT COMARATOR

TRUTH TABLE

A0 B0 A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

LOGIC DIAGRAM USING BASIC GATES

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LOGIC DESIGN LAB MANUAL 3rd Semester
TRUTH TABLE FOR 2 BIT COMPRATOR K MAP FOR
A>B

A12 A01 B12 B01 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0 K MAP FOR A=B
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

K MAP FOR A<B

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LOGIC DESIGN LAB MANUAL 3rd Semester

Circuit diagram

4 BIT MAGNITUDE COMPARATOR

IC 7485: The IC 7485 is a 4-bit magnitude comparator that can be expanded to almost any length. It
compares two 4 bit binary and producess three magnitude results
CASCADIG INPUTS CASCADIG OUTPUT
A3 B3 A2 B2 A1 B1 A0 B0 A>B A=B A<B A>B A=B A<B

A3>B3 X X X X X X 1 0 0
A3<B3 X X X X X X 0 0 1
A3=B3 A2>B2 X X X X X 1 0 0
A3=B3 A2<B2 X X X X X 0 0 1
A3=B3 A2=B2 A1>B1 X X X X 1 0 0
A3=B3 A2=B2 A1<B1 X X X X 0 0 1
A3=B3 A2=B2 A1=B1 A0>B0 X X X 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 X X X 0 0 1
A3=B3 A2=B2 A1=B1 AO=B0 1 0 0 1 0 0
A3=B3 A2=B2 A1=B1 AO=B0 0 0 1 0 0 1
A3=B3 A2=B2 A1=B1 AO=B0 X 1 X 0 1 0
A3=B3 A2=B2 A1=B1 AO=B0 0 0 0 1 0 1
A3=B3 A2=B2 A1=B1 AO=B0 1 0 1 0 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester

EXAMPLES-

A3 A2 A1 A0 B3 B2 B1 B0 A>B A=B A<B

0 0 1 0 1 1 0 1 0 0 1
1 1 1 1 1 1 1 0 1 0 0
1 0 0 1 1 0 0 1 1 0
0 1 0 1 0 0 0 0 1 0 0

Procedure:
1)Rig up the circuit for one bit &two bit comparator as shown in the figure using IC 7485
magnitude comparator and basic gates.
2)Verify the Table of values .the output obtained should match the required result.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-6

STUDY OF MUX/DEMUX AND USE OF 74153, 74139

FOR ARITHMETIC CIRCUITS AND CODE CONVERTER.

AIM: To Realise 4:1 MUX using (i) NAND gates and (ii) IC 74153

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 NANDgate(2 pin) 7400
2 NANDgate(4 pin) 7420
3 NANDgate(8 pin) 7480
4 MUX 74153
5 DEMUX 74139
6 Not gate 7404
7 Patch chords
Trainer Kit

Ic’s required: Ic 7400, 7410,7420,74153 and 74139.

Procedure:
(i) Set up the circuit as shown in figure
(ii) Apply any arbitary 4 –bit word.record this word, and verify the o/p sequence for
each combination of the select line and verify that it functions as a 4:1 mux.

Truth table (2:1 mux) SYMBOL

S0 Y
0 A
1 B

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

Truth table (4:1 MUX) SYMBOL

S1 S0 I0 I1 I2 I3 Y
0 0 I0 X X X I0
0 1 X I1 X X I1
1 0 X X I2 X I2
1 1 X X X I3 I3

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

PIN DETAILS OF 74153

IC 74153 : the IC 74153 is a dual 4-i/p mux that can select 2 bits of data from up to eight sources
under the control of the common select inputs (S0,S1). The two 4- i/p Mux circuits have individual
active low enables (E1,E2) which can be used to strobe the outputs independently outputs (Y1,Y2) are
forced low when the correspondinf enables (E1,E2) are high.

TRUTH TABLE FOR MUX 74153(DUAL 4:1 MUX)

E S1 S0 Yn When E1 and E2 =1, device is not enabled and outputs are zero
1 X X 0
0 0 0 An
0 0 1 Bn
0 1 0 Cn
0 1 1 Dn
REALISATION OF HALF ADDER USING IC

TRUTH TABLE
A B SUM Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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LOGIC DESIGN LAB MANUAL 3rd Semester

CIRCUIT DIAGRAM

FULL ADDER

TRUTH TABLE
Here the outputs sum and carry out are represented in terms of input cin.

A B Cin SUM Cout

0 0 0 0 0
0 0 1 1 0 A B SUM Cout
0 1 0 1 0 0 0 Cin 0
0 1 1 0 1 0 1 Cin
1 0 0 1 0 1 0 Cin
1 0 1 0 1 1 1 Cin 1
1 1 0 0 1
1 1 1 1 1

CIRCUIT DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

HALF SUTRACTOR

TRUTH TABLE CIRCUIT DIAGRAM

A B Diff Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester

FULL SUTRACTOR

TRUTH TABLE
A B Bin Diff Bout
0 0 0 0 0 A B Diff Bout
0 0 1 1 1 0 0 Bin Bin
0 1 0 1 1 0 1 1
0 1 1 0 1 1 0 0
1 0 0 1 0 1 1 Bin Bin
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

CIRCUIT DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

DEMULTIPLEXER

FUNCTIONAL TABLE SYMBOL

S1 S0 I Y0 Y1 Y2 Y3
0 0 I I 0 0 0
0 1 I 0 I 0 0
1 0 I 0 0 I 0
1 1 I 0 0 0 I

IC 74139 DEMUX/ DECODER

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LOGIC DESIGN LAB MANUAL 3rd Semester

FUNCTIONAL TABLE

A(S1) B(S0) Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

IC 74139: The ic 74139 is a high speed dual 1 of 4 decoder/ demultiplexer. this device has two
independent decoders each accepting two binary weighted inputs (a, b) and providing four mutually
exclusive active low o/ps(Y0-Y3).each decoder has an active low enable (E) when E=1 every o/p is
forced high. The enable can be uysed as the data input for a 1 of 4 DEMUX application

74139 AS A HALF ADDER/HALF SUBTRACTOR

A B Sum Carry Diff Bout

0 0 0 0 0 0 From truth table sum = ∑1,2
0 1 1 0 1 1 Carry =∑3
1 0 1 0 1 0 Diff =∑1,2
1 1 0 1 0 0 Bout =∑1

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

74139 AS A FULL ADDER

TRUTH TABLE
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum =∑1,2,4,7
Carry =∑3,5,6,7

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

74139 AS A FULL SUBTRACTOR

TRUTH TABLE

A B Bin Diff Bout

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Diff = ∑1,2,4,7
Bout = ∑1,2,3,7

LOGIC DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester
IC 74139 AS A BCD TO XS-3 CODE CONVERTOR

BCD XS3
B4 B3 B2 B1 X3 X2 X1 X0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 0 0
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

From truth table,

X3 = ∑5,6,7,8,9 ; X2 = ∑1,2,3,4,9 ; X1 = ∑0,3,4,7,8 ; X0 = ∑0,2,4,6,8 ;
LOGIC DIAGRAM

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 LOGIC DESIGN LAB MANUAL 3rd Semester

IC 74139 AS A BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE

BINARY GRAY CODE

G3 = ∑(8,9,10,11,12,13,14,15)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 G2 = ∑(4,5,6,7,8,9,10,11)
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 G1 = ∑(2,3,4,5,10.,11,12,13)
0 0 1 1 0 0 1 0
G0 = ∑(1,2,3,5,6,9,10,13,14)
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester
CIRCUIT DIAGRAM

Procedure:
1) Rig up the circuit using NAND gates and then with IC74139 and 74153 as shown in figure.

2)Verify the output with the truth table Values.

3)The output obtained practically should match the required result.

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LOGIC DESIGN LAB MANUAL 3rd Semester

EXPERIMENT-7

AIM : USE OF (a) DECODER CHIP TO DRIVE LED

(b)PRIORITY ENCODER

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 LED(CA) 7447
2 LED(CC) 7448
3 LCD 7448
4 Priority Encoder 74147
5 Patch chords
6 Trainer Kit

PIN DAIGRAM OF IC7447/8 AND LED(CC/CA)

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TRUTH TABLE CIRCUIT DIAGRAM

LED DISPLAY
INPUTS OUTPUTS
D C B A (7 SEG LED DISP)
0 0 0 0
0 0 0 1
0 0 1 0

0 0 1 1

0 1 0 0
0 1 0 1
0 1 1 0

0 1 1 1
1 0 0 0
1 0 0 1

Procedure:
1) set up the circuit as shown in figure.
2) Apply logic ‘0’ to LT (pin 3) and observe the seven segments of the LED. All
the segments must be ON.
3) Apply logic ‘1’ to LT (pin 3) and logic ‘0’ to RBI(pin 5) and BI/RBO (pin 4)
and observe the BI/RBO output and the numver displayed on the LED for all the inputs
0000 through. This is the normal decodeing mode with zero blinking

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LOGIC DESIGN LAB MANUAL 3rd Semester

PRIORITY ENCODER

A priority Encoder is an encoder circuit that includes the priority function. The operation
of the priority encoder is such that if two or more inputs are equal to 1 at the same time
the input having the highest priority wil takes precedence.

(1). To convert decimal to BCD using IC 74147

TRUTH TABLE

1 2 3 4 5 6 7 8 9 B0 BI B2 B3
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
X 0 1 1 1 1 1 1 1 1 1 0 1
X X 0 1 1 1 1 1 1 1 1 0 0
X X X 0 1 1 1 1 1 1 0 1 1
X X X X 0 1 1 1 1 1 0 1 0
X X X X X 0 1 1 1 1 0 0 1
X X X X X X 0 1 1 1 0 0 0
X X X X X X X 0 1 0 1 1 1
X X X X X X X X 0 0 1 1 0

PIN DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

CIRCUIT DIAGRAM

Procedure:
1.Rig up the ckt as shown in the figure.
2. Apply logic zero to LT signal and observe 7 segments of LED i.e all the lines must be ON.
3. Apply zero to blank i/p of BI and observe all the lines to be off.
4.Aplly logic 1 to LT and RBI and observe the number displayed on LED/LCD versus i/p
combinations 0000 to 1001 , this is normal decoding mode.
5 Apply logic 1 to LT and Zero to RBI and observe RBO o/p and number displayed on LED/LCD
versus i/p combinations . this is normal decoding mode with zero blanking.
6. Verify the truth table.
Observation:-
LT =0, all the segment are ON
BI and RBI=1
LT=0/1 , BI=0 RBI=1 all the segments are OFF
LT=1 , RBI=0 , RBO to Output.
Zero is not displayed

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LOGIC DESIGN LAB MANUAL 3rd Semester

EXPERIMENT-8
AIM:- Truth Table verification of flipflops:
(i) JK Master slave (ii) T type (iii) D –type.

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 Dual J.K FlipFlop 7476
2 NAND gate 7400
3 NOT gate 7404
4 Patch chords
5 Trainer Kit

THEORY: The flip-flops can be made to respond to trailing edge of a pulse by employing
two flip-flop circuits, one to hold the output state on the trailing edge and the other to
sample the i/p information on the leading edge. Such a combination is called a master-
slave flip-flop. The MS combination can be constructed for any type of FF. In case of JK
MS FF the information present at the J and K inputs is transmitted to the master FF on the
leading edge of the clk pulse and held there until the trailing edge of clock pulse occurs
offer which if is allowd to pass through to the slave FF.

SYMBOL OF MS-JK FF

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LOGIC DESIGN LAB MANUAL 3rd Semester

PIN DIAGRAM

TRUTH TABLE

Table 1
Inputs Output Operation
Clk Cr pr Q Performed
1 1 1 Qn+1 Normal FF(Table-2)
Note: - Keep Pr= Cr=1 for verifying the
(F.F. enabled) truth tables JK MS F.F, T and D type FF.
0 0 1 0 F.F. Cleared(Reset)

0 1 0 1 F.F. Preset(Set)

Table 2
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LOGIC DESIGN LAB MANUAL 3rd Semester

Inputs Output COMMENTS

Clk J K Qn+1

X X Qn No Change

0 0 Qn No change

0 1 0 Reset

Qn Set
1 0

F.F. Preset(Set)
1 1

T- Type FF using MS JK FF

D - Type FF using MS JK FF

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LOGIC DESIGN LAB MANUAL 3rd Semester

Procedure:
1)Rig up the circuit as shown in the diagarm.
2)Apply the i/ps to these flipflops as per the Truth table and observe the o/p
Verify with the truth table.

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-9
COUNTERS

AIM : -Realization of 3-bit counters as a sequential circuit and mod-N counter design
(7476, 7490, 74192, 74193)
a) Asynchronous type b) Synchronous type
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 JK flip flop 7476
2 NANDgate(3 pin)
3 AND gate 7408
4 OR gate 7432
5 Decade Counter 7490
6 Decade Up/down 74192
Counter
MOD 16 counter 74193
Patch chords
Trainer Kit

THEORY: A sequential circuit that gives a presecribed sequence of states upon the
application of input pulses is called counter. The straight binary sequence counter is the
simple and most straight forward. An n-bit binary counter has n flip-flops and can count
in binary from 0 to 2n -1.

(A). ASYNCRONOUS COUNTERS

A binary ripple (Asynchrounous) counter consists of a series connections of
T- flip-flops without any logic gates. Each FF is triggered by the output of it’s preceding
FF goes from 1 to 0.
(a) Realization of 3-bit binary counters using IC7476(MOD-8)

PIN DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

UP COUNT (MOD-8)

WAVE FORMS

TRUTH TABLE

Number of Flip Flop outputs

clock pulses Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 Engineering 0
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LOGIC DESIGN LAB MANUAL 3rd Semester

DOWN COUNT

TRUTH TABLE
Number of clock Flip Flop outputs
pulses Qc Qb Qa
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

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LOGIC DESIGN LAB MANUAL 3rd Semester

MOD-N COUNTER (UP COUNTER)

MOD-4 COUNTER: –

In MOD-4 counter 1 0 0 (Qa, Qb, Qc) is Invalid state

TRUTH TABLE

Number of Flip Flop outputs

clock pulses Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1

WAVE FORMS

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LOGIC DESIGN LAB MANUAL 3rd Semester
MOD-6 COUNTER
TRUTH TABLE
In MOD-6 counter 1 1 0 (QC, Qb, Qa) invalid state

WAVEFORMS

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LOGIC DESIGN LAB MANUAL 3rd Semester
MOD-N COUNTERS (DOWN COUNTER)

MOD-4 COUNTER-

Invalid state is from 1 0 0 to 1 1 1. Then sequence is 011(C, B, A), 010,001,000,011

TRUTH TABLE

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LOGIC DESIGN LAB MANUAL 3rd Semester

WAVE FORMS:-

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LOGIC DESIGN LAB MANUAL 3rd Semester
MOD-7 COUNTER
In MOD-7 Counter the invalid state is 111, the data sequence will starts from 110 and
should count down to 000
Ie. 110- 101-100-011-010-001-000-110
TRUTH TABLE

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LOGIC DESIGN LAB MANUAL 3rd Semester
WAVE FORMS

REALISATION OF 3 BIT UP/DOWN COUNTER

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LOGIC DESIGN LAB MANUAL 3rd Semester
WAVE FORMS

SYNCHRONOUS COUNTERS
THEORY:In Synchronous counters all FF are triggered simultaneously by the count pluse.
The FF is complemented only if its T input is equal to 1 the advantage of synchronous
counter is its speed, it takes only one propagation delay time for the correct binary count
to appear the clock edge bits.
UP COUNTER
DESIGN AND REALIZATION OF 3 BIT SYNCHRONOUS COUNTER USING IC7476
Excitation table

Present Next
state State J K
output output
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
STATE TABLE

PRESENT STATE NEXT STATE EXCITATION

Qc Qb Qa Qc Qb Qa JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
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1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1

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LOGIC DESIGN LAB MANUAL 3rd Semester

CIRCUIT DIAGRAM

WAVE FORMS

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LOGIC DESIGN LAB MANUAL 3rd Semester

MOD-6 COUNTER
In MOD-6 counter invalid state is 110

PRESENT STATE NEXT STATE EXCITATION

Qc Qb Qa Qc Qb Qa JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1

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LOGIC DESIGN LAB MANUAL 3rd Semester

CIRCUIT DIAGRAM

WAVE FORMS

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LOGIC DESIGN LAB MANUAL 3rd Semester

MOD-5 SYNCHRONOUS DOWN COUNTER

PRESENT STATE NEXT STATE FLIP-FLOPS

Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 0 0 1 X 0 X 0 X

SIMPLIFICATIONS

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LOGIC DESIGN LAB MANUAL 3rd Semester

CIRCUIT DIAGRAM

MOD-8 DOWN COUNTER

TRUTH TABLE

PRESENT STATE NEXT STATE EXCITATION

Qc Qb Qa Qc Qb Qa JC KC JB KB JA KA
1 1 1 1 1 0 X 0 X 0 X 1
1 1 0 1 0 1 X 0 X 1 1 X
1 0 1 1 0 0 X 0 0 X X 1
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 1 1 1 X 1 X 1 X

Dept Of Electronics & Communication Engineering

LOGIC DESIGN LAB MANUAL 3rd Semester

SIMPLIFICATIONS

CIRCUIT DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

MOD-N COUNTERS
To realize a MOD-N counter using IC-74193 with a given preset value, write down
the expected function table
Pin details of IC 74193(Synchronous counter)

[MOD-16 UP/DOWN COUNTER]

FUNCTION TABLE

Load Up Down Qd Qc Qb Qa
H X X X 0 0 0 0
L L X X D C B A
L H Cp H COUNT UP
L H H Cp COUNT DOWN
L H H H NO CHANGE

Design a counter which counts from (6-12)

Dept Of Electronics & Communication Engineering

LOGIC DESIGN LAB MANUAL 3rd Semester

Invalid state 1101

WAVE FORMS

REALIZE A (15-6) COUNTER USING IC 74193

Invalid state---0101
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LOGIC DESIGN LAB MANUAL 3rd Semester
Note:-Lo and Bo are used basically for cascading the counters
To realize a MOD-N counter using IC-7490

PIN DIAGRAM

INTERNAL DIAGRAM

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LOGIC DESIGN LAB MANUAL 3rd Semester

CONDITIONAL TABLE
R1 R2 S1 S2 Qa Qb Qc Qd
H H L X L L L L
H H X L L L L L
X L H H 1 0 0 1
L X L X MOD-2 COUNTER
X L X L MOD-5 COUNTER

7490 AS MOD-2 COUNTER

7490 AS MOD-5 COUNTER

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LOGIC DESIGN LAB MANUAL 3rd Semester

7490 AS MOD-10 COUNTER

7490 AS MOD-8 COUNTER

7490 AS MOD-6 COUNTER

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LOGIC DESIGN LAB MANUAL 3rd Semester

To realize a MOD-N counter using IC74192 with given preset value, write
down the expected function table

SYNCHRONOUS COUNTER

PIN DETAILS OF IC-74192[ MOD-10 UP/DOWN COUNTER]

MOD-6 UP COUNTER

Invalid state-0110

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LOGIC DESIGN LAB MANUAL 3rd Semester

MOD-9 DOWN COUNTER

DESIGN A COUNTER WHICH CAN COUNT FROM 7 TO 9

NOTE After 1001, out put becomes 0000

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LOGIC DESIGN LAB MANUAL 3rd Semester

EXPERIMENT NO-10

SHIFT REGISTERS

Aim- To demonstrate Shift lift shift right, SIPO, SISO, PISO, PIPO operations using IC
7495

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 Shift register 7495
2 Trainer kit
Patch Chords

The IC 7495 is a 4-bit shift register ,allowing

Serial in serial out(SISO)
Serial in parallel out(SIPO)
parallel in serial out(PISO)
parallel in parallel out(PIPO)
above all four are shift right operation and also to do Shift left operation.

PIN DIAGRAM
OF IC 7495

M=1 for parallel operation

M=0 for serial operation

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LOGIC DESIGN LAB MANUAL 3rd Semester

SERIAL IN SERIAL OUT (SISO)-shift right

Clk TIME Qa Qb Qc Qd
T0 1 1
T1 0 0 1
clks T2 1 1 0 1
T3 1 1 1 0 1
T4 x 1 1 0
T5 x x 1 1
T6 x x x 1

Serial in Parallel out (SIPO)

Time Serial Qa Qb Qc Qd
data
T0 1 1
T1 0 0 1
T2 1 1 0 1
T3 1 1 1 0 1

Parallel in serial out (PISO)

Clk TIME Qa Qb Qc Qd
T0 1 1 0 1
T1 x 1 1 0
Clks T2 x x 1 1
T3 x x x 1

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LOGIC DESIGN LAB MANUAL 3rd Semester
To check the serial out, M is made to 0 and clk is given clock pulse

Parallel in Parallel out (PIPO)

Shift Left (serial)

Clk TIME I/P Qa Qb Qc Qd

T0 1 1
T1 0 1 0
clks T2 1 1 0 1
T3 1 1 0 1 1
T4 0 1 1 X
T5 1 1 X X
T6 1 X X X

Parallel clk to be given

When mode M=0, i/p is given to A A-Qa, Qa-B, Qb-C,Qc-D,Qd-LSB

Dept Of Electronics & Communication Engineering

LOGIC DESIGN LAB MANUAL 3rd Semester

Procedure:
SERIAL IN SERIAL OUT (SISO)-shift right

(i)connect mode control(pin no 6) to ‘0’ and apply serial data at serial input at
pin no 1 terminal storing from lsb
(ii) apply clock pulses at clock one in (pin no 9) ,terminal after each data bit
and observe outputs
(iii)verify its operation as a right shift register

Parallel in serial out (PISO)

(i) to load the parallel input data in to the shift register ( ie to make Qa
Qb Qc Qd = parallell input data)
(ii) connect mode control pin no 6 to ‘1’ state the parallel inputs A B C
D to be loaded in to shift register are given to pin no 2,3,4,5
respectively.
(iii) Clck 2 (pin no 8) is pulsed once now A B C D parallel inputs
appeares in the respective out puts.
(iv) To convert this parallel input data in to serial out put data on Qd
line first connect mode control (pin no 6) to ‘0’ state ,apply clk
pulse at clock ‘1’ pin no 9 and observe the outputs.

SHIFT LEFT (SERIAL)

(i) connect mode control pin no 6 to logic ‘1’ and apply the serial
data at D input starting from MSB.
(ii) Appply clk pulse at clk 2 ie pin no 8 terminal and observe the
outputs Qa Qb Qc Qd,record out put states and verify its operation
as a left shift register.

Dept Of Electronics & Communication Engineering

LOGIC DESIGN LAB MANUAL 3rd Semester

EXPERIMENT-11

AIM –Design and testing of Ring counter/Johnson counter using IC-7495

RING COUNTER USING IC-7495

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 Ring Counter 7495
2 Patch chords
Trainer Kit

Procedure:
(i) Connect the circuit as in the figure
(ii) To circulate logic ‘1’ -- mode control pin no 6 = 0 ,apply data ‘1’
at the serilal in put pin no 1 and apply clk pulses at clk 1 pin no
9,and observe the outputs.
(iii) Apply a clck pulse of 1 khz at the clk 1 input observe the outputs
Qa Qb Qc Qd on a dual trace CRO with ref to the clk input.

TRUTH TABLE CIRCUIT DIAGRAM

CP QA QB QC QD
t0 1 0 0 0
t1 0 1 0 0
t2 0 0 1 0
t3 0 0 0 1
t4 1 0 0 0

Dept Of Electronics & Communication Engineering

LOGIC DESIGN LAB MANUAL 3rd Semester
JHONSON COUNTER USING IC7495

TRUTH TABLE CIRCUIT DIAGRAM

CP QA QB QC QD
t0 1 0 0 0
t1 1 1 0 0
t2 1 1 1 0
t3 1 1 1 1
t4 0 1 1 1
t5 0 0 1 1
t6 0 0 1 1
t7 0 0 0 1
t8 1 0 0 0

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LOGIC DESIGN LAB MANUAL 3rd Semester
EXPERIMENT-12

AIM: DESIGN A SEQUENCE GENERATOR

Sequence: 100010011010111
Design: There are 15 bits, so there will be 15 states s=15. So at least 4 flip-flops are required.
Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 7495
2 ExOR 7486
3 Trainer Kit
4 Patch Chords

Sequence generater which generates a prescribed sequence of bits in synchronous

with a clock is refered to as a Sequence generater.Shift register with feedback can be used
as sequence generator on waveform generator.

TRUTH TABLE CIRCUIT DIAGRAM

QA QB QC QD f
1 1 1 1 0
0 1 1 1 0
0 0 1 1 0
0 0 0 1 1
1 0 0 0 0
0 1 0 0 0
0 0 1 0 1
1 0 0 1 1
1 1 0 0 0
0 1 1 0 1
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1

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LOGIC DESIGN LAB MANUAL 3rd Semester

QA QB QC QD f
1 1 1 1 0
0 1 1 1 0
0 0 1 1 0
0 0 0 1 1
1 0 0 0 0
0 1 0 0 0
0 0 1 0 1
1 0 0 1 1
1 1 0 0 0
0 1 1 0 1
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1

Procedure:
(i) set up the circuit as shown in firgure
(ii) load the initial state by keeping mode control pin in HIGH state.
(iii) Set mode control = ‘0’ and apply clock pulses and record all
observations.

Dept Of Electronics & Communication Engineering