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Lab6 BCD-to-Excess-3 Code Conversion

This document describes a lab assignment on designing a BCD to excess-3 code converter. The objectives are to understand binary codes for decimals, design combinational logic circuits, and model circuits in Verilog. Students are asked to complete pre-lab tasks like making truth tables and deriving logic expressions. The lab tasks involve implementing the converter using NAND gates, and writing Verilog code for the circuit. Evaluation criteria include performance in the lab, analysis, tool usage, safety practices, and teamwork.

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Muhammad Asad Khalil Rao
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465 views

Lab6 BCD-to-Excess-3 Code Conversion

This document describes a lab assignment on designing a BCD to excess-3 code converter. The objectives are to understand binary codes for decimals, design combinational logic circuits, and model circuits in Verilog. Students are asked to complete pre-lab tasks like making truth tables and deriving logic expressions. The lab tasks involve implementing the converter using NAND gates, and writing Verilog code for the circuit. Evaluation criteria include performance in the lab, analysis, tool usage, safety practices, and teamwork.

Uploaded by

Muhammad Asad Khalil Rao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Department of Electrical Engineering

Faculty Member: ____________________ Dated: ________________

Group No.:
Semester: __________________________ Section: ________________

EE-221: Digital Logic Design

Lab 6: BCD to Excess-3 Code Conversion

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


Name Reg. Viva / Lab Analysis Modern Ethics and Individual Total
No Performance of data in Tool Usage Safety and Team marks
Lab Work Obtained
Report
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

Lab 6: BCD to Excess-3 Code Conversion

This Lab has been divided into two parts:


In first part you are required to design and implement a BCD to Excess-3 code converter.
The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you
first lab.
Objectives:
• Understand steps involved in design of combinational circuits
• Understand binary codes for decimals and their hardware realization
• Write code for combinational circuits using Verilog Gate Level Modeling
• Design a circuit in Verilog by calling different modules

Lab Instructions

• This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab
Viva session.
• The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
• The students will start lab task and demonstrate design steps separately for step-
wise evaluation (course instructor/lab engineer will sign each step after ascertaining
functional verification).

• Remember that a neat logic diagram with pins numbered coupled with nicely
patched circuit will simplify trouble-shooting process.

• After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
• The students will complete lab task and submit complete report to Lab Engineer
before leaving lab.
• There are related questions at the end of this activity. Give complete answers.
Pre-Lab Tasks: (To be done before coming to the lab) 3 marks
• What do you understand by decimal codes? Name any three of these. Express the last
four digits of your registration number duly negated in signed magnitude, 10’s
complement, and 9’s complement forms for the following codes:

• 8,4,2,1

• Excess-3

• What is the significance of BCD code? Write its application in digital circuits.

• In the lab you would be implementing a BCD to Excess-3 code converter. Make a truth
table for both the codes by filling in the following tables and simplify the expressions for
W, X, Y, Z in terms of A, B, C, D. (Use backside of the page if necessary). Use unused
combinations as don’t care conditions.

HINT:
Our inputs and outputs are of 4-bit decimal values. You will have to make
4 K-Maps (Consider W as independent function of input variables A, B, C,
D, Make K-Map and simplify it). Arrive at the simplest expression for each
output.

Dec Binary Excess 3


A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
W=
X=

Y=

Z=

• Draw the logic diagram for BCD to Excess-3 code converter using basic gates in the
space provided below.

• Draw the logic diagram for BCD to Excess-3 code converter using NAND gates in the
space provided below.
Choose the required gates out of the following gates.
Lab Tasks: (To be completed in the lab) 2 marks

Lab Task 1:

Realize the BCD to Excess-3 code converter using NAND gates only. Make the Schematic
Diagram. Show the results to your Teacher/Lab Engr.

Lab Task 2:

Design and simulate the dataflow-level model of the circuit you patched. Give the code in the
space provided below.

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