4-DIGIT HEX COUNTER USING SYNCHRONOUS ONE DIGIT

HEX COUNTER
 4-DIGIT HEX COUNTER USING SYNCHRONOUS ONE DIGIT HEX
COUNTER

Introduction
This Educational Trainer is a basic Trainer kit for the demonstration of
Synchronous counter. This consists of
1. 5V Regulated Power Supply
2. 1Hz Clock generator
3. Manual Pulsar
4. IC 74LS163
5. 7-Segment Displays
Block Diagram Description:
Regulated Power Supply
This consists of Bridge Rectifier, Capacitor filter, and three terminal regulators
to provide regulated DC voltage in the circuit i.e. +5V.

Clock Generator
This has been designed based on the application of CMOS Integrated Circuits
in Linear mode. Here IC4069 is used as an Active Device to generate Square
wave of 1Hz to use as a Clock in this experiment. CD4069 is a CMOS Hex
Inverters Integrated Circuits. Three inverters are used to form a Oscillator and
other three are connected in parallel to form a Buffer to Isolate oscillator from
Output and to improve current capability.

BCD-7 Segment display:

BCD- 7 Segment display along with BCD- Seven segment decoder (IC
7447) is provided on the front panel to read the output of the decade counter
in decimal. Inputs for the decoder are terminated with spring loaded contacts.

Pulse Generator:
A bounceless manual pulse is provided to use as clock when we desired to
see step-by-step operation of the circuit. This has been designed based on
the application of IC7414. The IC7414 is a HEX Schmitt Trigger inverter.

Aim: To study the operation of Synchronous Counter (using IC 74LS163)

Theory:
The counter is a circuit with a set of Flip-Flops, which counts the
number of pulses given at the clock input. There are two types of counters
1. Asynchronous Counters
2. Synchronous Counters.
Synchronous Counter
In a synchronous counter, the external clock input triggers all the
stages in the counter. All the flip-flops are triggered simultaneously.
Circuit Operation
The LS163A is a high-speed 4-bit synchronous counter. It is edge
triggered, synchronously presettable, and cascadable MSI building blocks for
counting, memory addressing, frequency division and other applications.

The LS163A has a Synchronous Reset (Clear) input that overrides all other
control inputs, but is active only during the rising clock edge.

 Synchronous Counting and Loading

 Two Count Enable Inputs for High Speed Synchronous Expansion
 Terminal Count Fully Decoded
 Edge-Triggered Operation
 Typical Count Rate of 35MHz
 ESD > 3500 Volts

CONNECTION DIAGRAM DIP (TOP VIEW)

PIN NAMES
/PE Parallel Enable (Active LOW) Input
P0-P3 Parallel Inputs
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
Clock (Active HIGH Going Edge)
CP
Input
Synchronous Reset (Active LOW)
/SR
Input
Q0-Q3 Parallel Outputs
TC Terminal Count Output
LOGIC SYMBOL

FUNCTIONAL DESCRIPTION

The LS163A is a 4-bit synchronous counter with synchronous Parallel Enable

(Load) feature. The counter consists of four edge triggered D flip-flops with
the appropriate data routing networks feeding the D inputs. All changes of the
Q outputs occur as a result of, and synchronous with, the LOW to HIGH
transition of the Clock Input (CP). As long as the set-up time requirements are
met there are no special timing or activity constraints on any of the mode
control or data inputs.

Three control inputs --- Parallel Enable (/PE), Count Enable Parallel (CEP)
and Count Enable Trickle (CET) --- select the mode of operation as shown in
the tables below. The Count Mode is enabled when the CEP, CET, and /PE
inputs are HIGH. When the /PE is LOW, the counters will synchronously load
the data from the Parallel inputs into the flip-flops on the LOW to HIGH
transition of the clock. Either the CEP or CET can be used to inhibit the count
sequence. With the /PE held HIGH, a LOW on either the CEP or CET inputs
at least one set-up time prior to the LOW to HIGH clock transition will cause
the existing output states to be retained. The AND feature of the two Count
Enable inputs (CET * CEP) allows synchronous cascading without external
gating and without delay accumulation over any practical number of bits or
digits.

The Terminal Count (TC) output is HIGH when the Count Enable Trickle
(CET) input is HIGH while the counter is in its maximum count state (HHHH).
Note that TC is fully decoded and will therefore; be HIGH only for one count
state.

The LS163A counts modulo 16 following a binary sequence. It generates TC

when the CET input is HIGH while the counter is in state 15 (HHHH). From
this state it increments to state 0 (LLLL).

The active LOW Synchronous Reset (/SR) input of the LS163A acts as an
edge-triggered control input, overriding CET, CEP and /PE, and resetting the
four counter flip-flops on the LOW to HIGH transition of the clock. This
simplifies the design from race-free logic controlled reset circuits, e.g., to reset
the counter synchronously after reaching a predetermined value.

MODE SELECT TABLE

Action on the Rising Clock
/SR /PE CET CEP
Edge
L X X X RESET (Clear)
H L X X LOAD (Pn --> Qn)
H H H H COUNT (Increment)
H H L X NO CHANGE (Hold)
H H X L NO CHANGE (Hold)
H=HIGH Voltage Level
L=LOW Voltage Level
X = Don't Care

Experimental Procedure
Connect the trainer to the mains and switch on the power supply,
measure
The output of the regulated power supply i.e. + 5V
Note. Power supply is internally connected to the circuit and so no
need to connect externally.
1. Observe the outputs of clock generator and pulsar using CRO.
2. Connect pulsar output to all CLK inputs.
3. Connect /P, /R to logic ‘1’.(To set the counter in count mode)
4. Now connect the outputs of the counter QA, QB, QC, QD to A, B, C,
D inputs of the 7-Segment Display respectively.(Internally
Connected)
5. Repeat the steps 2to 4 by replacing manual pulse with 1Hz clock.