FR9723B Fiti PDF
FR9723B Fiti PDF
FR9723B
85T
23V, 3A, 380KHz Asynchronous Step-Down
DC/DC Converter
Description Features
The FR9723B is a 380KHz step-down DC/DC ● Wide Input Voltage from 4.75V to 23V
converter that provides wide 4.75V to 23V input ● 3A Output Current
voltage range and 3A continuous load current ● Adjustable Output Voltage from 1.23V to 20V
capability. ● 100mΩ Integrated Power MOSFET
● High Efficiency up to 90%
Fault protection includes cycle-by-cycle current limit, ● Fixed 380KHz Switching Frequency
input UVLO and thermal shutdown. Besides, ● Current Mode Operation
adjustable soft-start function prevents inrush current ● Adjustable Soft-Start
at turn-on. This device uses current mode control ● Cycle-by-Cycle Current Limit
scheme that provides fast transient response. In ● Input Under Voltage Lockout
shutdown mode, the supply current is about 10μA. ● Over-Temperature Protection with Auto Recovery
● 10μA Shutdown Current
The FR9723B is available in an 8-pin SOIC package,
● Thermal Enhanced SOP-8 (Exposed Pad) Package
which provides a very compact system solution and ● RoHS Compliant
good thermal conductance.
Applications
● Set-Top-Box
● DVD,LCD Display
● OLPC, Netbook
● Distributed Power System
● DSL Modem
BS 1 8 SS G: Green
VIN 2 7 EN
SW 3 6 COMP Package Type
SP: SOP-8 (Exposed Pad)
GND 4 5 FB
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Typical Application Circuit
85T
C4
NO CONNECT = 10nF
AUTOMATIC STARTUP
7 1
EN BS L1
10μH
2 3
VIN VIN SW VOUT
5V to 23V 3.3V,3A
C1 R1
22μF/25V
FR9723B 16.8KΩ/1%
CERAMICX2 C2
6 5 47μF/6.3V
COMP FB
CERAMIC
C6 C5 D1
(optional) 10nF
GND SS B330A R2
R3 4 8 10KΩ/1%
5.6KΩ C3
0.1μF
D2
1N4148
NO CONNECT =
AUTOMATIC STARTUP C4 10nF
7 1
EN BS L1
4.7μH
2 3
VIN VIN SW VOUT
4.75V to 5V 1.8V, 3A
C1
FR9723B R1 C2
22μF/25V 4.7KΩ/1% 47μF/6.3V
CERAMIC x 2 6 COMP FB 5 CERAMIC
C5
10nF D1
C6 GND SS B330A R2
(optional)
R3
4 8 10KΩ/1%
5.6KΩ C3
0.1μF
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Functional Pin Description
85T
Pin Name Pin Function
High Side Gate Drive Boost Input. A 10nF or greater capacitor must be connected from this pin to SW. It can
BS
boost the gate drive to fully turn on the internal high side NMOS.
Power Supply Input Pin. Drive 4.75V to 23V voltage to this pin to power on this chip. Connect two 22μF ceramic
VIN
bypass capacitors between VIN and GND to eliminate noise.
SW Power Switching Output. It is the output pin of internal high side NMOS which is the switch to supply power.
Voltage Feedback Input Pin. Connect FB and VOUT with a resistive voltage divider. This IC senses feedback
FB
voltage via FB and regulates it at 1.23V.
Compensation Pin. This pin is used to compensate the regulation control loop. Connect a series RC network
COMP
from COMP pin to GND.
Enable Input Pin. This pin provides a digital control to turn the converter on or off. For automatic startup, leave
EN
EN unconnected.
Soft-Start Input Pin. This pin controls the soft-start period. Connect a capacitor from SS to GND to set the soft
SS
start period.
Block Diagram
VIN
1µA
UVLO Internal
ISEN VCC VCC
& Regulator
EN
POR OTP
BS
1.4V Oscillator
High-Side
6µA Current MOSFET
S
Comparator
FB Error
R PWM Driver
Amplifier SW
Control Logic
SS OTP
UVLO Low-Side
MOSFET
1.23V
COMP
Current
Limit
GND
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Absolute Maximum Ratings
85T
● Input Supply Voltage VIN --------------------------------------------------------------------------------- -0.3V to +25V
● SW Voltage VSW -------------------------------------------------------------------------------------------- -1V to VIN +0.3V
● BS Voltage VBS --------------------------------------------------------------------------------------------- Vsw -0.3V to Vsw +6V
● All Other Pins Voltage ------------------------------------------------------------------------------------ -0.3V to +6V
● Maximum Junction Temperature (T J) ----------------------------------------------------------------- +150℃
● Storage Temperature (TS) ------------------------------------------------------------------------------- -65℃ to +150℃
● Lead Temperature (Soldering, 10sec.) --------------------------------------------------------------- +260°C
● Power Dissipation @TA=25℃, (PD)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 2.08W
● Package Thermal Resistance, (θJA)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 60°C/W
● Package Thermal Resistance, (θJC)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 15°C/W
Note 1:Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.
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Electrical Characteristics
85T
(VIN=12V, TA=25℃, unless otherwise specified.)
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Typical Performance Curves
85T
VIN = 12V, VOUT = 3.3V, C1 = 22μF x 2, C2 = 47μF x 1, L1 = 10μH, TA = +25℃, unless otherwise noted.
Efficiency
70% 70%
Efficiency
60% 60%
50% 50%
VIN= 5V 40%
40%
VIN= 12V 30% VIN= 12V
30% VOUT= 3.3V 20%
VIN= 23V VOUT= 5V VIN= 23V
20% 10%
10% 0%
0% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Load Current (A)
Load Current (A)
1.24
Vfb (V)
1.235 390
1.23 380
1.225 370
1.22
360
1.215
350
1.21
VIN 12V / VOUT 3.3V VIN 12V / VOUT 3.3V
1.205 340
1.2 330
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
IOUT = 0A IOUT = 3A
VIN 500mV/div. (AC)
VIN 500mV/div. (AC)
VOUT 10mV/div. (AC)
VOUT 10mV/div. (AC)
IL 1A/div.
IL 1A/div.
2μs/div. 2μs/div.
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Typical Performance Curves (Continued)
85T
VIN = 12V, VOUT = 3.3V, C1 = 22μF x 2, C2 = 47μF x 1, L1 = 10μH, TA = +25℃,TA = +25℃, unless otherwise noted.
IOUT = 0.1A IOUT = 3A
VOUT 1V/div.
VOUT 1V/div.
IL 1A/div. IL 1A/div.
VSW 5V/div.
VSW 5V/div.
4ms/div. 4ms/div.
Figure 11. Startup Through Enable Waveform Figure 12. Startup Through Enable Waveform
IL 1A/div.
IL 1A/div.
Figure 13. Turn off Through Enable Waveform Figure 14. Turn off Through Enable Waveform
IL 1A/div.
IL 2A/div.
200μs/div. 80μs/div.
Figure 15. Load Transient Waveform Figure 16. Short Circuit Test Waveform
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Function Description
85T
The FR9723B is a constant frequency current mode Over Temperature Protection
step-down asynchronous DC/DC converter. It The FR9723B incorporates an over temperature
regulates input voltage from 4.75V to 23V, down to protection circuit to protect itself from overheating.
an output voltage as low as 1.23V, and can provide When the junction temperature exceeds the thermal
3A of continuous load current. shutdown threshold temperature, the regulator will
be shut down and re-enabled when the IC junction
Control Loop
temperature drops 10℃ (typ).
During normal operation, the output voltage is
sensed at FB pin by a resistive voltage divider and Compensation
amplified through the error amplifier. The voltage
of error amplifier output pin – COMP is compared to The stability of the feedback circuit is controlled by
the switch current to controls the RS latch. At COMP pin. The compensation value of the
each cycle, the high side NMOS will be turned on application circuit is optimized for particular
when the oscillator sets the RS latch and turned off requirements. If different conversions are required,
when current comparator resets the RS latch. some of the components may need to be changed to
When the load current increases, the FB pin voltage ensure stability.
will drop below 1.22V, and it will cause the COMP
voltage increasing until average inductor current
arrives at new load current.
Enable
The FR9723B EN pin provides digital control to turn
on/off the regulator. When the voltage of EN
exceeds the threshold voltage, the regulator will
start the soft start function. If the EN pin voltage is
lower than threshold voltage, only the bandgap
voltage will be alive. If the EN pin voltage is lower
than shutdown threshold voltage, the regulator will
be disabled and turn into shutdown mode.
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Application Information
85T
Output Voltage Setting Output Capacitor Selection
The output voltage VOUT is set by using a resistive The output capacitor is used to keep the DC output
divider from the output to FB. The FB pin voltage and supply the load transient current.
regulated voltage is 1.23V. Thus the output When operating in constant current mode, the
voltage is: output ripple is determined by four components:
R1 VRIPP E t =VRIPP E(C t VRIPP E(ESR t
VOUT =1.23 1 V
R2 t V
+VRIPP E(ES OISE (t
R2 recommended value is 10kΩ, so R1 is
The following figures show the form of the ripple
determined by:
contributions.
R1= .13 VOUT 1.23 kΩ
VRIPPLE(ESR)(t)
Table 1 lists recommended values of R1 and R2 for
most used output voltage.
II (RMS =IOUT D 1D
(t)
VOUT
D=
VI VOUT VOUT
VRIPP E(ESR, p-p = 1- ESR
FOSC VI
Where D is the duty cycle of the power MOSFET.
ES
A low ESR capacitor is required to keep the noise VRIPP E(ES , p p = VI
minimum. Ceramic capacitors are better, but ES
tantalum or low ESR electrolytic capacitors may VOUT VOUT
also suffice. When using tantalum or electrolytic VRIPP E(C, p p = 1
FOSC2 COUT VI
capacitors, a 0.1μF ceramic capacitor should be
placed as close to the IC as possible.
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Application Information (Continued)
85T
Where FOSC is the switching frequency, L is the Compensation Components Selection
inductance value, VIN is the input voltage, ESR is the
equivalent series resistance value of the output
capacitor, ESL is the equivalent series inductance COMP
value of the output capacitor and the COUT is the FR9723B
output capacitor. C6 C5
(optional
Low ESR capacitors are preferred to use. Ceramic, )
R3
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Application Information (Continued)
85T
PCB Layout Recommendation
The device’s performance and stability are dramatically
affected by PCB layout. It is recommended to follow
these general guidelines shown as below:
1. Place the input capacitors and output capacitors as
close to the device as possible. The traces which
connect to these capacitors should be as short and
wide as possible to minimize parasitic inductance
and resistance.
2. Place VIN bypass capacitors close to the VIN pin.
3. Place feedback resistors close to the FB pin.
4. Place compensation components close to the
COMP pin.
5. Keep the sensitive signal (FB, COMP) away from
the switching signal (SW).
6. The exposed pad of the package should be
soldered to an equivalent area of metal on the PCB.
This area should connect to the GND plane and
have multiple via connections to the back of the
PCB as well as connections to intermediate PCB
layers. The GND plane area which connects to the
exposed pad should be maximized to improve
thermal performance.
7. Multi-layer PCB design is recommended.
R3
R1
C6
C5
R2
8 7 6 5
C3
Exposed
GND
Pad
C1 C2
1 2 3 4 D1
VIN VOUT
C4
SW L1
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Outline Information
85T
SOP-8 (Exposed Pad) Package (Unit: mm)
Carrier dimensions