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Broadcom Interview Ques

The document contains a list of interview questions related to Broadcom's physical design flow and STA engineer role. Some of the key topics covered in the questions include timing analysis using Primetime, fixing timing issues during placement and routing, clock tree synthesis, handling crosstalk and IR drop, understanding design constraints, and using EDA tools like ICC and Innovus for physical implementation.

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Shaki Bhanu
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3K views5 pages

Broadcom Interview Ques

The document contains a list of interview questions related to Broadcom's physical design flow and STA engineer role. Some of the key topics covered in the questions include timing analysis using Primetime, fixing timing issues during placement and routing, clock tree synthesis, handling crosstalk and IR drop, understanding design constraints, and using EDA tools like ICC and Innovus for physical implementation.

Uploaded by

Shaki Bhanu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BROADCOM INTERVIEW QUESTIONS:

1. Explain PD flow?
2. What info .lib & .LEF & DEF will give?
3. Contents of SDC?
4. Why we will define uncertainity in SDC? Weather we will decrease or increase uncertainity
in next stages?
5. Why we need channel spacing between macros?
6. Techniques to reduce congestion at placement stage?
7. How will you fix timing issues at placement stage?
8. What are different Vt cells and which cells you will use in timing critical paths?
9. Will you address hold issues at placement stage?
10. What are the goals of CTS?
11. I have skew of 0ps and 100ps, which will be advantage for setup and hold?
12. Which will be better among clock buff and clock inverters and why?
13. What is clock gating and what is the advantage of it?
14. What is cell cloning?
15. What are the steps in routing? What will happen in Global routing?
16. What is cross talk & effect of cross talk?
17. How will you fix cross talk issues, without disturbing routing?
18. What is antenna violations? How will you fix antenna violations? Why only upper metal
layer?
19. What is Prime time?
20. What are the inputs for Prime time?
21. What are different methods to fix timing issues in PT?
22. What can eco fix for hold can contain?
23. What is OCV and how we are addressing OCV in backend?
24. What is Redhawk tool and for what purpose it is used?
25. What are the input for Redhawk tool?
26. What is difference between Static IR and Dynamic IR drop analysis?
27. What is VCD file and what info will it give?
28. What is LEC?
29. Different DRC issues?
30. What is EM Violation and how to fix it?
31. What is NDR and for what nets it will be applied and advantage of it?
32. What is temperature inversion?
33. What is DPT?
34. What is Star RC?
35. What info a spef will contain?
36. Draw CMOS NAND gate circuit?

1. Before starting interview, Suhash told that we looking for only STA engineer.
2. Explain your project related experience and challenges... I directed him in only STA.
3. How many clocks were there in your design you recently worked?
4. How many corners you used for signoff?
5. How many modes are there in you design and how you fixed timing for them?
6. How do you approach for timing fixes?
7. How will you report all aggressors and victim nets in pt?
8. How will you fix cross talk in pt?
9. If you have AND gate and input pin of AND gate having buffer. and you have cross-talk
between buffer and AND gate, How will you fix ?
10. How do you size aggressor for fixing cross talk?
11. Are you doing Physical aware pt eco or Normal?
12. How to fix setup and hold timing?
13. Are you doing DMSA? How tool was doing?
14. If you are adding buffer on input pin than where PnR toll will place that buffer? Is there and
switch in PT to place that cell near to pin?
15. How will you fix min pulse width and min period violation?
16. If you are adding back-to-back invertor than it, will affect skew, than how will you
approach?

1. Diff between 16nm and 28 nm


2. temperature inversion
3. floorplan techiniques,
4. Techniques to fix timings after placement.
5. How to fix congestion and different congestion reduction techniques?
6. Clock spec file contents? clock exceptions?
7. What are challenges faced in CTS?
8. What is ICG cells? Draw the circuit and explain with waveforms?
9. How will you validate routing of the design?
10. what are challenges faced in routing
11. What are pulse width violations and how fix Pulse with violations.
12. What is OCV?
13. Basic tcl expressions?

1. Diff between 16nm and 28 nm


2. temperature inversion
3. floorplan techniques,
4. Why need of pipelining? How it is done?
5. Congestion reduction given different scenarios?
6. Clock spec file contents? clock exceptions?
7. What are challenges faced in CTS?
8. ICG cell with waveform?
9. How will you validate routing of the design?
10. For ICC & PTSI correlation what steps are been taken?
11. Correlation b/w pre_cts and post CTS?
12. What are challenges faced in routing?
13. regsub & list in tcl?
14. Congestion reduction in post cts?
15. Specify cell padding how does it works?

1. What are the benefits in lower nodes


2. What is temperature inversion?
3. What are sync flops? How will you model them? What all are setup and hold check
required?
4. What are the ways to do async data transfer?
5. How to model PLL libs? How to converge PLL paths?
6. What is clock gating? Can you draw ICG ckt with waveform?
7. What are the advantages of using placement info in DC? What is wire load? Why is macro
info needed in DC’s input def?
8. How will you build a floorplan?
9. What will you review in a routed design?
10. What are the challenges in congestion that you have faced?
11. What will you ensure to get CTS as per your requirement? What is the sync point?
12. What are the issues faced in routing? What is Route Guide?

1. What have you done in floorplan? How much space is required for macros?
2. Did you do anything to optimize and balance the CTS?
3. Have you worked on Multi voltage design? Why is level shifter and isolator required?
4. Please explain block level design closure flow? What all inputs are required for synthesis?
5. What have you done at FC level?
6. How have you done the partitioning?
7. What are the Physical verification challenges you have faced?
8. What is a saif file? What is there in saif file and how will you generate it?
9. Name the clock gating methods used in your design. Did you merge the clock gating?
10. Which all corners have you used in closing your design?
11. What corners have been used for the best and worst case scenarios?

1. Please come up with setup and hold equation.


2. What does the ICC placer do?
3. Please explain design flow.
4. How will you do the ICC-PTSI correlation?
5. What to do to fix DFM?
6. Where do you perform hold fix in your design flow?
7. How does voltage and temperature influence the setup and hold?
8. Where will you come across setup and hold conflict? How can you fix it?
9. How to fix min pulse width violations?
10. How will you design power grid?
11. Design an OR gate using 2:1 MUX.
12. Did you face any IR issue? How can you fix it? How will you fix it in the final stage of
design?
13. Have you worked on Multi voltage design? Why is level shifter and isolator required?
14. What is Double Patterning Technology? What are the new checks for this?

1. Introduce yourself
2. Which EDA tools have you used for PNR
3. Have you been involved in Timing correlation / closure activity between PNR / SIGNOFF
Tool
4. Which technology have you been working on recently?
5. How about your previous 28nm project; which metal stack was used?
6. Is this chip power / timing critical? What were the challenges?
7. What is the best practise to achieve low power for your design? What steps will you do in
PNR so as to have best area / power
8. How to configure low power optimization in ICC?
9. How many modes & corners were used for Placement / CTS / Routing?
10. Justify which is better approach; use HVT throughout the flow & swap LVT @ end or allow
LVT within PNR
11. What types of derates were used in your previous project?
12. How was your involvement with customer; were you only working as independent
contractor?
13. Have you worked on F/C activities or any blocks having analog IP?
14. How about power signoff; can you provide details on the same?
15. Why do you do IR analysis @ block level; is it accurate?

1. Have you ever done RTL synthesis? In which Tool?


2. Have you done formal Verification? In which Tool?
3. Can you please explain Synthesis flow in design compiler?
4. After Synthesis, if timing is violating by more than half cycle, what will you do?
5. What is Lint Check?

1. Have you worked on PT/PT-SI?


2. What is Cell delay and Net Delay?
3. What is OCV and why do we need OCV margins?
4. Why do we have timing exceptions (especially multicycle paths) in the design?
5. What is crosstalk delay and crosstalk noise?
6. What is Virtual Clock?
7. What is the command to analyse timing in Primetime?
8. What is Path based and Graph based analysis in Primetime?
9. How did you decided floorplan and placement of D/I Cache?
10. Have you use bounds/groups for placement, if yes, in what scenario’s you have added those.
11. How did you resolve timing for read/write logic?
12. What commands you used for placement in ICC.
13. In CTS, what type of NDR’s you have used, why?
14. How you decided stop pins or leaf pins for balancing clock skew.
15. What issues you faced in Route and post Route stage.
16. What kind of physical libraries used?
17. How ICC knows routing on top of memories need to route or not?
18. Any macro modules?
19. How about PV and IR for CPU blocks.
20. LVS?
21. Have you done synthesis?
22. Do you need any nets to be pre-routed, why?
23. Did you face crosstalk issue on clock nets? Shielding of clock nets?
24. How you know about critical rage in ICC.
25. How CTS constraints are?
26. CLKA and CLKB are having communication, how did you take care these paths in CTS
stage?
27. What exactly you experimented during floorplan & macro placement?
28. Why do we do the CTS?
29. If there is only 50MHz clock frequency in the block. Then should I just connect clock
without Buffers? Will that be ok? Basic Reasons
30. What are the inputs you need for CTS?
31. Why do you need uncertainty for building CTS?
32. What after CTS – How you will move ahead?
1. What are the inputs to PNR?
2. Dbget commands and iccii commands related to cell instance finding
3. Have you open ir drop and EM reports, How look like and how to fix it?
4. congestion reduced techniques
5. LVS issues Debugging,DPT Violations
6. Temperature inversion?
7. Timing fixing with clock skewing? What are check u will do before clock skewing
8. Which command use for clock skewing in innovus and iccii?
9. Have you done manual routing? How you will confirm don't have Drc, opens, and shorts?
10. Blockages and commands?
11. How you will do pin Placement in Innovus
12. Static and Dynamic Power?
13. List given. How to remove fourth content in given list?
14. Explain Avago Clock Tree Structure?
15. What is difference you saw in innovus and iccii. Mainly in Routing?
16. AOCV Table?
17. What is GSR file? Have you worked on Redhawk?
18. Setup and hold questions?
19. Explain Multi Point CTS?
20. What is TLU+ file

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