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An efficient binary multiplier design for high speed applications using

Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Conference Paper · April 2015

DOI: 10.1109/GCCT.2015.7342650

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Cite as: S. Arish and R. K. Sharma, "An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm,"
2015 Global Conference on Communication Technologies (GCCT), Thuckalay, 2015, pp. 192-196. doi: 10.1109/GCCT.2015.7342650

An efficient binary multiplier design for high speed

applications using Karatsuba algorithm and Urdhva-
Tiryagbhyam algorithm
Arish S R.K.Sharma
School of VLSI Design and Embedded Systems School of VLSI Design and Embedded Systems
National Institute of Technology Kurukshetra National Institute of Technology Kurukshetra
Kurukshetra, India Kurukshetra, India
[email protected] [email protected]

Abstract: Binary multiplication is an important operation

in many high power computing applications and floating point II. KARATSUBA-URDHVA TIRYAGBHYAM BINARY
multiplier designs. And also multiplication is the most time, MULTIPLIER
area and power consuming operation. This paper proposes an The proposed model, Karatsuba-Urdhva binary multiplier, uses
efficient method for unsigned binary multiplication which a combination of Karatsuba algorithm and Urdhva-
gives a better implementation in terms of delay and area. A Tiryagbhyam algorithm to make multiplication more efficient.
combination of Karatsuba algorithm and Urdhva-Tiryagbhyam Multiplication operation requires more time compared to
algorithm (Vedic Mathematics) is used to implement the addition. And as the number of bits increase, it consumes more
proposed unsigned binary multiplier. Karatsuba algorithm is area and time. In the design of floating point multiplier,
best suited for higher bits and Urdhva-Tiryagbhyam algorithm unsigned binary multiplier is the important part. In double
is best for lower bit multiplication. A new algorithm by precision floating point format, we need a 53x53 bit multiplier
combining both helps to reduce the drawbacks of both. The and in single precision format we need 24x24 bit multiplier. It
multiplier is implemented using Verilog HDL, targeted on requires much time to perform these operations and it is the
Spartan-3E and Virtex-4 FPGA. major contributor to the delay of the floating point multiplier.
As the number of bits of operands increases, area and delay
Keywords: fpga, binary multiplier, unsigned, Vedic requirement increases drastically. The proposed model make
mathematics, Urdhva-Tiryagbhyam, Karatsuba the multiplication operation more area efficient and faster.
Karatsuba algorithm uses a divide and conquer approach
I. INTRODUCTION where it breaks down the inputs into Most Significant half and
Binary multiplication is the most important operation in Least Significant half and this process continues until the
binary arithmetic. Applications such as High Power Computing operands are of 8-bits wide. Karatsuba algorithm is best suited
(HPC), Image processing and Signal processing is based on for operands of higher bit length. But at lower bit lengths, it is
binary multiplication. Area and delay requirements of not as efficient as it is at higher bit lengths. To eliminate this
conventional binary multipliers are much more and hence problem, Urdhva Tiryagbhyam algorithm is used at the lower
efficient multiplication algorithms are used to reduce delay and stages. The model of Urdhva-Tiryagbhyam algorithm is shown
area requirement. Various multiplication algorithms are in Fig. 1.
described in [1]. Vedic mathematics methods [2] are the most Urdhva Tiryagbhyam algorithm is the best algorithm for
efficient in terms of delay and area. There are many literatures binary multiplication in terms of area and delay. But as the
available on Vedic mathematics methods [3, 4, 5, 6, 7, 8 and number of bits increases, delay also increases as the partial
9]. Karatsuba algorithm [10, 11] is the most used algorithm for products are added in a ripple manner. For example, for 4-bit
higher bit length multipliers. But every algorithm has its own multiplication, it requires 6 adders connected in a ripple
advantages and disadvantages. In the proposed model, a manner. And 8-bit multiplication requires 14 adders and so on.
combination of Urdhva-Tiryagbhyam algorithm (Vedic Compensating the delay will cause increase in area. So Urdhva
mathematics) and Karatsuba algorithm is used. By combining Tiryagbhyam algorithm is not that optimal if the number of bits
these two algorithms, best features of both the algorithms can is much more. If we use Karatsuba algorithm at higher stages
be used in an efficient manner to reduce both delay and area. and Urdhva Tiryagbhyam algorithm at lower stages, it can
somewhat compensate the limitations in both the algorithms
and hence the multiplier becomes more efficient. The circuit is
further optimized by using carry select andd carry save adders This method can be further opttimized to reduce the number of
instead of ripple carry adders. This reduces the
t delay to a great hardware. A more optimized hardware
h architecture [7, 9] is
extent with minimal increase in hardw ware. These two shown in Fig. 3. This model actually helps to eliminate the
algorithms are explained in detail in the below sections. need for three operand 7-bit addder and hence reduces hardware

Fig. 1 Karatsuba-Urdhva multiplier model

A. Urdhva Tiryagbhyam algorithm for multiiplication

Urdhva-Tiryagbhyam sutra is an ancient VedicV mathematics
method for multiplication [2, 3, 4 and 5]. It is a general formula
applicable to all cases of multiplication. Thhe formula is very
short and consists of only one compoundd word and means
‘Vertically and crosswise’. In Urdhva Tiryaggbhyam algorithm,
the number of steps required for multiplicatiion can be reduced
and hence the speed of multiplication is increeased.
An illustration of steps for computing thee product of two 4-
bit numbers is shown below [6, 7]. The two input are a 3 a 2 a 1 a 0 Fig. 2 Line notation of Urdhva Tiryagbhyam sutra
and b3 b2 b1 b0 and let the p7 p6 p5 p4 p3 p2 p1 p0 be the product. and delay. The adders are conneected in ripple manner.
And the temporary partial products are t 0 , t 1 , t 2 , … , t 6 . The The expressions for product bits
b are as shown below.
partial products are obtained from the stepss given below. The
line notation of the steps is shown in Fig. 2. p0 a 0 b0
p1 1
Step1: t 0 1 a0 b0 .
Step2: t 1 2 a1 b0 + a 0 b1 . a 1 b0 + a 0 b1
Step3: t 2 2 a 2 b0 + a 1 b1 + a 0 b2 p2 2
Step4: t 3 3 a 3 b0 + a 2 b1 + a 1 b2 + a 0 b3 . MSB ADDER1 +a2 b0 + a 1 b1 + a 0 b2
Step5: t 4 2 a 3 b1 + a 2 b2 + a 1 b3 . p3 3
Step6: t 5 2 a3 b2 + a 2 b3 . MSB ADDER 2 +a 3 b0 + a 2 b1 +
Step7: t 6 1 a3 b3 a1b2+a0b3
p4 4
The product is obtained by adding s1 , s2 s3 as shown DDER1 +a3 b1 + a 2 b2 + a 1 b3
MSB AD
below, where s1 , s2 s3 are the partial sum
m obtained. p5 5
MSB ADDER1 +a3 b2 + a 2 b3
s1 t6 t5 0 t4 0 t3 0 t2 0 t1 0 t0 p6 6
s2 t5 1 t4 1 t3 1 t2 1 t1 1 M
MSB ADDER1 +a 3 b3
s3 t3 2 p7 6
Product t6 t5 0 t4 0 t3 0 t2 0 t1 0 t0 + Since there are more than two operands in adders 2 to 5, we
t5 1 t4 1 t3 1 t2 1 t1 1 0 + can use carry save addition to implement adders 2 to 5. This
t3 2 0 0 0 0 technique reduces the delay to a great extend compared to the
ripple carry adder.
p7 p6 p5 p4 p3 p2 p1 p0
 Where Xl, Yl and Xr , Yr are the Most Significant half and
Least Significant half of X annd Y respectively, and n is the
number of bits.
Then,
. 2 . X l + X r . 2 . Yl + Yr
/
2 . X l Yl + 2 Xl Yr + X r Yl + X r Yr (3)

The Second term in equation (3) can be optimized to reduce the

number of multiplication operattions.

i.e.; Xl Yr + Xr Yl Xl + Xr Yl + Yr Xl Yl Xr Yr
(4)
The equation (3) can be re-writtten as,
. 2 . Xl Yl + Xr Yr + 2 Xl + Xr Yl + Yr
X l Yl X r Yr (5)
The recurrence of Karatsuba alggorithm is,
.
3 +
2

Fig. 3 Hardware architecture for 4x4 Urrdhva

Tiryagbhyam multiplier.
Fig. 4 Karatsubba multiplier
B. Karatsuba Algorithm for multiplication
Karatsuba multiplication algorithm [10, 11] is best suited for
multiplying very large numbers. This methood is discovered by
Anatoli Karatsuba in 1962. It is a divide annd conquer method, III. IMPLIMENTA
ATION AND RESULTS
in which we divide the numbers into their Most Significant half The main objective of this paaper is to design and implement
and Least Significant half and then multipliccation is performed. an unsigned multiplier which must
m be efficient in its operation
Karatsuba algorithm reduces the number of multipliers both in terms of delay and arrea. Since multiplication is the
required by replacing multiplication operaations by addition most important and complex opperation in binary arithmetic, we
operations. Additions operations are faster thhan multiplications designed a multiplier which can c operate at high speed and
and hence the speed of multiplier is increassed. As the number increase in delay and area is siggnificantly less with increase in
of bits of inputs increase, Karatsuba algoritthm becomes more number of bits. Proposed unsignedu binary multiplier is
efficient. This algorithm is optimal if widthh of inputs is more implemented using Verilog HDL and tested. The multiplier
than 16 bits. The hardware architecture of Karatsuba
K algorithm units are further optimized byy replacing simple adders with
is shown in Fig. 4. efficient adders like carry selecct adders and carry save adders.
Product . The model is synthesized and siimulated using Xilinx Synthesis
X and Y can be written as, Tools (ISE 14.7) targeted on Saprtan-3E and Virtex-4 fpga.
2 / . Xl + Xr (1) The summary of results on Viirtex-4 fpga is given in table I.
2 / . Yl + Yr (2)
Comparison with various multiplier units is given in tables II, efficient combination of Karatsuba and Urdhva-Tiryagbhyam
III, IV and V algorithms. The model can be further optimized in terms of
delay by using pipelining methods and also by using efficient
adders instead of ripple adders.
TABLE I
Performance analysis of Karatsuba-Urdhva multipliers
TABLE V
8-bit 16-bit 24-bit 32-bit Delay and area comparison of 32-bit multipliers with
multiplier multiplier multiplier multiplier proposed Karatsuba-Urdhva multiplier
LUTs Delay
Slices 113 410 972 1389
LUTs 120 451 1018 1545 Ref. [12]- Modified Booth 2721 12.081ns
multiplier (Radix-8)
IOBs 33 65 97 129 Ref. [12]- Modified Booth 7161 11.564ns
multiplier (Radix-16)
Delay 9.396ns 11.514ns 12.996ns 13.141ns
Ref. [12] 2704 9.536ns
274.469 248.964 226.508 209.606 Proposed multiplier 1545 13.141ns
(MHz)
Logic 14 22 31 39
levels

REFERENCES
TABLE II
Delay comparison of various 8-bit multipliers with proposed [1] Computer Arithmetic, Behrooz Parhami, Oxford
Karatsuba-Urdhva multiplier
University Press, 2000.
Ref. [6] Ref. [7] Ref. [8] Proposed
multiplier [2] “Vedic mathematics”, Swami Sri Bharati Krsna Thirthaji
Width 8-bit 8-bit 8-bit 8-bit Maharaja, Motilal Banarasidass Indological publishers and
Book sellers, 1965
Delay 28.27ns 15.050ns 23.973ns 9.396ns [3] R. Sridevi, Anirudh Palakurthi, Akhila Sadhula, Hafsa
Mahreen, “Design of a High Speed Multiplier (Ancient
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TABLE III
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