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Fig 1: Half Adder Circuit.: Carry Sum

The document summarizes the study of half adders and full adders. A half adder can add two bits and produces a sum and carry output. A full adder can add three bits and also produces a sum and carry output. The document explains the logic circuits and truth tables for both half adders and full adders. It then provides the procedure to construct each circuit using logic gates on a digital trainer board and verify the output for different input combinations.

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Siva Arun
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0% found this document useful (0 votes)
73 views

Fig 1: Half Adder Circuit.: Carry Sum

The document summarizes the study of half adders and full adders. A half adder can add two bits and produces a sum and carry output. A full adder can add three bits and also produces a sum and carry output. The document explains the logic circuits and truth tables for both half adders and full adders. It then provides the procedure to construct each circuit using logic gates on a digital trainer board and verify the output for different input combinations.

Uploaded by

Siva Arun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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STUDY OF HALF ADDER and FULL ADDER.

AIM: - To fabricate a half adder and full adder using gates and to study their operation as binary
adder circuits.

APPARATUS: - Digital Trainer Board, IC s 7400[NAND],7432 [OR],7408[AND], 7486[XOR],


connecting wires.
.
THEORY: - HALF ADDER: It is a logic circuit that adds 2 bits. The outputs are SUM &
CARRY.

A B
A B CARRY SUM

2 0 0 0 0
carr
3
1 0 1 0 1
y 1 0 0 1
2 1 1 1 0
Su
3
1

m
FIG 1: HALF ADDER CIRCUIT.

Table summarizes the operation. When A and B are 0’s, the SUM is 0 with a CARRY of
0. When A is 0 and B is 1, the SUM is 1 with a CARRY of 0. When A is 1 and B is 0, the SUM
is 1 with a CARRY of 0. Finally, when A is 1 and B is 1, the SUM is 1 with a CARRY of 1.
The logic circuit of fig 1 does electronically what we do mentally when we add 2 bits.
Applications for half adders are limited. What we need is a circuit that can add 3 bits at a time.

FULL ADDER: It is a logic circuit that can add 3 bits. Again there are two outputs, SUM
and CARRY. The Boolean equations are SUM = A⊕B ⊕ C , CARRY= AB + BC + AC
In this case, SUM equals A XOR B XOR C; CARRY equals AB OR AC OR BC.
Therefore, the SUM is 1 when the number of input 1s is odd; CARRY is a 1 when two or more
inputs are 1s.

Truth table summarizes the circuit action. A, B, and C are the bits being added. If you check
each entry, you will see that the circuit adds 3 bits at a time and comes up with the correct
answer.
The circuit of fig 2 does electronically what we do mentally when we add 3 bits. The
full adder can be cascaded to add large binary numbers.
A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

A B C

2
3
7408 1
2
3 SN7432 1

5
6
5 7408 4
6 SN7432 4
Carry
5
6
7408 4

2
3
SN7486 1

5
6 SN7486 4
Sum

PROCEDURE:

HALF ADDER
1. Construct the circuit as shown in the fig 3 using ICs 7486 (XOR), 7408 (AND).
2. Connect the inputs A and B to the logic input sockets available in the digital trainer board
below the respective toggle switches. The toggle switches can set the logic inputs 0 or 1.
3. Connect the output of XOR i.e. SUM & the output of AND i.e. CARRY to logic output
sockets available in digital trainer board below the dual color L E Ds. The dual color L E D
will indicate the state 0 as green and 1 as red.
4. Verify the table 1 for different inputs combinations of A and B.
FULL ADDER
5. Construct the circuit as shown in the fig 4 using I Cs 7486 (XOR), 7408 (AND), and
7432(OR).
6. Connect the inputs A, B and C to the logic input sockets available in the digital trainer
board.
7. Connect the output of XOR i.e. SUM & the output of OR i.e. CARRY to logic output
sockets.
8. Verify the table 2 for different inputs A, B and C.
9. Use Karnaugh map technique to obtain the SUM and CARRY for both Half and Full adder
circuits.

EXTRA: Fabricate Half adder or full adder using 2 input Nand gates
Result:

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