Low Power VLSI Circuits and
Systems
Unit V
Dr.P.Rajasekar, Professor,
Department of ECE,
Narayana Engineering College, Gudur.
Unit V
Leakage Power Minimization
• The threshold voltage to minimize leakage power
– Dependence of delay and leakage power on threshold voltage
– Various techniques for fabrication of multiple threshold
voltages.
– variable-threshold-voltage complementary metal–oxide–
semiconductor (VTCMOS)
• Leakage power can be minimized by using the stack effect
• Run-time leakage power minimization by using the
multiple- threshold -voltage metal –oxide– Semiconductor
(MTCMOS)
• Leakage power reduction by power gating
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Introduction
• Very-large-scale integration (VLSI) technology has moved from
the millimetre to nanometre era by providing increasingly
higher performance.
• supply voltage must continue to scale with device-size scaling
to maintain a constant field, the threshold voltage of the
metal–oxide–semiconductor (MOS) transistors should also be
scaled at the same rate to maintain gate overdrive ( Vcc/Vt) and
hence performance.
• The reduction of Vt leads to an exponential increase in the
subthreshold leakage current.
– for a 90-nm technology, the leakage power is 42 % of the total power
and for a 65-nm technology, the leakage power is 52 % of the total
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• Leakage power reduction techniques
– Standby and run-time leakage
• When a circuit or a part of it is not in use, it is kept in the
standby mode by a suitable technique such as clock
gating.
• Standby Reduction technique
– Transistor stacking,
– variable-threshold-voltage complementary metal–oxide–
semiconductor (VTCMOS),
– multiple-threshold-voltage complementary metal–oxide–
semiconductor (MTCMOS)
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• The reduction of the leakage power when a circuit is in
actual operation. These are known as run-time
leakage power reduction techniques.
• Classification on leakage power reduction techniques
based on technique is applied at the time of fabrication
of the chip or at run time.
• The approaches applied at fabrication time can be
classified as static approaches.
• The techniques that are applied at run time are known
as dynamic approaches
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Fabrication of Multiple Threshold Voltages
• Process technology allows the fabrication of metal–oxide–
semiconductor field-effect transistors (MOSFETs) of multiple
threshold voltages on a single chip.
• This has opened up the scope for using dual-Vt CMOS
circuits to realize high-performance and low-power CMOS
circuits.
• The basic idea is to use high-Vt transistors to reduce
leakage current and low-Vt transistors to achieve high
performance.
• Multiple Channel Doping
• Multiple Oxide CMOS
• Multiple Channel Length
• Multiple Body Bias
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Multiple Channel Doping
• It realize multiple-VT MOSFETs is to
use different channel-doping
densities.
• A higher doping density results in a
higher threshold voltage.
• To fabricate two types of transistors
with different threshold voltages,
two additional masks are required
compared to the conventional single-
Vt fabrication process.
• This makes the dual-Vt fabrication
costlier than single-Vt fabrication
technology.
• Due to the non-uniform distribution
of the doping density, it may be
difficult to achieve dual threshold
voltage when these are very close to
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Multiple Oxide CMOS
• Threshold voltage is strong
dependence on the value of Cox, the
unit gate capacitance.
• Different gate capacitances can be
realized by using different gate oxide
thicknesses.
• A lower gate capacitance due to
higher oxide thickness reduces
subthreshold leakage current.
• Reduced gate oxide tunnelling
because the oxide tunnelling
current exponentially decreases
with the increase in oxide thickness.
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Multiple Channel Length
• Threshold voltage
decreases as the channel
length is reduced, which
is known as Vth roll-off.
• For transistors with
feature sizes close to 0.1
μm, halo techniques
have to be used to
suppress the short-
channel effects
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Multiple Body Bias
• Reverse body bias to the well-to-source junction leads to an
increase in the threshold voltage due to the widening of the bulk
depletion region, which is known as body effect.
• This effect can be utilized to realize MOSFETs having multiple
threshold voltages.
• This necessitates separate body biases to be applied to different
nMOS transistors, which means the transistors cannot share the
same well.
• Costly triple-well technologies are to be used for this purpose.
• Alternative is to use silicon-on-insulator (SoI) technology, where
the devices are isolated naturally.
• A smaller delay of low-Vt devices and a smaller power
consumption of high-Vt devices, a balanced mix of both low-Vt and
high-Vt devices may be used.
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VTCMOS Approach
• Low supply voltage along with low-threshold voltage provides a reduced
overall power dissipation without a degradation in performance.
• low-Vt transistors inevitably leads to increased subthreshold leakage
current.
• VTCMOS circuits make use of the body effect to reduce the subthreshold
leakage current, when the circuit is in normal mode
• Vt is a function of the voltage difference between the source and the
substrate
• The substrate terminals of all the n-channel metal–oxide–semiconductor
(nMOS) transistors are connected to the ground potential
• The substrate terminals of all the p-channel metal–oxide–semiconductor
(pMOS) transistors are connected to Vdd,
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VTCMOS Approach
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VTCMOS Approach
• VTCMOS circuits, the
substrate bias voltages
of nMOS and pMOS
transistors are
controlled with the help
of a substrate bias
control circuit
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Operation
Active Mode operation
• In the active mode, the substrate bias voltages for nMOSand pMOS
transistors are VBn =0 and VBp =Vdd
• Assuming Vdd = 1V , the corresponding threshold voltages for the nMOS
transistors and pMOS transistors are Vtn = 0.2V and Vtp = −0.2V ,
Standby mode
• In standby mode, the substrate bias control circuit generates a lower
substrate bias voltage of VBn= −VB for the nMOS transistor, a higher
substrate bias voltage VBp = VB +Vdd for the pMOS transistors.
• It increases in threshold voltages for nMOS and pMOS transistors to V =
0.5V and V = −0.5V,
• It leads to substantial reduction in subthreshold leakage currents because
of the exponential dependence of subthreshold leakage current on the
threshold voltage.
• It has been found that for every 100-mV increase in threshold voltage, the
subthreshold leakage current reduces
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Disadvantages
• It requires a twin-well or triple-well CMOS
fabrication technology so that different substrate
bias voltages can be applied to different parts of the
chip.
• Separate power pins may also be required if the
substrate bias voltage levels are not generated on
chip.
• The additional area required for the substrate bias
control circuitry is negligible compared to the overall
chip area.
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Transistor Stacking
• A more than one transistor is in series in a CMOS circuit, the leakage
current has a strong dependence on the number of turned off
transistors This is known as the stack effect.
Example :
• A Four nMOS devices of a four-input NAND gate in a stack
• voltages are generated due to a small drain current passing
through the circuit.
• The source voltages of the three transistors on top of the stack have
positive values.
• Assuming all gate voltages are equal to zero, the gate-to-source
voltages of the three transistors are negative.
• The drain-to-source potential of the MOS transistors is also reduced.
• The following three mechanisms come into play to reduce the
leakage current: Dr.P.Rajasekar, Professor,
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ECE, NECG- Gudur
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Transistor Stacking
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Transistor Stacking
• Due to the exponential dependence of the
subthreshold current on gate-to-source voltage, the
leakage current is greatly reduced because of negative
gate-to-source voltages.
• The leakage current is also reduced due to body effect,
because the body of all the three transistors is reverse-
biased with respect to the source.
• As the source-to-drain voltages for all the transistors
are reduced, the subthreshold current due to drain-
induced barrier lowering (DIBL) effect will also be
lesser.
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Transistor Stacking
• The leakage currents will be minimum when all the transistors
are turned off, which happens when the input vector is 0000.
• The leakage current passing through the circuit depends on
the input vectors applied to the gate and it will be different for
different input vectors.
• For example, for a three-input NAND gate, the leakage current
contributions for different input vectors are given in Table.
• It may be noted that the highest leakage current is 99 times
the lowest leakage current.
• The current is lowest when all the transistors in series are
OFF, whereas the leakage current is highest when all the
transistors are ON
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Transistor Stacking
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MTCMOS Approach
• It is introduced the MTCMOS approach to
implement high-speed and low-power circuits
operating from a 1-V power supply.
• MOSFETs with two different threshold voltages
are used in a single chip.
• It uses two operational modes—active and sleep
for efficient power management.
• The CMOS logic gate is realized with transistors of
low-threshold voltage of about 0.2–0.3 V.
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MTCMOS Approach
• Instead of connecting the power
terminal lines of the gate directly to
the power supply lines Vdd and GND,
here these are connected to the
‘virtual’ power supply lines (VDDV and
GNDV).
• The real and virtual power supply lines
are linked by the MOS transistor Q1
and Q2.
• These transistors have a high-threshold
voltage in the range 0.5–0.6 V and
serve as sleep control transistors.
• Sleep control signals SL andSL’ are
connected to Q1 and Q2, respectively,
and used for active/sleep mode
control.
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MTCMOS Approach
• In the active mode, when SL • In the sleep mode, SL is set
is set to LOW, both Q1 and to HIGH to turn both Q1 and
Q2 are turned ON Q2 OFF, thereby isolating the
connecting the real power real supply lines from VDDV
lines to VDDV and GNDV. and GNDV.
• In this mode, the NAND gate • As the sleep transistors have
operates at a high speed a high-threshold voltage (0.6
corresponding to the low- V), the leakage current
threshold voltage of 0.2 V, flowing through these two
which is relatively low transistors will be
compared to the supply significantly smaller in this
voltage of 1.0 V. mode
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MTCMOS Approach
• Speed performance affect of an MTCMOS circuit are:
– The width of the sleep control transistors and the
capacitances of the virtual power line.
– The sleep transistors should have their widths large enough so
that the ON resistances are small
• Advantage of MTCMOS
– easily implemented using existing circuits, without
modification of the cell library.
• Disadvantage
– Alarge inserted sleep transistors increase both area and delay.
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Power Gating
• The MTCMOS implementation has been generalized and extended
in the name of power management or power gating.
• Types of power modes:
– Active Mode
– Low power Mode
• An active mode, which is the normal operating mode of the circuit
• A low-power mode when the circuit is not in use.
• The low-power mode is commonly termed as sleep mode.
• At an appropriate time, the circuit switches from one mode to the
other in an appropriate manner such that the energy drawn from
the power source is maximized with minimum or no impact on the
performance.
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Clock Gating Versus Power Gating
• The clock-gating approach for the reduction of
switching power
• No dynamic power dissipation takes place when the
circuit is clock-gated.
• Leakage power dissipation takes place even when the
circuit is clock-gated.
• Power gating can be implemented by inserting power-
gating transistors in the stack between the logic
transistors and either power or ground, thus creating a
virtual supply rail or a virtual ground rail, respectively
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• The logic block contains all low-Vth transistors for fastest
switching speeds while the switch transistors, header or footer,
are built using high-Vth transistors to minimize the leakage
power.
• Power gating can be implemented without using multiple
thresholds, but it will not reduce leakage as much as if
implemented with multiple thresholds. MTCMOS refers to the
use of transistors with multiple threshold voltages in power
gating circuits.
• The most common implementations of power gating use a
footer switch alone to limit the switch area overhead.
• High-Vth NMOS footer switches are about half the size of
equivalent-resistanceDr.P.Rajasekar,
high-Vth PMOS header switches due to
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differences in majority carrier mobilities.
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• Power gating reduces leakage by reducing the gate-
to-source voltage,
• It drives the logic transistors deeper into the cutoff
region. This occurs because of the stack effect.
• The source terminal of the bottom-most transistor
in the logic stack is no longer at ground, but rather
at a voltage somewhat above ground due to the
presence of the power-gating transistor.
• Leakage is reduced due to the reduction of the Vgs.
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• The clock-gating approach does not affect the
functionality of the circuit and does not
require changes in the resistor–transistor logic
(RTL) representation.
• The power gating affects inter-block interfaces
and introduces significant time delays in order
to safely enter and exit power-gated modes.
• The most basic form of power-gating control,
and the one with the lowest long-term leakage
power, is an externally switched power supply.
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• off-chip power supply, that is, the supply
provides power only to the CPU
– shut down this power supply and reduce the
leakage in the CPU
• Internal power gating, where internal
switches are used to control power to selected
blocks, is a better solution when the blocks
have to be powered down for shorter periods
of time
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Power Gate issues
• Various issues involved in the design of power-
gated circuits
– Power-gating granularity
– Power-gating topologies
– Switching fabric design
– Isolation strategy
– Retention strategy
– Power-gating controller design
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Power-Gating Granularity
• Fine-grained power gating
• Coarse-grained power gating.
Fine-grained power gating
– The power-gating switch is placed locally as part of the standard cell.
– The switch must be designed to supply the worst case current requirement
of the cell
– Size of the switch is usually large (2 × to 4 × the size of the original cell) and
there is significant area overhead.
– Separate sleep control signals are used to control different building blocks
such as instruction decoder, execution unit, and memory controller
– It is used to reduce run-time leakage power
– timing impact of the current passing through a switch with equivalent
resistance R resulting in IR drop across the switch can be easily characterized
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Coarse-grained power gating
– A larger block, say a processor, or a block of gates is power
switched by a block of switch cells
– Single sleep control signal is used to power down the
entire chip
– It reduces leakage during standby and not affect run-time
leakage
– Timing impact is more difficult because the exact switching
activity of the logic block may not be known at design time
– Lesser area overhead
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Power-Gating Topologies
Categorized into three types
– Global power gating
– Local power gating
– Switch in cell gating
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Global Power Gating
• A multiple switches are
connected to one or
more blocks of logic
• a single virtual ground
is shared in common
among all the power-
gated logic blocks
• Effective for large blocks
(coarse-grained)
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Local power gating
• Logical topology in
which each switch
singularly gates its own
virtual ground
connected to its own
group of logic.
• A multiple segmented
virtual grounds for a
single sleep domain
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Switch in cell gating
• Switch in cell may be
thought of as an extreme
form of local power-gating
Implementation
• Advantages are that delay
calculation is very
straightforward.
• The area overhead is
substantial
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Switching fabric design
• The switching fabric involves many highly
technology specific issues.
• The architectural issue to decide whether to
use only header switch using pMOS transistors
or use only footer switch using nMOS
transistors or use both.
• Designs at 90 nm or smaller than 90 nm, either
the header or footer switch is recommended
due to the tight voltage margin, significant IR
drop and large area, and delay penalties
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Header-versus-footer switch
• High-VtPMOS transistors are
used to realize the header
switch
– External and internal power
gating are used together,
– Header switch is the most
appropriate
– multiple power rails and/or
voltage swings are used on the
chip
• High-VtNMOS transistors are
used to realize footer the
switch
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• The switch efficiency of sleep transistors is defined as
the ratio of drain current in the ON and OFF states
(Ion/Ioff).
• The maximum value of switch efficiency is desirable to
achieve a high current drive in normal operation and
low leakage in sleep condition.
• It has been found that for the same drive current, the
header switch using pMOS transistors results in 2.67
times more leakage current than the footer switches
realize using nMOS transistors.
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Implementation Styles
• Ring styles
– The switches are placed
external to the power-gated
block by encapsulating it by a
ring of switches
– Switches connect VDD to the
virtual VVDD of the power-
gated block.
– This is the only style that can
be used to supply power to
an existing hard block by
placing the switches outside
it
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• Grid styles
– the switches are
distributed throughout
the power-gated region
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Isolation Strategy
• In general outputs and internal nodes may neither discharge to
ground level nor fully charge to supply voltage level, because of
finite leakage currents.
• if the output of power-down block drives a power-up block, there is
possibility of short-circuit power (also known as crowbar power) in
the power-up block.
• It is necessary to ensure that the floating output of the power-down
block does not result in spurious behaviour of the power-up block.
• This can be achieved by using an isolation cell to clamp the output of
power-down block to some well-defined logic level.
• Isolation cells can be categorized into three types:
– cells those clamp the output to ‘0’ logic level,
– cells those clamp to ‘1’ logic level
– cells those clamp the output toProfessor,
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• The output should be clamped is based on the
inactive state of the power-up block.
• In active high logic, the output is clamped to
logic ‘0’ and in case of low-active logic, the
output is clamped to logic ‘1’ level.
• Power-down block is driving a combinational
logic circuit, the output can be clamped to a
particular value that reduces the leakage
current using stack effect
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• The output of a power-gated block is clamped
with the help of an AND gate.
• Isolation cell to clamp the output to ‘0’ logic
level can be accomplished using an AND gate.
• The output is clamped to ‘0’ as long as the
isolation (ISOLN) signal is active
• Isolation cell to clamp the output to ‘1’ logic
level can be accomplished using an OR gate
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• It can be realized using a NOR gate and an
inverter.
• The output is forced to ‘1’ as long as the ISOL
signal is held high.
• An alternative approach is to use pull-up or pull-
down transistors to avoid full gate delay .
• If we want to clamp the output to the last value,
it is necessary to use a latch to hold the last
value.
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State Retention Strategy
• Power gating possible in a block using switching fabric and an
isolation strategy.
• All state information will be lost when the block is powered
down.
• At the power resume condition
– state restored from an external source
– build up its state from the reset condition
• Types of approaches
– A software approach based on reading and writing registers
– A scan-based approach based on the reuse of scan chains to store state
off chip
– A register-based approach that uses retention registers
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Software-Based Approach
• Power down :CPU reads the registers of the power-
gated blocks and stores in the processor’s memory.
• Power up: the CPU writes back the registers from the
memory
• Bus traffic slows down the power-down and power-up
sequence and bus conflicts may make powering down
unviable.
• Software must be written and integrated into the
system’s software for handling power down and
power up
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Scan-Based Approach
• Scan chains used for built-in self-test (BIST)
can be reused.
• During power-down sequence, the scan
register outputs are routed to an on-chip or
off-chip memory.
• It can be significant saving of chip area.
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Retention Registers
• A standard registers are replaced by retention
registers.
• A retention register contains a shadow register
that can preserve the registers state during
power down and restore it at power up.
• High-Vt transistors are used in the slave latch,
the clock buffers, and the inverter that
connects the master latch to the slave latch
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Retention Registers
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Power-Gating Controller
• Controlling the switching fabric is to limit the
in-rush of current when power to the block is
switched on.
• An excessive in-rush current can cause
voltage spikes on the supply, possibly
corrupting registers in the always-on blocks
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Power-gating control without retention
Sequence is followed at the time of switching OFF
• Flush through any bus or external operation in
progress
• Stop the clock at appropriate phase.
• Assert the isolation control signal
• Assert reset to the block
• Assert the power-gating control signal to power
down the block
At the time of switching ON, the same signals are
sent in reverse order as follows:
• De-assert the power-gating control signal
• De-assert reset to the block
• De-assert the isolation control signal to restore
all outputs
• Restart the clocks, without glitches and without
violating minimum pulse width
• design
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Power-gating control with retention
Sequence is followed at the time of switching OFF:
• Flush through any bus or external operation in
progress
• Stop the clock at appropriate phase
• Assert the isolation control signal
• Assert the state retention save condition
• Assert reset to the block
• Assert the power-gating control signal to power
down the block
At the time of switching ON, the same signals are
sent in reverse order as follows:
• De-assert the power-gating control signal to power
back up the block
• De-assert reset to ensure clean initialization
following the gated power-up
• Assert the state retention restore condition
• De-assert the isolation control signal to restore all
outputs
• Restart the clocks, without glitches and without
violating minimum pulse width design constraints
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Power Management
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Adiabatic Logic Circuits
• Adiabatic switching is a circuit-level approach that has made it
possible to realize the ultra-low-power computing applications
without scaling the supply voltage.
• The term ‘adiabatic’ refers to the thermodynamic processes that
exchange no heat with the environment.
• The energy consumption is minimized by slowing down the charge
transport between the drain and source terminals of MOSFET switch
and recovering the energy without dissipating as heat
• A time-varying voltage source ensures the slow charge transport,
keeping small potential across the on-resistance encountered by the
MOSFET switches.
• It slower speed of operation.
• In ultra-low-power applications for which conventional energy is
limited and speed is not critical
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Conventional Charging Adiabatic Charging
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Conventional Circuit
• As the switch is closed at time t = 0, current starts flowing.
Initially, at time t = 0, the capacitor does not have any
charge and therefore the voltage across the capacitor is 0
V and the voltage across the resistor is Vdd
• So, a current of Vdd/R flows through the circuit. As current
flows through the circuit, charge accumulates in the
capacitor and voltage builds up.
• As the time progresses, the voltage across the resistor
decreases with a consequent reduction in current through
the circuit. At any instant of time, V= IR + Q/C, where Q is
the charge stored in the capacitor.
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Adiabatic charging
• A capacitor C is charged through a resistor R
using a constant current I( t) instead of a fixed
voltage Vdd
• It is assumed that initially at time t = 0, there is
no charge in the capacitor. The voltage across
the capacitor Vc (t) is a function of time
Dr.P.Rajasekar, Professor, ECE, NECG- Gudur
66
AP
