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Non-Volatile Magnetic Random Access Memories (MRAM) : R.C. Sousa, I.L. Prejbeanu

This document summarizes magnetic random access memory (MRAM) technology. MRAM uses magnetic tunnel junctions as memory cells that can store data in non-volatile manner with two resistance states. Writing data is done by applying a magnetic field to change the magnetic orientation in the tunnel junction. MRAM promises fast read/write times comparable to volatile memories while being non-volatile like flash. Scaling challenges include reducing the resistance-area product of the tunnel junctions and improving selectivity in the memory cell array.

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0% found this document useful (0 votes)
109 views10 pages

Non-Volatile Magnetic Random Access Memories (MRAM) : R.C. Sousa, I.L. Prejbeanu

This document summarizes magnetic random access memory (MRAM) technology. MRAM uses magnetic tunnel junctions as memory cells that can store data in non-volatile manner with two resistance states. Writing data is done by applying a magnetic field to change the magnetic orientation in the tunnel junction. MRAM promises fast read/write times comparable to volatile memories while being non-volatile like flash. Scaling challenges include reducing the resistance-area product of the tunnel junctions and improving selectivity in the memory cell array.

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Physics

Non-volatile magnetic random access memories (MRAM)


R.C. Sousa, I.L. Prejbeanu
Spintec (URA 2512 CEA/CNRS), 17 rue des Martyrs, 38 054 Grenoble, FRANCE

Received *****; accepted after revision +++++

Abstract

Magnetic random access memories (MRAM) are a new non-volatile memory technology trying establish itself as a
mainstream technology. This paper reviews briefly the most important progress realized in the past 10 years. Basic
MRAM cell operation is described as well as the main subsisting design challenges. Special emphasis is placed on
bit write strategies and their respective scaling perspectives. To cite this article: R.C. Sousa, I.L. Prejbeanu, C.
R. Physique 6 (2005).
Résumé
Mémoires magnétiques non-volatiles à access aleatoire. Les mémoires magnétiques à access aléatoire
(MRAM) sont une nouvelle technologie de mémoires non volatiles cherchant à s’imposer comme technologie
majeure. Cet article fait un resumé des progrès les plus importants realisés au cours des 10 dernières années. Le
mode de fonctionnement des MRAM est décrit ainsi que les défis qui subsistent encore pour leur réalisation. Les
diverses stratégies d’écriture et leurs perspectives en termes de réduction de taille de cellule sont discutées. Pour
citer cet article : R.C. Sousa, I.L. Prejbeanu, C. R. Physique 6 (2005).

Key words: MRAM ; non-volatile ; magnetic tunnel junction ; memory


Mots-clés : MRAM ; jonctions tunnel magnétiques ; mémoire

1. Introduction

Magnetism contributes greatly to the goal of storing information for long time periods (10 years), in the form
of hard disk drive and magnetic tape storage systems. In these two examples data access time is limited by
the fact that these are mechanical systems. Only solid state memories like Dynamic Random Access Memory
(DRAM) and the Static Random Access Memory (SRAM) are capable of ns access times in both read and
write operations. These memories are volatile and data is stored only as long as power is supplied to refresh
the capacitor charge in DRAM and to keep the transistors on in SRAM. The need for a non-volatile memory is
reflected in the increasing demand for Flash memory, fuelled by its use in digital consumer products. However
Flash technology suffers from slow write access time in the µs range and poor bit cyclability limited to 106 write
events. Magnetic random access memories (MRAM) is one technology proposing to close the performance gap

Email addresses: [email protected] (R.C. Sousa), [email protected] (I.L. Prejbeanu).

Preprint submitted to Elsevier Science 12th October 2005


between existing volatile and non-volatile memory technologies. Other alternatives are ferroelectric random access
memories (FeRAM) based on ferroelectric materials and phase change based Ovonyx unified memory (OUM).
The most important characteristics of all these memory types are summarized in Table 1. MRAM devices have
already been demonstrated based on giant magnetoresitive (GMR) elements [1] and more recently using magnetic
tunnel junctions (MTJ) [2,3]. This paper reviews the principles in MTJ based MRAMs and highlights the latest
developments and new approaches being investigated.
Table 1
Comparison of memory technologies
Feature DRAM SRAM (6T) FLASH OUM MRAM FeRAM
Cell size [F 2 ] 8-12 50-80 4-11 5-8 6-20 4-16
Non Volatile No No Yes Yes Yes Yes
Endurance write/read ∞/∞ ∞/∞ 106 /∞ > 1012 /∞ > 1015 /∞ > 1012 /> 1012
Non Destructive Read No Partial Yes Yes Yes No
Direct overwrite Yes Yes No Yes Yes Yes
Signal margin 100-200mV 100-200mV ∆ current 10-100 × R 60-200% R 100-200mV
Write/Read 50ns/50ns 8ns/8ns 200µs/60ns 10ns/20ns 30ns/30ns 80ns/80ns
Erase 50ns 8ns 1-100ms (block) 50ns 30ns 80ns
Transistor performance Low High High voltage (HV) High High High
Scalability limits Capacitor 6 Transistors Tunnel oxide/HV Litho. Current density Capacitor

2. Conventional MRAM operation

The basic MRAM cell element consists of a magnetic tunnel junction structure in which two ferromagnetic
electrodes are separated by a thin insulating barrier. The tunneling current flowing through the structure de-
pends upon the relative orientation of the magnetization in both electrodes. The resistance change between the
low resistance parallel alignment and the high resistance anti-parallel alignment is defined as Tunnel Magneto-
Resistance (TMR). The direction of the reference layer is fixed using an exchange biasing anti-ferromagnetic layer.
Writing a bit consists in setting the magnetization direction of the free storage layer using a magnetic field. The
basic operation in reading one bit cell is to find the resistance state of the tunnel junction, i.e. the magnetization
configuration. The knowledge on spin dependent magnetic tunnel junctions has increased dramatically since in
1995 when the first tunnel magnetoresistance (TMR) signals were measured at room temperature [4]. Since then,
the evolution observed in tunnel junctions has been enormous, with advances made in the field summarized in
some extended reviews [5,6]. Recent breakthroughs in tunnel junction fabrication led to TMR signals close to 70%
in CoFeB/AlOx/CoFeB [7] and over 200% [8,9] in junctions with a MgO tunnel barrier. The higher the TMR
signals, the greater the separation of the low and high resistance values corresponding to the two bit states. The
bit resistance mainly determines the RC time constant and read access time, with typical cell values of 10kΩ
allowing for ns access times [10,11], depending on the lead line capacitance. The characteristic resistance × area
product (R×A)is determined by the tunnel barrier height φ and thickness t. Resistance dispersion around the
central resistance values occurs due to issues in junction patterning, area dimensional control and barrier thickness
non-uniformity induced by electrode roughness. It has been shown that it is possible to keep a maximum TMR
signal over R×A values ranging from 106 − 100Ω × µm2 corresponding to AlOx thickness between 20Å and 9Å[12].
Much investigation is being realized for further decreases below 1Ω × µm2 keeping full TMR to allow the use of
spin polarization to write the bit cell. Bit cell scaling requires also lowering R×A values to keep a constant bit
resistance while shrinking the bit cell below the 90nm node.

2.1. MRAM architectures

Dense MRAM arrays are organized in matrix with bit elements at each line-column intersection. One bit readout
requires a controlled current flow in the matrix in order to correctly address the resistance state of a single element.
One method is to use a semiconductor device, either a diode [13] or a transistor [14], in series with the tunnel
junction to provide the necessary selectivity (fig.1a). The two terminal element of the junction-diode matrix makes

2
it the simplest implementation. However, integration with amorphous Si diodes [15] requires large diode areas to
source the read current and GaAs diodes is not a mainstream semiconductor technology [16]. Attempts to create
a high density cell using a MTJ integrated with a metal/insulator/metal diode showed only poor current densities
(0.2µA/µm2 ) and diode rectification ratios of ≈ 20 [17]. The transistor matrix is the preferred choice because
it provides a higher current saturation for the same cell size. The maximum cell current change (read margin)
is obtained when the current flow in the bit element is limited by the resistance of the tunnel junction and not
by the transistor saturation current. This is achieved when the junction load curve intercepts the transistor I-V
characteristic in the linear region.
Word line field
Magnetization alignment Parallel Antiparallel
Write current Magnetic field Rlow Rhigh Toggle operating
Word line window
R = Rlow x TMR

Frequency [#]
Rref

Bit line field


1 2
Storage layer

Tunnel junction Read margin


R-12 σ

Initial state
Pinned layer

Transistor 3
Bit line
Final
Write current Resistance state

Figure 1. Elementary MRAM cell (left). Distribution of resistance values in tunnel junction array showing the required 12σ read
margin (center). Toggle switching sequence (right).

Another possibility to achieve very high density is to use a matrix design with no semiconductor elements. At
the expense of a more elaborated measuring scheme preventing parasitic current paths it is possible to accurately
measure the resistance of one given tunnel junction in the matrix. One proposed scheme [18] relies on the current
measurement circuitry to create a virtual ground. The virtual ground can be created using a operational amplifier
with a feedback network, and the current flow can be measured using an inverted amplifier topology. Since all
column leads are connected to either the virtual ground or a real ground, the junction voltage drop is set by the
bias applied to one of the matrix lines. Other approaches follow the same spirit of controlling the bias voltage of
the column and row lines to define unique current paths [19]. The drawbacks are an increased access time due to
the time required to establish the necessary voltage levels in the lead lines and a greater design complexity and
surface area of the readout circuitry.

2.2. Reading a bit

To assess the bit state the bit resistance is compared to a reference value mid-way between the bit high (Rhigh )
and low (Rlow ) resistance values. The inevitable resistance dispersion centered on Rhigh and Rlow must be reduced
since it impacts directly on the read margin. Since the tails of the resistance dispersion must not overlap to be
correctly assessed, the available read margin is only ∆R − 12σ, where the resistance change ∆R = Rlow × T M R
and σ is the dispersion standard deviation. The requirement of a 6σ tail reduces the probability of one bit being
outside the ±6σ interval to 1 in 109 . The 12σ margin is necessary to accommodate for process drifts and allow the
fabrication of large memory sizes. The bit resistance is determined reading the current flowing through the tunnel
junction at a fixed voltage. Typical read voltage values are 300mV, close to the voltage V1/2 at which TMR drops
to half its maximum low bias value and where maximum current variation is expected.

2.3. Writing a bit

The most widely adopted method to achieve write selectivity in MRAM relies on the Stoner-Wohlfarth theory
of coherent rotation in single domain particles. Energy minimization can be used to find that the easy axis field He
required to reverse the magnetization is reduced by applying simultaneously a second perpendicular field along the
2/3 2/3 2K 2/3
hard axis Hh . The solution yields an astroid equation, Hh +He = ( M s
) , where K is the effective anisotropy,
accounting for crystalline and shape anisotropies, and Ms the saturation magnetization. Switching occurs for any
combination of fields for which the resulting field vector lyes outside the astroid. This allows the selective switching
of one bit in the matrix by choosing easy and hard axis fields which lie inside the astroid. This approach has been
applied with success to switch individual bits, but dispersion in the switching fields is difficult to control. The

3
reason is that switching fields are mostly determined by shape anisotropy. Small deviations in shape dimensions
and edge roughness have a too large influence in the switching field distribution in large bit arrays. Also, a fully
single domain behavior cannot be warranted for all bits and domain configurations are not always reproducible.
Another issue is the thermal activation of half-selected bits which increases the risk of addressing errors. Finding a
set of fields which can be used to program all cells becomes difficult or unusable due to the very narrow operating
window [20]. Several approaches have been tried to overcome these problems. One was the use of special bit
shapes trying to find reproducible magnetic domain configurations with higher selectivity to the hard axis field,
either by using end shape tapering [21,22] and more recently a ”goggle” shape [23]. Recent works achieved to
reduce vortex formation [24] using a soft adjacent layer of NiFe to provide magnetic flux closure and reduce the
demagnetizing field created by the magnetic charges on the storage layer edges. Another proposed solution is the
use of synthetic ferrimagnet (SF) storage layers, two ferromagnetic layers coupled anti-ferromagnetically by a Ru
spacer, to increase the single domain character [25,26] and reduce sensitivity to shape anisotropy [27].
SF structures have another significant advantage over simple ferromagnetic layers, in that it is possible to
reduce the effective magnetization, Mef f = M1 − M2 , without decreasing the total magnetic volume. This is
beneficial for the thermal stability of the memory element, since the energy barrier, Eb , between the two possible
magnetization configurations of the storage layer is equal to KV (1 − HM 2K
s
). The commonly accepted requirement
for 10 year stability is Eb ≥50kb T [28], with kb T being the thermal energy. Higher margins are required when
taking into account that commercial operating temperature range must be specified up to 70◦ C and that during
write operations half-selected bits are subjected to magnetic fields that reduce the energy barrier Eb . Using SF
layers it is possible to increase the effective magnetic volume without increasing the switching field [29] [30],
however the improvement in thermal stability of non-circular elements is very limited.

2.4. Toggle writing

The toggle approach which was proposed originally by Savtchenko [31], provides a more reproducible magne-
tization reversal process than the Stoner-Wohlfarth astroid. The toggle write sequence is illustrated in Figure 1.
The storage layer is a SF free layer and the current lines generating the field are at 45◦ to the bit easy axis. For an
applied magnetic field higher than the spin-flop field, the SF free layer system minimizes the magnetostatic energy
by a scissoring of the two coupled ferromagnetic electrodes and orienting itself perpendicular to the applied field.
Detailed analytical treatment of the system can be found in recent publications [32,33]. This property is used
in the toggle mode to rotate the SF free layer first perpendicular to bitline field (1), then perpendicular to the
resulting bit and word line field (2), and finally perpendicular to the wordline field (3). When the field is removed
the SF layer will orient itself along the bit easy axis, with the magnetization directions of the two ferromagnetic
layers of the SF structure reversed compared to their initial orientation. The bit writing sequence now requires
the sequential application of the fields created by the current lines with a time overlap of ≈5ns [34]. In toggle
writing it is only possible to reverse the initial SF free layer orientation. Therefore, prior to the write process the
bit state must be read to determine if a change in bit resistance state is required. This drawback is compensated
by the advantage of a single current polarity to create the magnetic field, independently of the bit value being
written. This allows the optimization of the CMOS transistors for current sinking or sourcing.

2.5. Current line cladding

In both toggle or astroid approaches a current flow in electrical leads is used to generate a local magnetic field.
A simple expression for the created field is obtained when the current line can be considered as a sheet of current
(width ≫ thickness), in which case [35] the maximum field value at the center of the line is I/(2w), where I is
the current and w the line width. To decrease power consumption with simple lines it is possible to reduce the
distance to the sensor or the lateral line dimensions. One other method proposed to increase the created field [36]
is using a magnetic ”cladding” layer. The principle is to ’divert’ the field generated on the back side of the current
line, so that it will add to the field on the bit cell side. The field on back of the line aligns the magnetization
of the cladding layer, generating a stray field that adds or subtracts to that of the line depending on the side.
The illustrating schematic is shown in Fig. 2. Cladding is most effective when the sidewalls and bottom of the
current line are covered. The field generated by the cladded line increases by a factor of 2 reaching typical values
of 2-10Oe/mA. It is worth noting that the cladding also acts as a shield against external magnetic fields.

4
3. New approaches in MRAM

As described in the previous section, the first MRAM generation relies on the superposition of two orthogonal
magnetic fields to create the selectivity. The use of the simple Stoner-Wohlfarth astroid as a write selection scheme
has to face poor write margin as well as endurance and reliability issues due to the thermal activation of half-
selected bits. The toggle approach may be suitable for the two next technological nodes, despite the penalty of a
much higher switching energy, but alternative write schemes are necessary beyond the 65nm node to allow for an
appropriate scaling along the ITRS roadmap scheme.

3.1. Thermally assisted MRAM

An alternative write scheme is to assist thermally the switching of the magnetization [37–40]. This approach is
based upon the reduction by heating of the required switching fields. There are many possible designs proposed
in the literature for the MRAM cell, where the heating method or the thermal dependence of the magnetic prop-
erties of the MRAM cell varies: low Curie point design [38], exchange biased storage layer [37,40], perpendicular
ferromagnetic layer [41]. Furthermore, the heating is achieved either by passing the current through the sense
and/or word lines [38,39] or by sending the current directly through the junction [40].
A first design proposed by Daughton and co-workers [38,42] uses a low Curie point ferromagnetic cell with
shape anisotropy. The dot can be relatively thick for thermal stability at low temperatures, and can be written
with relatively small fields as the dot is cooled through the Curie point. The proposed cell configuration has a
heating element, the MRAM bit and an orthogonal digit line that applies a field that determines the state of the
bit. The heating element sits above a thin dielectric layer deposited on the silicon substrate that serves as a heat
sink. The write current raises the temperature of the heating element slightly above the Curie point of the storage
layer. Ferromagnetic magnetization changes very rapidly at temperatures just under the Curie temperature.

Magnetic cladding
Current line field Hm
field Hbias

Effective field
= Hbias - Hm
Current line
+++
||||

Magnetic cladding

Effective field =
Hbias + Hm

Figure 2. Diagram of current line cladding(left-a). Demonstration of thermally assisted writing using 20ns voltage pulse of 2V and
an applied magnetic field of 20Oe (center-b).

In a second design the MTJ stack of the cell is slightly modified: the storage layer comprises a ferromagnetic
layer exchange biased by a low blocking temperature (TB ) antiferromagnetic material [40,43,44]. The cell is heated
directly by flowing a heating current through the junction during the write procedure. The hot electrons injected
through the tunnel barrier relax by emission of phonons and magnons which in turn heat up the storage layer.
When the storage layer temperature exceeds TB , the ferromagnetic layer is freed and can be reversed under the
application of a small magnetic field provided by a single digit line. The magnetic field is maintained beyond the
heating voltage pulse in order to cool the MTJ under magnetic field and ensure a correct pinning of the storage
layer. This write scheme offers many advantages. First, the selectivity is very good as only the selected heated
junctions can be written regardless of the external field amplitude (non heated cells are field imune, due to the
exchange bias). Second, the exchange bias storage layer has an increased intrinsic anisotropy due to exchange
bias which allows (i) dots with a low aspect ratio down to 1:1 which minimizes the switching field and makes
it scaling-independent (ii) thermally stable cells even for small feature sizes and without the need to increase
the thickness of the storage layer. Finally, the exchange biasing of the storage layer guarantees a high protection
against magnetic erasure (the memory can only be erased by the superposition of a high temperature and a
magnetic field). Fig.2b shows the magnetic loops of the storage layer before and after write operation. The loops
are clearly shifted from zero field due to the exchange bias on the storage layer. In zero magnetic field, we have
two distinct states corresponding to the digital information 0 or 1. The write operation was performed using 20ns
heating voltage pulse of 2V and a small external magnetic field of 20Oe. To minimize the required power density

5
while keeping a constant value upon scaling requires to add thermal barriers on each size of the MTJ. These
thermal barriers made from low thermal conductivity material with reasonably low resistivity are very efficient
to decrease the heating power density as they help to confine the generated heat into the MTJ. It is important
to point out that in this scheme, the power density becomes size-independent - an important factor for future
scaling.
In order to prevent magnetization curling at the edges of the cell favoring vortex structures the aspect ratio
should be larger than 2 for in plane magnetization [45] or to align the magnetization perpendicular to plane.
Uniform magnetization distribution can be achieved for rare-earth (RE) and transition metal (TM) compounds
given the low saturation magnetization. Since the coercivity of RE-TM alloys strongly depends on temperature,
MRAM cells composed of RE-TM alloys [41] may possess high coercivity with stable domain structures at room
temperature and meanwhile a small switching field can be achieved by using thermally assisted-writing. The
magnetization of the free layer of the giant magnetoresistance films, composed of RE-TM alloys with perpendicular
magnetization, can be switched at the field of 10Oe by heating the sample above the Curie temperature of the
free layer.
To conclude this paragraph, the thermally assisted approach offers a promising solution for the next generations
of MRAM as it can solve most of the current issues (write selectivity, power consumption, thermal stability) whilst
offering full scalability to 65nm node and beyond. Further work on the dynamics of the magneto-thermal switching
and durability of the materials under temperature and voltage stress will be required however to gain confidence
in this approach.

3.2. Use of precessional switching for ultra-fast MRAMs

To achieve sub-ns write time, several groups have proposed to use precessional switching of magnetization
[46–48]. For such precessional switching, fast rising in plane field pulses orthogonal to the initial direction of the
magnetization are applied - Fig.3a-c. These field pulses initiate a large angle precession which can be used to switch
the magnetization. Stopping the field pulse when the precessing magnetization is oriented near the reversed easy
direction will consequently lead to relaxation towards the reversed direction and thus to magnetization switching.
So far precessional switching of soft magnetic cells has been observed on Co based thin films [49] microscopic
spin valves [50], permalloy platelets [51] and microscopic magnetic tunnel junctions [52]. For the case of MTJ,
reversible switching back and forth of large domains of the free layer magnetization by transverse pulses as
short as 170ps was obtained. The method was in consequence proposed as a way towards efficient, ultrafast,
reliable, and energy cost effective precessional switching of the free layer magnetization in MRAMs. Devolder et
al [53] described analytically the magnetization trajectories of a loss-free thin anisotropic macrospin subjected
to two orthogonal field pulses. Magnetization switching is known to occur if the fields are above the dynamical
astroid, calculated from numerical integration of the Landau-Lifschitz equation. The authors explained that a
robust reversal scenario requires a hard-axis field pulse unipolar, short, and fast rising. Conversely, the easy-axis
field should be bipolar to select the state to be written and it should be of longer duration with no stringent
constraint on its rise and fall times. Their analytical charts are useful to define which sets of field parameters can
make reliable precessional switching in MRAM, where complicated other phenomena (intercell dipolar, coupling,
magnetic parameter dispersion, etc.) can render the purely numerical optimizations extremely cumbersome. The
modest size of the addressing window engenders quite a strong motivation to find technical solutions that minimize
the intercell dipolar coupling in dense MRAM arrays. Maunoury et al [54] implemented direct write and toggle
switching in the precessional limit on micron-sized magnetic tunnel junctions, with a combined pulsed hard-axis
field and a quasistatic easy-axis field. They measured the amplitudes and duration of orthogonal applied magnetic
fields leading to reliable switching for pulse durations as short as 178ps. The authors discussed finally the best field
timing for the largest writing operation window. They compared the size of the writing window in two scenarios of
orthogonal field timing: synchronous pulses or imbricate pulses (easy-axis field lasting longer than hard-axis field)
and found that imbricate pulses lead to sizeable increase of the writing window. All these results on precessional
switching represent certainly a step further to assess the technological potential for ultrafast MRAM applications.

3.3. Current induced magnetic switching MRAM

A novel switching method by spin-polarized current [55,56] has been demonstrated in several recent experiments
[57–59]. It is based on the injection of polarized spin current of high densities through a submicron pillar made

6
of normal metal sandwiched between a thin and a thick ferromagnet and works with no applied magnetic field
- Fig.3d-e. According to most spin transfer models, the thick layer polarizes the spin of the incoming electrons.
The polarized current transfers to the local magnetization of the thin layer the transverse part of the spin angular
momentum. When the current is sufficiently large, the spin transfer torque can counterbalance the damping term
and eventually reverse the thin layer magnetization direction. Applied to MRAMs, the spin induced reversal
mechanism could restore the scalability of the cell size beyond several Gbit/chip. However, even if the proof of
concept has been done, some problems still subsist. In particular, low switching current density and high read signal
are required for the application of the spin induced switching to MRAM. This raises considerable challenges since
the MRAM cells must be able to withstand high current densities (107 A/cm2 ) without exceeding the breakdown
voltage of the barrier. Moreover, the write current determines the size of the write transistor, which sets a limit
on the memory areal density. Therefore, it is beneficial to lower the resistance of the MTJ [60] or to boost the
magnitude of spin torque to enable switching at lower current [61–63]. Among other major concerns are to obtain
a fast switching within a few ns and to understand the associated thermal influences on switching [64,65].

Figure 3. Sketch of the layer scheme in precessional switching experiments (left-a). Optical micrograph of the device (left-b) and
sketch of the magnetic field configuration(left-c). Schematic cross section of the nanopillar (center-d) and micrograph of the Co
nanomagnet (right-e).

Low resistance MTJ’s have been studied for several years primarily in order to replace the current in-plane read
heads for high density magnetic recording [60,66]. As the typical critical current density needed for reversal is
as high as 106 -107 A/cm2 , it was important to develop low RA MTJ with high breakdown voltage and high MR
ratios for current induced switching MRAM applications [67,68].
Based on the spin-momentum transfer model, the critical current at 0K is proportional to Ms V(Hext ± Hani
± Ms/2m0 )/g, where Ms is the saturation magnetization of a magnet cell, V is the volume of the magnetic cell,
g corresponds to the efficiency of spin-transfer switching, Hext is the external applied field, Hani is a uniaxial
anisotropy field, and Ms /2m0 is half of the anisotropy field in the plane. To decrease the critical current density
by more than an order of magnitude, several approaches are possible: decreasing the volume V of the magnetic cell
[69], increasing the efficiency g of the spin transfer switching using a double spin filter structure [70] and reducing
the saturation magnetization Ms by using a CoFeB magnetic layer [71].
Finally, the switching speed scales with |I − IC |ln u0 , where I − IC is the overdrive current and u0 the initial
misalignment between the transported spin polarization and the macrospin to be reversed [65]. However, in
experiments so far u0 was the misalignment of the magnetization of the free layer from its easy axis, mostly
arising from finite temperature fluctuations. Increasing the switching speed can thus be done by increasing either
the current pulse I, which is not desirable or by preparing a more favorable initial condition. A straightforward
strategy is to change u0 by a field pulse transverse to the easy axis, as classically done in magnetic field switching
[72]. However in practical memory architectures, this strategy would require additional addressing lines and
large transistors to provide enough current, which would significantly increase the technological complexity. A
strategy to decrease the current pulse duration needed for a spin-transfer switching event while keeping the
full magnetoresistance ratio and not requiring applying any magnetic field was recently proposed [73]. In this
approach, the pillar was initially precharged with a dc bias current to excite a steady state precession. In this
way, the magnetization is very unlikely to be collinear with the spin of the incoming spins when the write current
pulse is sent. The so-prepared precession increases the efficiency of the pulsed current and significantly accelerates
the reversal for given current amplitude. Equivalently, it reduces the total current needed to reverse in certain

7
duration. This strategy was proven efficient for pulse duration between 200ps and 2ns, with potential usefulness
down to 60ps.

Summary

This paper reviews the present state-of-the-art MRAM technology and its perspective evolution. The working
principle of conventional cross point architecture based on the Stoner-Wohlfarth selection astroid is described
and its main limitations are discussed. New writing procedures proposed recently are presented, including: toggle
writing, thermal assisted switching, precessional and the spin transfer induced switching. The advantages / disad-
vantages of each technology are discussed in terms of thermal stability, selectivity, writing speed and scalability.

Acknowledgements

The authors would like to acknowledge O. Redon, M. Kerekes, B. Dieny, J.P. Nozières and P.P. Freitas for
fruitful discussions, comments and shared data.

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