AccuCell

Introduction to Cell
Characterization
 Overview

ß Objective of Cell Characterization

ß Digital Design Tools that Use Standard Cell Models
ß Input Data Files Required by Digital Design Tools
ß Types of Standard Cell Libraries
ß Input Views of Circuits – Bridging Analog and Digital
ß Cell Library Attributes
ß Cell Library Model Quality
ß Synopsys Liberty Format (.lib)
ß Characterization of Gates
ß Characterization of Sequential Circuits

2
 Summary Slide

ß Objective of Cell Characterization ß Combinational Timing Arcs

ß Digital Design Tools That Use Standard Cell Models ß Sequential Timing Arcs
ß Input Data Files Required by Digital Design Tools (Generated ß Timing Arcs Between Single and Multiple Pins
by AccuCell) ß Three-State Timing Arcs
ß Input Data Files Required by Digital Design Tools (Generated ß Edge-Sensitive Timing Arcs
by Other Tools) ß Preset Arcs
ß Types of Standard Cell Libraries ß Clear Arcs
ß Digital Circuit Representation – Inverter ß Defining Delay Arcs With Lookup Tables
ß Analog Circuit Description - Inverter ß Defining Lookup Table Templates
ß Input Views of Circuits ß Assigning Values to Lookup Tables
Bridging Analog and Digital
ß Timing Constraints
ß Static Timing Analysis Use of Liberty Format
ß Setup and Hold Constraints
ß Cell Library Attributes
ß Non Sequential Setup and Hold Constraints
ß Measurements
ß Recovery Timing Constraints
ß Cell Library Model Quality
ß Removal Timing Constraints
ß Liberty .lib File Structure
ß .lib of State Table Flip Flop
ß Operating Conditions
ß .lib of Type ff D Flip Flop
ß Cell Attributes in .lib File
ß Components of Power Dissipation
ß Datasheet View of AND2
ß Power Modeling
ß Pin Attributes
ß State Dependent Leakage Power
ß Setting Output Load Limits
ß Modeling Internal Power Lookup Tables
ß Delay Modeling Concepts
ß Internal Power Calculations
ß Total Delay Equation
ß Clock Pin Power
ß Slope Delay
ß Output Pin Power
ß Slew Modeling
ß Power Lookup Tables Descriptions 1D, 2D, 3D
ß Intrinsic and Transition Delays
ß Internal Power Table for Cell Output
ß Connect Delay
ß Calculating Switching Power
ß Interconnect Delay
ß Switching Power Calculations
ß 3Timing Arcs
 Objective of Cell Characterization

ß Create a set of high quality models

of a standard cell library that
accurately and efficiently model cell
behavior. This set of models are
used by several different digital
design tools for different purposes.

4
 Digital Design Tools That Use Standard Cell
Models

ß Synthesis Tools
ß Place and Routing Systems
ß High level Design Language (HDL) Simulators (Verilog and
VHDL)
ß Floorplanning Tools
ß Physical Placement tools
ß Static Timing Analysis (STA) tools
ß Power Analysis tools
ß Formal Verification tools
ß Automatic Test Program Generation (ATPG) tools
ß Library Compiler

5
 Input Data Files Required by Digital Design
Tools (Generated by AccuCell)

ß .lib Technology library source files

ß .v Generated Verilog simulation libraries
ß .vhd Generated VHDL simulation libraries
ß atpg.lib ATPG library
ß .tbench Verilog testbench to compare SPICE to Verilog
with same stimulus
ß .html HTML datasheet

6
 Input Data Files Required by Digital Design
Tools (Generated by Other Tools)

ß .db Compiled technology libraries in Synopsys internal

database format
ß Synopsys Milkyway Files - Abstracts or Bounding Boxes
ß Cadence Encounter Files - Abstracts or Bounding Boxes
ß .LEF
ß .DEF
ß GDS

7
 Types of Standard Cell Libraries

ß There are often several cell libraries per semi process that
typically contain 100 to 1,000 cells including:
ß Functions
ß Gates – inverter, AND, NAND, NOR, XOR, AOI, OAI
ß Flops – Flip flops (D, RS, JK), Latches, Scan Flops, Gated Flops
ß I/O Cells – Input pads, Output pads, Bidirectional Pads, Complex
ß Process Options
ß Mask layer options, gate shrinks, # of metals, special diffusions, thick
metal, multiple oxides
ß Cell Options
ß Drive strengths, sets, resets, scans, substrate ties, antenna diodes
ß Optimized for Addressing Tradeoffs Between
ß High speed, high density, low power, low leakage, low voltage, low
noise
ß Cell Libraries are Produced by Foundries, IP Vendors,
Fabless and IDMs
8
 Digital Circuit Representation – Inverter

Inverter
IEEE-1164 Verilog Logic States
Strength State Value
U Uninitialized
Driven X Unknown
Driven 0 Low
Driven 1 High
Z High impedance
Resistive W Weak X
Resistive L Weak 0 Rise/Fall
Resistive H Weak 1 Diagram
-- Don’t care

Verilog Language Description of Inverter

not i1 (out, in); // basic inverter
not #(5,3)i1 (out, in); // Rise=5ns, Fall=3ns

9
 Analog Circuit Description - Inverter

Schematic Netlist

*svc_inv.sch
M3 y a gnd gnd nmos L=0.35u W=4.0u
M2 y a vdd vdd pmos L=0.35u W=4.0u
.END

Transistor Inverter Schematic Schematic Netlist with Parasitics

*svc_inv.sch
M3 y a gnd gnd nmos L=0.35u W=4.0u
M2 y a vdd vdd pmos L=0.35u W=4.0u
C1 …..
C2 …..
C3 …..
.END

10
Input Views of Circuits
Bridging Analog and Digital

ß Timing back annotation

for Verilog simulator
(gate, behavioral) Model
must work in Verilog-XL,
VCS, NCsim, Modelsim,
SILOS
ß Methodology has
limitations on accuracy
(load based only)
ß STA is preferred
methodology

11
 Static Timing Analysis Use of Liberty Format

ß In a standalone flow, STA operates independently of

characterization reading both a Verilog netlist and multiple
timing libraries in Liberty format. It can also read
interconnect parasitic data in SPF or SDF formats.

12
 Cell Library Attributes

pin (A) {
ß Pin Types direction : output ;
ß direction function : "X + Y" ;
ß function }
ß Loads lu_table_template(wire_delay_table_template) {
ß Capacitive variable_1 : fanout_number;
variable_2 : fanout_pin_capacitance;
ß Active variable_3 : driver_slew;
index_1 ("1.0 , 3.0");
ß Fanout and wire loads index_2 ("0.12, 4.24");
ß Stimulus }
index_3 ("0.1, 2.7, 3.12");

ß PWL for slope lu_table_template(trans_template) {

variable_1 : total_output_net_capacitance;
ß Active drivers index_1 ("0.0, 1.5, 2.0, 2.5");

ß Indexes }
wire_load("05x05") {
ß Load resistance : 0 ;
capacitance : 1 ;
ß Input slope area : 0 ;
slope : 0.186 ;
fanout_length(1,0.39) ;
interconnect_delay(wire_delay_table_template)
values("0.00,0.21,0.3", "0.11,0.23,0.41", \
"0.00,0.44,0.57", "0.10 0.3, 0.41");
}

13
 Measurements

ß Capacitance
ß Thresholds/switching points
ß Rise Time
ß Fall Time
ß Delay (propagation + transition = cell) (i.e. timing arcs)
ß Power ( static state dependent leakage, dynamic, short-
circuit, hidden, internal ) (i.e. power arcs)

14
 Cell Library Model Quality

ß Accuracy to silicon over the required power supply voltage,

load range, input signal slope range
ß Completeness of characterization (state, types[rise/fall],
indexes, pins ) – all timing arcs are included
ß Conformance with digital tool format requirements (syntax,
units, thresholds)
ß Conformance with digital tool value constraints
(monotonicity) and multi-tool timing engine correlation
ß Model Efficiency - speed of execution of model in digital tool
that runs many times on large circuits using generated
models
ß Characterization time efficiency – runs once but
characterizing a single flop can take hours
ß Minimum size of model file - .lib files can become huge,
especially with noise data
15
Synopsys Liberty .lib File Structure

ß Structural information
ß Describes each cell’s connectivity to
the outside world, including cell,
bus, and pin descriptions.
ß Functional information
ß Describes the logical function of
every output pin of every cell so that
the digital design tools can map the
logic of a design to the actual
technology.
ß Timing information
ß Describes the parameters for pin-to-
pin timing relationships and delay
calculation for each cell in the
library.
ß Environmental information
ß Describes the manufacturing
process, operating temperature,
supply voltage variations, and
design layout, all of which directly
affect the efficiency of every design.
16
 Liberty .lib File Library Level Attributes

library (name) {
technology (name) ;/* library-level attributes */
delay_model : generic_cmos | table_lookup |
cmos2 | piecewise_cmos | dcm |
polynomial ;
Default Units
bus_naming_style : string ;
routing_layers(string);
time_unit : unit ;
voltage_unit : unit ;
current_unit : unit ;
pulling_resistance_unit : unit ;
capacitive_load_unit(value,unit);
leakage_power_unit : unit ;

Defines units for entire library

17
Operating Conditions

ß name
ß The name (WCCOM in the example)
identifies the set of operating
conditions.
ß process
ß The scaling factor accounts for
variations in the outcome of the actual
semiconductor manufacturing steps.
This factor is typically 1.0 for normal
operating conditions.
ß temperature
ß The ambient temperature in which the
design is to operate.
ß voltage
ß The operating voltage of the design
ß tree_type
ß The definition for the environment
interconnect model.
ß power_rail
ß The voltage value for a power supply.

18
 Cell Attributes in .lib File

ß Structure
ß The cell, bus, and pin structure that describes each cell’s connection to
the outside world.
ß Function
ß The logical function of every output pin of each cell that digital design
tools use to map the logic of a design to the actual technology.
ß Timing
ß Timing analysis and design optimization information, such as the
parameters for pin-to-pin timing relationships, delay calculations, and
timing constraints for sequential cells.
ß Power
ß Modeling for state-dependent and path-dependent power
ß Other parameters
ß These parameters describe area and design rules.

19
Datasheet View of AND2

ß Correlation between datasheet

and .lib representation of a 2
input AND gate

20
 Pin Attributes

ß direction
ß Defines the direction of each pin. In the example on the previous page, A and B are
defined as input pins and Z as an output pin.
ß capacitance
ß Defines the input pin load (input capacitance) placed on the network. Load units
should be consistent with other capacitance specifications throughout the library.
Typical units of measure for capacitance are picofarads and standardized loads.
ß function
ß Defines the logic function of an output pin in terms of the cell’s input or inout pins. In
the example, the function of pin Z is defined as the logical AND of pins A and B.
ß timing
ß Describes timing groups. The timing groups describe the following:
ß - A pin-to-pin delay
ß - A timing constraint such as setup and hold
ß In the example, the timing group for pin Z describes the delays between pin Z and
pins A and B.

21
 Setting Output Load Limits

ß fanout_load
ß Specifies how much to add to the fanout on the net.
ß max_fanout
ß Specifies the maximum number of loads a pin can drive.
ß max_transition
ß Specifies the maximum rise or fall transition time on an output due to total
capacitive load.
ß max_capacitance
ß Specifies the maximum total capacitive load that an output pin can drive.
ß min_fanout
ß Specifies the minimum number of loads that a pin can drive.
ß min_capacitance
ß Specifies the minimum total capacitive load that an output pin can drive.

22
 Delay Modeling Concepts

ß Total Delay Equation

ß Total Delay Scaling
ß Slope Delay
ß Intrinsic Delay
ß Transition Delay
ß Connect Delay
ß Interconnect Delay
ß Delay Calculation Example

23
Total Delay Equation

ß Dtotal = DI + DS + DC + DT
ß DI
ß Intrinsic delay inherent in the
gate and independent of
ß particular instantiation.
ß DS
ß Slope delay caused by the
ramp time of the input signal.
ß DC
ß Connect media delay to an
input pin (wire delay).
ß DT
ß Transition delay caused by
loading of the output pin.

24
 Total Delay Scaling

ß When calculating total delay, the digital tool scales each

parameter of Dtotal individually.
ß Each component of the total delay has its own global
parameters to model the effects on the nominal case of
variations in process, temperature, and voltage.

*Total Delay is typically measured

from 50% to 50%, regardless
of where transition thresholds are set

25
 Slope Delay

ß The slope delay of an element (DS) is the incremental time delay caused by slowly
changing input signals. This is not used by AccuCell.
ß In some technologies, this delay is a strong function of the ramp time.
ß D is calculated with the transition delay at the previous output pin, plus a slope
sensitivity factor, as shown here:

ß This equation calculates both the rise and fall delays. Where applicable, use
the “rise” parameter to calculate the rise delay and the “fall” parameter to
calculate the fall delay.
ß DS
ß Transition delay is calculated at the previous stage of logic. Therefore, the
calculation of DS enforces a global order on local analysis.
ß SS
ß Slope sensitivity factor. This factor accounts for the time during which the input
voltage begins to rise but has not reached the threshold level at which channel
conduction begins. The attributes that define it in the timing group of the
driving pin are slope_rise and slope_fall.
ß DT(prevstage)
ß The transition delay calculated at the previous output pin.
26
Slew Modeling

ß Slew is the time it takes for the

voltage value to fall or rise
between two designated
threshold points on an input,
an output, or a bidirectional
port.
ß The designated threshold
points must fall within a
voltage falling from 1 to 0 or
rising from 0 to 1.

27
 Intrinsic and Transition Delays

ß Intrinsic Delay
ß The intrinsic delay of a circuit element (DI) is the portion of the
total delay that is independent of the circuit element’s usage. This
portion is the fixed (or zero load) delay from the input pin to the
output pin of a circuit element.
ß Transition Delay
ß The transition delay of a circuit element is the time it takes the
driving pin to change state. The transition time of the output pin
on a net is a function of the capacitance of all pins on the net and
the capacitance of the interconnect network that ties the pins
together.
ß This equation calculates the rise and fall delays.

28
Connect Delay

ß The connect delay of an

element (DC) is the time
it takes the voltage at
an input pin to charge
after the driving output
pin has made a
transition.
ß This delay is also
known as time-of-flight
delay, which is the time
it takes a waveform to
travel along a wire.

29
Interconnect Delay

ß Interconnect delay is
defined as the delay
caused by connect delay
and fanout. It is calculated
as the sum of DT and DC.
ß Include the capacitance
attribute in the pin group of
the input pin.
ß Give zero capacitance to
the pin group of the output
pin.
ß Resistance is attributed
entirely to the output pin.

30
 Timing Arcs

ß Timing arcs can be delay arcs or constraint arcs.

ß Each timing arc has a startpoint and an endpoint.
ß The startpoint can be an input, output, or inout pin.
ß The endpoint is always an output pin or an inout pin.
ß The only exception is a constraint timing arc, such as a setup,
hold, recovery or removal constraint between two input pins.
ß related_pin
ß This attribute defines the pin or pins representing the startpoint of a timing
arc.
ß All delay information in a library refers to an input-to-output pin
pair or an output-to-output pin pair defined as:
ß intrinsic delay
ß The fixed delay from input to output pins.
ß transition delay
ß The time it takes the driving pin to change state. Transition delay attributes
represent the resistance encountered in making logic transitions.
ß slope sensitivity
ß The incremental time delay due to slow change of input signals.
31
 Combinational Timing Arcs

ß A combinational timing arc describes the timing

characteristics of a combinational element. The timing arc is
attached to an output pin, and the related pin is either an
input or an output. AccuCell does not use these.
ß A combinational timing arc is of one of the following types:
ß combinational AND Gate With Timing Arc
ß combinational_rise
ß combinational_fall
ß three_state_disable
ß three_state_disable_rise
XOR Gate With State-Dependent Timing Arc
ß three_state_disable_fall
ß three_state_enable
ß three_state_enable_rise
ß three_state_enable_fall
32
 Sequential Timing Arcs

ß A sequential timing arc is of one of the following types:

ß Edge-sensitive (rising_edge or falling_edge)
ß Preset or clear
ß Setup or hold (setup_rising, setup_falling, hold_rising, or
hold_falling)
ß Nonsequential setup or hold (non_seq_setup_rising,
non_seq_setup_falling, non_seq_hold_rising,
non_seq_hold_falling)
ß • Recovery or removal (recovery_rising, recovery_falling,
removal_rising, or removal_falling)
ß • No change (nochange_high_high, nochange_high_low,
nochange_low_high, nochange_low_low)

33
 Timing Arcs Between Single and Multiple Pins

Pin and a Single Related Pin Pin and Multiple Related Pins

*Timing Arcs can also be between pins, groups, and busses

34
 Three-State Timing Arcs

ß Assign related_pin to the enable pin of the three-state

function.
ß Define the Z-to-1 propagation time with the intrinsic_rise
statement.
ß Define the Z-to-0 propagation time with the intrinsic_fall
statement.
ß Include the timing_type : three_state_enable statement.

35
 Edge-Sensitive Timing Arcs

ß Edge-sensitive timing arcs, such as the arc from the clock

on a flipflop, are identified by the following values of the
timing_type attribute in the timing group.
ß rising_edge
ß Identifies a timing arc whose output pin is sensitive to a rising
signal at the input pin.
ß falling_edge
ß Identifies a timing arc whose output pin is sensitive to a falling
signal at the input pin.
ß These arcs are path-traced; the path tracer propagates only
the active edge (rise or fall) path values along the timing
arc.

36
 Preset Arcs

ß Select
ß timing_type : preset;
ß timing_sense :
ß positive_unate
ß Indicates that the rise arrival time of the arc’s source pin is used to
calculate the arc’s delay. This calculation produces the rise arrival time on
the arc’s endpoint pin. In the case of slope delays, the source pin’s rise
transition time is added to the arc’s delay. The source pin is active-high.
ß negative_unate
ß Indicates that the fall arrival time of the arc’s source pin is used to
calculate the arc’s delay. This calculation produces the rise arrival time on
the arc’s endpoint pin. In the case of slope delays, the source pin’s fall
transition time is added to the arc’s delay. The source pin is active-low.
ß non_unate
ß Indicates that the maximum of the rise and fall arrival times of the arc’s
source pin is used to calculate the arc’s delay. This calculation produces
the maximum arrival time on the arc’s endpoint pin. In the case of slope
delays, the maximum of the source pin’s rise and fall transition times is
added to the arc’s delay.
37
 Clear Arcs

ß Clear arcs affect only the fall arrival time of the arc’s endpoint pin. A clear
arc means that you are asserting a logic 0 on the output pin when the
designated related_pin is asserted.
ß Select
ß timing_type : clear;
ß timing_sense :
ß positive_unate
ß Indicates that the fall arrival time of the arc’s source pin is used to calculate the
arc’s delay. This calculation produces the fall arrival time on the arc’s endpoint pin.
In the case of slope delays, the source pin’s fall transition time is added to the arc’s
delay. The source pin is active-low.
ß negative_unate
ß Indicates that the rise arrival time of the arc’s source pin is used to calculate the
arc’s delay. This calculation produces the fall arrival time on the arc’s endpoint pin.
In the case of slope delays, the source pin’s rise transition time is added to the arc’s
delay. The source pin is active-high.
ß non_unate
ß Indicates that the maximum of the rise and fall arrival times of the arc’s source pin
is used in calculating the arc’s delay. This calculation produces the maximum fall
arrival time on the arc’s endpoint pin. In the case of slope delays, the maximum of
the source pin’s rise and fall transition times is added to the arc’s delay.
38
 Defining Delay Arcs With Lookup Tables

ß Transition time is the time it takes for an output signal to

make a transition between the high and low logic states.
With nonlinear delay models, it is computed by table lookup
and interpolation. Transition delay is a function of
capacitance at the output pin and input transition time.
ß Group attributes:
ß cell_rise To specify cell delay independently of transition delay,
use one of these timing group attributes as your lookup table:
ß cell_fall
ß rise_propagation To specify transition delay as a term in the total cell delay,
use one of these timing group attributes as your lookup table
ß fall_propagation
ß retaining_rise
ß retaining_fall
ß retain_rise_slew
ß retain_fall_slew
39
Defining Lookup Table Templates

ß CMOS Nonlinear Delay Model is

specified by a one or two
dimensional table of delay
values dependent on input net
transition and output
capacitance

40
Assigning Values to Lookup Tables

ß Referring to tables
defined in previous
slide
ß Pin a is two
dimensional 4X4
ß Pin b is one
dimensional X4
ß These timing values
are the results of
SmartSpice
.MEASURE
statements within
AccuCell

41
 Timing Constraints

ß setup and hold arcs

ß Set these constraints to ensure that a data signal has stabilized,
before latching its value.
ß recovery and removal arcs
ß Use the recovery timing arc and the removal timing arc for
asynchronous control pins such as clear and preset.
ß skew
ß This is another constraint that the VHDL library generator uses for
simulation.
ß You can also set state-dependent and conditional
constraints.

42
Setup and Hold Constraints

Setup and Hold Constraints for Rising-Edge-Triggered Flip-Flop

Setup and Hold Constraints for High-Enable Latch

43
 Non Sequential Setup and Hold Constraints

ß In some nonsequential cells,

the setup and hold timing
constraints are specified on
the data pin with a nonclock
pin as the related pin.
ß The signal of a pin must be
stable for a specified period of
time before and after another
pin of the same cell range
Nonsequential Setup and Hold Constraints state for the cell to function as
expected.

44
Recovery Timing Constraints

Recovery Timing Constraint for a Rising-Edge-Triggered Flip-Flop

Recovery Timing Constraint for a Low-Enable Latch

45
 Removal Timing Constraints

Timing Diagram for Removal Constraint ß Removal Constraint

ß This constraint is also known as the
asynchronous control signal hold
time.
ß The removal constraint describes
the minimum allowable time
between the active edge of the clock
pin while the asynchronous pin is
active and the inactive edge of the
same asynchronous control pin
No-Change Timing Check ß No-Change Timing Constraints
ß You can model no-change timing
checks to use in static timing
verification during synthesis.
ß A no-change timing check checks a
constrained signal against a level-
sensitive related signal.
ß The constrained signal must remain
stable during an established setup
period, for the width of the related
pulse, and during an established
hold period.
46
.lib of State Table Flip Flop

47
.lib of Type ff D Flip Flop

ß The ff group statement

replaces the statetable group
statement
ß The function attribute, rather
than the internal_node
attribute, defines the output
pin’s function
ß The D flip-flop defines two
variables, IQ and IQN
ß The next_state equation
determines the value of IQ
after the next clocked_on
transition.
ß In this example IQ is assigned
the value of the D input.
48
Components of Power Dissipation

49
 Power Modeling

ß Leakage Power
ß Leakage power is the static (or quiescent) power dissipated when a gate
is not switching.
ß Short-Circuit Power
ß Short-circuit or internal power is the power dissipated whenever a pin
makes a transition. This can be handled in two ways:
ß Include the effect of the output capacitance in the internal_power group
(defined in a pin group within a cell group), which gives the output pins zero
capacitance
ß Give the output pins a real capacitance, which causes them to be included in
the switching power, and model only the short-circuit power as the cell’s
internal power (in the internal_power group)
ß Switching Power
ß Switching (or interconnect) power is the power dissipated in the circuit as
a result of a logical transition of the capacitive load. Switching power
(along with internal power) is used to compute the design’s total dynamic
power dissipation.

50
State Dependent Leakage Power

ß Leakage power is
state dependent
based on input pin
state values

51
 Modeling Internal Power Lookup Tables

ß You should measure the energy dissipated by varying either input voltage
transition or output load while holding the other constant.
ß Because a table indexed by T input transition times and C output load
capacitances has TxC entries, the cell’s internal power must be
characterized TxC times, once for each input transition time and output
load capacitance combination.
ß For example, if internal power will be modeled by use of a 3x3 table at the
output of the cell, the design will have 9 input voltage transitions—output
load combinations where energy dissipation must be measured.
ß The library group supports a one-, two-, or three-dimensional internal
power lookup table indexed by the total output load capacitances (best
model), the input transition time, or both.
ß NOTE: The input pin power is added to the output pin
power. When you model the library, avoid double counting.

52
Modeling Internal Power Lookup Tables

Power is calculated by integrating energy

53
 Internal Power Calculations

ß To calculate the internal power for cell U1, use the following
equation:

ß PInt
ß Total internal power for the cell.
ß E
ß Internal energy for the pin.
ß AF
ß Activity factor.
ß Accurate sequential modeling requires a separate table for
the clock and for the output pin the clock controls. The two
tables are used to ensure that clock pin power and output
power are accounted for separately, because a clock pin
often toggles without causing any observable state change
on the output pin.
54
 Clock Pin Power

ß This energy is characterized by simulation of a single full

cycle (one rise transition and one fall transition) of the clock,
with no transition at the output and input pins. A one-
dimensional internal power table indexed by input transition
time should be attached to the clock pin. Total energy
dissipated in the cell during this simulation is measured. If
separate rise and fall power modeling is not used, the
energy measured must be divided by 2 to get the energy
dissipated by the clock pin transition, because the
measurement is done for two transitions of the clock.
ß Clk_Pin_Energy = Clk_Total / 2
ß Add Clk_Pin_Energy as an entry indexed by input transition
time in the one-dimensional internal power table attached to
the clock pin.
55
 Output Pin Power

ß This power is characterized by simulation of two full cycles

of the clock, with two rise and fall transitions at the output. A
twodimensional internal power table should be attached to
the output pin. Total energy dissipated in the cell during the
two-full-cycle simulation (Out_total) is measured. If separate
rise and fall power modeling is not used, the energy
measured must be divided by 2, because the measurement
is done for two transitions.

ß Output_Pin_Energy = (Out_total)/2 - 2*(Clk_Pin_Energy)

56
Power Lookup Tables Descriptions 1D, 2D, 3D

ß The example at left shows

shows four
power_lut_template groups
that have one-, two-, or
three-dimensional
templates.
ß The index values are lists
of floating-point numbers
greater than or equal to 0.0.
ß The values in the list must
be in increasing order.
ß The number of floating-
point numbers in the
indexes determines the
size of each dimension
57
Internal Power Table for Cell Output

58
 Calculating Switching Power

ß Switching (or interconnect) power is the power dissipated in the circuit as

a result of a logical transition of the capacitive load
ß With internal power, switching power is used to compute the design’s
total dynamic power dissipation.
ß Switching power information is a function of a net’s capacitive loading,
associated clock frequency, and the supply voltage level of the design.
ß An explicit units attribute is not required for switching power, because the
units are implicitly determined by the units of the voltage, time, and
capacitance attributes.

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 Switching Power Calculations

ß For a single net with a total load of 100 femtofarad, a toggle

rate of two transitions every 100 ns, and a supply voltage of
5 volts, the calculation of the net’s power dissipation is:

ß TR
ß Toggle rate (number of toggles per unit of time).
ß CLoad
ß Capacitive load of each net.

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 Syllabus for Advanced Cell Characterization

ß Review of Introduction to Cell Characterization

ß Latches
ß Scan Flop
ß Gated Clocks
ß Definition of I/O cell terms
ß Example of I/O Cell
ß Active Loads
ß Active Drivers
ß Derating factors, K factors
ß Verilog Timing Checks
ß Noise Considerations (CCS, ECSM)

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