HEF4093B

Quad 2-input NAND Schmitt trigger

Rev. 04 — 12 June 2008 Product data sheet

1. General description
The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.
The gate switches at different points for positive-going and negative-going signals. The
difference between the positive voltage (VT+) and the negative voltage (VT−) is defined as
hysteresis voltage (VH).

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. The
HEF4093B is suitable for use over both the industrial (−40 °C to +85 °C) and automotive
(−40 °C to +125 °C) temperature ranges.

2. Features
n Schmitt trigger input discrimination
n Fully static operation
n 5 V, 10 V, and 15 V parametric ratings
n Standardized symmetrical output characteristics
n Operates across the automotive temperature range from −40 °C to +125 °C
n Complies with JEDEC standard JESD 13-B
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V

3. Applications
n Wave and pulse shapers
n Astable multivibrators
n Monostable multivibrators

4. Ordering information
Table 1. Ordering information
All types operate from −40 °C to +125 °C.
Type number Package
Name Description Version
HEF4093BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
HEF4093BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

5. Functional diagram

1
1A
3
1Y
2
1B

5
2A
4
2Y
6
2B

8
3A
10
3Y
9
3B

12
4A
11
4Y nA
13
4B nY
nB
001aag104 001aag105

Fig 1. Functional diagram Fig 2. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

1A 1 14 VDD

1B 2 13 4B

1Y 3 12 4A

2Y 4 HEF4093B 11 4Y

2A 5 10 3Y

2B 6 9 3B

VSS 7 8 3A

001aag106

Fig 3. Pin configuration

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 5, 8, 12 input
1B to 4B 2, 6, 9, 13 input

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 2 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

Table 2. Pin description …continued

Symbol Pin Description
1Y to 4Y 3, 4, 10, 11 output
VDD 14 supply voltage
VSS 7 ground (0 V)

7. Functional description
Table 3. Function table[1]
Input Output
nA nB nY
L L H
L H H
H L H
H H L

[1] H = HIGH voltage level; L = LOW voltage level.

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +18 V
IIK input clamping current VI < 0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage −0.5 VDD + 0.5 V
IOK output clamping current VO < 0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current - 50 mA
Tstg storage temperature −65 +150 °C
Tamb ambient temperature −40 +125 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C
DIP14 [1] - 750 mW
SO14 [2] - 500 mW
P power dissipation per output - 100 mW

[1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K.
[2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 3 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

9. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 3 15 V
VI input voltage 0 VDD V
Tamb ambient temperature in free air −40 +125 °C
∆t/∆V input transition rise and fall rate VDD = 5 V - 3.75 ns/V
VDD = 10 V - 0.5 ns/V
VDD = 15 V - 0.08 ns/V

10. Static characteristics

Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min Max Min Max Min Max Min Max
VIH HIGH-level |IO| < 1 µA 5V 3.5 - 3.5 - 3.5 - 3.5 - V
input voltage 10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level |IO| < 1 µA 5V - 1.5 - 1.5 - 1.5 - 1.5 V
input voltage 10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level |IO| < 1 µA 5V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage 10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level |IO| < 1 µA 5V - 0.05 - 0.05 - 0.05 - 0.05 V
output voltage 10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - −1.1 - mA
output current VO = 4.6 V 5V −0.64 - −0.5 - −0.36 - −0.36 - mA
VO = 9.5 V 10 V −1.6 - −1.3 - −0.9 - −0.9 - mA
VO = 13.5 V 15 V −4.2 - −3.4 - −2.4 - −2.4 - mA
IOL LOW-level VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
II input leakage 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 µA
current
IDD supply current all valid input 5V - 0.25 - 0.25 - 7.5 - 7.5 µA
combinations; 10 V - 0.5 - 0.5 - 15.0 - 15.0 µA
IO = 0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 µA
CI input - - - 7.5 - - - - pF
capacitance

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 4 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

11. Dynamic characteristics

Table 7. Dynamic characteristics
Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW nA or nB to nY 5V 63 + 0.55 × CL - 90 185 ns
propagation delay 10 V 29 + 0.23 × CL - 40 80 ns
15 V 22 + 0.16 × CL - 30 60 ns
tPLH LOW to HIGH nA or nB to nY 5V 58 + 0.55 × CL - 85 170 ns
propagation delay 10 V 29 + 0.23 × CL - 40 80 ns
15 V 22 + 0.16 × CL - 30 60 ns
tTHL HIGH to LOW output nY to LOW 5V 10 + 1.0 × CL - 60 120 ns
transition time 10 V 9 + 0.42 × CL - 30 60 ns
15 V 6 + 0.28 × CL - 20 40 ns
tTLH LOW to HIGH output nA or nB to 5V 10 + 1.00 × CL - 60 120 ns
transition time HIGH 10 V 9 + 0.42 × CL - 30 60 ns
15 V 6 + 0.28 × CL - 20 40 ns

[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula where:
PD dynamic power 5V PD = 1300 × fi + Σ(fo × CL) × VDD2 (µW) fi = input frequency in MHz;
dissipation 10 V PD = 6400 × fi + Σ(fo × CL) × VDD2 (µW) fo = output frequency in MHz;
15 V PD = 18700 × fi + Σ(fo × CL) × VDD (µW) 2 CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 5 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

12. Waveforms

tr tf
VI
90 %
nA, nB input VM
10 %
0V

t PHL t PLH

VOH
90 %
nY output VM
10 %
VOL
t THL t TLH
001aag197

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
tr, tf = input rise and fall times.
Fig 4. Propagation delay and output transition time

Table 9. Measurement points

Supply voltage Input Output
VDD VM VM
5 V to 15 V 0.5VDD 0.5VDD

VDD

VI VO
G DUT

RT CL

001aag182

Test data given in Table 10.

Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5. Test circuit

Table 10. Test data

Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 6 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

13. Transfer characteristics

Table 11. Transfer characteristics
VSS = 0 V; Tamb = 25 °C; see Figure 6 and Figure 7.
Symbol Parameter Conditions VDD Min Typ Max Unit
VT+ positive-going threshold voltage 5V 1.9 2.9 3.5 V
10 V 3.6 5.2 7 V
15 V 4.7 7.3 11 V
VT− negative-going threshold voltage 5V 1.5 2.2 3.1 V
10 V 3 4.2 6.4 V
15 V 4 6.0 10.3 V
VH hysteresis voltage 5V 0.4 0.7 - V
10 V 0.6 1.0 - V
15 V 0.7 1.3 - V

VO
VT+
VI VH
VT−

VI VO
VH
VT− VT+ 001aag107 001aag108

Fig 6. Transfer characteristic Fig 7. Waveforms showing definition of VT+ and VT−
(between limits at 30 % and 70 %) and VH

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 7 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

001aag109 001aag110
200 1000

IDD IDD
(µA) (µA)

100 500

0 0
0 2.5 5 0 5 10
VI (V) VI (V)

a. VDD = 5 V; Tamb = 25 °C b. VDD = 10 V; Tamb = 25 °C

001aag111
2000

IDD
(µA)

1000

0
0 10 20
VI (V)

c. VDD = 15 V; Tamb = 25 °C
Fig 8. Typical drain current as a function of input

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 8 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

001aag112
10

VI
(V)

VT+

VT−
5

0
2.5 5 7.5 10 12.5 15 17.5
VDD (V)

Tamb = 25 °C.
Fig 9. Typical switching levels as a function of supply voltage

14. Application information

Some examples of applications for the HEF4093B are:

• Wave and pulse shapers

• Astable multivibrators
• Monostable multivibrators

Cp

VDD VDD
14 14
1 R 1
3 3
2 2
VDD VDD

7 C 7

001aag113 001aag114

Fig 10. Astable multivibrator Fig 11. Schmitt trigger driven via a
high-impedance input

If a Schmitt trigger is driven via a high-impedance (R > 1 kΩ), then it is necessary to

C V DD – V SS
incorporate a capacitor C with a value of ------- > -------------------------
- ; otherwise oscillation can occur
CP VH
on the edges of a pulse.

Cp is the external parasitic capacitance between inputs and output; the value depends on
the circuit board layout.

Remark: The two inputs may be connected together, but this will result in a larger
through-current at the moment of switching.
HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 9 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

15. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

D ME
seating plane

A2 A

L A1

c
Z e w M
b1
(e 1)
b
14 8 MH

pin 1 index
E

1 7

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 2.2
1.13 0.38 0.23 18.55 6.20 3.05 7.80 8.3
0.068 0.021 0.014 0.77 0.26 0.14 0.32 0.39
inches 0.17 0.02 0.13 0.1 0.3 0.01 0.087
0.044 0.015 0.009 0.73 0.24 0.12 0.31 0.33

Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT27-1 050G04 MO-001 SC-501-14
03-02-13

Fig 12. Package outline SOT27-1 (DIP14)

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 10 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

y HE v M A

14 8

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
o
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT108-1 076E06 MS-012
03-02-19

Fig 13. Package outline SOT108-1 (SO14)

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 11 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

16. Abbreviations
Table 12. Abbreviations
Acronym Description
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

17. Revision history

Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4093B_4 20080612 Product data sheet - HEF4093B_CNV_3
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Temperature range maximum increased from 85 °C to 125 °C throughout the data sheet.
• Section 4 “Ordering information” and Section 15 “Package outline” package SOT73
removed.
• Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the
HE4000B Family Specifications data sheet.
• Section 10 “Static characteristics” IOH, IOL, II and IDD values updated.
• Section 11 “Dynamic characteristics” typical temperature coefficient for propagation delays
and output transitions removed.
• Section 16 “Abbreviations” added.
HEF4093B_CNV_3 19950101 Product specification HEF4093B_CNV_2
HEF4093B_CNV_2 19950101 Product specification -

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 12 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

18. Legal information

18.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no
use of such information. representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended Limiting values — Stress above one or more limiting values (as defined in
for quick reference only and should not be relied upon to contain detailed and the Absolute Maximum Ratings System of IEC 60134) may cause permanent
full information. For detailed and full information see the relevant full data damage to the device. Limiting values are stress ratings only and operation of
sheet, which is available on request via the local NXP Semiconductors sales the device at these or any other conditions above those given in the
office. In case of any inconsistency or conflict with the short data sheet, the Characteristics sections of this document is not implied. Exposure to limiting
full data sheet shall prevail. values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
18.3 Disclaimers at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
General — Information in this document is believed to be accurate and explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
reliable. However, NXP Semiconductors does not give any representations or any inconsistency or conflict between information in this document and such
warranties, expressed or implied, as to the accuracy or completeness of such terms and conditions, the latter will prevail.
information and shall have no liability for the consequences of use of such
No offer to sell or license — Nothing in this document may be interpreted
information.
or construed as an offer to sell products that is open for acceptance or the
Right to make changes — NXP Semiconductors reserves the right to make grant, conveyance or implication of any license under any copyrights, patents
changes to information published in this document, including without or other industrial or intellectual property rights.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof. 18.4 Trademarks
Suitability for use — NXP Semiconductors products are not designed,
Notice: All referenced brands, product names, service names and trademarks
authorized or warranted to be suitable for use in medical, military, aircraft,
are the property of their respective owners.
space or life support equipment, nor in applications where failure or

19. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

HEF4093B_4 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 04 — 12 June 2008 13 of 14

NXP Semiconductors HEF4093B
Quad 2-input NAND Schmitt trigger

20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Transfer characteristics. . . . . . . . . . . . . . . . . . . 7
14 Application information. . . . . . . . . . . . . . . . . . . 9
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
19 Contact information. . . . . . . . . . . . . . . . . . . . . 13
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 June 2008
Document identifier: HEF4093B_4