Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Design
Methodologies

© Digital Integrated Circuits2nd Design Methodologies

 Implementation Choices

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

© Digital Integrated Circuits2nd Design Methodologies

 A Historical Perspective: the PLA
Product terms

x0 x1
x2
AND OR
plane plane

f0 f1

x0 x1 x2

© Digital Integrated Circuits2nd Design Methodologies

 Two--Level Logic
Two
Every logic function can be
expressed in sum-of-products
format (AND-OR)

minterm

Inverting format (NOR-

NOR) more effective

© Digital Integrated Circuits2nd Design Methodologies

 Array--Based Programmable Logic
Array
I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O 3O 2O 1O 0 O3O2O1O0 O 3O 2O 1O 0

PLA PROM PAL

Indicates programmable connection
Indicates fixed connection

© Digital Integrated Circuits2nd Design Methodologies

 More Complex PAL
programmable AND array (2 i 3 jk ) k macrocells

product
1 terms
j -wide OR array

D Q
j OUT

j
macrocell
CLK
A B C i i inputs

i inputs, j minterms/macrocell, k macrocells

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 What is an FPGA?

Configurable
Logic
Blocks
Block RAMs

Block RAMs
I/O
Blocks

Block
RAMs

© Digital Integrated Circuits2nd Design Methodologies

 XC4000 Architecture
Vcc
Slew Passive
CLB CLB Rate Pull-Up,
Control Pull-Down

Switch
Matrix D Q
Output Pad
Buffer

Input
CLB CLB Buffer
Q D
Delay

Programmable
Interconnect I/O Blocks (IOBs)
C1 C2 C3 C4

H1 DIN S/R EC
S/R
Control

G4 DIN
G3 G F'
SD

G2 Func. G' D Q

Gen. H'

G1
EC
RD
1

H G'
Y
Func. H'
S/R

F4 Gen. Control

F3 F DIN
Func. SD
F2 Gen.
F'
G' D Q

F1 H'

EC
RD
1
H'
F'
X
K

Configurable
Logic Blocks (CLBs)

© Digital Integrated Circuits2nd Design Methodologies

 XC4000E/X Configurable Logic Blocks
C1 C2 C3 C4

2 Four-input function
generators (Look Up H1 DIN S/R EC
Tables) S/R
Control

- 16x1 RAM or G4 DIN

SD
G3 G F'
D Q YQ
Logic function G2 Func.
G'
H'
Gen.

2 Registers G1 EC
RD
- Each can be H G'
1

Y
H'
configured as Flip Func S/R

.Gen.
Control

Flop or Latch F4
F3 F DIN
SD
- Independent Func. F'
Q XQ
F2 Gen. G'
H'
D

clock polarity F1
EC
- Synchronous and H'
1
RD

X
asynchronous K
F'

Set/Reset

© Digital Integrated Circuits2nd Design Methodologies

 Look Up Tables

Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB Look Up Table

Example: 4-bit address
Combinatorial Logic
A B C D Z
A 4
0 0 0 0 0 (2 )
B
Z 0 0 0 1 0 2
C
D
0 0 1 0 0 = 64K !
0 0 1 1 1
0 1 0 0 1
 Capacity is limited by number 0 1 0 1 1
of inputs, not complexity . . .
 Choose to use each function 1 1 0 0 0
generator as 4 input logic (LUT) 1 1 0 1 0
or as high speed sync.dual port 1 1 1 0 0
RAM WE 1 1 1 1 1
G4
G3 G
G2 Func.
Gen.
© Digital Integrated Circuits 2ndG1 Design Methodologies
 LUT (Look-
(Look-Up Table) Functionality
x1
x2
y
• Look-Up tables
x1 x2 x3 x4 y x3 LUT x1 x2 x3 x4 y
0 0 0 0 1
x4
0 0 0 0 0 are primary
0 0 0 1 1 0 0 0 1 1
0 0 1 0 1 0 0 1 0 0 elements for
0 0 1 1 1 0 0 1 1 0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
logic
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
0
1 implementation
1 0 0 0 1 1 0 0 0 0
1
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0 • Each LUT can
1 0 1 1 1 1 0 1 1 0
1 1 0 0 0 1 1 0 0 1 implement any
1 1 0 1 0 x1 x2 x3 x4 1 1 0 1 1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
1
0
0
function of 4
inputs
x1 x2

© Digital Integrated Circuits2nd Design Methodologies

 5-Input Functions implemented using two LUTs
X5 X4 X3 X2 X1 Y
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 1 0 LUT
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1 OUT
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
LUT
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 0

© Digital Integrated Circuits2nd Design Methodologies

 Array--Based Programmable Wiring
Array
Interconnect
Point
M

Programmed interconnection Input/output pin

Cell

Horizontal
tracks

Vertical tracks

© Digital Integrated Circuits2nd Design Methodologies

 Transistor Implementation of Mesh

© Digital Integrated Circuits2nd Courtesy Dehon and Wawrzyniek Design Methodologies

 Fuse--Based FPGA
Fuse
antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2l

Open by default, closed by applying current pulse

© Digital Integrated Circuits2nd From Smith97 Design Methodologies