Module 1
The Von Neumann Model
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Generations of Computer
Vacuum tube - 1946-1957
Transistor - 1958-1964
Small scale integration - 1965 on
◦ Up to 100 devices on a chip
Medium scale integration - to 1971
◦ 100-3,000 devices on a chip
Large scale integration - 1971-1977
◦ 3,000 - 100,000 devices on a chip
Very large scale integration - 1978 to date
◦ 100,000 - 100,000,000 devices on a chip
Ultra large scale integration
◦ Over 100,000,000 devices on a chip
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ENIAC - details
Electronic Numerical Integrator And Computer
18,000 vacuum tubes
20 accumulators of 10 digits
Programmed manually by switches
30 tons
1500 square feet
140 kW power consumption
5,000 additions per second
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The Von Neumann Model
• On the ENIAC,
all programming
was done at the
digital logic level.
• Programming the
computer
involved moving
plugs and wires.
Stored-program computers have become known as von Neumann
Architecture systems 4
Von Neumann
Stored Program concept
Main memory storing programs and data
ALU operating on binary data
Control unit interpreting instructions from memory and
executing
Input and output equipment operated by control unit
Princeton Institute for Advanced Studies
◦ IAS
Although not Completed till 1952, This is the prototype for
all today's general computer
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Structure of von Neumann machine
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Structure of von Neumann machine
Main Memory : for storing data and instruction.
ALU : Capable of operating BINARY data.
control unit : Interprets the instructions in memory
and causes them to be executed.
Input and output (I/O): equipment operated by
the control unit
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IAS Computer
1000 storage locations word of 40 bits.
Both data and program are stored there.
Numbers binary format.
Each instruction binary coded
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IAS Computer ….
A word may also contain two 20-bit instructions, with
each instruction consisting of an 8-bit operation code
(opcode) specifying the operation to be performed and a
12-bit address designating one of the words in memory
(numbered from 0 to 999).
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Main Memory
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The von Neumann Model
This is a general
depiction of a von
Neumann system:
These computers
employ a fetch-
decode-execute cycle
to run programs as
follows . . .
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The von Neumann Model
• The control unit fetches the next instruction from memory using
the program counter to determine where the instruction is
located.
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The von Neumann Model
• The instruction is decoded into a language that the ALU can
understand.
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The von Neumann Model
• Any data operands required to execute the instruction are fetched
from memory and placed into registers within the CPU.
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The von Neumann Model
• The ALU executes the instruction and places results in registers or
memory.
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IAS - details
Set of registers (storage in CPU)
◦ Memory Buffer Register (MBR)
◦ Memory Address Register (MAR)
◦ Instruction Register (IR)
◦ Instruction Buffer Register (IBR)
◦ Program Counter (PC)
◦ Accumulator (AC)
◦ Multiplier Quotient (MQ)
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Four registers are essential to instruction execution:
Program Counter (PC): Contains the address of an instruction to be
fetched. Typically, the PC is updated by the CPU after each instruction
fetched so that it always points to the next instruction to be executed. A
branch or skip instruction will also modify the contents of the PC.
Instruction Register (IR): Contains the instruction most recently fetched.
The fetched instruction is loaded into an IR, where the opcode and operand
specified are analyzed.
Instruction buffer register (IBR): Employed to hold temporarily the right-
hand instruction from a word in memory.
Memory Address Register (MAR): Contains the address of a location of
main memory from where information has to be fetched or information has
to be stored. Contents of MAR is directly connected to the address bus.
Memory Buffer Register (MBR): Contains a word of data to be written to
memory or the word most recently read. Contents of MBR is directly
connected to the data bus. It is also known as Memory Data Register
(MDR).
I/O address register (I/OAR): specifies a particular I/O device.
I/O buffer (I/OBR) register: is used for the exchange of data between an
I/O module and the CPU.
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Structure of
IAS –
detail
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IAS Instruction Set
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Van Neumann Vs. Harvard
Van Neumann Vs. Harvard
Van Neumann Harvard
The data and Program are stored in The data and Program are stored in
same memory separate memory
The code is executed serially and The code is executed parallel and
takes more time takes less time.
There is no exclusive multiplier Separate MAC is available
Absence of Barrel Shifter Barrel shifter used for rotation and
floating point multiplications.
Programs are optimum in size Programs are bigger in size
Used in conventional PCs and Used in DSPs, Image processing,
Embedded Systems with only Recent Embedded systems
control functions
