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NAND Gate DDL Complete PDF

The NAND gate is an electronic circuit with two or more inputs and a single output. The output is high if any input is low, and only low if all inputs are high. NAND gates are commonly used in digital circuits because they can be efficiently implemented using CMOS technology. A NAND gate can be constructed using diodes, a transistor, and a battery, with the output going high when either input is low and low only when both inputs are high.

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540 views4 pages

NAND Gate DDL Complete PDF

The NAND gate is an electronic circuit with two or more inputs and a single output. The output is high if any input is low, and only low if all inputs are high. NAND gates are commonly used in digital circuits because they can be efficiently implemented using CMOS technology. A NAND gate can be constructed using diodes, a transistor, and a battery, with the output going high when either input is low and low only when both inputs are high.

Uploaded by

Sarkarali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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NAND GATE

Theory :
NAND Gate is an Electronic circuit which has two or more inputs but only One output.
The NAND Gate is natural implementation for the simplest and fastest Electronic circuits. The output is
High if at least One of its input is Low . The output is Low only when all the inputs are High. The term
NAND is a contraction of NOT – AND. The NAND Gate is a combination of an AND Gate followed by NOT
Gate. NAND represents NOT AND. The small “bubble” circle represents the invert function. The NAND
Gate is implemented efficiently in CMOS Technology in terms of chip area and speed

Symbolic Representation :

Boolean Expression :
Boolean Expression for 2 – Input NAND Gate :
Truth Table :

Apparatus :
I. Bread Board

II. Resistors

III. Transistor

IV. Diodes

V. Battery

VI. Connecting Wires

VII. LED

VIII. Buttons
Working :

 Case 1 :- When Both the input A and B are Low ( 0V ), both the diodes D1
and D2 are forward biased . Therefore the voltage at the junction P of the diodes become
zero. This drives the transistor Q to cut off .As a result the output becomes High ( + V cc )

 Case 2 :- When the input A is Low and B is High, the diode D1 is forward
biased whereas diode D2 is reverse biased . Therefore the voltage at the junction P of
the diodes becomes zero. This drives the transistor Q to cut off. As a result the output
becomes High ( + V cc ) .

 Case 3 :- When the input A is High and B is Low the diode D2 is forward
biased whereas diode D1 is reverse biased .Therefore the voltage at the junction P
becomes zero. This drives the transistor Q to cut off. As a result the output becomes
High ( + V cc )

 Case 4 :- When both the input A and B are High both the diodes D and D
are reverse biased .Therefore the voltage drives at the junction P becomes ( + V cc). This
large voltage drives the transistor Q to act saturation. The transistor acts as a clased
circuit. As a result the output becomes Low .
Circuit Diagram :

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