Class Notes -Module 3
Reference: Digital Design and Computer Architecture
David Money Harris
Sarah L. Harris
A. Pseudoinstructions
If an instruction is not available in the MIPS instruction set, the same operation can be
performed using one or more existing MIPS instructions. MIPS is a reduced instruction set
computer (RISC), so the instruction size and hardware complexity are minimized by keeping the
number of instructions small.
MIPS defines pseudoinstructions that are not actually part of the instruction set but are
commonly used by programmers and compilers. When converted to machine code,
pseudoinstructions are translated into one or more MIPS instructions. Table 6.5 gives examples
of pseudoinstructions and the MIPS instructions used to implement them. For example, the load
immediate pseudoinstruction (li) loads a 32-bit constant using a combination of lui and ori
instructions. The no operation pseudoinstruction (nop, pronounced “no op”) performs no
operation. The PC is incremented by 4 upon its execution. No other registers or memory values
are altered. The machine code for the nop instruction is 0x00000000.
B.Exceptions
An exception is like an unscheduled function call that jumps to a new address.
Exceptions may be caused by hardware or software. For example, the processor may receive
notification that the user pressed a key on a keyboard. The processor may stop what it is doing,
determine which key was pressed, save it for future reference, then resume the program that was
running. Such a hardware exception triggered by an input/output (I/O) device such as a
keyboard is often called an interrupt.
Alternatively, the program may encounter an error condition such as an undefined
instruction. The program then jumps to code in the operating system (OS), which may choose to
terminate the offending program. Software exceptions are sometimes called traps. Other
causes of exceptions include division by zero, attempts to read nonexistent memory, hardware
malfunctions, debugger breakpoints, and arithmetic overflow .
Steps
1) The processor records the cause of an exception and the value of the Program Counter(PC) at
the time the exception occurs. MIPS uses another special-purpose register called the Exception
Program Counter (EPC) to store the value of the PC at the time an exception takes place.
2)It then jumps to the exception handler function(subroutine function). In MIPS, the exception
handler is always located at 0x80000180. The exception handler saves registers on the stack.
3) The exception handler code reads a special-purpose register, called the Cause register to
determine how to handle the exception. mfc0 (move from coprocessor 0) instruction copies these
and other special-purpose registers into one of the general purpose registers. Different codes are
used to record different exception causes, as given in Table 6.7.
4) Using the cause register the address of exceptions are obtained, and respective exception
stored at location is executed.
5) It then returns to the program that was executing before the exception took place. When the
handler is finished, it restores the registers from the stack, copies the return address from EPC to
$k0 using mfc0, and returns using jr $k0.
The EPC and Cause registers are not part of the MIPS register file.
