A Low-Voltage, Low-Power 4-bit BCD Adder,

designed using the Clock Gated Power Gating, and

the DVT Scheme
Dipankar Saha1, Subhramita Basak1, Sagar Mukherjee2, C. K. Sarkar1
1
Department of Electronics and Telecommunication Engineering
Jadavpur University
Kolkata, West Bengal, India
2
Department of Electronics and Communication Engineering
MCKV Institute of Engineering
Liluah, Howrah, West Bengal, India
[email protected], [email protected], [email protected],
[email protected]

Abstract—This paper proposes a Low-Power, Energy Efficient 4- And, once the processing is completed, those are again
bit Binary Coded Decimal (BCD) adder design where the converted back into the decimal format. The conversion
conventional 4-bit BCD adder has been modified with the Clock between the decimal and the binary formats causes a
Gated Power Gating Technique. Moreover, the concept of DVT significant amount of Delay [5]. Again, when the conversion
(Dual-vth) scheme has been introduced while designing the full
takes place for the fractional decimal numbers such as 0.110,
adder blocks to reduce the Leakage Power, as well as, to
maintain the overall performance of the entire circuit. The 0.1 etc., there occurs error (which is not tolerable for most of
reported architecture of 4-bit BCD adder is designed using 45 nm the financial and commercial applications) due to the
technology and it consumes 1.384 µWatt of Average Power while approximated representations [5, 6]. Therefore, for all those
operating with a frequency of 200 MHz, and a Supply Voltage reasons as mentioned above, designers have to look for a
(Vdd) of 1 Volt. The results obtained from different simulation decimal arithmetic hardware in financial and commercial
runs on SPICE, indicate the superiority of the proposed design applications.
compared to the conventional 4-bit BCD adder. Considering the Now, in all arithmetic units, whether binary or decimal, the
product of Average Power and Delay, for the operating use of an adder circuit is obvious. So far, different techniques
frequency of 200 MHz, a fair 47.41 % reduction compared to the
have been invented and proposed in literature for the purpose
conventional design has been achieved with this proposed
scheme. of doing the decimal additions (even though it is less popular
than the binary addition) [5], [7-11].
The conventional 4-bit BCD adder consists of two 4-bit full
adders and a carry detection logic circuit [9]. At the first stage,
Keywords- BCD; Decimal Arithmetic; RCA; Full Adder; DVT one of the two 4-bit full adders can be used to produce the
Scheme; Power Gating; Sleep Transistor; Delay; Leakage Power binary addition results. If the value of the result obtained, is
greater than the decimal number ‘9’, then a carry output is
generated. As well as, the result needs to be corrected by
adding the decimal number ‘6’ with it. This is actually done, at
I. INTRODUCTION the next stage, by the other one of those two 4-bit full adders.
There are quite a few reasons behind the use of binary data Besides, a carry detection logic circuit is there, which is
for doing the arithmetic operations in almost all the computer formed using two AND gates and one OR gate. In [10],
systems. The speed and simplicity of binary arithmetic, Shirazi, et. al., proposed a Redundant Binary coded Decimal
efficiency in storing the binary data etc. are the most important (RBCD) adder, where the addition operation is done in three
among those [1, 2]. But, for the financial and commercial steps. Firstly, the BCD input is converted into RBCD. Then,
applications, the use of decimal arithmetic is still relevant. In in the next stage, the result of the addition is obtained using
case of the financial applications, in order to obtain the the RBCD adder. At the final step, this RBCD adder-result is
decimal results, a decimal software use to run on top of the again converted back into the BCD format. But, as the
underlying binary hardware. But the speed (which is almost conversion of RBCD adder-result back into the BCD format
100 to 1000 times slower) is the major concern for the decimal requires carry propagation, therefore the Delay caused due to
softwares [3, 4]. Moreover, the commercial databases contain this, becomes dependent on the length of the input operands
more decimal data than binary data. For the purpose of [10]. In [11], a 4-bit BCD adder with Clock Gated Power
processing, these decimal data are converted into binary data. Gating has been reported using 65 nm technology. As well as,
a performance analysis, showing the comparison among Cox is the per unit area gate oxide capacitance, µ0 is the zero
“Conventional BCD adder”, “BCD adder with DSTN bias mobility [13].
(Distributed Sleep Transistor Network)”, and “BCD adder And as there exists an exponential relationship of the
with Clock Gated Power Gating” has been presented there. leakage current to the change in vth, therefore assigning the
Now, considering the Average Power consumption and the higher-vth to the transistors in a circuit can be very useful in
Delay, as shown in [11], the 4-bit BCD adder with Clock reducing the leakage current, and thereby reducing the
Gated Power Gating is happened to be the most efficient one Leakage Power [14]. But, the problem is that the higher-vth
out of those three. increases the equivalent ON-resistance for the transistors, and
In our proposed architecture for the 4-bit BCD adder, we that in turn increases the Delay [14].
have mainly modified the conventional 4 bit BCD adder The propagation Delay through a transistor is generally
design [9] with the Clock Gated Power Gating. Besides, the denoted as,
entire design is carried out in 45 nm technology, and thereby a C V
T  L dd (2)
serious consideration about the means by which the Leakage delay 
current can be reduced becomes very much important. We K .(V  V )
dd th
introduced the concept of the DVT (Dual-vth) scheme in our Where, K is a factor which depends on the gate size, as well
proposed design for the purpose of reduction of the Leakage as on the process.  takes any value between 1 and 2
Power. Moreover, to verify the efficiency of the proposed
depending on channel length [15].
architecture, a comparison of this with the conventional 4-bit
Therefore, we can see that the reduction of the vth can be
BCD adder and the 4-bit BCD adder with DVT scheme
useful to improve the overall performance at low supply
(without Power Gating) has also been presented.
voltages [16]. But, as we reduce the vth of the transistor,
Rest of the paper is organized as follows. In section II, a
leakage current starts playing a dominant role [13, 16]. Thus,
detailed discussion about the effectiveness of the DVT (Dual-
maintaining the performance of the circuit as well as reducing
vth) scheme in reducing the Leakage Power, has been
the Leakage Power dissipation becomes a key challenge for
presented. In section III, a brief review of the several Power
designing any low-voltage, low power digital circuit.
Gating strategies available in literature has been described.
Gate level DVT scheme is one of the most efficient
The details of the proposed design of 4-bit BCD adder have
techniques, for reducing the Leakage Power in a CMOS
been illustrated in section IV. Section V, deals with the
circuit. For a gate level DVT circuit, all the transistors within
analysis of the results obtained from different simulation runs.
any particular gate may have the same vth which is either the
Finally, in section VI, the conclusion summary of the entire
low-vth or the high-vth. Thus, the gates used in the logic circuit,
work, has been discussed.
can either be the low-vth gates or else, the high-vth gates [17].

II. LEAKAGE POWER & DVT SCHEME

For the digital circuits used in VLSI, power dissipation can III. POWER GATING STRATEGIES
be categorized mainly into three parts, Switching Power
For the low leakage, high performance operation of any
dissipation, Short-Circuit Power dissipation, and Static Power
VLSI circuit, the Power Gating technique is treated as the
dissipation [12]. While considering the power dissipated by a
most effective one which can substantially reduce the leakage
MOS device, until recent years, the Static Leakage Power
current in standby mode. Now, considering the previously
component has been assumed to be negligible. But, in the
proposed circuit level approaches, the use of sleep transistors
cases where we have to consider the sub-micron technologies,
for Power Gating is found to be the most popular one [18-23].
or, deep-sub-micron technologies, this assumption proving to
When the circuit is in active mode these sleep transistors are
be no longer true. Now, in standby mode, the power
‘ON’. But, for the standby mode of operation, these transistors
dissipation that occurs in a CMOS circuit is mainly due to the
get turned ‘OFF’, and that in turn disconnects the logic cells
sub-threshold leakage current. The sub-threshold current of a
from the Vdd (or, Ground) rail. Now, the major concern
MOSFET can be modeled as [13],
associated with the insertion of sleep transistors, is the

 q / n ' KT ) .VG  VS  VTo 'VS VDS  

degradation in performance [18]. It is found, for a specific
qV / KT  placement technique, the amount of performance degradation
I  Ae. 1  e DS  (1) of the circuit usually depends on the size of the sleep
sub
  transistors [18]. In conventional Power Gating architecture, a
Where, the drain to source voltage is represented as VDS , and ‘header’ and a ‘footer’ switch (which are basically the sleep
transistors) used to be connected in series with the PUN (Pull-
the gate voltage is denoted by VG . Up Network) and PDN (Pull-Down Network) of the logic
2 gates respectively. As illustrated in Fig. 1, the virtual-Vdd rail
 KT 
Weff
1.8 (virtual-Ground rail) could be disconnected from the actual
A  0Cox   e , Vdd (Ground) by turning-off the ‘header’ (‘footer’) sleep-
Leff  q 
 adders are basically Ripple Carry Adders (RCAs), where carry
output of one full adder block is fed as the carry input for the
next full adder. Besides that, for the purpose of forming the
carry detection logic circuit, two AND gates and one OR gate
have been used. Now, the full adder being the basic building
block for designing the proposed 4-bit BCD adder, the proper
selection of the 1-bit full adder cell becomes obvious. The
design criteria of a full adder are actually multi-fold. Besides
the transistor count which is one of the primary concerns, the
two other important design criteria are the power consumption
and the speed [24]. There are large numbers of full adder
designs already available in literature, and those designs are
relying upon different logic styles like, static CMOS, dynamic,
transmission gate, or pass transistor logic [12], [16], [24-28].
However, considering the advantages like lesser Delay,
elimination of the Short-Circuit Power component within the
cell, fewer glitches at outputs, and importantly lesser power
consumption, the circuit of the 16 transistor full adder which is
Figure 1. Conventional Power Gating architecture
reported in [28] has been adopted in this work. Fig. 3 shows
transistor; and thereby reducing the Leakage Power. But in the architecture of the 16 transistor 1-bit full adder cell where
active mode, these sleep transistors need to be turned ‘ON’, the actual design of [28] has been modified with the DVT
such that the logic circuit works fine as per its functionality. scheme. In our proposed design of 4-bit BCD adder, we have
Now, instead of using both ‘header’ and ‘footer’ sleep actually used this modified 16 transistor 1-bit full adder cell
transistors, the same Leakage Power reduction can be for the purpose of implementing the two 4-bit full adder
achieved by using any one of the two switches. Considering structures.
the perspective of area required, effective conductance etc., it
is better to use NMOS sleep transistors as the footer switches
[19, 20]. But, looking at the other-factors like noise on
Power/Ground rails, Leakage etc., the implementation of
PMOS header switches can also be very useful [22].
As mentioned above, the effectiveness of the Power Gating
technique actually depends on the proper sizing of the sleep
transistors. For the larger sleep transistors, it can be seen that
the performance degradation is lesser [18]. But simultaneously
those larger transistors require larger area, and a significant
amount of driving energy [23]. Whereas, the insertion of
smaller sleep transistors may cause an increase in performance
degradation, which is also not acceptable [18]. So, there is a
trade-off in between the power consumption and the
performance of the circuit. Several works have already been
reported in literature to find out the feasible solution to
mitigate the aforesaid problem [18-22]. DSTN, Clustering-
based sleep transistor sizing algorithms etc. are the major
among those. Besides, there is one other important technique,
called Clock Gated Power Gating, where a clock signal is used
to excite the sleep transistors. In case of the Clock Gated
Figure 2. Conventional 4-bit BCD adder
Power Gating scheme, the frequency of the clock signal is
actually set depending up on the Delay among the Moreover, the concept of multiple channel length technique
intermediate results which are obtained from the different has also been utilized in the proposed architecture. For the
clusters of the circuit [11]. conventional CMOS technology, the multiple channel length
technique is known to be one of the popular means by which
we can reduce the Leakage Power [29]. As per the technique,
IV. DESIGN OF THE 4-BIT BCD ADDER
the channel length of the transistors used in a circuit can be
As illustrated in Fig. 2, for designing the conventional 4 bit increased, wherever it is needed to control the leakage current.
BCD adder we need two 4-bit full adders. These 4-bit full On the other hand, wherever it is required to maintain the
performance (specially, for the transistors in critical path), we
need to increase the width of the transistors [29]. For the V. RESULTS AND DISCUSSIONS
proposed design, the effective sizing of the sleep transistors
The analytical reasoning behind the modification of the
and the transistors used in transmission gates has been done
conventional 4-bit BCD adder is verified here with circuit
using this technique.
simulations. From Table I we are getting the details like power
From the block level representation of the proposed 4-bit
consumption, maximum Delay at output etc. for the proposed
BCD adder (as shown in Fig. 4), it can be seen that the CLK1
BCD adder along with the comparison of the proposed scheme
and CLK2 are the two different clock signals which actually
with other state-of-the-art designs [30], [31]. Table II shows
used for the purpose of Power Gating.
the comparison of the different performance parameters, for
the proposed architecture with the conventional 4-bit BCD
adder and the 4-bit BCD adder with DVT scheme (without
Power Gating). The simulation results are obtained for an
operating frequency of 200 MHz and a supply voltage of 1
Volt.

Table I. Different design styles for Low-Power BCD adders

[30] [31] This Work Unit

(using
CSLA)
BCD adder
Unified designed
Flagged
Architecture adder/ using DVT,
BCD adder
subtractor Clock Gated
PowerGating

Technology -- 180 45 nm
Figure 3. 16 transistor 1-bit full adder, modified with DVT scheme [28]

4-bit addition/ 4-bit

Operation
addition subtraction addition

Operating
Frequency
-- 1000 200 MHz

Power 2.55×10-3 14.50×10-3 1.384×10-6 Watt

Sec-
Delay 15.65×10-9 3.46×10-9 1.618×10-10
ond

Table II. Comparison of Performances

Conventional 4-bit BCD adder

Proposed
4-bit BCD with DVT
4-bit BCD Unit
adder (without Power
adder
Gating)

Average 3.722× 1.668× 1.384×

Watt
Power 10-6 10-6 10-6

11.440× 19.229× 16.181×

Delay Second
10-11 10-11 10-11
Figure 4. Block diagram of the proposed 4-bit BCD adder design
(Average
42.588× 32.077× 22.394×
Power × Joule
Delay) 10-17 10-17 10-17
 Fig. 5 shows the graphical representation of the details of VI. CONCLUSION
Average Power consumption for the proposed 4-bit BCD
Due to the limited battery life-time of the devices used in
adder, the conventional 4-bit BCD adder and the 4-bit BCD
Low-Power applications, and the aggressive scaling of the
adder with DVT scheme (without Power Gating); for actually
transistor dimensions, the Leakage Power has become one of
three different frequencies (50 MHz, 100 MHz, and 200
the major concerns while designing the digital circuits in
MHz). And as it is illustrated there, it can be observed that the
VLSI. In this paper we have mainly focused to search for the
proposed design performs extremely well for the higher values
means by which we can significantly reduce the power
of frequencies, while consuming significantly lesser amount of
consumption of the circuit; and for that reason, we have
Average Power. Furthermore, considering the products of
modified the conventional 4-bit BCD adder architecture with
Average Power and Delay, for the different frequency values,
Clock Gated Power Gating, and the DVT scheme.
we can see that the proposed architecture provides the best
Now, one of the possible drawbacks that the conventional
case results (as shown in Fig.6).
BCD adder suffers from is the extra Delay at its output. And a
large number of BCD adder designs have already been
reported in literature [5], [10], [30] which can effectively be
used to mitigate the problem. But, as we have mainly aimed to
analyze the impact of the implementation of the proposed
design scheme in improving the overall power performance,
that is the why, here we have actually opted the conventional
architecture.
From the results, as obtained from the different simulation
runs on SPICE, it can be seen that a drastic reduction in
Average Power consumption has become possible for the 4-bit
BCD adder circuit, by using proposed design scheme. For an
operating frequency of 200 MHz, the proposed architecture
consumes 62.8 % less power compared to the conventional 4-
bit BCD adder design.

ACKNOWLEDGMENT
Figure 5. Average Power consumption details
Authors would like to thank SMDP-II project lab., IC Design
& Fabrication Centre, Jadavpur University for getting the
opportunity to carry out this work using SPICE Tools .

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