A B C D E

Compal confidential 1

Schematics Document
Mobile Penryn uFCPGA with Intel
2 Cantiga_GM+ICH9-M SFF core logic 2

SKYY
2008-07-29
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 1 of 36
A B C D E
 A B C D E

Compal confidential
File Name : LA-4021P SKYY
CK505 Accelerometer
Docking CONN.(Opus 1.0)
Thermal Sensor Mobile Penym
1 *RJ-45(LED*2) EMC2103 LV/ULV Dual Core Clock Generator LIS302DLTR 1

*CRT uFCPGA-956 CPU - SFF ICS9LPRS397

*LINE IN page 4
page 16 page 26
*LINE OUT page 4,5,6,7
*USB x4
*DC JACK Fan Control
*Power on signal page 4 H_A#(3..35) FSB
H_D#(0..63)
*Docked indicator 667/800/1066MHz 1.05V
signal
*AC present indicator LCD conn
page 18
signal
CRT
Intel Cantiga GMS DDR2 800MHz 1.8V
DDR2-SO-DIMM X 2
page 17 BANK 0, 1, 2, 3 page 14,15
FCBGA 1363 - SFF Dual Channel
CRT to docking
page 34

page 8,9,10,11,12,13
S-Video to Docking
page 34
USB x1(Docking) page 34

2
Express Card 54 WWAN Card 2
WWAN + PCIE X1 FingerPrinter AES2810
PCIE X1 + USB X1 daughter board
+ USB X1 DMI X4 USBx1
page 25 page 25 page 31

USB conn x 3(For I/O)

PCI-E BUS USB2.0 BT Conn USB x 1 page 31
Intel ICH9-M Azalia

WBMMAP-569 - SFF
SATA0 USB x1(Camara)
10/100/1000 LAN CardBus Controller PCI BUS
SATA1 page 18
Intel Boaz GbE Rico R5C833
page 20,21,22,23
PHY MDC V1.5
page 30
page 24 page 27

Audio CKT TPA6043

SPI
AD1984HD page 28 AMP & Audio Jack page 29
24HST1041A-3
3 RJ45 CONN 1394 port SD/MMC Slot 2.5" SATA HDD Connector
3

page 25
SPI ROM OR
AT26DF321 SATA ODD Connector
page 21
LED LPC BUS page 32
page 19
1.8" SATA HDD Connector
page 21

RTC CKT.
TPM1.2 SMSC KBC 1091
page 21
SLB9635TT page 33
page 32

Power OK CKT.
page 35 Touch Pad CONN. Int.KBD
page 30 page 30

4
Power On/Off CKT. TrackPoint CONN. 4

page 30
page 30

Security Classification Compal Secret Data Compal Electronics, Inc.

2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
SCHEMATIC, M/B LA-4021P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 36 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 2 of 36
A B C D E
 A

( O MEANS ON X MEANS OFF )

Voltage Rails
Symbol Note :
+B +5VALW +1.8V +5VS
+3VALW +3VS
+3VM +1.5VS
: means Digital Ground
power
plane +1.05VM +0.9V
+VCCP
+CPU_CORE : means Analog Ground
+0.9V
@ : means just reserve , no build
CONN@ : means ME part.
State
45@ : means install after SMT.

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

SERIAL THERMAL
SOURCE INVERTER BATT EEPROM SENSOR SODIMM CLK CHIP MINI CARD LCD
(CPU)

SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X V V V X
LCD_CLK
LCD_DAT Cantiga
X X X X X X X V

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 3 of 36
A
 5 4 3 2 1

XDP Connector
JP1
1 2 +VCCP
XDP_BPM#5 GND0 GND1
3 OBSFN_A0 OBSFN_C0 4
XDP_BPM#4 5 6
OBSFN_A1 OBSFN_C1 XDP_TDI R2 54.9_0402_1%
7 GND2 GND3 8 1 2
XDP_BPM#3 9 10
XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_TMS R3 54.9_0402_1%
11 OBSDATA_A1 OBSDATA_C1 12 1 2
13 GND4 GND5 14
XDP_BPM#1 15 16 XDP_TDO R4 1 2 54.9_0402_1%
XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
17 OBSDATA_A3 OBSDATA_C3 18
D XDP_BPM#5 R5 54.9_0402_1% D
19 GND6 GND7 20 1 2
21 OBSFN_B0 OBSFN_D0 22
23 24 XDP_HOOK1 R6 1 2 @ 54.9_0402_1%
OBSFN_B1 OBSFN_D1
25 GND8 GND9 26
27 28 XDP_TRST# R7 1 2 51_0402_1%
+VCCP OBSDATA_B0 OBSDATA_D0
Place close to U1. 29 OBSDATA_B1 OBSDATA_D1 30
31 32 XDP_TCK R8 1 2 54.9_0402_1%
GND10 GND11
<8> H_A#[3..16] 33 OBSDATA_B2 OBSDATA_D2 34
U1A R9 35 36 This shall place near CPU
H_A#3 1K_0402_5% OBSDATA_B3 OBSDATA_D3
P2 A[3]# ADS# M4 H_ADS# <8> 37 GND12 GND13 38
H_A#4 V4 J5 <5,21> H_PWRGOOD 2 1 H_PWRGOOD_R 39 40 CLK_CPU_XDP <16>
A[4]# BNR# H_BNR# <8> PWRGOOD/HOOK0 ITPCLK/HOOK4
H_A#5 W1 L5 XDP_HOOK1 41 42 CLK_CPU_XDP# <16>
A[5]# BPRI# H_BPRI# <8> HOOK1 ITPCLK#/HOOK5

2
56_0402_5%
H_A#6 T4 +VCCP 43 44 +VCCP
A[6]# VCC_OBS_AB VCC_OBS_CD

ADDR GROUP 0
H_A#7 AA1 N5 R609 2 1 45 46 H_RESET#_R R11 1 2 22.6_0402_1% H_RESET#
A[7]# DEFER# H_DEFER# <8> HOOK2 RESET#/HOOK6
H_A#8 AB4 F38 51_0402_1% C1 0.1U_0402_16V4Z 47 48 XDP_DBRESET#
A[8]# DRDY# H_DRDY# <8> HOOK3 DBR#/HOOK7
H_A#9 T2 J1 49 50
A[9]# DBSY# H_DBSY# <8> GND14 GND15

R10
H_A#10 AC5 9/20 51 52 XDP_TDO

1
A[10]# SDA TD0

CONTROL
H_A#11 AD2 M2 53 54 XDP_TRST#
A[11]# BR0# H_BR0# <8> SCL TRST#
H_A#12 AD4 55 56 XDP_TDI R14
H_A#13 A[12]# XDP_TCK TCK1 TDI XDP_TMS 0_0402_5%
AA5 A[13]# IERR# B40 57 TCK0 TMS 58 Place R191 within 200ps
H_A#14 AE5 D8 59 60 XDP_PRE 1 2 (~1") to CPU
A[14]# INIT# H_INIT# <21> GND16 GND17
H_A#15 AB2
H_A#16 A[15]# CONN@ SAMTE_BSH-030-01-L-D-A
AC1 A[16]# LOCK# N1 H_LOCK# <8>
<8> H_ADSTB#0 Y4 ADSTB[0]#
G5 H_RESET#
RESET# H_RESET# <8>
<8> H_REQ#0 R1 REQ[0]# RS[0]# K2 H_RS#0 <8>
<8> H_REQ#1 R5 REQ[1]# RS[1]# H4 H_RS#1 <8>
<8> H_REQ#2 U1 REQ[2]# RS[2]# K4 H_RS#2 <8>
P4 L1
<8>
<8>
H_REQ#3
H_REQ#4 W5
REQ[3]#
REQ[4]#
TRDY#
H2
H_TRDY# <8>
+3VS
Thermal Sensor EMC2103-2 with CPU PWM FAN
<8> H_A#[17..35] HIT# H_HIT# <8>
H_A#17 AN1 A[17]# HITM# F2 H_HITM# <8> Change R18 to 2.94k_1% to change initial
C H_A#18 C
AK4 A[18]# Add 0 ohm per EMI request. Correct to Swap DN&DP. (11/26) thermal shutdown temp to 85C. 2/13
H_A#19 AG1 AY8 XDP_BPM#0
A[19]# BPM[0]#

2
ADDR GROUP 1

H_A#20 AT4 BA7 XDP_BPM#1 10/17 U2

H_A#21 A[20]# BPM[1]# XDP_BPM#2 R15
AK2 A[21]# BPM[2]# BA5 Change R17 to 10K for HW critical
H_A#22 AT2 AY2 XDP_BPM#3 R48 68_0402_5% H_THERMDC 1 16 REMOTE2+
H_A#23 A[22]# BPM[3]# XDP_BPM#4 0_0402_5% DN DP2/DN3 shutdown to internal diode
AH2 AV10
XDP/ITP SIGNALS

H_A#24 A[23]# PRDY# XDP_BPM#5_R XDP_BPM#5

AF4 AV2 1 2 1 2 H_THERMDA 2 15 REMOTE2- temperature. 4/23

1
H_A#25 A[24]# PREQ# XDP_TCK C3 2200P_0402_50V7K DP DN2/DP3
AJ5 A[25]# TCK AV4
H_A#26 AH4 AW7 XDP_TDI +3VS_THER 3 14 R18 1 2 2.05K_0402_1%
H_A#27 A[26]# TDI XDP_TDO VDD TRIP_SET @ R643 1
AM4 A[27]# TDO AU1 2 10K_0402_5%
H_A#28 XDP_TMS +5VS
AP4 A[28]# TMS AW5 1 C2 R24 4 GPIO1 SHDN_SEL 13 R17 1 2 10K_0402_5% +3VS
H_A#29 AR5 AV8 XDP_TRST# 0.1U_0402_16V4Z 10K_0402_5%
H_A#30 A[29]# TRST# XDP_DBRESET# JP2
AJ1 A[30]# DBR# J7 XDP_DBRESET# <22> +3VS 1 2 5 GPIO2 GND 12 1 2
H_A#31 AL1 9/14 R13 10K_0402_5% 1 4
A[31]# H_PROCHOT# <42> 2 1 4
H_A#32 AM2 6 11 FAN_PWM 2 5
A[32]# <22> THERM_SCI# ALERT# PWM 2 G5
H_A#33 AU5 A[33]# THERMAL Place Close to U1. +VCCP 1 2 +3VS 3 3 G6 6
H_A#34 AP2 +3VS 1 2 7 10 TACH R16 10K_0402_5%
H_A#35 A[34]# R20 SYS_SHDN# TACH
AR1 D38 1 2 68_0402_5% R23 @ 10K_0402_5% CONN@ ACES_85205-04001

GND
A[35]# PROCHOT# H_THERMDA_R R21 H_THERMDA
<8> H_ADSTB#1 AN5 ADSTB[1]# THERMDA BB34 1 2 0_0402_5% <22,26> ICH_SM_DA 8 SMDATA SMCLK 9 ICH_SM_CLK <22,26>
BD34 H_THERMDC_R R22 1 2 0_0402_5% H_THERMDC Chnage JP2 to 4pin. 12/06
THERMDC EMC2103-2-AX_QFN16_4X4
<21> H_A20M# C7 <37,39> MAINPWON 1 2

17
A20M# H_THERMTRIP# R324 @ 0_0402_5%
<21> H_FERR# D4 FERR# THERMTRIP# B10 H_THERMTRIP# <8,21>
ICH

F10 H_THERMTRIP# 1 2
<21> H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together, R641 0_0402_5%
<21> H_STPCLK# F8 STPCLK# Add R641 per HP request. 3/28
<21> H_INTR C9 H CLK Trace width / Spacing = 10 / 10 mil
LINT0
<21> H_NMI C5 LINT1 BCLK[0] A35 CLK_CPU_BCLK <16>
<21> H_SMI# E5 SMI# BCLK[1] C35 CLK_CPU_BCLK# <16> Change R23, R24 connect to +3VS and add PU/PD for U2. (9/3)
PAD T97 V2 RSVD01 NI R23, reserve R324 and connect to MAINPWON. (10/5)
PAD T98 Y2 RSVD02
AG5
PAD T99 RSVD03
REMOTE thermal sensor
RESERVED

B B
PAD T100 AL5 RSVD04
PAD T101 J9 RSVD05
PAD T102 F4 RSVD06
PAD T103 H8 RSVD07

1
C
REMOTE2+ 2 Q45
B MMBT3904W_SOT323-3
E

3
PENRYN SFF_UFCBGA956 2 Layout Note:
C314
2200P_0402_50V7K place near the hottest spot area for
1 NB & top SODIMM.
REMOTE2-

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 4 of 36
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
<8> H_D#[0..15] H_D#[32..47] <8>
U1B U1C
H_D#0 F40 AP44 H_D#32 F32 AB28
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
G43 D[1]# D[33]# AR43 G33 VCC[002] VCC[069] AD30
H_D#2 E43 AH40 H_D#34 H32 AD28
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
J43 D[3]# D[35]# AF40 J33 VCC[004] VCC[071] Y26

DATA GROUP 0
D H_D#4 H_D#36 D
H40 D[4]# D[36]# AJ43 K32 VCC[005] VCC[072] AB26
H_D#5 H44 AG41 H_D#37 L33 AD26
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
G39 AF44 M32 AF30

DATA GROUP 2
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E41 D[7]# D[39]# AH44 N33 VCC[008] VCC[075] AF28
H_D#8 L41 AM44 H_D#40 P32 AH30
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
K44 D[9]# D[41]# AN43 R33 VCC[010] VCC[077] AH28
H_D#10 N41 AM40 H_D#42 T32 AF26
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
T40 D[11]# D[43]# AK40 U33 VCC[012] VCC[079] AH26
H_D#12 M40 AG43 H_D#44 V32 AK30
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
G41 D[13]# D[45]# AP40 W33 VCC[014] VCC[081] AK28
H_D#14 M44 AN41 H_D#46 Y32 AM30
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
L43 D[15]# D[47]# AL41 AA33 VCC[016] VCC[083] AM28
H_DSTBN#0 K40 AK44 H_DSTBN#2 AB32 AP30
<8> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <8> VCC[017] VCC[084]
H_DSTBP#0 J41 AL43 H_DSTBP#2 AC33 AP28
<8> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <8> VCC[018] VCC[085]
H_DINV#0 P40 AJ41 H_DINV#2 AD32 AK26
<8> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <8> VCC[019] VCC[086]
<8> H_D#[16..31] H_D#[48..63] <8> AE33 VCC[020] VCC[087] AM26
AF32 VCC[021] VCC[088] AP26
H_D#16 P44 AV38 H_D#48 AG33 AT30
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
V40 D[17]# D[49]# AT44 AH32 VCC[023] VCC[090] AT28
H_D#18 V44 AV40 H_D#50 AJ33 AV30
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
AB44 D[19]# D[51]# AU41 AK32 VCC[025] VCC[092] AV28
H_D#20 R41 AW41 H_D#52 AL33 AY30
D[20]# D[52]# VCC[026] VCC[093]

DATA GROUP 1
H_D#21 W41 AR41 H_D#53 AM32 AY28
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
N43 BA37 AN33 AT26

DATA GROUP 3
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
U41 D[23]# D[55]# BB38 AP32 VCC[029] VCC[096] AV26
H_D#24 AA41 AY36 H_D#56 AR33 AY26
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
AB40 D[25]# D[57]# AT40 AT34 VCC[031] VCC[098] BB30
H_D#26 AD40 BC35 H_D#58 AT32 BB28 +VCCP
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
AC41 D[27]# D[59]# BC39 AU33 VCC[033] VCC[100] BD30
H_D#28 AA43 BA41 H_D#60 AV32
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
Y40 D[29]# D[61]# BB40 AY32 VCC[035] VCCP_001 J11 R26 1 2 0_0402_5%
H_D#30 Y44 BA35 H_D#62 BB32 E11 R27 1 2 0_0402_5%
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP_002 C
T44 D[31]# D[63]# AU43 BD32 VCC[037] VCCP_003 G11 R28 1 2 0_0402_5%
H_DSTBN#1 U43 AY40 H_DSTBN#3 B28 J37 1
<8> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <8> VCC[038] VCCP_004
H_DSTBP#1 W43 AY38 H_DSTBP#3 B30 K38 Change to 330u_R9,
<8> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <8> VCC[039] VCCP_005 +
H_DINV#1 R43 BC37 H_DINV#3 B26 L37 C4
<8> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <8>
D28
VCC[040] VCCP_006
N37 330U_D2E_2.5VM_R9 casue high
V_CPU_GTLREF COMP0 VCC[041] VCCP_007 limitation. 12/14
AW43 GTLREF COMP[0] AE43 D30 VCC[042] VCCP_008 P38
COMP1 2
E37 TEST1 MISC COMP[1] AD44 F30 VCC[043] VCCP_009 R37
TEST2 D40 AE1 COMP2 F28 U37
T105 TEST2 COMP[2] VCC[044] VCCP_010

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
C43 AF2 COMP3 H30 V38
TEST3 COMP[3] VCC[045] VCCP_011

1 R33

1 R34
AE41 TEST4 H28 VCC[046] VCCP_012 W37

1 R31

1 R32
TEST5 AY10 G7 D26 AA37
T3 TEST5 DPRSTP# H_DPRSTP# <8,21,42> VCC[047] VCCP_013
TEST6 AC43 B8 F26 AB38
T4 TEST6 DPSLP# H_DPSLP# <21> VCC[048] VCCP_014
DPWR# C41 H_DPWR# <8> H26 VCC[049] VCCP_015 AC37
<16> CPU_BSEL0 A37 BSEL[0] PWRGOOD E7 H_PWRGOOD <4,21> K30 VCC[050] VCCP_016 AE37
<16> CPU_BSEL1 C37 BSEL[1] SLP# D10 H_CPUSLP# <8> K28 VCC[051]
B38 BD10 H_PSI# M30 B34
<16> CPU_BSEL2 BSEL[2] PSI# T124 VCC[052] VCCA[01] +1.5VS
M28 D34

2
VCC[053] VCCA[02]

10U_0805_6.3V6M
Near pin B34
0.01U_0402_16V7K
PENRYN SFF_UFCBGA956

Near pin D34

K26 VCC[054]
Cause CPU core power change to M26 VCC[055] VID[0] BD8 CPU_VID0 <42>
P30 BC7 1 1
1 phase, and not need support P28
VCC[056] VID[1]
BB10
CPU_VID1 <42>
VCC[057] VID[2] CPU_VID2 <42>
the pin, leave it as TP. 10/02 T30 VCC[058] VID[3] BB8 CPU_VID3 <42>
C6 C7
layout note: Route TEST3 & TEST5 traces on Resistor placed within T28 VCC[059] VID[4] BC5 CPU_VID4 <42> 2 2
V30 BB4 CPU_VID5 <42>
ground referenced layer to the TPs 0.5" of CPU pin.Trace V28
VCC[060] VID[5]
AY4
VCC[061] VID[6] CPU_VID6 <42>
should be at least 25 P26 VCC[062]
T26
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other V26
VCC[063]
BD12 VCCSENSE
VCC[064] VCCSENSE VCCSENSE <42>
toggling signal. Y30 VCC[065]
COMP[0,2] trace width is Y28 VCC[066]
AB30 BC13 VSSSENSE VSSSENSE <42>
VCC[067] VSSSENSE
166 0 1 1 18 mils. COMP[1,3] trace
B PENRYN SFF_UFCBGA956 B
width is 4 mils.

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0

+VCC_CORE

R36
1 2 VCCSENSE
+VCCP 100_0402_1%

R38
1

1 2 VSSSENSE
100_0402_1%
R35
1K_0402_1%
2

V_CPU_GTLREF

Close to CPU pin

1

R37
within 500mils.
A 2K_0402_1% A
2

Close to CPU pin AW43

within 500mils. Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 5 of 36
5 4 3 2 1
 A
B
C
D

5
5

BD28 VCC_101 VCCP_021 AL37

BB26 VCC_102 VCCP_022 AN37
BD26 VCC_103 VCCP_023 AP38
B22 VCC_104 VCCP_024 B32
B24 VCC_105 VCCP_025 C33
D22 VCC_106 VCCP_026 D32
D24 VCC_107 VCCP_027 E35
F24 VCC_108 VCCP_028 E33
F22 VCC_109 VCCP_029 F34
H24 VCC_110 VCCP_030 G35
H22 VCC_111 VCCP_031 F36
K24 VCC_112 VCCP_032 H36
K22 VCC_113 VCCP_033 J35
M24 VCC_114 VCCP_034 L35
M22 VCC_115 VCCP_035 N35
P24 VCC_116 VCCP_036 K36
P22 VCC_117 VCCP_037 R35
T24 VCC_118 VCCP_038 U35
T22 VCC_119 VCCP_039 P36
V24 VCC_120 VCCP_040 V36
V22 VCC_121 VCCP_041 W35
Y24 VCC_122 VCCP_042 AA35
Y22 VCC_123 VCCP_043 AC35
AB24 VCC_124 VCCP_044 AB36
AB22 VCC_125 VCCP_045 AE35
AD24 VCC_126 VCCP_046 AG35
AD22 VCC_127 VCCP_047 AJ35
AF24 VCC_128 VCCP_048 AF36
AF22 VCC_129 VCCP_049 AL35
AH24 VCC_130 VCCP_050 AN35
AH22 VCC_131 VCCP_051 AK36
AK24 VCC_132 VCCP_052 AP36
AK22 VCC_133 VCCP_053 B12
AM24 B14

4
4

VCC_134 VCCP_054
AM22 VCC_135 VCCP_055 C13
AP24 VCC_136 VCCP_056 D12
AP22 VCC_137 VCCP_057 D14
AT24 VCC_138 VCCP_058 E13
AT22 VCC_139 VCCP_059 F14
AV24 VCC_140 VCCP_060 F12
AV22 VCC_141 VCCP_061 G13
AY24 VCC_142 VCCP_062 H14
AY22 VCC_143 VCCP_063 H12
BB24 VCC_144 VCCP_064 J13
BB22 VCC_145 VCCP_065 K14
BD24 VCC_146 VCCP_066 K12
BD22 VCC_147 VCCP_067 L13
B16 VCC_148 VCCP_068 L11
B18 VCC_149 VCCP_069 M14
B20 VCC_150 VCCP_070 N13
D16 VCC_151 VCCP_071 N11
D18 VCC_152 VCCP_072 K10
F18 VCC_153 VCCP_073 P14
F16 VCC_154 VCCP_074 P12
H18 VCC_155 VCCP_075 R13
H16 VCC_156 VCCP_076 R11
D20 VCC_157 VCCP_077 T14
F20 VCC_158 VCCP_078 U13
H20 VCC_159 VCCP_079 U11
K18 VCC_160 VCCP_080 V14
K16 VCC_161 VCCP_081 V12
M18 VCC_162 VCCP_082 W13
M16 VCC_163 VCCP_083 W11
K20 VCC_164 VCCP_084 P10
M20 VCC_165 VCCP_085 V10
P18 VCC_166 VCCP_086 Y14
P16 AA13

Issued Date
VCC_167 VCCP_087
T18 VCC_168 VCCP_088 AA11

3
3

T16 VCC_169 VCCP_089 AB14

V18 AB12

Security Classification
VCC_170 VCCP_090
V16 VCC_171 VCCP_091 AC13
P20 VCC_172 VCCP_092 AC11
T20 VCC_173 VCCP_093 AD14
V20 VCC_174 VCCP_094 AB10
Y18 VCC_175 VCCP_095 AE13
Y16 VCC_176 VCCP_096 AE11
AB18 VCC_177 VCCP_097 AF14
AB16 VCC_178 VCCP_098 AF12
AD18 VCC_179 VCCP_099 AG13
AD16 VCC_180 VCCP_100 AG11
Y20 AH14

2006/02/13
VCC_181 VCCP_101
AB20 VCC_182 VCCP_102 AJ13
AD20 VCC_183 VCCP_103 AJ11
AF18 VCC_184 VCCP_104 AF10
AF16 VCC_185 VCCP_105 AK14
AH18 VCC_186 VCCP_106 AK12
AH16 VCC_187 VCCP_107 AL13
AF20 VCC_188 VCCP_108 AL11
AH20 VCC_189 VCCP_109 AN13
AK18 VCC_190 VCCP_110 AN11
AK16 VCC_191 VCCP_111 AP12
AM18 VCC_192 VCCP_112 AR13
AM16 VCC_193 VCCP_113 AR11
AP18 VCC_194 VCCP_114 AK10
AP16 VCC_195 VCCP_115 AP10
AK20 VCC_196 VCCP_116 AU13
AM20 VCC_197 VCCP_117 AU11

Compal Secret Data

AP20 VCC_198 VCCP_118 L9

Deciphered Date
AT18 VCC_199 VCCP_119 L7
AT16 VCC_200 VCCP_120 N9
AV18 VCC_201 VCCP_121 N7
AV16 VCC_202 VCCP_122 R9
AY18 R7

2
2

VCC_203 VCCP_123
AY16 VCC_204 VCCP_124 U9
AT20 VCC_205 VCCP_125 U7
AV20 VCC_206 VCCP_126 W9
AY20 VCC_207 VCCP_127 W7
BB18 VCC_208 VCCP_128 AA9
BB16 AA7
2006/03/10

VCC_209 VCCP_129
BD18 VCC_210 VCCP_130 AC9
BD16 VCC_211 VCCP_131 AC7
BB20 VCC_212 VCCP_132 AE9
BD20 VCC_213 VCCP_133 AE7
AM14 VCC_214 VCCP_134 AG9
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AP14 VCC_215 VCCP_135 AG7

AT14 VCC_216 VCCP_136 AJ9
AV14 VCC_217 VCCP_137 AJ7
AY14 VCC_218 VCCP_138 AL9
BB14 VCC_219 VCCP_139 AL7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

BD14 VCC_220 VCCP_140 AN9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AN7
Title

Date:

VCCP_141
+VCC_CORE

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom

AF38 VCCP_017 VCCP_142 AR9

AG37 VCCP_018 VCCP_143 AR7
AJ37 VCCP_019 VCCP_144 A33
AK38 VCCP_020 VCCP_145 A13
+VCCP
+VCCP

401554
U1F

Size Document Number

Wednesday, June 03, 2009

1
1

PENRYN SFF_UFCBGA956

Sheet
6
of
Compal Electronics, Inc.

36
SCHEMATIC, M/B LA-4021P
Rev
B
A
B
C
D
 5 4 3 2 1

U1D U1E +VCC_CORE Mid Frequence Decoupling

B42 VSS[001] VSS[082] AM36 G25 VSS_164 VSS_280 AA15
F44 VSS[002] VSS[083] AR35 G23 VSS_165 VSS_281 AC15
D44 VSS[003] VSS[084] AU35 G21 VSS_166 VSS_282 Y10
D42 VSS[004] VSS[085] AV34 J25 VSS_167 VSS_283 AD10

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
F42 VSS[005] VSS[086] AW35 J23 VSS_168 VSS_284 AH12
H42 VSS[006] VSS[087] AW33 J21 VSS_169 VSS_285 AE15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K42 VSS[007] VSS[088] AY34 L25 VSS_170 VSS_286 AG15
M42 VSS[008] VSS[089] AT36 L23 VSS_171 VSS_287 AJ15

C8

C9

C10

C16

C17

C18

C21

C22

C23

C29

C30

C31

C11

C12

C13

C14

C15

C19

C20

C24

C25

C26

C27

C28
P42 VSS[009] VSS[090] AV36 L21 VSS_172 VSS_288 AH10
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
T42 VSS[010] VSS[091] BA33 N25 VSS_173 VSS_289 AM12
V42 VSS[011] VSS[092] BC33 N23 VSS_174 VSS_290 AL15
Y42 VSS[012] VSS[093] BB36 N21 VSS_175 VSS_291 AN15
D D
AB42 VSS[013] VSS[094] BD36 R25 VSS_176 VSS_292 AR15
AD42 VSS[014] VSS[095] C27 R23 VSS_177 VSS_293 AM10
AF42 VSS[015] VSS[096] C29 R21 VSS_178 VSS_294 AT12
AH42 VSS[016] VSS[097] C31 U25 VSS_179 VSS_295 AV12
AK42 VSS[017] VSS[098] E29 U23 VSS_180 VSS_296 AW13
AM42 VSS[018] VSS[099] E27 U21 VSS_181 VSS_297 AW11
AP42 VSS[019] VSS[100] G29 W25 VSS_182 VSS_298 AY12
AY44 VSS[020] VSS[101] G27 W23 VSS_183 VSS_299 AU15
AV44 VSS[021] VSS[102] E31 W21 VSS_184 VSS_300 AW15
AT42 VSS[022] VSS[103] G31 AA25 VSS_185 VSS_301 AT10
+VCC_CORE
AV42 VSS[023] VSS[104] J29 AA23 VSS_186 VSS_302 BA13
AY42 VSS[024] VSS[105] J27 AA21 VSS_187 VSS_303 BA11 High Frequence Decoupling
BA43 VSS[025] VSS[106] L29 AC25 VSS_188 VSS_304 BB12
BB42 VSS[026] VSS[107] L27 AC23 VSS_189 VSS_305 BC11
C39 VSS[027] VSS[108] N29 AC21 VSS_190 VSS_306 BA15

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
E39 VSS[028] VSS[109] N27 AE25 VSS_191 VSS_307 BC15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
G37 VSS[029] VSS[110] J31 AE23 VSS_192 VSS_308 B6
H38 VSS[030] VSS[111] L31 AE21 VSS_193 VSS_309 D6

C620

C621

C622

C623

C624

C625

C626

C627

C628

C629

C630

C631

C632

C633

C634

C635

C636

C637

C638

C639

C640

C641

C642

C643
J39 VSS[031] VSS[112] N31 AG25 VSS_194 VSS_310 E9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
L39 VSS[032] VSS[113] R29 AG23 VSS_195 VSS_311 F6
M38 VSS[033] VSS[114] R27 AG21 VSS_196 VSS_312 G9
N39 VSS[034] VSS[115] U29 AJ25 VSS_197 VSS_313 H6
R39 VSS[035] VSS[116] U27 AJ23 VSS_198 VSS_314 K8
T38 VSS[036] VSS[117] R31 AJ21 VSS_199 VSS_315 K6
U39 VSS[037] VSS[118] U31 AL25 VSS_200 VSS_316 M8
W39 VSS[038] VSS[119] W29 AL23 VSS_201 VSS_317 M6
Y38 VSS[039] VSS[120] W27 AL21 VSS_202 VSS_318 P8 6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
AA39 VSS[040] VSS[121] W31 AN25 VSS_203 VSS_319 P6
AC39 VSS[041] VSS[122] AA29 AN23 VSS_204 VSS_320 T8
AD38 VSS[042] VSS[123] AA27 AN21 VSS_205 VSS_321 T6
AE39 VSS[043] VSS[124] AC29 AR25 VSS_206 VSS_322 V8
AG39 VSS[044] VSS[125] AC27 AR23 VSS_207 VSS_323 V6
C C
AH38 VSS[045] VSS[126] AA31 AR21 VSS_208 VSS_324 U5
AJ39 VSS[046] VSS[127] AC31 AU25 VSS_209 VSS_325 Y8
AL39 VSS[047] VSS[128] AE29 AU23 VSS_210 VSS_326 Y6
AM38 AE27 AU21 AB8
AN39
AR39
VSS[048]
VSS[049]
VSS[129]
VSS[130] AG29
AG27
AW25
AW23
VSS_211
VSS_212
VSS_327
VSS_328 AB6
AD8
ESR <= 1.5m ohm
VSS[050] VSS[131] VSS_213 VSS_329
AR37 VSS[051] VSS[132] AJ29 AW21 VSS_214 VSS_330 AD6
AT38 AJ27 BA25 AF8
AU39
VSS[052]
VSS[053]
VSS[133]
VSS[134] AE31 BA23
VSS_215
VSS_216
VSS_331
VSS_332 AF6 Near CPU CORE regulator
AU37 VSS[054] VSS[135] AG31 BA21 VSS_217 VSS_333 AH8
AW39 VSS[055] VSS[136] AJ31 BC25 VSS_218 VSS_334 AH6
AW37 VSS[056] VSS[137] AL29 BC23 VSS_219 VSS_335 AK8
+VCC_CORE
BA39 VSS[057] VSS[138] AL27 BC21 VSS_220 VSS_336 AK6
BC41 VSS[058] VSS[139] AN29 C17 VSS_221 VSS_337 AM8
BD40 VSS[059] VSS[140] AN27 C19 VSS_222 VSS_338 AM6
BD38 VSS[060] VSS[141] AL31 E19 VSS_223 VSS_339 AP8
B36 VSS[061] VSS[142] AN31 E17 VSS_224 VSS_340 AP6

220U_D2_2VK_R9

220U_D2_2VK_R9

220U_D2_2VK_R9
H34 VSS[062] VSS[143] AR29 G19 VSS_225 VSS_341 AT8 1 1 1

C34

C35

C36
D36 VSS[063] VSS[144] AR27 G17 VSS_226 VSS_342 AT6
K34 AR31 J19 AU9 + + +
VSS[064] VSS[145] VSS_227 VSS_343
M34 VSS[065] VSS[146] AU29 J17 VSS_228 VSS_344 AV6
M36 VSS[066] VSS[147] AU27 L19 VSS_229 VSS_345 AU7
2 2 2
P34 VSS[067] VSS[148] AW29 L17 VSS_230 VSS_346 AW9
T34 VSS[068] VSS[149] AW27 N19 VSS_231 VSS_347 AY6
V34 VSS[069] VSS[150] AU31 N17 VSS_232 VSS_348 BA9
T36 VSS[070] VSS[151] AW31 R19 VSS_233 VSS_349 BB6
Y34 VSS[071] VSS[152] BA29 R17 VSS_234 VSS_350 BC9
AB34 VSS[072] VSS[153] BA27 U19 VSS_235 VSS_351 BD6
AD34 VSS[073] VSS[154] BC29 U17 VSS_236 VSS_352 B4
Y36 VSS[074] VSS[155] BC27 W19 VSS_237 VSS_353 C3
AD36 VSS[075] VSS[156] BA31 W17 VSS_238 VSS_354 E3 Del C37 to improve power plan. 6/14
AF34 VSS[076] VSS[157] BC31 AA19 VSS_239 VSS_355 G3
B B
AH34 VSS[077] VSS[158] C21 AA17 VSS_240 VSS_356 J3
AH36 VSS[078] VSS[159] C23 AC19 VSS_241 VSS_357 L3
AK34 VSS[079] VSS[160] C25 AC17 VSS_242 VSS_358 N3
AM34 VSS[080] VSS[161] E25 AE19 VSS_243 VSS_359 R3
AP34 VSS[081] VSS[162] E23 AE17 VSS_244 VSS_360 U3
VSS[163] E21 AG19 VSS_245 VSS_361 W3
AG17 VSS_246 VSS_362 AA3
AJ19 VSS_247 VSS_363 AC3
PENRYN SFF_UFCBGA956 AJ17 AE3
VSS_248 VSS_364
AL19 VSS_249 VSS_365 AG3
AL17 VSS_250 VSS_366 AJ3
AN19 AL3 +VCCP
VSS_251 VSS_367
AN17 VSS_252 VSS_368 AN3
AR19 VSS_253 VSS_369 AR3
AR17 VSS_254 VSS_370 AU3
AU19 VSS_255 VSS_371 AW3
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
AU17 VSS_256 VSS_372 BA3 1 1 1 1 1 1 1 1 1 1 1 1
AW19 VSS_257 VSS_373 BC3
AW17 VSS_258 VSS_374 D2
C38

C39

C40

C41

C42

C43

C552

C553

C554

C555

C556

C557
BA19 VSS_259 VSS_375 E1
2 2 2 2 2 2 2 2 2 2 2 2
BA17 VSS_260 VSS_376 G1
BC19 VSS_261 VSS_377 AW1
BC17 VSS_262 VSS_378 BA1
C11 VSS_263 VSS_379 BB2
C15 VSS_264 VSS_380 A41
E15 VSS_265 VSS_381 A39
G15 VSS_266 VSS_382 A29
H10 VSS_267 VSS_383 A27
M12 VSS_268 VSS_384 A31
J15 VSS_269 VSS_385 A25
L15 VSS_270 VSS_386 A23
N15 VSS_271 VSS_387 A21
A A
M10 VSS_272 VSS_388 A19
T12 VSS_273 VSS_389 A17
R15 VSS_274 VSS_390 A11
U15 VSS_275 VSS_391 A15
W15 VSS_276 VSS_392 A7
T10 VSS_277 VSS_393 A5
Y12 VSS_278 VSS_394 A9
AD12 BD4
VSS_279 VSS_395 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
PENRYN SFF_UFCBGA956
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 7 of 36
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] <4> U4B

<5> H_D#[0..63] U4A
L15 H_A#3 J43
H_A#_3 T5 RSVD1
H_D#0 J7 B14 H_A#4 L43 BB32 M_CLK_DDR0 <14>
H_D#_0 H_A#_4 T6 RSVD2 SA_CK_0
H_D#1 H6 C15 H_A#5 J41 BA25

DDR CLK/ CONTROL/COMPENSATION

H_D#_1 H_A#_5 T7 RSVD3 SA_CK_1 M_CLK_DDR1 <14>
H_D#2 L11 D12 H_A#6 L41 BA33 M_CLK_DDR2 <15>
H_D#_2 H_A#_6 T8 RSVD4 SB_CK_0
H_D#3 J3 F14 H_A#7 AN11 BA23 M_CLK_DDR3 <15>
H_D#_3 H_A#_7 T9 RSVD5 SB_CK_1
H_D#4 H4 G17 H_A#8 AM10
H_D#_4 H_A#_8 T10 RSVD6
H_D#5 G3 B12 H_A#9 Add them for Boundary Scan. 10/23 AK10 BA31
H_D#_5 H_A#_9 T11 RSVD7 SA_CK#_0 M_CLK_DDR#0 <14>
H_D#6 K10 J15 H_A#10 AL11 BC25
H_D#_6 H_A#_10 T12 RSVD8 SA_CK#_1 M_CLK_DDR#1 <14>
H_D#7 K12 D16 H_A#11 F12 BC33
H_D#_7 H_A#_11 T13 RSVD9 SB_CK#_0 M_CLK_DDR#2 <15>

RSVD
H_D#8 L1 C17 H_A#12 R251 1 2 @ 1K_0402_5% TCK AN45 BB24
H_D#_8 H_A#_12 RSVD10 SB_CK#_1 M_CLK_DDR#3 <15>
H_D#9 M10 D14 H_A#13 R281 1 2 @ 4.7K_0402_5% TDI AP44
H_D#10 H_D#_9 H_A#_13 H_A#14 R311 @ 4.7K_0402_5% TDO RSVD11
M6 H_D#_10 H_A#_14 K16 1 2 AT44 RSVD12 SA_CKE_0 BC35 DDR_CKE0_DIMMA <14>
H_D#11 N11 F16 H_A#15 +3VS R619 1 2 @ 1K_0402_5% TMS AN47 BE33
D H_D#_11 H_A#_15 RSVD13 SA_CKE_1 DDR_CKE1_DIMMA <14> D
H_D#12 L7 B16 H_A#16 C27 BE37
H_D#_12 H_A#_16 T18 RSVD14 SB_CKE_0 DDR_CKE2_DIMMB <15>
H_D#13 K6 C21 H_A#17 D30 BC37
H_D#_13 H_A#_17 T19 RSVD15 SB_CKE_1 DDR_CKE3_DIMMB <15>
H_D#14 M4 D18 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
K4 H_D#_15 H_A#_19 J19 T20 J9 RSVD17 SA_CS#_0 BK18 DDR_CS0_DIMMA# <14>
H_D#16 P6 J21 H_A#20 BK16
H_D#_16 H_A#_20 SA_CS#_1 DDR_CS1_DIMMA# <14>
H_D#17 W9 B18 H_A#21 BE23
H_D#_17 H_A#_21 SB_CS#_0 DDR_CS2_DIMMB# <15>
H_D#18 V6 D22 H_A#22 AW42 BC19
H_D#_18 H_A#_22 T21 RSVD20 SB_CS#_1 DDR_CS3_DIMMB# <15>

0.01U_0402_25V7K
H_D#19 H_A#23

2.2U_0603_6.3V4Z
V2 H_D#_19 H_A#_23 G19
H_D#20 P10 J17 H_A#24 BJ17 M_ODT0 <14>
H_D#21 H_D#_20 H_A#_24 H_A#25 +1.8V SA_ODT_0
W7 H_D#_21 H_A#_25 L21 SA_ODT_1 BJ19 M_ODT1 <14>
H_D#22 H_A#26 +1.8V
N9 H_D#_22 H_A#_26 L19 T22 BB20 RSVD22 SB_ODT_0 BC17 M_ODT2 <15>
H_D#23 P4 G21 H_A#27 1 1 BE19 BE17 M_ODT3 <15>
H_D#_23 H_A#_27 T23 RSVD23 SB_ODT_1

1
C44

C45
H_D#24 U9 D20 H_A#28 BF20
H_D#_24 H_A#_28 T24 RSVD24
H_D#25 V4 K22 H_A#29 BF18 BL25 SMRCOMP R42 1 2 80.6_0402_1%
H_D#_25 H_A#_29 T25 RSVD25 SM_RCOMP
H_D#26 U1 F18 H_A#30 R39 BK26 SMRCOMP# R43 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 2 2 1K_0402_1% SM_RCOMP#
W3 H_D#_27 H_A#_31 K20
H_D#28 V10 F20 H_A#32 BK32 SMRCOMP_VOH

2
H_D#29 H_D#_28 H_A#_32 H_A#33 SMRCOMP_VOH SM_RCOMP_VOH SMRCOMP_VOL
U7 H_D#_29 H_A#_33 F22 SM_RCOMP_VOL BL31
H_D#30 W11 B20 H_A#34
H_D#_30 H_A#_34

1
H_D#31 U11 A19 H_A#35 BC51 V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 R40 SM_VREF SM_PWROK R44
AC11 H_D#_32 SM_PWROK AY37 1 2 10K_0402_1%
H_D#33 AC9 F10 3.01K_0402_1% BH20 SM_REXT R45 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# <4> SM_REXT
H_D#34 Y4
HOST A15 BA37 TP_SM_DRAMRST# T26 PAD
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4> SM_DRAMRST#
H_D#35 Y10 C19 H_ADSTB#1 <4>

2
H_D#36 H_D#_35 H_ADSTB#_1 SMRCOMP_VOL
AB6 H_D#_36 H_BNR# C9 H_BNR# <4> DPLL_REF_CLK B42 CLK_MCH_DREFCLK <16>
H_D#37 AA9 B8 D42
H_D#_37 H_BPRI# H_BPRI# <4> DPLL_REF_CLK# CLK_MCH_DREFCLK# <16>

1
0.01U_0402_25V7K
H_D#38

2.2U_0603_6.3V4Z
AB10 H_D#_38 H_BREQ# C11 H_BR0# <4> DPLL_REF_SSCLK B50 MCH_SSCDREFCLK <16>
H_D#39 AA1 E5 1 1 R41 D50
H_D#_39 H_DEFER# H_DEFER# <4> DPLL_REF_SSCLK# MCH_SSCDREFCLK# <16>
H_D#40 AC3 D6 1K_0402_1%
H_D#_40 H_DBSY# H_DBSY# <4>

C46

C47
H_D#41 AC7 AH10 R49
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16> PEG_CLK CLK_MCH_3GPLL <16>
H_D#42 AD12 AJ11 P50
CLK_MCH_BCLK# <16> CLK_MCH_3GPLL# <16>

2
H_D#43 H_D#_42 HPLL_CLK# 2 2 PEG_CLK#
AB4 G11

CLK
C H_D#_43 H_DPWR# H_DPWR# <5> C
H_D#44 Y6 H2
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AD10 C7
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AA11 F8 AG55
H_D#_46 H_HITM# H_HITM# <4> DMI_RXN_0 DMI_TXN0 <22>
H_D#47 AB2 A11 AL49
H_D#_47 H_LOCK# H_LOCK# <4> DMI_RXN_1 DMI_TXN1 <22>
H_D#48 AD4 D8 AH54
H_D#_48 H_TRDY# H_TRDY# <4> DMI_RXN_2 DMI_TXN2 <22>
H_D#49 AE7 AL47
H_D#_49 DMI_RXN_3 DMI_TXN3 <22>
H_D#50 AD2
H_D#51 H_D#_50
AD6 H_D#_51 DMI_RXP_0 AG53 DMI_TXP0 <22>
H_D#52 AE3 K26 AK50
H_D#_52 <16> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <22>
H_D#53 AG9 L9 G23 AH52
H_D#_53 H_DINV#_0 H_DINV#0 <5> <16> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <22>
H_D#54 AG7 N7 G25 AL45
H_D#_54 H_DINV#_1 H_DINV#1 <5> <16> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <22>
H_D#55 AE11 AA7 J25
H_D#_55 H_DINV#_2 H_DINV#2 <5> T27 CFG_3
H_D#56 AK6 AG3 L25 AG49
H_D#_56 H_DINV#_3 H_DINV#3 <5> T28 CFG_4 DMI_TXN_0 DMI_RXN0 <22>
H_D#57 AF6 L27 AJ49
H_D#_57 <10> CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 <22>
H_D#58 AJ9 K2 F24 AJ47
H_D#_58 H_DSTBN#_0 H_DSTBN#0 <5> <10> CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 <22>
H_D#59 AH6 N3 D24 AG47
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5> <10> CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 <22>
H_D#60 AF12 AA3 D26

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5> T88 CFG_8

CFG
H_D#61 AH4 AF4 J23 AF50
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5> <10> CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 <22>
H_D#62 AJ7 B26 AH50
H_D#_62 <10> CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 <22>
H_D#63 AE9 L3 A23 AJ45
H_D#_63 H_DSTBP#_0 H_DSTBP#0 <5> T89 CFG_11 DMI_TXP_2 DMI_RXP2 <22>
H_DSTBP#_1 M2 H_DSTBP#1 <5> <10> CFG12 C23 CFG_12 DMI_TXP_3 AG45 DMI_RXP3 <22>
H_DSTBP#_2 Y2 H_DSTBP#2 <5> <10> CFG13 B24 CFG_13
H_SWNG B6 AF2 B22
H_SWING H_DSTBP#_3 H_DSTBP#3 <5> T90 CFG_14
H_RCOMP D4 K24
H_RCOMP T91 CFG_15
H_REQ#_0 J13 H_REQ#0 <4> <10> CFG16 C25 CFG_16

GRAPHICS VID
H_REQ#_1 L13 H_REQ#1 <4> T92 L23 CFG_17
H_REQ#_2 C13 H_REQ#2 <4> T93 L33 CFG_18
H_REQ#_3 G13 H_REQ#3 <4> <10> CFG19 K32 CFG_19
<4> H_RESET# J11 H_CPURST# H_REQ#_4 G15 H_REQ#4 <4> <10> CFG20 K34 CFG_20 GFX_VID_0 G33 DFGT_VID_0 <43>
<5> H_CPUSLP# G9 H_CPUSLP# GFX_VID_1 G37 DFGT_VID_1 <43>
H_RS#_0 F4 H_RS#0 <4> GFX_VID_2 F38 DFGT_VID_2 <43>
H_RS#_1 F2 H_RS#1 <4> GFX_VID_3 F36 DFGT_VID_3 <43>
B B
H_RS#_2 G7 H_RS#2 <4> <22> PM_BMBUSY# J35 PM_SYNC# GFX_VID_4 G35 DFGT_VID_4 <43>
L17 H_AVREF <5,21,42> H_DPRSTP# F6 PM_DPRSTP#
H_VREF K18 PM_EXTTS#0 J39 Modify in 9/26
H_DVREF <14> PM_EXTTS#0 PM_EXT_TS#_0

PM
PM_EXTTS#1 L39
<15> PM_EXTTS#1 PM_EXT_TS#_1
Trace < = 500mils CANTIGA GMCH SFF_FCBGA1363 R327 1 2 0_0402_5% AY39 G39
<22,33,42,43> PM_PWROK PWROK GFX_VR_EN GFXVR_EN <43> +1.05VM
layout note: R428 1 2 100_0402_1% BB18
<20,26,32> PLT_RST# RSTIN#
<4,21> H_THERMTRIP# 1 2 K28 THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace width, <22,42> PM_DPRSLPVR R49 0_0402_5% K36 DPRSLPVR

1
spacing and impedance (55 ohm) same as FSB data layout note:
Add R428 in 9/26

C48
AK52 R50
CL_CLK CL_CLK0 <22>
traces Place them close to U4 pin BC51. 1 AK54 1K_0402_1%
CL_DATA CL_DATA0 <22>
A7 NC_1 CL_PWROK AW40 M_PWROK <22,35>

ME
A49 AL53 CL_RST# <22>

2
+1.8V NC_2 CL_RST#

@ 0.1U_0402_16V4Z
Layout Note: Layout Note: V_DDR_MCH_REF trace A52 AL55 CL_VREF
2 NC_3 CL_VREF
width and spacing is 20/20. A54
H_RCOMP / H_VREF / H_SWNG NC_4

1
B54 NC_5 1
1

trace width and spacing is 10/20 D55 C49 R51

R52 NC_6 511_0402_1%
G55 NC_7 DDPC_CTRLCLK F34 T29
10K_0402_1%

NC
BE55 F32 0.1U_0402_16V4Z
NC_8 DDPC_CTRLDATA T30 2
BH55 B38 T31

2
+VCCP NC_9 SDVO_CTRLCLK
BK55 A37

MISC
T32
2

+VCCP V_DDR_MCH_REF NC_10 SDVO_CTRLDATA

<14,15> V_DDR_MCH_REF BK54 NC_11 CLKREQ# C31 CLKREQ#_B <16>
BL54 NC_12 ICH_SYNC# K42 MCH_ICH_SYNC# <22>
221_0603_1%
1K_0402_1%

C50
0.1U_0402_16V4Z

BL52 NC_13
1

1 BL49 NC_14
R53 R54 R55 BL7 D10 TSATN# R616 1 2 54.9_0402_1% +VCCP
10K_0402_1% NC_15 TSATN#
BL4 NC_16
BL2 NC_17
2
BK2
2

H_VREF H_RCOMP H_SWNG NC_18

BK1 NC_19
BH1 NC_20
24.9_0402_1%
R59

0.1U_0402_16V4Z

BE1 NC_21
1

1
100_0402_1%

A A
0.1U_0402_16V4Z

1 1 G1 NC_22 HDA_BCLK C29 Romoved, cause

C51 R60 R61 C52 B30
HDA_RST# don't need HDMI.
2K_0402_1%

HDA
HDA_SDI D28
+3VS
HDA_SDO A27 7/19
2 2
B28
2

HDA_SYNC
PM_EXTTS#0 R46 1 2 10K_0402_5%

@ Near B6 pin PM_EXTTS#1 R47 1 2 10K_0402_5%

Security Classification Compal Secret Data
CANTIGA GMCH SFF_FCBGA1363
Compal Electronics, Inc.
within 100 mils from NB Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
Del R48. 9/27
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 8 of 36
5 4 3 2 1
 5 4 3 2 1

D D

<14> DDR_A_D[0..63] <15> DDR_B_D[0..63]

U4D U4E
DDR_A_D0 AP46 BC21 DDR_B_D0 AP54 BJ13
SA_DQ_0 SA_BS_0 DDR_A_BS0 <14> SB_DQ_0 SB_BS_0 DDR_B_BS0 <15>
DDR_A_D1 AU47 BJ21 DDR_B_D1 AM52 BK12
SA_DQ_1 SA_BS_1 DDR_A_BS1 <14> SB_DQ_1 SB_BS_1 DDR_B_BS1 <15>
DDR_A_D2 AT46 BJ41 DDR_B_D2 AR55 BK38
SA_DQ_2 SA_BS_2 DDR_A_BS2 <14> SB_DQ_2 SB_BS_2 DDR_B_BS2 <15>
DDR_A_D3 AU49 DDR_B_D3 AV54
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AR45 SA_DQ_4 SA_RAS# BH22 DDR_A_RAS# <14> AM54 SB_DQ_4
DDR_A_D5 AN49 BK20 DDR_B_D5 AN53 BE21
SA_DQ_5 SA_CAS# DDR_A_CAS# <14> SB_DQ_5 SB_RAS# DDR_B_RAS# <15>
DDR_A_D6 AV50 BL15 DDR_A_WE# <14> DDR_B_D6 AT52 BH14
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# <15>
DDR_A_D7 AP50 DDR_B_D7 AU53 BK14 DDR_B_WE# <15>
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AW47 SA_DQ_8 AW53 SB_DQ_8
DDR_A_D9 BD50 DDR_B_D9 AY52
DDR_A_D10 SA_DQ_9 DDR_B_D10 SB_DQ_9
AW49 SA_DQ_10 DDR_A_DM[0..7] <14> BB52 SB_DQ_10
DDR_A_D11 BA49 AT50 DDR_A_DM0 DDR_B_D11 BC53
SA_DQ_11 SA_DM_0 SB_DQ_11 DDR_B_DM[0..7] <15>
DDR_A_D12 BC49 BB50 DDR_A_DM1 DDR_B_D12 AV52 AP52 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
DDR_A_D14 BA47 BE39 DDR_A_DM3 DDR_B_D14 BD52 BJ49 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43

A
DDR_A_D16 BF46 BE7 DDR_A_DM5 DDR_B_D16 BF54 BH12 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
DDR_A_D18 BF50 AR9 DDR_A_DM7 DDR_B_D18 BH48 AY2 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BF48 SA_DQ_19 DDR_A_DQS[0..7] <14> BK48 SB_DQ_19 SB_DM_7 AJ3
DDR_A_D20 BC43 AR47 DDR_A_DQS0 DDR_B_D20 BE53
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] <15>

MEMORY
DDR_A_D21 BE49 BA45 DDR_A_DQS1 DDR_B_D21 BH52 AR53 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BA43 SA_DQ_22 SA_DQS_2 BE45 BK46 SB_DQ_22 SB_DQS_1 BA53
DDR_A_D23 BE47 BC41 DDR_A_DQS3 DDR_B_D23 BJ47 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BH50
DDR_A_D24 BF42 BC13 DDR_A_DQS4 DDR_B_D24 BL45 BK42 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BC39 SA_DQ_25 SA_DQS_5 BB10 BJ45 SB_DQ_25 SB_DQS_4 BH8
DDR_A_D26 BF44 BA7 DDR_A_DQS6 DDR_B_D26 BL41 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
BF40 SA_DQ_27 SA_DQS_7 AN7 DDR_A_DQS#[0..7] <14> BH44 SB_DQ_27 SB_DQS_6 AV2
DDR_A_D28 BB40 AR49 DDR_A_DQS#0 DDR_B_D28 BH46 AM2 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] <15> C
DDR_A_D29 BE43 AW45 DDR_A_DQS#1 DDR_B_D29 BK44 AT54 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
BF38 SA_DQ_30 SA_DQS#_2 BC45 BK40 SB_DQ_30 SB_DQS#_1 BB54
DDR_A_D31 BE41 BA41 DDR_A_DQS#3 DDR_B_D31 BJ39 BJ51 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BA15 SA_DQ_32 SA_DQS#_4 BA13 BK10 SB_DQ_32 SB_DQS#_3 BH42
DDR_A_D33 BE11 BA11 DDR_A_DQS#5 DDR_B_D33 BH10 BK8 DDR_B_DQS#4
SYSTEM

DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5

BE15 SA_DQ_34 SA_DQS#_6 BA9 BK6 SB_DQ_34 SB_DQS#_5 BC3
DDR_A_D35 BF14 AN9 DDR_A_DQS#7 DDR_B_D35 BH6 AW3 DDR_B_DQS#6
DDR_A_D36 SA_DQ_35 SA_DQS#_7 DDR_B_D36 SB_DQ_35 SB_DQS#_6 DDR_B_DQS#7

SYSTEM
BB14 SA_DQ_36 DDR_A_MA[0..14] <14> BJ9 SB_DQ_36 SB_DQS#_7 AN3
DDR_A_D37 BC15 BC23 DDR_A_MA0 DDR_B_D37 BL11 DDR_B_MA[0..14] <15>
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BE13 SA_DQ_38 SA_MA_1 BF22 BG5 SB_DQ_38 SB_MA_0 BJ15
DDR_A_D39 BF16 BE31 DDR_A_MA2 DDR_B_D39 BJ5 BJ33 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BF10 SA_DQ_40 SA_MA_3 BC31 BG3 SB_DQ_40 SB_MA_2 BH24
DDR_A_D41 BC11 BH26 DDR_A_MA4 DDR_B_D41 BF4 BA17 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
BF8 SA_DQ_42 SA_MA_5 BJ35 BD4 SB_DQ_42 SB_MA_4 BF36
DDR_A_D43 BG7 BB34 DDR_A_MA6 DDR_B_D43 BA3 BH36 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BC7 SA_DQ_44 SA_MA_7 BH32 BE5 SB_DQ_44 SB_MA_6 BF34
DDR_A_D45 BC9 BB26 DDR_A_MA8 DDR_B_D45 BF2 BK34 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
DDR

BD6 SA_DQ_46 SA_MA_9 BF32 BB4 SB_DQ_46 SB_MA_8 BJ37

DDR_A_D47 BF12 BA21 DDR_A_MA10 DDR_B_D47 AY4 BH40 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV6 SA_DQ_48 SA_MA_11 BG25 BA1 SB_DQ_48 SB_MA_10 BH16
DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
BB6 SA_DQ_49 SA_MA_12 BH34 AP2 SB_DQ_49 SB_MA_11 BK36
DDR_A_D50 AW7 BH18 DDR_A_MA13 DDR_B_D50 AU1 BH38 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AY6 SA_DQ_51 SA_MA_14 BE25 AT2 SB_DQ_51 SB_MA_13 BJ11
DDR_A_D52 AT10 DDR_B_D52 AT4 BL37 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AW11 SA_DQ_53 AV4 SB_DQ_53
DDR_A_D54 AU11 DDR_B_D54 AU3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AW9 SA_DQ_55 AR3 SB_DQ_55
DDR_A_D56 AR11 DDR_B_D56 AN1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AT6 SA_DQ_57 AP4 SB_DQ_57
DDR_A_D58 AP6 DDR_B_D58 AL3
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AL7 SA_DQ_59 AJ1 SB_DQ_59
DDR_A_D60 AR7 DDR_B_D60 AK4
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AT12 SA_DQ_61 AM4 SB_DQ_61
DDR_A_D62 AM6 DDR_B_D62 AH2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AU7 SA_DQ_63 AK2 SB_DQ_63
CANTIGA GMCH SFF_FCBGA1363 CANTIGA GMCH SFF_FCBGA1363

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 9 of 36
5 4 3 2 1
 5 4 3 2 1

U4C Strap Pin Table

PEGCOMP trace width +VCC_PEG 000 = FSB 1066MHz
and spacing is 20/25 mils. CFG[2:0] FSB Freq select
<18> BLON_PWM D38 010 = FSB 800MHz
L_BKLT_CTRL PEGCOMP
<18> ENABLT C37 U45 1 2
R65 1 2 10K_0402_5% K38
L_BKLT_EN PEG_COMPI
T44 R64 49.9_0402_1% 011 = FSB 667MHz
+3VS L_CTRL_CLK PEG_COMPO
Others = Reserved
R66 1 2 10K_0402_5% L37 layout note:
L_CTRL_DATA
<18> DDC2_CLK J37 L_DDC_CLK PEG_RX#_0 D52
<18> DDC2_DATA L35 L_DDC_DATA PEG_RX#_1 G49 Place R64 <500mils to U4 pin U45&T44. CFG[4:3] Reserved
PEG_RX#_2 K54
PEG_RX#_3 H50 0 = DMI x 2
<18> ENAVDD B36 L_VDD_EN PEG_RX#_4 M52 CFG5 (DMI select) 1 = DMI x 4
D
R67 1
T33
2 4.22K_0402_1% F50
H46
LVDS_IBG
LVDS_VBG
PEG_RX#_5
PEG_RX#_6
N49
P54
*
0 = The iTPM Host Interface is enable D
P44 LVDS_VREFH PEG_RX#_7 V46 CFG6
K46 Y50 1 = The iTPM Host Interface is disable
<18> TXCLK_L-
<18> TXCLK_L+
D46
B46
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_8
PEG_RX#_9 V52
W49 0 =(TLS)chiper suite with no confidentiality
*
LVDSA_CLK PEG_RX#_10

LVDS
D44 LVDSB_CLK# PEG_RX#_11 AB54 CFG7 (Intel Management
10/18 B44 AD46 1 =(TLS)chiper suite with confidentiality
<18> TXOUT_L0- G45
LVDSB_CLK PEG_RX#_12
PEG_RX#_13 AC55
AE49
Engine Crypto strap)
*
LVDSA_DATA#_0 PEG_RX#_14
<18> TXOUT_L1- F46 LVDSA_DATA#_1 PEG_RX#_15 AF54

GRAPHICS
<18> TXOUT_L2- G41 LVDSA_DATA#_2 CFG8 Reserved
C45 E51
10/19 LVDSA_DATA#_3 PEG_RX_0
F48
PEG_RX_1
<18> TXOUT_L0+ F44 LVDSA_DATA_0 PEG_RX_2 J55 CFG9 0 = Reverse Lane,15->0, 14->1
<18> TXOUT_L1+ G47 LVDSA_DATA_1 PEG_RX_3 J49
F40 M54 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
<18> TXOUT_L2+
10/19 A45
LVDSA_DATA_2
LVDSA_DATA_3
PEG_RX_4
PEG_RX_5 M50
P52
*
PEG_RX_6
B40 LVDSB_DATA#_0 PEG_RX_7 U47 0 = Enable
A41 LVDSB_DATA#_1 PEG_RX_8 AA49 CFG10 (PCIE Lookback enable)
F42 V54 1 = Disable
LVDSB_DATA#_2 PEG_RX_9
*

10/18
For make layout clearance, del D48 LVDSB_DATA#_3 PEG_RX_10 V50
TP for channel B. 10/18 PEG_RX_11 AB52 CFG11 Reserved
D40 LVDSB_DATA_0 PEG_RX_12 AC47
CFG[13:12] (XOR/ALLZ) 00 = Reserved

PCI-EXPRESS
C41 LVDSB_DATA_1 PEG_RX_13 AC53
G43 LVDSB_DATA_2 PEG_RX_14 AD50 01 = XOR Mode Enabled
B48 LVDSB_DATA_3 PEG_RX_15 AF52 10 = All Z Mode Enabled
11 = Normal Operation(Default)
For EMI. 9/26 PEG_TX#_0 L47
F52 CFG[15:14] Reserved
*
R572 1 PEG_TX#_1
2 @ 75_0402_5% J27 TVA_DAC PEG_TX#_2 P46

TV
R336 1 2 @ 75_0402_5% E27 H54
C R337 1 TVB_DAC PEG_TX#_3 C
2 @ 75_0402_5% G27 TVC_DAC PEG_TX#_4 L55 CFG16 (FSB Dynamic ODT) 0 = Disabled
PEG_TX#_5 T46
Del TV_LUMA & CRMA in 10/12. F26 R53 1 = Enabled
TVA_RTN PEG_TX#_6
PEG_TX#_7 U49
T54
*
PEG_TX#_8
PEG_TX#_9 Y46 CFG[18:17] Reserved
B34 TV_DCONSEL_0 PEG_TX#_10 AB46
D34 TV_DCONSEL_1 PEG_TX#_11 W53
Y54 CFG19 (DMI Lane Reversal) 0 = Normal Operation
Tie to GND. 9/28
PEG_TX#_12
PEG_TX#_13 AC49
AF46 (Lane number in Order)
*
PEG_TX#_14
PEG_TX#_15 AD54
1 = Reverse Lane
<17> D_BLUE D_BLUE J29 J47
CRT_BLUE PEG_TX_0
PEG_TX_1 F54
D_GREEN G29 N47 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
<17> D_GREEN
D_RED F30
CRT_GREEN PEG_TX_2
PEG_TX_3 H52
L53 1 = PCIE/SDVO are operating simu.
*
<17> D_RED CRT_RED PEG_TX_4

VGA
PEG_TX_5 R47
E29 CRT_IRTN PEG_TX_6 R55
PEG_TX_7 T50
<17> CRT_DDC_CLK D36 CRT_DDC_CLK PEG_TX_8 T52
<17> CRT_DDC_DATA C35 CRT_DDC_DATA PEG_TX_9 W47
<17> CRT_HSYNC R70 1 2 30.1_0402_1% CRT_HSYNC_R J33 AA47
CRT_HSYNC PEG_TX_10 R91 @ 2.21K_0402_1%
D32 CRT_TVO_IREF PEG_TX_11 W55 <8> CFG5 1 2
<17> CRT_VSYNC R72 1 2 30.1_0402_1% CRT_VSYNC_R G31 Y52
CRT_VSYNC PEG_TX_12 R69 @ 2.21K_0402_1%
PEG_TX_13 AB50 <8> CFG6 1 2
PEG_TX_14 AE47
2

Close to pin D32 and keep AD52 R71 1 2 @ 2.21K_0402_1%

PEG_TX_15 <8> CFG7
R74
30mil space to other 1.02K_0402_1% R75 1 2 @ 2.21K_0402_1%
<8> CFG9
part/trace. CANTIGA GMCH SFF_FCBGA1363
B R76 @ 2.21K_0402_1% B
<8> CFG10 1 2
1

R78 1 2 @ 2.21K_0402_1%
<8> CFG12
R79 1 2 @ 2.21K_0402_1%
<8> CFG13
R93 1 2 @ 2.21K_0402_1%
<8> CFG16

Remove R84 ~ R86 since

already have 75ohm of +3VS
Del R82, R83. 10/18 page17. 10/27
R90 1 2 @ 4.02K_0402_1%
<8> CFG19
R92 1 2 @ 4.02K_0402_1%
<8> CFG20

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 10 of 36
5 4 3 2 1
 5 4 3 2 1

9/27
9/27 +1.05VM_DPLLA +1.05VM +V1.05VM_AXF 9/27 +1.05VM
R94
Change to 330u_R9, 1 2 R95 1 2 0_0603_5%
BLM18PG181SN1D_0603
casue high +VCCP

10U_0805_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z
1

220U_D2_4VM_R15
limitation. 12/14

@
1 1 1
U4H +
+3VS +3VS_DAC_CRT

C54

C53

C55

C56
BLM18PG181SN1D_0603 R13
R96 VTT_1 2 2 2 2

330U_D2E_2.5VM_R9
VTT_2 T12

0.47U_0603_10V7K

2.2U_0805_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
2 1 J31 VCCA_CRT_DAC VTT_3 R11 1
+3VS_DAC_BG VTT_4 T10 1 1 1 1
+3VS
0.1U_0402_16V4Z

10U_0603_6.3V

0.1U_0402_16V4Z

0.01U_0402_16V7K
R9 + 9/27
R97 VTT_5
1 1 1 1 VTT_6 T8

C60
C58

C59

C61

C57
2 1 L31 R7

CRT
BLM18PG181SN1D_0603 VCCA_DAC_BG VTT_7 2 2 2 2 2 +1.05VM_DPLLB +1.05VM +1.8V_SM_CK +1.8V

0.01U_0402_16V7K
D M33 VSSA_DAC_BG VTT_8 T6 9/27 D
C617

C618

C62

C63 R98
R5

22U_0805_6.3V
2 2 2 2 VTT_9 R99
1 1 9/27 VTT_10 T4 1 2 1 2 0_0805_5%
R3 BLM18PG181SN1D_0603
VTT_11

0.1U_0402_16V4Z
+1.05VM_DPLLA J45 VCCA_DPLLA VTT_12 T2 1

2
C64

C65

220U_D2_4VM_R15
@

0_0603_5%
R1 1

VTT
2 2 VTT_13

0.1U_0402_16V4Z

10U_0805_6.3V6M
L49 +
+1.05VM_DPLLB VCCA_DPLLB +3VS_TVDAC +3VS
1 1

PLL

C70

C66

R597
install 0.1U & 10U for wavy issue. 7/29 +1.05VM_HPLL AF10 VCCA_HPLL 2 2
R100

C68

C69
+1.05VM_MPLL AE1 VCCA_MPLL VCCA_TV_DAC K30 1 2
+1.8V_TXLVDS 2 2

10U_0805_6.3V6M
BLM18PG181SN1D_0603

TV

0.01U_0402_16V7K

0.1U_0402_16V4Z
9/27 1
change 0.1U to 22U for wavy issue. 5/20 R101 1 1

A PEG A LVDS
U43 0_0402_5%
+1.5VS_PEG_BG VCCA_LVDS1 +1.05VM_HPLL +1.05VM

C67
1 U41 A31 1 2

D TV/CRT HDA
VCCA_LVDS2 VCC_HDA 2

C71

C72
C73 R102
1000P_0402_50V7K 2 2
V44 VSSA_LVDS 1 2
BLM18PG181SN1D_0603
2

0.1U_0402_16V4Z

4.7U_0805_10V4Z
VCCD_QDAC N34 +1.5VS_QDAC
+1.5VS R104 1 2 0_0603_5% AJ43 1 1
VCCA_PEG_BG
VCCD_TVDAC N32 +1.5VS_TVDAC
1

C74

C75
C78
2 2
9/27 +1.05VM_PEGPLL AG43 VCCA_PEG_PLL Tie to GND. 9/27
0.1U_0402_16V4Z
2
9/27 9/27
AW24 VCCA_SM_1
AU24
+1.05VM +1.05VM_A_SM
AW22
AU22
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
POWER +1.05VM_MPLL
R105
+1.05VM +1.5VS_TVDAC +1.5VS

AU21 1 2 R103
VCCA_SM_5 BLM18PG181SN1D_0603
AW20 VCCA_SM_6 1 2

10U_0805_6.3V6M
BLM18PG181SN1D_0603

0.1U_0402_16V4Z
AU19 VCCA_SM_7

0.01U_0402_16V7K

0.1U_0402_16V4Z
C80

C81
R106 1 2 0_0805_5% AW18 1 1

A SM
C VCCA_SM_8 C
AU18 VCCA_SM_9 1 1
10U_0805_6.3V6M

4.7U_0805_10V4Z

1U_0603_10V4Z
100U_D2_6.3VM

1 1 1 1 AW16 VCCA_SM_10
AU16 VCCA_SM_11 2 2

C76

C77
+ AT16 VCCA_SM_12 2 2
C83

C84

C85

AR16 VCCA_SM_13
2 2 2
C82

AU15 VCCA_SM_14
2 AT15 VCCA_SM_15 9/27
AR15 VCCA_SM_16
AW14 VCCA_SM_17 VCC_AXF_1 M25 +V1.05VM_AXF +1.8V_TXLVDS +1.8V
9/21
N24

AXF
VCC_AXF_2
AT24 VCCA_SM_NCTF_1 VCC_AXF_3 M23 +1.05VM
AR24 R108 1 2 0_0603_5% +VCC_PEG
VCCA_SM_NCTF_2

1000P_0402_50V7K
AT22 VCCA_SM_NCTF_3
AR22 VCCA_SM_NCTF_4
AT21 1 1 R107 1 2 0_0805_5%
VCCA_SM_NCTF_5 C90
AR21 VCCA_SM_NCTF_6 VCC_SM_CK_1 BK24 +1.8V_SM_CK

4.7U_0805_10V4Z

10U_0805_6.3V6M

220U_D2_4VM_R15
AT19 BL23 @ 10U_0805_6.3V6M 1

SM CK
VCCA_SM_NCTF_7 VCC_SM_CK_2

C89
AR19 VCCA_SM_NCTF_8 VCC_SM_CK_3 BJ23 1 1
+1.05VM_A_SM_CK 2 2 +
AT18 VCCA_SM_NCTF_9 VCC_SM_CK_4 BK22
AR18 VCCA_SM_NCTF_10 +3VS_HV

C87

C88

C86
2 2 2
9/27
VCC_TX_LVDS T41 +1.8V_TXLVDS
R110 1 2 0_0603_5% AU27 9/27
VCCA_SM_CK_4 +1.05VM_PEGPLL +1.05VM
AU28 VCCA_SM_CK_3 VCC_HV_1 C33
10U_0805_6.3V6M

0.1U_0402_16V4Z

AU29 A33 L1 9/21

VCCA_SM_CK_2 VCC_HV_2
1 1 AU31 1 2
HV

VCCA_SM_CK_1

0.1U_0402_16V4Z
AT31 BLM18PG121SN1D_0603
VCCA_SM_CK_NCTF_1 +1.05VM_DMI

0.1U_0402_16V4Z

10U_0805_10V4Z
AR31 1 9/29 +1.05VM
VCCA_SM_CK_NCTF_2
C92

C93

AT29 VCCA_SM_CK_NCTF_3 VCC_PEG_1 AB44 +VCC_PEG 1 1

2 2 AR29 Y44
VCCA_SM_CK_NCTF_4 VCC_PEG_2

C94
AT28 AC43 R109 1 2 0_0603_5%
PEG

VCCA_SM_CK_NCTF_5 VCC_PEG_3 2

C95

C96

0.1U_0402_16V4Z
AR28 VCCA_SM_CK_NCTF_6 VCC_PEG_4 AA43
2 2
AT27 VCCA_SM_CK_NCTF_7 1
B AR27 VCCA_SM_CK_NCTF_8
B

C91
VCC_DMI_1 AM44 +1.05VM_DMI 2
VCC_DMI_2 AN43
AL43 9/29
DMI

VCC_DMI_3
+1.05VM_HPLL AH12 VCCD_HPLL
0.1U_0402_16V4Z

+1.05VM_PEGPLL AE43 VCCD_PEG_PLL +VCCP_D

C97

1
0.1U_0402_16V4Z

9/27 K14
VTTLF

VTTLF1
C98

1 M46 VCCD_LVDS_1 VTTLF2 Y12

LVDS

+1.8V R111 2 1 0_0603_5% L45 P2

2 VCCD_LVDS_2 VTTLF3 R112 1
+VCCP 2 1 2 10_0402_5% R113 1 2 0_0402_5% +3VS_HV
1U_0603_10V4Z

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

1 D1 CH751H-40_SC76
2
1 1 1 +3VS
+1.8V_LVDS CANTIGA GMCH SFF_FCBGA1363
C99

2
C100

C101

C102

2 2 2
+1.5VS_QDAC +1.5VS

R114
1 2
BLM18PG181SN1D_0603

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0603_6.3V
1 1 1

C103

C104

C619
2 2 2

install 4.7U for wavy issue. 7/29

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 11 of 36
5 4 3 2 1
 5 4 3 2 1

U4G

+VCCGFX
3000mA
Extnal Graphic: 1210.34mA VCC_AXG_NCTF_1 T32
BB36 U31
integrated Graphic: 1930.4mA BE35
VCC_SM_1 VCC_AXG_NCTF_2
T31
VCC_SM_2 VCC_AXG_NCTF_3
+1.8V AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
U4F AW32 U29
VCC_SM_4 VCC_AXG_NCTF_5

330U_D2E_2.5VM_R9

10U_0805_6.3V6M

10U_0805_6.3V6M

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.22U_0402_10V4Z

4.7U_0805_10V4Z
9/21 BK30 VCC_SM_5 VCC_AXG_NCTF_6 T29 1 1 1
1 BH30 VCC_SM_6 VCC_AXG_NCTF_7 R29
1 1 2 BF30 VCC_SM_7 VCC_AXG_NCTF_8 U28
+1.05VM

C108

C109

C110

C111
+

C105

C106

C107
BD30 VCC_SM_8 VCC_AXG_NCTF_9 U27
D 2 2 2 D
BB30 VCC_SM_9 VCC_AXG_NCTF_10 T27
AW30 VCC_SM_10 VCC_AXG_NCTF_11 R27
2 2 2 1
AT41 VCC_1 BL29 VCC_SM_11 VCC_AXG_NCTF_12 U25
AR41 VCC_2 BJ29 VCC_SM_12 VCC_AXG_NCTF_13 T25
AN41 VCC_3 BG29 VCC_SM_13 VCC_AXG_NCTF_14 R25
AJ41 VCC_4 BE29 VCC_SM_14 VCC_AXG_NCTF_15 U24
AH41 VCC_5 BC29 VCC_SM_15 VCC_AXG_NCTF_16 U22

POWER
AD41 VCC_6 BA29 VCC_SM_16 VCC_AXG_NCTF_17 T22
AC41 VCC_7 AY29 VCC_SM_17 VCC_AXG_NCTF_18 R22
Y41 VCC_8 BK28 VCC_SM_18 VCC_AXG_NCTF_19 U21
W41 VCC_9 BH28 VCC_SM_19 VCC_AXG_NCTF_20 T21
AT40 VCC_10 BF28 VCC_SM_20 VCC_AXG_NCTF_21 R21
220U_D2_4VM_R15

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AM40 VCC_11 BD28 VCC_SM_21 VCC_AXG_NCTF_22 AM19
10U_0805_6.3V6M

1 AL40 VCC_12 BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19

1 1 1 1 BL27 VCC_SM_23 VCC_AXG_NCTF_24 AH19
C112

C113

C114

C115

C116
+ AJ40 BJ27 AG19
VCC_13 VCC_SM_24 VCC_AXG_NCTF_25

VCC CORE
AH40 VCC_14 BG27 VCC_SM_25 VCC_AXG_NCTF_26 AE19

VCC SM
AG40 VCC_15 BE27 VCC_SM_26 VCC_AXG_NCTF_27 AD19
2 2 2 2 2
AE40 BC27 AC19

VCC GFX NCTF

VCC_16 VCC_SM_27 VCC_AXG_NCTF_28
AD40 VCC_17 BA27 VCC_SM_28 VCC_AXG_NCTF_29 W19
AC40 VCC_18 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
AA40 VCC_19 AW26 VCC_SM_30 VCC_AXG_NCTF_31 AM18
Y40 VCC_20 BF24 VCC_SM_31 VCC_AXG_NCTF_32 AL18
AN35 VCC_21 BL19 VCC_SM_32 VCC_AXG_NCTF_33 AJ18
AM35 VCC_22 BB16 VCC_SM_33 VCC_AXG_NCTF_34 AH18
AJ35 +VCCGFX AG18
VCC_23 VCC_AXG_NCTF_35
AH35 VCC_24 VCC_AXG_NCTF_36 AE18
AD35 VCC_25 VCC_AXG_NCTF_37 AD18
AC35 VCC_26 VCC_AXG_NCTF_38 AC18
W35 VCC_27 W32 VCC_AXG_1 VCC_AXG_NCTF_39 AA18
AM34 VCC_28 AG31 VCC_AXG_2 VCC_AXG_NCTF_40 Y18

10U_0805_6.3V

10U_0805_6.3V

1U_0603_10V4Z

0.1U_0402_16V4Z
AL34 VCC_29 9/21 1 AE31 VCC_AXG_3 VCC_AXG_NCTF_41 W18

C118

C119

C120

C121
C C
AJ34 VCC_30 1 1 1 1 AD31 VCC_AXG_4 VCC_AXG_NCTF_42 U18
AH34 C117 + AC31 T18
VCC_31 +1.05VM 330U_D2E_2.5VM_R9 VCC_AXG_5 VCC_AXG_NCTF_43
AG34 VCC_32 AA31 VCC_AXG_6 VCC_AXG_NCTF_44 R18
AE34 VCC_33 Y31 VCC_AXG_7
2 2 2 2 2
POWER
AD34 VCC_34 W31 VCC_AXG_8
VCC_NCTF_1 AT38 AH29 VCC_AXG_9
AC34 VCC_35 VCC_NCTF_2 AR38 AG29 VCC_AXG_10
AA34 VCC_36 VCC_NCTF_3 AN38 AE29 VCC_AXG_11
VCC_NCTF_4 AM38 AD29 VCC_AXG_12 VCC_AXG_62 AJ16
Y34 VCC_37 VCC_NCTF_5 AL38 AC29 VCC_AXG_13 VCC_AXG_63 AH16
W34 VCC_38 VCC_NCTF_6 AG38 AA29 VCC_AXG_14 VCC_AXG_64 AD16
AM32 VCC_39 VCC_NCTF_7 AE38 Y29 VCC_AXG_15 VCC_AXG_65 AC16
AL32 VCC_40 VCC_NCTF_8 AA38 W29 VCC_AXG_16 VCC_AXG_66 AA16
AJ32 VCC_41 VCC_NCTF_9 Y38 AH28 VCC_AXG_17 VCC_AXG_67 U16
AH32 VCC_42 VCC_NCTF_10 W38 AG28 VCC_AXG_18 VCC_AXG_68 T16

VCC GFX
AE32 VCC_43 VCC_NCTF_11 U38 AE28 VCC_AXG_19 VCC_AXG_69 R16
AD32 VCC_44 VCC_NCTF_12 T38 AA28 VCC_AXG_20 VCC_AXG_70 AM15
AA32 VCC_45 VCC_NCTF_13 R38 AH27 VCC_AXG_21 VCC_AXG_71 AL15
AM31 VCC_46 VCC_NCTF_14 AT37 6326.84mA AG27 VCC_AXG_22 VCC_AXG_72 AJ15
AL31 VCC_47 VCC_NCTF_15 AR37 AE27 VCC_AXG_23 VCC_AXG_73 AH15
AJ31 VCC_48 VCC_NCTF_16 AN37 AD27 VCC_AXG_24 VCC_AXG_74 AG15
AH31 VCC_49 VCC_NCTF_17 AM37 AC27 VCC_AXG_25 VCC_AXG_75 AE15
AM29 VCC_50 VCC_NCTF_18 AL37 AA27 VCC_AXG_26 VCC_AXG_76 AA15
AL29 VCC_51 VCC_NCTF_19 AJ37 Y27 VCC_AXG_27 VCC_AXG_77 Y15
AM28 VCC_52 VCC_NCTF_20 AH37 W27 VCC_AXG_28 VCC_AXG_78 W15
AL28 VCC_53 VCC_NCTF_21 AG37 AH25 VCC_AXG_29 VCC_AXG_79 U15
AJ28 VCC_54 VCC_NCTF_22 AE37 AD25 VCC_AXG_30 VCC_AXG_80 T15
AM27 VCC_55 VCC_NCTF_23 AD37 AC25 VCC_AXG_31
AL27 VCC_56 VCC_NCTF_24 AC37 W25 VCC_AXG_32
VCC NCTF

AM25 VCC_57 VCC_NCTF_25 AA37 AJ24 VCC_AXG_33

AL25 VCC_58 VCC_NCTF_26 Y37 AH24 VCC_AXG_34
AJ25 VCC_59 VCC_NCTF_27 W37 AG24 VCC_AXG_35
B B
AM24 VCC_60 VCC_NCTF_28 U37 AE24 VCC_AXG_36
N36 VCC_61 VCC_NCTF_29 T37 AD24 VCC_AXG_37
VCC_NCTF_30 R37 AC24 VCC_AXG_38
VCC_NCTF_31 AT35 AA24 VCC_AXG_39
VCC_NCTF_32 AR35 Y24 VCC_AXG_40
VCC_NCTF_33 U35 W24 VCC_AXG_41
VCC_NCTF_34 AT34 AM22 VCC_AXG_42
VCC_NCTF_35 AR34 AL22 VCC_AXG_43
VCC_NCTF_36 U34 AJ22 VCC_AXG_44

VCC GFX
VCC_NCTF_37 T34 AH22 VCC_AXG_45
VCC_NCTF_38 R34 AG22 VCC_AXG_46
AE22 VCC_AXG_47
AD22 VCC_AXG_48
AC22 VCC_AXG_49
AA22 AU45 VCCSM_LF1
VCC_AXG_50 VCC_SM_LF1

VCC SM LF
AM21 BF52 VCCSM_LF2
VCC_AXG_51 VCC_SM_LF2 VCCSM_LF3
AL21 VCC_AXG_52 VCC_SM_LF3 BB38
AJ21 BA19 VCCSM_LF4
VCC_AXG_53 VCC_SM_LF4 VCCSM_LF5
AH21 VCC_AXG_54 VCC_SM_LF5 BE9

C122 0.22U_0603_10V7K

C123 0.22U_0603_10V7K

C124 0.47U_0402_6.3V6K

C125 1U_0603_10V4Z

C126 1U_0603_10V4Z
AD21 AU9 VCCSM_LF6 1 1 1 1 1
VCC_AXG_55 VCC_SM_LF6 VCCSM_LF7
AC21 VCC_AXG_56 VCC_SM_LF7 AL9

C127 0.1U_0402_16V4Z

C128 0.1U_0402_16V4Z
AA21 VCC_AXG_57 1 1
Y21 VCC_AXG_58 2 2 2 2 2
W21 VCC_AXG_59
AM16 VCC_AXG_60
CANTIGA GMCH SFF_FCBGA1363 2 2
AL16 VCC_AXG_61

PAD T46 AG13 VCC_AXG_SENSE

PAD T47 AE13 VSS_AXG_SENSE

A A

CANTIGA GMCH SFF_FCBGA1363

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 12 of 36
5 4 3 2 1
 5 4 3 2 1

U4I

BA55 C43 U4J

VSS_1 VSS_100
AU55 VSS_2 VSS_101 A43
AN55 VSS_3 VSS_102 BD42 AN25 VSS_199 VSS_300 AM8
AJ55 VSS_4 VSS_103 H42 AG25 VSS_200 VSS_301 AK8
AE55 VSS_5 VSS_104 BG41 AE25 VSS_201 VSS_302 AH8
AA55 VSS_6 VSS_105 AY41 AA25 VSS_202 VSS_303 AF8
U55 VSS_7 VSS_106 AU41 Y25 VSS_203 VSS_304 AD8
N55 VSS_8 VSS_107 AM41 E25 VSS_204 VSS_305 AB8
BD54 VSS_9 VSS_108 AL41 A25 VSS_205 VSS_306 Y8
BG53 VSS_10 VSS_109 AG41 BD24 VSS_206 VSS_307 V8
AJ53 VSS_11 VSS_110 AE41 AN24 VSS_207 VSS_308 P8
AE53 VSS_12 VSS_111 AA41 AL24 VSS_208 VSS_309 M8
D D
AA53 VSS_13 VSS_112 R41 H24 VSS_209 VSS_310 K8
U53 VSS_14 VSS_113 M41 BG23 VSS_210 VSS_311 H8
N53 VSS_15 VSS_114 E41 AY23 VSS_211 VSS_312 BJ7
J53 VSS_16 VSS_115 BD40 E23 VSS_212 VSS_313 E7
G53 VSS_17 VSS_116 AU40 BD22 VSS_213 VSS_314 BF6
E53 VSS_18 VSS_117 AR40 BB22 VSS_214 VSS_315 BC5
K52 VSS_19 VSS_118 AN40 AN22 VSS_215 VSS_316 BA5
BG51 VSS_20 VSS_119 W40 Y22 VSS_216 VSS_317 AW5
BA51 VSS_21 VSS_120 U40 W22 VSS_217 VSS_318 AU5
AW51 VSS_22 VSS_121 T40 H22 VSS_218 VSS_319 AR5
AU51 VSS_23 VSS_122 R40 BL21 VSS_219 VSS_320 AN5
AR51 VSS_24 VSS_123 K40 BG21 VSS_220 VSS_321 AL5
AN51 VSS_25 VSS_124 H40 AY21 VSS_221 VSS_322 AJ5
AL51 VSS_26 VSS_125 BL39 AN21 VSS_222 VSS_323 AG5
AJ51 VSS_27 VSS_126 BG39 AG21 VSS_223 VSS_324 AE5
AG51 VSS_28 VSS_127 BA39 AE21 VSS_224 VSS_325 AC5
AE51 VSS_29 VSS_128 E39 M21 VSS_225 VSS_326 AA5
AC51 VSS_30 VSS_129 C39 E21 VSS_226 VSS_327 W5
AA51 VSS_31 VSS_130 A39 A21 VSS_227 VSS_328 U5
W51 VSS_32 VSS_131 BD38 BD20 VSS_228 VSS_329 N5
U51 AU38 H20 L5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
BG19
AY19
VSS_229
VSS_230
VSS_231
VSS VSS_330
VSS_331
VSS_332
J5
G5
L51 VSS_36 VSS_135 AU37 M19 VSS_232 VSS_333 C5
J51 VSS_37 VSS_136 M37 E19 VSS_233 VSS_334 BH4
G51 VSS_38 VSS_137 E37 BD18 VSS_234 VSS_335 BE3
C51 VSS_39 VSS_138 BD36 N18 VSS_235 VSS_336 U3
BK50 VSS_40 VSS_139 AW36 H18 VSS_236 VSS_337 E3
AM50 VSS_41 VSS_140 H36 BL17 VSS_237 VSS_338 BC1
K50 VSS_42 VSS_141 BL35 BG17 VSS_238 VSS_339 AW1
BG49 VSS_43 VSS_142 BG35 AY17 VSS_239 VSS_340 AR1
E49 VSS_44 VSS_143 AY35 M17 VSS_240 VSS_341 AL1
C C
C49 VSS_45 VSS_144 AU35 E17 VSS_241 VSS_342 AG1
BD48 VSS_46 VSS_145 AL35 A17 VSS_242 VSS_343 AC1
BB48 VSS_47 VSS_146 AG35 BD16 VSS_243 VSS_344 W1
AY48 VSS_48 VSS_147 AE35 AN16 VSS_244 VSS_345 N1
AV48 VSS_49 VSS_148 AA35 AG16 VSS_245 VSS_346 J1
AT48 VSS_50 VSS_149 Y35 AE16 VSS_246 VSS_347 AU43
AP48 VSS_51 VSS_150 M35 Y16 VSS_247 VSS_348 BB42
AM48 VSS_52 VSS_151 E35 W16 VSS_248 VSS_349 AW38
AK48 VSS_53 VSS_152 A35 N16 VSS_249 VSS_350 BA35
AH48 VSS_54 VSS_153 BD34 H16 VSS_250 VSS_351 L29
AF48 VSS_55 VSS_154 AU34 BG15 VSS_251 VSS_352 N28
AD48 VSS_56 VSS_155 AN34 AY15 VSS_252 VSS_353 N22
AB48 VSS_57 VSS_156 H34 AN15 VSS_253 VSS_354 N20
Y48 VSS_58 VSS_157 BL33 AD15 VSS_254 VSS_355 N14
V48 VSS_59 VSS_158 BG33 AC15 VSS_255 VSS_356 AL13
T48 VSS_60 VSS_159 AY33 R15 VSS_256 VSS_357 B10
P48 VSS_61 VSS_160 E33 M15 VSS_257 VSS_358 AN13
M48 VSS_62 VSS_161 BD32 E15 VSS_258
K48 VSS_63 VSS_162 AU32 BD14 VSS_259 VSS_359 N42
H48 VSS_64 VSS_163 AN32 H14 VSS_260 VSS_360 N40
BL47 VSS_65 VSS_164 AG32 BL13 VSS_261 VSS_361 N38
BG47 VSS_66 VSS_165 AC32 BG13 VSS_262 VSS_362 M39
E47 VSS_67 VSS_166 Y32 AY13 VSS_263
C47 VSS_68 VSS_167 H32 AU13 VSS_264
A47 VSS_69 VSS_168 B32 AR13 VSS_265 VSS_NCTF_1 AJ38
BD46 VSS_70 VSS_169 BJ31 AJ13 VSS_266 VSS_NCTF_2 AH38
AY46 VSS_71 VSS_170 BG31 AC13 VSS_267 VSS_NCTF_3 AD38
AM46 VSS_72 VSS_171 AY31 AA13 VSS_268 VSS_NCTF_4 AC38
AK46 VSS_73 VSS_172 AN31 W13 VSS_269 VSS_NCTF_5 T35
AH46 M31 U13 R35

VSS NCTF
VSS_74 VSS_173 VSS_270 VSS_NCTF_6
BG45 VSS_75 VSS_174 E31 M13 VSS_271 VSS_NCTF_7 AT32
AE45 VSS_76 VSS_175 N30 E13 VSS_272 VSS_NCTF_8 AR32
B B
AC45 VSS_77 VSS_176 H30 A13 VSS_273 VSS_NCTF_9 U32
AA45 VSS_78 VSS_177 AN29 BD12 VSS_274 VSS_NCTF_10 R32
W45 VSS_79 VSS_178 AJ29 AV12 VSS_275 VSS_NCTF_11 T28
R45 VSS_80 VSS_179 M29 AP12 VSS_276 VSS_NCTF_12 R28
N45 VSS_81 VSS_180 A29 AM12 VSS_277 VSS_NCTF_13 AT25
E45 VSS_82 VSS_181 AW28 AK12 VSS_278 VSS_NCTF_14 AR25
BD44 VSS_83 VSS_182 AN28 AB12 VSS_279 VSS_NCTF_15 T24
BB44 VSS_84 VSS_183 AD28 V12 VSS_280 VSS_NCTF_16 R24
AV44 VSS_85 VSS_184 AC28 P12 VSS_281 VSS_NCTF_17 AN19
AK44 VSS_86 VSS_185 Y28 H12 VSS_282 VSS_NCTF_18 AJ19
AH44 VSS_87 VSS_186 W28 BG11 VSS_283 VSS_NCTF_19 AA19
AF44 VSS_88 VSS_187 H28 AG11 VSS_284 VSS_NCTF_20 Y19
AD44 VSS_89 VSS_188 F28 E11 VSS_285 VSS_NCTF_21 T19
K44 VSS_90 VSS_189 AN27 BD10 VSS_286 VSS_NCTF_22 R19
H44 VSS_91 VSS_190 AJ27 AY10 VSS_287 VSS_NCTF_23 AN18
BL43 VSS_92 VSS_191 M27 AP10 VSS_288
BG43 VSS_93 VSS_192 BF26 H10 VSS_289
AY43 VSS_94 VSS_193 BD26 BL9 VSS_290
AR43 VSS_95 VSS_194 N26 BG9 VSS_291
W43 VSS_96 VSS_195 H26 E9 VSS_292
R43 BJ25 A9 BL55 MCHGND1 R222 1 2 @ 0_0402_5%
VSS_97 VSS_196 VSS_293 VSS_SCB_1 MCHGND2 R224 1
M43 AY25 BD8 BL1 2 @ 0_0402_5%

VSS SCB
VSS_98 VSS_197 VSS_294 VSS_SCB_2 MCHGND3 R225 1
E43 VSS_99 VSS_198 AU25 BB8 VSS_295 VSS_SCB_3 A55 2 @ 0_0402_5%
AY8 VSS_296 VSS_SCB_4 D1
AV8 B55 R25 1 2 0_0402_5%
CANTIGA GMCH SFF_FCBGA1363 VSS_297 VSS_SCB_5 MCHGND4 R228 1
AT8 VSS_298 VSS_SCB_6 B2 2 @ 0_0402_5%
AP8 VSS_299 VSS_SCB_7 A4

CANTIGA GMCH SFF_FCBGA1363

+3VS +3VS +3VS +3VS
A A
100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%
2

2
R270

R396

R397

R398

CRACK_BGA CRACK_BGA CRACK_BGA CRACK_BGA

CRACK_BGA <23,33>

Security Classification Compal Secret Data Compal Electronics, Inc.

1

1
1

D D D D
MCHGND1 2 MCHGND2 2 MCHGND3 2 MCHGND4 2 2006/02/13 2006/03/10 Title
G G G G
Issued Date Deciphered Date
Q68 S Q69 S Q70 S Q71 S SCHEMATIC, M/B LA-4021P
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 13 of 36
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<9> DDR_A_DQS#[0..7] V_DDR_MCH_REF <8,15>

<9> DDR_A_D[0..63] JP36

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2

C129

C130
3 4 DDR_A_D6 1 1
<9> DDR_A_DM[0..7] VSS DQ4
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<9> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<9> DDR_A_MA[0..14] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
DDR_A_D3 DQ2 VSS DDR_A_D13
19 DQ3 DQ12 20
D DDR_A_D12 D
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D14 DQ8 VSS DDR_A_DM1
25 DQ9 DM1 26
27 VSS VSS 28
Layout Note: DDR_A_DQS#1 29 30
DQS1# CK0 M_CLK_DDR0 <8>
DDR_A_DQS1 31 32
Place near JP36 DQS1 CK0# M_CLK_DDR#0 <8>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDR_A_D16 43 44 DDR_A_D20
+1.8V DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
47 VSS VSS 48
Change C131 to 330uF. 9/26 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <8>
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 54
330U_D2E_2.5VM_R9

VSS VSS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C131

1 DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
1 1 1 1 1 1 1 1 1 57 DQ19 DQ23 58
C132

C133

C134

C135

C136

C137

C138

C139

C140
+ 59 60
DDR_A_D29 VSS VSS DDR_A_D28
61 DQ24 DQ28 62
DDR_A_D24 63 64 DDR_A_D25
2 2 2 2 2 2 2 2 2 2 DQ25 DQ29
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA
C <8> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <8> C
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86 DDR_A_MA14
<9> DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: DDR_A_MA8
91 A9 A7 92
DDR_A_MA6
93 A8 A6 94
Place one cap close to every 2 pullup 95 96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V 97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <9>
DDR_A_BS0 107 108 DDR_A_RAS#
<9> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <9>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
<9> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
+0.9V <9> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<8> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
<8> M_ODT1 M_ODT1 119 120
NC/ODT1 NC
121 VSS VSS 122
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_D37 123 124 DDR_A_D39

DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
1 1 1 1 1 1 1 1 1 1 1 1 1 127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D34
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
C141

C142

C143

C144

C145

C146

C147

C148

C149

C150

C151

C152

C153

DDR_A_D32 137 138

DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
DDR_A_D44 DQ40 DQ45
143 DQ41 VSS 144
B DDR_A_DQS#5 B
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 M_CLK_DDR1 <8>
165 VSS CK1# 166 M_CLK_DDR#1 <8>
DDR_A_DQS#6 167 168
+0.9V DDR_A_DQS6 DQS6# VSS DDR_A_DM6
Layout Note: 169 DQS6 DM6 170
Place these resistor 171 VSS VSS 172
DDR_A_D54 173 174 DDR_A_D51
DDR_A_MA5 closely JP9,all DQ50 DQ54
1 4 4 1 DDR_A_BS2 DDR_A_D50 175 DQ51 DQ55 176 DDR_A_D55
DDR_A_MA8 2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" 177 178
56_0404_4P2R_5% RP1 RP2 56_0404_4P2R_5% DDR_A_D61 VSS VSS DDR_A_D57
179 DQ56 DQ60 180
DDR_A_D60 181 182 DDR_A_D56
DDR_A_MA1 DQ57 DQ61
1 4 4 1 DDR_A_MA6 183 VSS VSS 184
DDR_A_MA3 2 3 3 2 DDR_A_MA7 DDR_A_DM7 185 186 DDR_A_DQS#7
56_0404_4P2R_5% RP3 RP4 56_0404_4P2R_5% DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D59 189 190
DDR_CS0_DIMMA# 1 DQ58 VSS
4 4 1 DDR_A_MA9 DDR_A_D58 191 DQ59 DQ62 192 DDR_A_D62
DDR_A_RAS# 2 3 3 2 DDR_A_MA12 193 194 DDR_A_D63
56_0404_4P2R_5% RP5 RP6 56_0404_4P2R_5% VSS DQ63
195 SDA VSS 196
<15,16,22> ICH_SMBDATA 197 198
DDR_A_BS0 <15,16,22> ICH_SMBCLK SCL SA0
1 4 4 1 DDR_A_MA2 +3VM 199 VDDSPD SA1 200
DDR_A_MA10 2 3 3 2 DDR_A_MA4

1
10K_0402_5%

10K_0402_5%
C154

C155
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

56_0404_4P2R_5% RP7 RP8 56_0404_4P2R_5%

1 1 CONN@ FOX_ASOA426-M2RN-7F

R115

R116
DDR_A_CAS# 1 4 4 1 DDR_A_BS1
A DDR_A_WE#
56_0404_4P2R_5%
2 3
RP9
3
RP10
2 DDR_A_MA0
56_0404_4P2R_5%
SO-DIMM A A

4mm Height

2
2 2
DDR_CS1_DIMMA# 2 3 4 1 DDR_A_MA13
M_ODT1 1 4 3 2 M_ODT0 Top side
56_0404_4P2R_5% RP11 RP12 56_0404_4P2R_5%

4 1 DDR_A_MA14
DDR_A_MA11 1
56_0402_5%
2
R117
3
RP13
2 DDR_CKE1_DIMMA
56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 14 of 36
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<9> DDR_B_DQS#[0..7]

<9> DDR_B_D[0..63] V_DDR_MCH_REF

V_DDR_MCH_REF <8,14>
JP3
<9> DDR_B_DM[0..7]

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_B_D60 1 1
<9> DDR_B_DQS[0..7] VSS DQ4

C564

C565
DDR_B_D57 5 6 DDR_B_D61
DDR_B_D56 DQ0 DQ5
<9> DDR_B_MA[0..14] 7 DQ1 VSS 8
9 10 DDR_B_DM7
DDR_B_DQS#7 VSS DM0 2 2
11 DQS0# VSS 12
DDR_B_DQS7 13 14 DDR_B_D62
DQS0 DQ6 DDR_B_D59
15 VSS DQ7 16
DDR_B_D58 17 18
D DDR_B_D63 DQ2 VSS DDR_B_D52 D
19 DQ3 DQ12 20
21 22 DDR_B_D53
DDR_B_D48 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_B_D49 25 26 DDR_B_DM6
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_B_DQS#6 29 30 M_CLK_DDR3 <8>
DDR_B_DQS6 DQS1# CK0
31 DQS1 CK0# 32 M_CLK_DDR#3 <8>
33 VSS VSS 34
DDR_B_D51 35 36 DDR_B_D54
DDR_B_D50 DQ10 DQ14 DDR_B_D55
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V Reserve C524. 9/26 41 42

DDR_B_D40 VSS VSS DDR_B_D45
43 DQ16 DQ20 44
DDR_B_D44 45 46 DDR_B_D41
DQ17 DQ21
47 48
330U_D2E_2.5VM_R9

VSS VSS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C524

1 DDR_B_DQS#5 49 50
DQS2# NC PM_EXTTS#1 <8>
1 1 1 1 1 1 1 1 1 DDR_B_DQS5 51 52 DDR_B_DM5
DQS2 DM2
C566

C567

C568

C569

C570

C571

C572

C573

C574
+ 53 54
DDR_B_D42 VSS VSS DDR_B_D46
55 DQ18 DQ22 56
DDR_B_D47 57 58 DDR_B_D43
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_B_D37 61 62 DDR_B_D36
DDR_B_D32 DQ24 DQ28 DDR_B_D33
63 DQ25 DQ29 64
65 VSS VSS 66
@ DDR_B_DM4 67 68 DDR_B_DQS#4
DM3 DQS3# DDR_B_DQS4
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D39 73 74 DDR_B_D34
DDR_B_D35 DQ26 DQ30 DDR_B_D38
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE2_DIMMB DDR_CKE3_DIMMB C
<8> DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB <8>
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS2 85 86 DDR_B_MA14
<9> DDR_B_BS2 BA2 NC/A14
87 VDD VDD 88
Layout Note: DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
Place one cap close to every 2 pullup DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
resistors terminated to +0.9V 95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <9>
DDR_B_BS0 107 108 DDR_B_RAS#
<9> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <9>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<9> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
111 VDD VDD 112
+0.9V DDR_B_CAS# 113 114 M_ODT2
<9> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
<8> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
M_ODT3 119 120
<8> M_ODT3 NC/ODT1 NC
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

121 VSS VSS 122

DDR_B_D30 123 124 DDR_B_D26
DDR_B_D27 DQ32 DQ36 DDR_B_D31
1 1 1 1 1 1 1 1 1 1 1 1 1 125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#3 129 130 DDR_B_DM3
DDR_B_DQS3 DQS4# DM4
131 DQS4 VSS 132
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_D24
133 VSS DQ38 134
C575

C576

C577

C578

C579

C580

C581

C582

C583

C584

C585

C586

C587

DDR_B_D25 135 136 DDR_B_D29

DDR_B_D28 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDR_B_D18
DDR_B_D23 VSS DQ44 DDR_B_D19
141 DQ40 DQ45 142
B DDR_B_D22 B
143 DQ41 VSS 144
145 146 DDR_B_DQS#2
DDR_B_DM2 VSS DQS5# DDR_B_DQS2
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D17 151 152 DDR_B_D21
DDR_B_D16 DQ42 DQ46 DDR_B_D20
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D11 157 158 DDR_B_D14
DDR_B_D10 DQ48 DQ52 DDR_B_D15
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 M_CLK_DDR2 <8>
Layout Note: 165 VSS CK1# 166 M_CLK_DDR#2 <8>
DDR_B_DQS#1 167 168
+0.9V Place these resistor DDR_B_DQS1 DQS6# VSS DDR_B_DM1
169 DQS6 DM6 170
closely JP10,all 171 172
DDR_B_D12 VSS VSS DDR_B_D13
trace length Max=1.5" 173 DQ50 DQ54 174
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_D9 175 176 DDR_B_D8
DDR_B_MA3 DDR_B_MA12 DQ51 DQ55
2 3 3 2 177 VSS VSS 178
56_0404_4P2R_5% RP22 RP23 56_0404_4P2R_5% DDR_B_D2 179 180 DDR_B_D7
DDR_B_D3 DQ56 DQ60 DDR_B_D6
181 DQ57 DQ61 182
DDR_B_BS0 1 4 4 1 DDR_CKE3_DIMMB 183 184
DDR_B_MA10 DDR_B_MA14 DDR_B_DM0 VSS VSS DDR_B_DQS#0
2 3 3 2 185 DM7 DQS7# 186
56_0404_4P2R_5% RP24 RP25 56_0404_4P2R_5% 187 188 DDR_B_DQS0
DDR_B_D0 VSS DQS7
189 DQ58 VSS 190
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_D5 191 192 DDR_B_D1
DDR_B_BS1 DDR_B_MA8 DQ59 DQ62 DDR_B_D4
2 3 3 2 193 VSS DQ63 194
56_0404_4P2R_5% RP26 RP27 56_0404_4P2R_5% 195 196
<14,16,22> ICH_SMBDATA SDA VSS R73
197 SCL SAO 198
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 <14,16,22> ICH_SMBCLK 199 200 1 2
+3VM VDDSPD SA1 +3VM
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6

1
10K_0402_5%
C588

C589

0.1U_0402_16V4Z
2.2U_0603_6.3V6K

56_0404_4P2R_5% RP28 RP29 56_0404_4P2R_5% 10K_0402_5%

R77
1 1 CONN@ SUYIN_600008FB200G103ZL
A DDR_B_CAS# DDR_B_MA4 A
1 4 4 1
DDR_B_WE#
56_0404_4P2R_5%
2 3 3
RP30 RP31
2 DDR_B_MA2
56_0404_4P2R_5%
SO-DIMM B
REVERSE

2
2 2
DDR_CS3_DIMMB# 2 3 4 1 M_ODT2
M_ODT3 1 4 3 2 DDR_B_MA13 Bottom side
56_0404_4P2R_5% RP32 RP33 56_0404_4P2R_5%

DDR_B_MA11
4 1 DDR_B_BS2
DDR_CKE2_DIMMB
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 3 2 Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
56_0402_5% R80 RP34 56_0404_4P2R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 15 of 36
5 4 3 2 1
 5 4 3 2 1

+3VM_CK505 +1.05VM +1.05VM_CK505

Mount C157 & C166 tp solve

+3VM C156 1 CLK_48M_ICH
FSLC FSLB FSLA CPU FSB SRC PCI 2
@ 5P_0402_50V8C
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz C157 1 2 CLK_14M_ICH

WWAN noise issue. 1/23

1 2 1 2 12P_0402_50V8J
R118 0_1206_5% R58 0_1206_5% C165 2 1 CLK_PCI_ICH

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0 0 0 266 1066 100 33.3 @ 4.7P_0402_50V8C
1 1 1 1 1 1 1 1 1 1 1 1 1 C166 1 2 CLK_14M_KBC
12P_0402_50V8J
0 1 0 200 800 100 33.3 C167 2 1 CLK_PCI_EC

C158

C159

C160

C161

C162

C163

C164

C171

C172

C173

C174

C175

C176
@ 4.7P_0402_50V8C
2 2 2 2 2 2 2 2 2 2 2 2 2 C168 2 1 CLK_PCI_TCG
0 1 1 166 667 100 33.3 @ 4.7P_0402_50V8C
C169 2 1 CLK_PCI_1394
@ 5P_0402_50V8C
D D
C170 2 1 CLK_PCI_DB
@ 5P_0402_50V8C
+VCCP
Place close to U5

2
R127 R119 1 2 10K_0402_5% +3VS
@ 56_0402_5% R123 1 2 10K_0402_5% +3VS
CLKREQ#_B_R R120 2 1 475_0402_1% CLKREQ#_B <8>
CLKREQG_WWAN#_R R121 2 1 475_0402_1% CLKREQ_WLAN#_R R124 2 1 475_0402_1%
CLKREQG_WWAN# <26> CLKREQ_WLAN# <26>
1
CLKSATAREQ#_R R125 2 1 475_0402_1%
CLKSATAREQ# <22>
FSA 2 1 1 2 R122 1 2 10K_0402_5% +3VS
MCH_CLKSEL0 <8>
R128 2.2K_0402_5% R129 1K_0402_5% R126 1 2 10K_0402_5% +3VS

1 2 +3VM_CK505 U5
<5> CPU_BSEL0
R130 0_0402_5%
6 VDDREF NC 11
1

12 VDDPCI
9/14 19 VDD48
R131 +1.05VM_CK505 23
@ 1K_0402_5% VDD96_IO
27 VDDPLL3 SCLK 10 ICH_SMBCLK <14,15,22>
55 9 ICH_SMBDATA <14,15,22>
2

VDDSRC SDATA
72 VDDCPU
PCI_STOP# 54 H_STP_PCI# <22>
CPU_STOP# 53 H_STP_CPU# <22>

CPUT0_LPR_F 71 CLK_CPU_BCLK <4>

+1.05VM_CK505 70
+VCCP CPUC0_LPR_F CLK_CPU_BCLK# <4>
31 VDDPLL3_IO CPUT1_LPR_F 68 CLK_MCH_BCLK <8>
38 VDDSRC_IO CPUC1_LPR_F 67 CLK_MCH_BCLK# <8>
C C
52 VDDSRC_IO
2

62 65 CLKREQ#_B_R
R137 VDDSRC_IO CR7#
66 VDDCPU_IO
@ 1K_0402_5% 64 R_CPU_XDP RP14 1 4 0_0404_4P2R_5%
CPUT2_ITP_LPR/SRCT8_LPR CLK_CPU_XDP <4>
63 R_CPU_XDP# 2 3
CPUC2_ITP_LPR/SRCC8_LPR CLK_CPU_XDP# <4>
R138
1

1K_0402_5% 61
SRCT7_LPR CLK_MCH_3GPLL <8>
FSB 1 2 60
MCH_CLKSEL1 <8> SRCC7_LPR CLK_MCH_3GPLL# <8>

<5> CPU_BSEL1 1 2 13 PCI CR#6 58

R139
0_0402_5% <27> CLK_PCI_1394 CLK_PCI_1394 22_0402_5% 1 2 R132 PCI2_TME 14 57
PCI2/TME SRCT6_LPR
1

CLK_PCI_TCG 22_0402_5% 1 2 R133 56

<32> CLK_PCI_TCG SRCC6_LPR
R62 CLK_PCI_EC 33_0402_1% 1 2 R134 PCI_CLK3 15
<33> CLK_PCI_EC PCI3
@ 0_0402_5% Add for PCIE 49 CLKREQ_WLAN#_R
33_0402_1% 1 CR10#
<26> CLK_PCI_DEBUG 2 R338
port80 debug 50 CLK_PCIE_MCARD <26>
2

port. 10/18. CLK_PCI_DB 33_0402_1% 1 SRCT10_LPR

<32> CLK_PCI_DB 2 R135 27_SEL 16 PCI4/27_Select SRCC10_LPR 51 CLK_PCIE_MCARD# <26>
CLK_PCI_ICH 33_0402_1% 1 2 R136 ITP_EN 17 46 CLKREQG_WWAN#_R
<20> CLK_PCI_ICH PCI_F5/ITP_EN CR#11

SRCT11_LPR 48 CLK_PCIE_WAN <26>

SRCC11_LPR 47 CLK_PCIE_WAN# <26>
CLK_XTAL_IN 5 X1
CR#9 43
CLK_XTAL_OUT 4 X2
SRCT9_LPR 44
SRCC9_LPR 45

9/20
FSC 2 1 1 2 41
MCH_CLKSEL2 <8> CR#4 CLKREQA# <26>
R143 10K_0402_5% R144 1K_0402_5%
B B
<5> CPU_BSEL2 1 2 SRCT4_LPR 39 CLK_PCIE_EXP <26>
R145 0_0402_5% CLK_48M_ICH 33_0402_1% 1 2 R140 FSA 20 40
<22> CLK_48M_ICH USB_48MHz/FSLA SRCC4_LPR CLK_PCIE_EXP# <26>
1

CR#3 37
R146 FSB 2
0_0402_5% FSLB/TEST_MODE R_PCIE_ICH RP35 2
SRCT3_LPR 35 3 0_0404_4P2R_5% CLK_PCIE_ICH <22>
36 R_PCIE_ICH# 1 4
SRCC3_LPR CLK_PCIE_ICH# <22>
<22> CLK_14M_ICH CLK_14M_ICH 33_0402_1% 1 2 R141 FSC 7
2

CLK_14M_KBC 33_0402_1% 1 R142 FSLC/TEST_SEL/REF0

<33> CLK_14M_KBC 2
Install. 11/06
SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA <21>
SRCC2_LPR/SATAC_LPR 33 CLK_PCIE_SATA# <21>

SRCT0_LPR/DOTT_96_LPR 24 CLK_MCH_DREFCLK <8>

SRCC0_LPR/DOTC_96_LPR 25 CLK_MCH_DREFCLK# <8>
59 GNDSRC
27MHz_NonSS/SRCT1_LPR/SE1 28 MCH_SSCDREFCLK <8>
18 GNDPCI 27MHz_SS/SRCC1_LPR/SE2 29 MCH_SSCDREFCLK# <8>
14.31818MHZ_20P_1BX14318BE1A

22 GND48
CLK_XTAL_OUT 26 1 CK_PWRGD <22>
+3VS +3VS +3VS GND CK_PWRGD/PD#
CLK_XTAL_IN 30 GND
2

69 21 CLKSATAREQ#_R
R147 R148 R149 GNDCPU CR#A
10K_0402_5% @10K_0402_5% 10K_0402_5% 34 GNDSRC
Y1
42 8
1

GNDSRC REF1
2 1
A ITP_EN 27_SEL PCI2_TME A
3 GNDREF
9/14 2 2 9/14 ICS9LPRS397DKLFT MLF 72P
2

33P_0402_50V8J C177 C178 R150 R151 R152

33P_0402_50V8J @10K_0402_5% 10K_0402_5% @10K_0402_5%
1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

1

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 16 of 36
5 4 3 2 1
 A B C D E

+5VS +RCRT_VCC
Del L20. 5/16 +CRTVDD

CRT Connector D_RED

D_GREEN
F1
1.1A_6VDC_FUSE
D2
CH491D_SC59
<34> BLUE
<34> GREEN
BLUE
GREEN
RED
1 2 2 1 <34> RED
D_BLUE W=40mils D_HSYNC

R153

R154

R155
D_VSYNC
1

1
C179

SUYIN_070546FR015S235ZR_15P

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3
L Place cloce to GMCH

D3

D4

D5

D6

D7
0.1U_0402_16V4Z

1
2
JP4

2
75_0402_5%

75_0402_5%

75_0402_5%
L2 L17 6
TAIYO BK1608LL560-T 0603 0_0805_5% 11
1 D_RED RED 1
<10> D_RED 1 2 1 2 1
L3 L18 +CRTVDD
7

3
TAIYO BK1608LL560-T 0603 0_0805_5% 12
<10> D_GREEN D_GREEN 1 2 1 2 GREEN 2 @ @ @ @ @

CONN@
L4 L19 8
TAIYO BK1608LL560-T 0603 0_0805_5% 13
<10> D_BLUE D_BLUE 1 2 1 2 BLUE 3
9

C180

C181

C182

C183

C184

C185
14 16

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1 1 1 1 1 1 4 17
10
+5VS +5VS 15
5
C186 C187 2 2 2 2 2 2
+CRTVDD +3VS
10/25
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2
RED_R, GREEN_R, & BLUE_R should
still be connected to output of RGB
filter (L17-2, L18-2, L19-2). JP4
5
1

U6 pins should only connect to RED,

D_HSYNC <34>
SN74AHCT1G125GW_SOT353-5
P
OE#

2
2 4 HSYNC R156 1 2 0_0603_5% D_HSYNC GREEN, & BLUE.
<10> CRT_HSYNC A Y
G

5
1

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
P D_VSYNC <34>
OE#
3

2 4 VSYNC R161 1 2 0_0603_5% D_VSYNC

<10> CRT_VSYNC

R157 2

R158 2

R159 1

R160 1
A Y
G
R162

R163

U7

2
SN74AHCT1G125GW_SOT353-5

G
1 1
3

C188 C189
2

<34> D_DDCDATA 1 3 CRT_DDC_DATA <10>

2 @ 5P_0402_50V8C @ 5P_0402_50V8C 2

S
2 2 Q2
L Place cloce to GMCH

2
BSS138_SOT23

G
1

1
51K_0402_5%

51K_0402_5%

<34> D_DDCCLK 1 3 CRT_DDC_CLK <10>

S
Q3
layout note: D_HSYNC BSS138_SOT23
& D_VSYNC should be
routed to docking Place cloce to GMCH
connector then to VGA
L
connector

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 17 of 36
A B C D E
 5 4 3 2 1

LCD/PANEL BD. CONN.

D B+_LCD +3VS D
Del D41, Q64, C558, C598, R493
& Q65. 01/29
add 4.7UH inductor for CMO flicker issue C190 2 1 0.1U_0603_50V

C191 2 1 68P_0402_50V8J

R87

R88
L5 JP5
Modify design in 1/29. B+ 1 2 2 1

2
LQM21FN4R7N00L_0805 TXOUT_L0- <10>
+5VALW +5VS +5VS_INV 4 3
+3VS 6 5 TXOUT_L0+ <10>
8 7 HP request. (9/4)
LCDVDD 10 9 TXOUT_L1- <10>
TXOUT_L1+ <10>

2.2K_0402_5% 1

2.2K_0402_5% 1
12 11
<22> ALS_EN 14 13
4.7K_0402_5%

<10> BLON_PWM 16 15 TXOUT_L2- <10>

2

+5VALW +5V_WEBCAM

S
Q5

D
3 1 18 17 TXOUT_L2+ <10>
SI2301BDS_SOT23
Q4 20 19
22 21 TXCLK_L- <10>
R164

S
SI2301BDS_SOT23
G

D
+5V_WEBCAM TXCLK_L+ <10> 3 1

2
24 23
1

26 25

1U_0603_10V4Z

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
<22> USB20_P10 28 27 DDC2_CLK <10> 1 1 1 1

100K_0402_5%

G
DDC2_DATA <10>

2
DISPLAY_OFF <22> USB20_N10 30 29
+3VALW

C559

C313

C560

C561
32 31 2 2 2 2

R600
ACES_88242-3001_30P

1
6

Q81A CONN@

2
22_0402_5%
2N7002DW-T/R7_SOT363-6
1 R601 1 2
1

D 10K_0402_5% R602 47K_0402_5%

<10> ENABLT 2 R165
2
C Q83 G C
2 1
1

1
R81 2N7002_SOT23 @ D
S 1
3

100K_0402_1% 2 Q7 C562
<22> WEBCAM_ON/OFF#
G RHU002N06_SOT323 0.1U_0402_16V4Z
S

3
3

Q81B 2 +5VALW
2N7002DW-T/R7_SOT363-6

<19,22,33> LID_SW# 5

2 1
Reserve for power
+3VS
4

R634 saving. 3/19

10K_0402_5%

Add 10K pull down to prevent floating issue. 2/23

LCD POWER CIRCUIT

LCDVDD +3VS

LCDVDD
Connect LCD power source to
Q6 +3VS directly. 5/16
3 SI2301 1P_SOT23

S
1
1

B B
R166
100_0402_1%

G
2
R167 1 2 1M_0402_5%
1 2

D
Q41 2 R168 1 2 47K_0402_5% C192 1 2 0.1U_0402_16V4Z
RHU002N06_SOT323 G
S 1 1 1
3

C193 C194 C195

0.1U_0402_16V4Z 4.7U_0805_10V4Z @ 4.7U_0805_10V4Z
1

2 2 2
OUT

<10> ENAVDD 2 IN Q8
GND

DTC124EKAT146_SC59-3
2

R169
3

100K_0402_1%
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 18 of 36
5 4 3 2 1
 5 4 3 2 1

D D
+3VS +3VS

3
47K
R570 Q9
47K_0402_5% DTA114YKAT146_SOT23-3
10K 2 WL_LED# <26>

2
<30> WL/BT_LED WL/BT_LED

1
6
WL_LED
Q10A

1
BT_LED 2 2N7002DW-T/R7_SOT363-6
<31> BT_LED
Q10 & Q11
change to 2 in

3
1 package. 3/17 <26> WW_LED# 2 10K Q79
DTA114YKAT146_SOT23-3
Q10B
WL_LED 5 2N7002DW-T/R7_SOT363-6 47K

3
4
+3VS
BT_LED R170 1 2 100K_0402_5%
C C
WL_LED R171 1 2 100K_0402_5%

Cause space issue, move them from LED board to M/B. 10/09

+3VS

Q32
47K To LED BOARD
3

DTA114YKAT146_SOT23-3

2 10K
+5VS +3VL +3VS

To LID switch Board

1

D
HDD_HALTLED 2 Q80 JP6
<22> HDD_HALTLED
1

G 2N7002_SOT23 1 +3VS
1
S 2
3

B 2 D45 B
3 3
1

AMBER_BATLED# 4 @ BAV99_SOT323-3
<33> AMBER_BATLED# 4
@ R334 GREEN_BATLED# 5 3
<33> GREEN_BATLED# 5
100K_0402_5% IDE_LED# 6 1
<21> IDE_LED# 6
HDD_STP# 7 2
STB_LED 7
<30,34> STB_LED 8
2

WL/BT_LED 8 JP8
9 9
10 10 1 1
11 GND <18,22,33> LID_SW# 2 2 G1 4
12 GND 3 3 G2 5

CONN@ ACES_85201-1005N CONN@ ACES_85204-03001

+3VL

POWER LED
1

R620
360_0402_5%
2
2

D42
A A
aquq white QSMW-B121
1

STB_LED
Security Classification Compal Secret Data Compal Electronics, Inc.
Add in 11/28. Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
Place them close to SW1.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 19 of 36
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL#
R172 8.2K_0402_5%
1 2 PCI_STOP#
R173 8.2K_0402_5%
1 2 PCI_TRDY#
R174 8.2K_0402_5% <27> PCI_AD[0..31]
1 2 PCI_FRAME# U8B
R175 8.2K_0402_5% PCI_AD0 A11 G4 PCI_REQ0#
PCI_PLOCK# PCI_AD1 AD0 REQ0# PCI_GNT0#
D
1
R176
2
8.2K_0402_5% PCI_AD2
B12
A10
AD1 PCI GNT0# E1
A9 PCI_REQ1# D
PCI_IRDY# PCI_AD3 AD2 REQ1#/GPIO50
1 2 C12 AD3 GNT1#/GPIO51 E12 MODEM_DISABLE# <30>
R177 8.2K_0402_5% PCI_AD4 A8 B11 PCI_REQ2#
AD4 REQ2#/GPIO52 PCI_REQ2# <27>
1 2 PCI_SERR# PCI_AD5 A12 C10
AD5 GNT2#/GPIO53 PCI_GNT2# <27>
R178 8.2K_0402_5% PCI_AD6 E10 D6 PCI_REQ3#
PCI_PERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C11 AD7 GNT3#/GPIO55 C6
R179 8.2K_0402_5% PCI_AD8 B9
PCI_AD9 AD8 PCI_CBE#0
D8 AD9 C/BE0# D10 PCI_CBE#0 <27>
PCI_AD10 A4 A5 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 <27>
PCI_AD11 E8 E6 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 <27>
PCI_AD12 A3 C9 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 <27>
PCI_AD13 D9
PCI_AD14 AD13 PCI_IRDY#
C8 AD14 IRDY# C3 PCI_IRDY# <27>
+3VS PCI_AD15 C2 B1 PCI_PAR
AD15 PAR PCI_PAR <27>
PCI_AD16 D7 T3 PCI_RST#
AD16 PCIRST# PCI_RST# <26,27>
PCI_AD17 B3 A7 PCI_DEVSEL#
AD17 DEVSEL# PCI_DEVSEL# <27>
1 2 PCI_PIRQA# PCI_AD18 D11 D4 PCI_PERR#
AD18 PERR# PCI_PERR# <27>
R180 8.2K_0402_5% PCI_AD19 B6 C5 PCI_PLOCK#
PCI_PIRQB# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 D5 AD20 SERR# H5 PCI_SERR# <27,33>
R181 8.2K_0402_5% PCI_AD21 D3 A6 PCI_STOP#
AD21 STOP# PCI_STOP# <27>
1 2 PCI_PIRQC# PCI_AD22 F4 A2 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <27>
R182 8.2K_0402_5% PCI_AD23 E3 B8 PCI_FRAME#
AD23 FRAME# PCI_FRAME# <27>
1 2 PCI_PIRQD# PCI_AD24 E4
R183 8.2K_0402_5% PCI_AD25 AD24 PLT_RST#
B2 AD25 PLTRST# A21 PLT_RST# <8,26,32>
1 2 PCI_PIRQE# PCI_AD26 C4 B5 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH <16>
R184 8.2K_0402_5% PCI_AD27 C1 T1 PCI_PME#
AD27 PME# PCI_PME# <26>
1 2 ODD_DET# PCI_AD28 D1
R185 47K_0402_5% PCI_AD29 AD28
E2 AD29
1 2 PCI_PIRQG# PCI_AD30 J4
R186 8.2K_0402_5% PCI_AD31 AD30
H2 AD31
2 1 PCI_PIRQH#
R187 8.2K_0402_5%
C
1 2 PCI_REQ0# Change to ODD_DET#. 10/18 PCI_PIRQA# F1
Interrupt I/F G3 PCI_PIRQE# C
PIRQA# PIRQE#/GPIO2 PCI_PIRQE# <27>
R188 8.2K_0402_5% PCI_PIRQB# F5 G1 ODD_DET#
PIRQB# PIRQF#/GPIO3 ODD_DET# <21>
1 2 PCI_REQ1# PCI_PIRQC# F2 F3 PCI_PIRQG#
PIRQC# PIRQG#/GPIO4 PCI_PIRQG# <27>
R189 8.2K_0402_5% PCI_PIRQD# C7 H4 PCI_PIRQH# 2 1
PIRQD# PIRQH#/GPIO5 ACCEL_INT# <26>
1 2 PCI_REQ2# R190 0_0402_5%
R191 8.2K_0402_5% ICH9-M SFF ES_FCBGA569
1 2 PCI_REQ3#
R192 8.2K_0402_5%

A16 swap override Strap Boot BIOS Strap Place closely pin B10
B B
Low= A16 swap override Enble CLK_PCI_ICH
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

1
@
R193
10_0402_5%

0 1 SPI *

2
PCI_GNT3# 1
@
1 0 PCI C196
1

8.2P_0402_50V
2
R194
@ 1K_0402_5% 1 1 LPC
2

PCI_GNT0#
<22> KBC_SPI_CS1#
1

R195 R196
1K_0402_5% @ 1K_0402_5%
2

A A

DEL J3. 9/29

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 20 of 36
5 4 3 2 1
 5 4 3 2 1

+RTCVCC

1 2 LAN100_SLP
R197 330K_0402_1%
1 2 SM_INTRUDER#
R198 1M_0402_5%
1 2 ICH_INTVRMEN
R199 330K_0402_1%

0_0402_5%

0_0402_5%
R201

R202
1 2 ICH_SRTCRST#

2
R200 20K_0402_5%
Change from 180K to 20K C197
1
& 0.1u to 1u. 9/29
1U_0603_10V4Z @ @

1
D 2 D

ICH_RSVD HDA_SDOUT_CODEC Description

0 0 RV U8A
LPC_AD[0..3] <26,32,33>
ICH_RTCX1 F25 H3 LPC_AD0 9/27
0 1 XOR R205 ICH_RTCX2 G25
RTCX1
RTCX2
FWH0/LAD0
FWH1/LAD1 J3 LPC_AD1
20K_0402_5% K5 LPC_AD2
1 0 Normal(D) +RTCVCC 1 2 ICH_RTCRST# G24 RTCRST#
FWH2/LAD2
FWH3/LAD3 L3 LPC_AD3 Del PU R203~R204 9/27
ICH_SRTCRST# C24
1 1 PCIE Bit1

RTC
LPC
SRTCRST# for H_DPRSTP# &

CLRP1
SM_INTRUDER#

SHORT PADS
C23 INTRUDER# FWH4/LFRAME# J2 LPC_FRAME# <26,32,33>
XOR CHAIN ENTRANCE STRAP:RSVD 1 H_DPSLP#. +1.05VM

1
C198 ICH_INTVRMEN E25 H1
+3VS INTVRMEN LDRQ0# T111 PAD
LAN100_SLP D25 J1
LAN100_SLP LDRQ1#/GPIO23 T48 PAD
1U_0603_10V4Z

2
2 GATEA20
<24> GLAN_CLK G22 GLAN_CLK A20GATE N3 GATEA20 <33>
1 2 AC97_SDOUT AB23 R207
A20M# H_A20M# <4>
R206 @ 1K_0402_5% <24> LAN_RSTSYNC D14 56_0402_5%
ICH_RSVD LAN_RSTSYNC H_DPRSTP_R# R209
1 2 ICH_RSVD <22> DPRSTP# AE23 1 2 0_0402_5% H_DPRSTP# <5,8,42>
R208 @ 1K_0402_5% <24> LAN_RXD0 A14 AE24

LAN / GLAN
H_DPSLP# <5>

1
LAN_RXD0 DPSLP#
<24> LAN_RXD1 D12 LAN_RXD1
<24> LAN_RXD2 B14 AD25 H_FERR#_R R210 1 2 56_0402_5% H_FERR#
LAN_RXD2 FERR# H_FERR# <4>

<24> LAN_TXD0 D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGOOD <4,5>

<24> LAN_TXD1 C13 LAN_TXD1
Place Close to U8.
Add C599 ~ C602 to solve WWAN noise issue. 1/23 <24> LAN_TXD2 A13 AD23 +3VS
LAN_TXD2 IGNNE# H_IGNNE# <4>

CPU
PAD T50 D15 GPIO56 INIT# AE21 H_INIT# <4>
56P_0402_50VNPO AD24 +VCCP GATEA20 R216 1 2 10K_0402_5%
C INTR H_INTR <4> C
C599 2 1 H22 L1 KB_RST# KB_RST# R218 1 2 10K_0402_5%
GLAN_COMPI RCIN# KB_RST# <33>
+1.5VS R220 1 2 24.9_0402_1% GLAN_COMP H21 GLAN_COMPO

1
Remove R227 & C199 <30> AC97_BITCLK_MDC AC97_BITCLK_MDC R211 1 2 33_0402_5% AD21
NMI H_NMI <4>
<28> AC97_BITCLK_CODEC AC97_BITCLK_CODEC R212 1 2 33_0402_5% HDA_BITCLK AE7 AC21 H_SMI# R223
HDA_BIT_CLK SMI# H_SMI# <4>
R213 1 2 33_0402_5% HDA_SYNC AB7 56_0402_5%
<28> AC97_SYNC_CODEC HDA_SYNC
2 1 R214 1 2 33_0402_5% AC25 H_STPCLK#
<30> AC97_SYNC_MDC STPCLK# H_STPCLK# <4>
C600 R215 1 2 33_0402_5% HDARST# AA7
<28> AC97_RST#_CODEC

2
56P_0402_50VNPO R217 33_0402_5% HDA_RST# THRMTRIP_ICH# R226
<30> AC97_RST#_MDC 1 2 THRMTRIP# AC23 1 2 54.9_0402_1% H_THERMTRIP# <4,8>
<28> AC97_SDIN0 AB6 HDA_SDIN0
placed within 2" from
<30> AC97_SDIN1 AE6 HDA_SDIN1 TP11 AC22 T49 PAD ICH9M
56P_0402_50VNPO AC6

IHDA
HDA_SDIN2
C601 2 1 Swap in 9/28 AA5 HDA_SDIN3
SATA4RXN AD12
AC97_SDOUT_MDC R219 1 2 33_0402_5% AC97_SDOUT AC7 AE12
<30> AC97_SDOUT_MDC HDA_SDOUT SATA4RXP
AC97_SDOUT_CODEC R221 1 2 33_0402_5% AB12
<28> AC97_SDOUT_CODEC SATA4TXN
<33> G_BATLED# AD8 HDA_DOCK_EN#/GPIO33 SATA4TXP AA12
2 1 PAD T114 AB8 HDA_DOCK_RST#/GPIO34
C602 +3VS 2 1 AC11
56P_0402_50VNPO R229 10K_0402_5% SATA5RXN
<19> IDE_LED# AC9 SATALED# SATA5RXP AD11
SATA5TXN AB10
SATA_RXN0_C AE14 AA10
SATA_RXP0_C SATA0RXN SATA5TXP
AD14 SATA0RXP

SATA
SATA_TXN0_CR R646 1 2 0_0402_5% SATA_TXN0_R AC15 AC16 CLK_PCIE_SATA#
SATA0TXN SATA_CLKN CLK_PCIE_SATA# <16>
SATA_TXP0_CR R647 1 2 0_0402_5% SATA_TXP0_R AD15 AB16 CLK_PCIE_SATA
SATA0TXP SATA_CLKP CLK_PCIE_SATA <16>
SATA_RXN1_C AD13 AD10
SATA_RXP1_C SATA1RXN SATARBIAS# R230
AC13 SATA1RXP SATARBIAS AE10 1 2 18_0402_1%
SATA_TXN1_CR R648 1 2 0_0402_5% SATA_TXN1_R AA14
SATA_TXP1_CR R649 1 2 0_0402_5% SATA_TXP1_R AB14
SATA1TXN Within 500 mils
SATA1TXP

B
SATA CD-ROM Connector
JP9
ICH9-M SFF ES_FCBGA569

ICH_RTCX1 B
7/3 change 24.9 ohm to 18 ohm for signal integrity.
CONN@ OCTEK_SAT-22DE1G_NRSUYIN_127059FR022S305ZL
R231
1 1 2 ICH_RTCX2
GND SATA_TXP1_C
C203 1
A+ 2 20.01U_0402_50V7K SATA_TXP1_CR
3 SATA_TXN1_C
C202 1 20.01U_0402_50V7K SATA_TXN1_CR 10M_0402_5%
A-
GND 4
1.8" SATA HDD CONN

C206

C207
5 SATA_RXN1 C204 1 2 0.01U_0402_50V7K SATA_RXN1_C
B- SATA_RXP1 C205 1 SATA_RXP1_C
B+ 6 2 0.01U_0402_50V7K
7 Y2
GND

4
1 1

32.768KHZ_12.5P_1TJS125BJ2A251
IN

OUT
8 R357 1 2 0_0402_5% JP10
DP ODD_DET# <20>
9 SATA_TXP0_CR 0.01U_0402_50V7K 2 1 C201 SATA_TXP0_C
V5 1 2 2
0.1U_0402_16V4Z

10 +5VS 1 SATA_TXN0_CR 0.01U_0402_50V7K 2 1 C200 SATA_TXN0_C ZZZ1

V5 2
12P_0402_50V8J

12P_0402_50V8J
NC

NC
MD 11 3
12 SATA_RXN0_C 0.01U_0402_50V7K 2 1 C208 SATA_RXN0
GND SATA_RXP0_C 0.01U_0402_50V7K 2 4
13 1 C209 SATA_RXP0

3
GND 2 5
C593

GND 14 6
GND 15 7
+3VS 8 PCB-MB
CONN@ ACES_85201-08051
JBATT1
+RTCVCC +3VL
C211

C212

C213

C214
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D8
+5VS 1 1 1 1 3 R233
R232 1 2 0_0402_5% 1 1K_0402_5%

2 2 2 2 1
2 RTC1 1 2 RTC2 1 + + - - 2
C219

C220

C221

C222
0.1U_0402_16V4Z

C210 DAN202UT106_SC70-3 W=20mils

L
10U_0805_10V4Z

A A
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1U_0603_10V4Z
2
Place component's CONN@ SUYIN_060003FA002G202NL
2 2 2 2
L closely SATA
CONN.(JP10)
Security Classification Compal Secret Data Compal Electronics, Inc.
Place component's Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

L closely SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
CONN.(JP9) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 21 of 36
5 4 3 2 1
 5 4 3 2 1

+3VS +3VALW
Add R326 10K. 10/04 VRMPWRGD R595 1 2 10K_0402_5% +3VS
1 2 LAN_STATUS#_D PM_PWROK_R 1 2 PM_PWROK <8,33,42,43>

RHU002N06_SOT323
R326 10K_0402_5% R328 0_0402_5%
1 2 SIRQ Reserve for DB1 test. 10/05 Change HDD_HALTLED from

1
R234 10K_0402_5% R235 R236 D
1 2 PM_CLKRUN# 2.2K_0402_5% 2.2K_0402_5% GPIO18 to GPIO19. 11/26 2 R596 1 2 0_0402_5%
R237 8.2K_0402_5% U8C G CLK_ENABLE# <42>

Q63
1 2 THERM_SCI# ICH_SMBCLK R241 2 1 @ 0_0402_5% ICH_SMB_CLK C18 AE19 GPIO21 S

3
R242 @ 8.2K_0402_5% ICH_SMBDATA R243 SMBCLK SATA0GP/GPIO21
2 1 @ 0_0402_5% ICH_SMB_DATA C15 SMBDATA SATA1GP/GPIO19 AA18 HDD_HALTLED
HDD_HALTLED <19> 1
1 2 HDD_HALTLED LINKALERT# B21 AE20 NPCI_RST# C547

SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 NPCI_RST# <33>

GPIO
SMB
R245 47K_0402_5% 9/21 ME__EC_CLK1 E18 AA20 GPIO37
SMLINK0 SATA5GP/GPIO37
1 2 GPIO22 ME__EC_DATA1 A24 SMLINK1
@ 0.1U_0402_16V4Z
R246 8.2K_0402_5% CLK_14M_ICH 2
CLK14 K1 CLK_14M_ICH <16>
1 2 NPCI_RST# +3VM ICH_RI# C20 AB5 CLK_48M_ICH

Clocks
D RI# CLK48 CLK_48M_ICH <16> D
R248 10K_0402_5%
1 2 ALS_EN# <32> LPC_PD# T5 SUS_STAT#/LPCPD# SUSCLK R3 ICH_SUSCLK T53 PAD
R244 @ 8.2K_0402_5% XDP_DBRESET# C25 Add for find tune timing.(If have glich issue)
<4> XDP_DBRESET# SYS_RESET#

1
1 2 GPIO21 D18 SLP_S3#
SLP_S3# SLP_S3# <24,26,28,33,35,36,38,41,42,44>
R68 8.2K_0402_5% R249 R250 PM_BMBUSY# L2 B20 SLP_S4#
<8> PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# <36,40> +3VL
1 2 GPIO37 @ 10K_0402_5% @ 10K_0402_5% D16 SLP_S5#
SLP_S5# SLP_S5# <36>
R508 8.2K_0402_5% GPIO11 A23 Reserve R254 at 9/19.
SMBALERT#/GPIO11
1 2 GPIO18 Add R621 in 12/03. E14 S4_STATE#
S4_STATE# <31>

2
S4_STATE#/GPIO26

2
R621 10K_0402_5% H_STP_PCI# B15
<16> H_STP_PCI# STP_PCI#/GPIO15
GPIO57 R253 1 2 0_0402_5% R_STP_CPU# PM_PWROK_R R254 1 2 @ 10K_0402_5%

SYS GPIO
1 2 <16> H_STP_CPU# A20 STP_CPU#/GPIO25 PWROK D23
R626 @ 10K_0402_5% R257
+3VALW PM_CLKRUN# M5 M1 DPRSLPVR 1 2 100K_0402_5%
<27,32,33> PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR <8,42>
R256 0_0402_5%

1
Power MGT
1 2 LINKALERT# <26> PCIE_WAKE#
PCIE_WAKE# C21 WAKE# BATLOW# C16 ICH_LOW_BAT# 2 1 LOW_BAT# <33>
R252 10K_0402_5% SIRQ L4 D9 CH751H-40_SC76
<27,32,33> SIRQ SERIRQ
1 2 PCIE_WAKE# Change in 7/13 <4> THERM_SCI#
THERM_SCI# AD20 THRM# PWRBTN# U4 ON/OFFBTN# <30>
R255 10K_0402_5%
1 2 ICH_RI# <42> VGATE
R262 1 2 @ 0_0402_5% VRMPWRGD B24 VRMPWRGD LAN_RST# D22 LAN_DISABLE_N <33>
R258 10K_0402_5% R325 1 2 @ 100K_0402_5% R366 1 2 0_0402_5% RPGOOD <39>
1 2 XDP_DBRESET# Reserve in 10/08. PAD T54 A19 TP12 RSMRST# D19 RSMRST# 1 2 PM_RSMRST# <33>
R259 1K_0402_5% R263 10K_0402_5%
1 2 S4_STATE# Change R251 to CH751. 10/04 <44> OCP# AE16 GPIO1 CK_PWRGD U1 CK_PWRGD_R 1 2 CK_PWRGD <16>
R260 10K_0402_5% AE18 R265 0_0402_5%
<33> RUNSCI_EC# GPIO6
1 2 ICH_LOW_BAT# LAN_STATUS# 1 2 LAN_STATUS#_D AD18 GPIO7 CLPWROK T4 M_PWROK
M_PWROK <8,35>
R321 10K_0402_5% D40 CH751H-40_SC76 ISO_PREP# B25
R268 1 LAN_PHYPC_R GPIO8
Add R321 in 10/03. <24,25,33> LAN_PHYPC 2 10K_0402_5% C14 GPIO12 SLP_M# B23 PM_SLP_M# <33,36,40,41>
<18,19,33> LID_SW# D20 R271
GPIO13
1 2 SUS_PWR_ACK ALS_EN# AE17 GPIO17 CL_CLK0 C22 CL_CLK0
CL_CLK0 <8>
3.24K_0402_1%
R266 10K_0402_5% for Intel LAN_PHYPC glitch issue 5/7 GPIO18 K3 A18 CL_CLK1 1 2 +3VM
GPIO18 CL_CLK1 CL_CLK1 <26>

0.1U_0402_16V4Z
1 2 AC_PRESENT PAD T95 AC8 GPIO20

1
453_0402_1%
R269 @ 10K_0402_5% GPIO22 AC19 E22 CL_DATA0
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>

Controller Link
1 2 ME__EC_CLK1 Add EXP_RST# in 10/09. D17 B18 CL_DATA1 1

GPIO
PAD T55 GPIO27 CL_DATA1 CL_DATA1 <26>

R274
C R272 10K_0402_5% C
PAD T96 E20 GPIO28
1 2 ME__EC_DATA1 <16> CLKSATAREQ# M4 SATACLKREQ#/GPIO35 CL_VREF0 F21 CL_VREF0_ICH

C225
R273 10K_0402_5% +3VS 1 2 GPIO38 AB18 A17 CL_VREF1_ICH

2
SLOAD/GPIO38 CL_VREF1 2
1 2 LAN_PHYPC_R R275 8.2K_0402_5%
PAD T107
GPIO39 AC18 SDATAOUT0/GPIO39
R331 10K_0402_5% EXP_RST AB19 C17 CL_RST#
<26> EXP_RST SDATAOUT1/GPIO48 CL_RST0# CL_RST# <8>
AC20 B17 CL_RST#1 R277
+3VALW PAD T116 GPIO49 CL_RST1# CL_RST#1 <26>
R276 GPIO57 A16 3.24K_0402_1%
R276 1 GPIO57/CLGPIO5
low -->default +3VS 2 @ 1K_0402_5% MEM_LED/GPIO24 A22 1 2 +3VALW

0.1U_0402_16V4Z
RP16 High -->No boot SB_SPKR K4 E16 SUS_PWR_ACK
<28> SB_SPKR SPKR GPIO10/SUS_PWR_ACK SUS_PWR_ACK <33>

453_0402_1%
1
5 4 USB_OC#7 MCH_ICH_SYNC# AB20 A15 AC_PRESENT 1
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT <33>
6 3 USB_OC#5 ICH_RSVD C19 D21
<21> ICH_RSVD TP3 WOL_EN/GPIO9 LAN_WOL_EN <33,36>

R278
+3VALW

MISC
7 2 USB_OC#0 PAD T56 AB17 Add in 10/04.
TP8

C226
8 1 USB_OC#4 PAD T57 AC17 Add WOL_EN back. 10/10
TP9 2
PAD T58 AD17

2
TP10
1

10K_1206_8P4R_5% +3VALW +3VM_LAN

RP15 R280 ICH9-M SFF ES_FCBGA569
5 4 USB_OC#1 10K_0402_5% Change design in 10/08. Add R626, R627 for U8D
6 3 USB_OC#6 iTPM test. 12/11 T25 PERN1 DMI0RXN V25 DMI_RXN0 DMI_RXN0 <8>

5
2 WXMIT_OFF# DMI_RXP0 U10

Direct Media Interface

7 T24 PERP1 V24 DMI_RXP0 <8>
2

DMI0RXP
8 1 USB_OC#2 R332 1 2 0_0402_5% ISO_PREP# R24 PETN1 U24 DMI_TXN0 1 SLP_S3#

P
<25,34> PREP# DMI0TXN DMI_TXN0 <8> IN1
R23 PETP1 U23 DMI_TXP0 DMI_TXP0 <8> 4
10K_1206_8P4R_5% DMI0TXP O
IN2 2

G
1 2 GPIO11 <26> PCIE_RXN2
PCIE_RXN2 P25 PERN2 DMI1RXN W23 DMI_RXN1 DMI_RXN1 <8>
R238 10K_0402_5% PCIE_RXP2 P24 W24 DMI_RXP1 DMI_RXP1 <8> SN74AHC1G08DCKR_SC70
<26> PCIE_RXP2

3
PERP2 DMI1RXP
1 2 XMIT_OFF# <26> PCIE_TXN2 C227 1 2 0.1U_0402_16V4Z PCIE_C_TXN2 P21 PETN2 WLAN DMI1TXN V21 DMI_TXN1 DMI_TXN1 <8>
R603 10K_0402_5% <26> PCIE_TXP2 C228 1 2 0.1U_0402_16V4Z PCIE_C_TXP2 P22 V22 DMI_TXP1 DMI_TXP1 <8>
PETP2 DMI1TXP
Add in 9/14.
PCIE_RXN3 N23 Y24 DMI_RXN2 DMI_RXN2 <8>
Add RP15 back. 9/27 +3VM <26> PCIE_RXN3 PERN3 DMI2RXN
PCIE_RXP3 N24 Y25 DMI_RXP2

PCI-Express
<26> PCIE_RXP3 PERP3 DMI2RXP DMI_RXP2 <8>
1 2 EXP_RST <26> PCIE_TXN3 C229 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 M21 EXP Y21 DMI_TXN2 DMI_TXN2 <8>
PETN3 DMI2TXN

2
G
R335 10K_0402_5% <26> PCIE_TXP3 C230 1 2 0.1U_0402_16V4Z PCIE_C_TXP3 M22 PETP3 DMI2TXP Y22 DMI_TXP2 DMI_TXP2 <8> R294 2 110K_0402_5% +3VALW
1 2 GPIO57 R283
1

B R627 @ 10K_0402_5% 2.2K_0402_5% PCIE_RXN4 DMI_RXN3 LAN_STATUS# B

<26> PCIE_RXN4 M25 PERN4 DMI3RXN AB24 DMI_RXN3 <8><24,25,33> LANLINK_STATUS# 3 1
R282 PCIE_RXP4 DMI_RXP3 Q17

D
<26> PCIE_RXP4 M24 PERP4 DMI3RXP AB25 DMI_RXP3 <8>
2.2K_0402_5% Q12 <26> PCIE_TXN4 C231 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 L24 WWAN AA23 DMI_TXN3 DMI_TXN3 <8> RHU002N06_SOT323
PETN4 DMI3TXN
RHU002N06_SOT323 <26> PCIE_TXP4 C232 1 2 0.1U_0402_16V4Z PCIE_C_TXP4 L23 PETP4 DMI3TXP AA24 DMI_TXP3 DMI_TXP3 <8>
2

2
S

ICH_SMBDATA 3 1 ICH_SMB_DATA K24 T21 CLK_PCIE_ICH#

<14,15,16> ICH_SMBDATA ICH_SMB_DATA <26> PERN5 DMI_CLKN CLK_PCIE_ICH# <16>
K25 T22 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH <16>
S

ICH_SMBCLK 3 1 ICH_SMB_CLK K21

<14,15,16> ICH_SMBCLK ICH_SMB_CLK <26> PETN5
Within 500 mils
G

K22 AB21
2

+3VM Q13 PETP5 DMI_ZCOMP DMI_IRCOMP R284 1

DMI_IRCOMP AB22 2 24.9_0402_1% +1.5VS
RHU002N06_SOT323 GLAN_RXN
G

<24> GLAN_RXN H24

2

GLAN_RXP PERN6/GLAN_RXN
+3VS <24> GLAN_RXP
C233 1 0.1U_0402_16V4Z GLAN_TXN_C
H25 PERP6/GLAN_RXP USBP0N GLAN AE2 USB20_N0 <31>
<24> GLAN_TXN 2 J24 PETN6/GLAN_TXN USBP0P AD1 USB20_P0 <31>MB
<24> GLAN_TXP C234 1 2 0.1U_0402_16V4Z GLAN_TXP_C J23 AD3
PETP6/GLAN_TXP USBP1N
USBP1P AD4
R285 1 2 15_0402_5% KBC_SPI_CLK E24 AC2
<33> KBC_SPI_CLK_R SPI_CLK USBP2N USB20_N2 <26>
<33> KBC_SPI_CS0#_R
R286 1 2 15_0402_5% KBC_SPI_CS0# E23 SPI_CS0# USBP2P AC3 USB20_P2 <26>EXPRESS
1

R290 1 2 15_0402_5% KBC_SPI_CS1# F23 AC5

<33> KBC_SPI_CS1#_R SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 <26>WLAN
R287 R288 AB4
<20> KBC_SPI_CS1# USBP3P USB20_P3 <26>
2.2K_0402_5% 2.2K_0402_5% R289 1 2 15_0402_5% KBC_SPI_SI F22 AB2 Place closely pin AF3 Place closely pin H1
<33> KBC_SPI_SI_R SPI_MOSI USBP4N USB20_N4 <31>
SPI

<33> KBC_SPI_SO G23 SPI_MISO USBP4P AB1 USB20_P4 <31>MB

Q14 AA3 USB20_N5 <31>
2

RHU002N06_SOT323 USB_OC#0 USBP5N CLK_48M_ICH CLK_14M_ICH

P4 OC0#/GPIO59 USBP5P AA2 USB20_P5 <31>MB
USB_OC#1 N4 Y1
OC1#/GPIO40 USBP6N USB20_N6 <31>
S

ICH_SMB_DATA USB_OC#2
<4,26> ICH_SM_DA 3 1 N1 OC2#/GPIO41 USB
USBP6P Y2 USB20_P6 <31>Bluetooth

1
WXMIT_OFF# P5 W2 @ @
<26> WXMIT_OFF# OC3#/GPIO42 USBP7N USB20_N7 <26>
S

<4,26> ICH_SM_CLK 3 1 ICH_SMB_CLK USB_OC#4 P1 OC4#/GPIO43 USBP7P W3 USB20_P7 <26>WWAN

R239 R240
Q15 USB_OC#5 10_0402_5% 10_0402_5%
G

P2 V1 USB20_N8 <32>
2

RHU002N06_SOT323 USB_OC#6 OC5#/GPIO29 USBP8N

M3 OC6#/GPIO30 USBP8P V2 USB20_P8 <32>Fingerprint
USB_OC#7
G

M2 Y5
2

2
+3VS R291 1 0_0402_5% OC7#/GPIO31 USBP9N USB20_N9 <34>
<31> BT_OFF 2
XMIT_OFF#
P3 OC8#/GPIO44 USBP9P Y4 USB20_P9 <34>DOCK
+5VS <26> XMIT_OFF# R1 OC9#/GPIO45 USBP10N U3 USB20_N10 <18> 1 @ 1 @
A C223 C224 A
<18> WEBCAM_ON/OFF# R4 OC10#/GPIO46 USBP10P U2 USB Camera
USB20_P10 <18>
2

R292 R2 V4
<32> FPR_OFF OC11#/GPIO47 USBP11N
USBP11P V5 Pin connection error, modify in 10/24. 4.7P_0402_50V8C 4.7P_0402_50V8C
USBRBIAS 2 2
AE5 USBRBIAS
330_0402_5% AD5 USBRBIAS#
1

Within 500 mils

1

ICH9-M SFF ES_FCBGA569

ALS_EN <18>
R293
Security Classification Compal Secret Data Compal Electronics, Inc.
1

D 22.6_0402_1%
ALS_EN# 2 Q16 2006/02/13 2006/03/10 Title
Issued Date Deciphered Date
2

G RHU002N06_SOT323
S SCHEMATIC, M/B LA-4021P
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 22 of 36
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U8E

20 mils U8F B4 U5
VSS[001] VSS[107] +3VS
G17 VCCRTC VCC1_05[01] L11 B7 VSS[002] VSS[108] U10

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCC1_05[02] L12 B10 VSS[003] VSS[109] W11

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 ICH_V5REF_RUN G7 L13 B13 U14
V5REF VCC1_05[03] VSS[004] VSS[110]

100K_0402_5%
C235

C236
VCC1_05[04] L14 1 1 B16 VSS[005] VSS[111] W16

2
ICH_V5REF_SUS U7 L15 B19 U21
V5REF_SUS VCC1_05[05] VSS[006] VSS[112]

R247
VCC1_05[06] M11 B22 VSS[007] VSS[113] U22
2 2

C237

C238
J19 M15 D2 U25 CRACK_BGA
+1.5VS_PCIE_ICH VCC1_5_B[01] VCC1_05[07] 2 2 VSS[008] VSS[114]
K18 VCC1_5_B[02] VCC1_05[08] N11 D24 VSS[009] VSS[115] V3
K19 N15 E5 V8

1
VCC1_5_B[03] VCC1_05[09] VSS[010] VSS[116]

1
D
L18 VCC1_5_B[04] VCC1_05[10] P11 E7 VSS[011] VSS[117] V19
L19 P15 E9 V23 ICHGND1 2
R295 VCC1_5_B[05] VCC1_05[11] VSS[012] VSS[118]
40 mils M18 VCC1_5_B[06] VCC1_05[12] R11 E11 VSS[013] VSS[119] W1 G
+1.5VS 1 2 M19 R12 E13 W4 Q72 S

3
D BLM18PG181SN1D_0603 VCC1_5_B[07] VCC1_05[13] VSS[014] VSS[120] RHU002N06_SOT323 D
N18 VCC1_5_B[08] VCC1_05[14] R13 E15 VSS[015] VSS[121] W5

10U_0805_10V4Z

10U_0805_10V4Z

2.2U_0603_6.3V4Z
1 1 1 N19 VCC1_5_B[09] VCC1_05[15] R14 E17 VSS[016] VSS[122] W7

220U_D2_4VM_R15
1 P18 VCC1_5_B[10] VCC1_05[16] R15 E19 VSS[017] VSS[123] W9
+
R18 VCC1_5_B[11] 9/29 E21 VSS[018] VSS[124] W15

C239

C240

C241
T18 R296 F24 W19
2 2 2 VCC1_5_B[12] VSS[019] VSS[125]
T19 VCC1_5_B[13] 1 2 +1.5VS G2 VSS[020] VSS[126] W21
VCC_DMI

C242

0.01U_0402_16V7K

10U_0805_10V4Z
U18 G5 W22

CORE
2 VCC1_5_B[14] VSS[021] VSS[127]
U19 VCC1_5_B[15] 1 1 MBK1608301YZF 0603 G10 VSS[022] VSS[128] W25
+3VS

1U_0603_10V4Z
G13 VSS[023] VSS[129] Y3
1 G16 VSS[024] VSS[130] Y23

C243

C244
G19 VSS[025] VSS[131] AA1
2 2

100K_0402_5%
G21 VSS[026] VSS[132] AA4

2
C245
H10 VSS[027] VSS[133] AA6
2

R414
H12 VSS[028] VSS[134] AA8
VCCDMIPLL P19 +1.5VS_DMIPLL H18 VSS[029] VSS[135] AA11 CRACK_BGA
9/29 9/29 +VCCP
H23 VSS[030] VSS[136] AA13
T17 R297 J5 AA15

1
VCC_DMI[1] VSS[031] VSS[137]

1
+5VS +3VS +5VALW +3VALW VCC_DMI D
VCC_DMI[2] U17 1 2 +VCCP J9 VSS[032] VSS[138] AA16
(DMI) J10 AA17 ICHGND3 2
MBK1608301YZF 0603 VSS[033] VSS[139] G
V_CPU_IO[1] V16 J11 VSS[034] VSS[140] AA19
1

2 U16 J12 AA21 Q73 S

3
V_CPU_IO[2] VSS[035] VSS[141]

0.1U_0402_16V4Z

4.7U_0805_10V4Z
R298 D11 R299 D12 J13 AA22 RHU002N06_SOT323
VSS[036] VSS[142]
VCC3_3[01] V18 +3VS 1 1 J15 VSS[037] VSS[143] AA25
100_0402_5% CH751H-40_SC76 10_0402_5% CH751H-40_SC76 J21 AB3
VSS[038] VSS[144]

VCCA3GP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AE9 J22 AB9
2

VCC3_3[02] VSS[039] VSS[145]

C246

C247
ICH_V5REF_SUS 1 1 1 J25 AB11
ICH_V5REF_RUN 2 2 VSS[040] VSS[146]
20 mils K2 VSS[041] VSS[147] AB13
20 mils K9 VSS[042] VSS[148] AB15

C248

C249

C250
1 1 VCC3_3[03] AA9 K10 VSS[043] VSS[149] AC24
C251 C252 2 2 2
VCC3_3[04] V14 K11 VSS[044] VSS[150] AC1
W14 +3VS K12 AC4
1U_0603_10V4Z 0.1U_0402_16V4Z VCC3_3[05] VSS[045] VSS[151] +3VS
9/19 2 2
K13 VSS[046] VSS[152] AC10

VCCP_CORE
C C
K15 VSS[047] VSS[153] AC12

0.1U_0402_16V4Z
VCC3_3[06] G8 K17 VSS[048] VSS[154] AC14

100K_0402_5%
VCC3_3[07] H7 1 K23 VSS[049] VSS[155] AD2

2
VCC3_3[08] H8 L5 VSS[050] VSS[156] AD6

R488
L9 VSS[051] VSS[157] AD9

C253
L10 AD16 CRACK_BGA
2 VSS[052] VSS[158]
L16 VSS[053] VSS[159] AD19
+1.5VS_VCCSATAPLL L17 AD22

1
VSS[054] VSS[160]

1
D

PCI
L21 VSS[055] VSS[161] AE3
AD7 +3VS L22 AE4 ICHGND2 2
VCCHDA VSS[056] VSS[162]

0.1U_0402_16V4Z
R300 L25 AE11 G
VSS[057] VSS[163] Q74
+1.5VS 1 2 W17 V10 +3VALW M9 AE13 S

3
VCCSATAPLL VCCSUSHDA VSS[058] VSS[164]

0.1U_0402_16V4Z
MBK1608301YZF 0603 1 M10 AE15 RHU002N06_SOT323
VSS[059] VSS[165]
1U_0603_10V4Z

10U_0805_10V4Z

+1.5VS U13 T7 VCCSUS1_05_ICH_1 T59 1 M12 V17

VCC1_5_A[01] VCCSUS1_05[1] VSS[060] VSS[166]
1U_0603_10V4Z

1 1 V13 VCC1_5_A[02] VCCSUS1_05[2] H15 VCCSUS1_05_ICH_2 T60 M13 VSS[061] VSS[167] AE8

C254
1 W13 VCC1_5_A[03] M14 VSS[062] VSS[168] V9
2
ARX

C255
VCCSUS1_5[1] H16 VCCSUS1_5_ICH_1 T61 M16 VSS[063] VSS[169] J16
2
C256

C257

M17 VSS[064]
2 2
C258

V7 VCCSUS1_5_ICH_2 T62 M23

2 VCCSUS1_5[2] VSS[065]
N2 VSS[066]
N5 VSS[067]
G14 N9 +3VS
VCCSUS3_3[01] +3VALW VSS[068]
U12 VCC1_5_A[04] VCCSUS3_3[02] G15 N10 VSS[069]
1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V12 VCC1_5_A[05] VCCSUS3_3[03] H14 N12 VSS[070]
VCCPSUS

100K_0402_5%
1 W12 VCC1_5_A[06] 1 1 N13 VSS[071]

2
+3VALW
ATX

N14 VSS[072]

R491
N16 VSS[073]
C259

C260

C261
VCCSUS3_3[04] W8 N17 VSS[074]
2 2 2
N21 VSS[075]

4.7U_0805_10V4Z
J7 N22

1
VCCSUS3_3[05] VSS[076]

1
D
VCCSUS3_3[06] J8 1 N25 VSS[077]
W10 K7 P9 ICHGND4 2
B VCC1_5_A[07] VCCSUS3_3[07] VSS[078] B
0.1U_0402_16V4Z

K8 P10 G
VCCSUS3_3[08] VSS[079] Q75
1 U15 L7 P12 S

3
VCC1_5_A[08] VCCSUS3_3[09] 2 VSS[080]

C262
V15 L8 P13 RHU002N06_SOT323
VCC1_5_A[09] VCCSUS3_3[10] VSS[081]
VCCSUS3_3[11] M7 P14 VSS[082]
W18 VCC1_5_A[10] VCCSUS3_3[12] M8 P16 VSS[083]
2
C263

N7 P17 CRACK_BGA
VCCSUS3_3[13] VSS[084] <13,33> CRACK_BGA
VCCPUSB

G9 VCC1_5_A[11] VCCSUS3_3[14] N8 P23 VSS[085]

H9 VCC1_5_A[12] VCCSUS3_3[15] P7 R5 VSS[086]
VCCSUS3_3[16] P8 R7 VSS[087]
+1.5VS_USBPLL V11 R8
VCC1_5_A[13] VSS[088]
U11 VCC1_5_A[14] 9/21 R9 VSS[089]
C217 R10
R301 0.1U_0402_16V4Z VSS[090]
R16 VSS[091]
+1.5VS 1 2 U8 G18 VCCCL1_05_ICH 1 2 R17
VCCUSBPLL VCCCL1_05 VSS[092]
R19 VSS[093]
0.1U_0402_16V4Z

0.1U_0402_16V4Z

MBK1608301YZF 0603 1 1 T9 H17 1 2 R21 A1 ICHGND1 R358 1 2 @ 0_0402_5%

VCC1_5_A[15] VCCCL1_5 VSS[094] VSS_NCTF[01]
USB CORE

U9 C264 1U_0603_10V4Z R22 A25 ICHGND2 R361 1 2 @ 0_0402_5%

VCC1_5_A[16] VSS[095] VSS_NCTF[02] ICHGND3 R368 @ 0_0402_5%
J14 +3VM_WOL R25 AE1 1 2
VCCCL3_3[1] 9/21 VSS[096] VSS_NCTF[03]
C265

C266

K14 T2 AE25 ICHGND4 R399 1 2 @ 0_0402_5%

2 2 C267 VCCCL3_3[2] VSS[097] VSS_NCTF[04]
T8 VSS[098]
0.1U_0402_16V4Z T10
+3VM_WOL VCC_LAN1_05_INT_ICH VSS[099]
2 1 G11 VCCLAN1_05[1] T11 VSS[100]
H11 VCCLAN1_05[2] T12 VSS[101]
R302 T13 VSS[102]
1 2 G12 VCCLAN3_3[1] T14 VSS[103]
R303 H13 T15
MBK1608301YZF 0603 MBK1608301YZF 0603 VCCLAN3_3[2] VSS[104]
T16 VSS[105]
+1.5VS 1 2 +1.5VS_GLAN J17 T23
VCCGLANPLL VSS[106]
0.1U_0402_16V4Z

1
GLAN POWER

H19 ICH9-M SFF ES_FCBGA569

+1.5VS_PCIE_ICH VCCGLAN1_5[1]
10U_0805_10V4Z

1 J18 VCCGLAN1_5[2]
C268

2
10U_0805_10V4Z

A A
1
C269

2
+3VS K16 VCCGLAN3_3
C270

2 ICH9-M SFF ES_FCBGA569

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 23 of 36
5 4 3 2 1
 5 4 3 2 1

+3VM_WOL +3VM_LAN
R304 1 2 @ 0_1206_5%

Q18
SI2301BDS_SOT23

S
Add R638 & Q84. 3/21

D
3 1
Change value. 11/06

1
1000P_0402_50V7K
C272

G
1

2
2
C271 +3VM_LAN Q19 +1.8VM
2
R305 10U_0805_10V4Z R638 BCP69_SOT223
1M_0402_5% 470_0402_5% 4
D 2 D
3 2

2
1

5.1K_0402_1%
C273

R307

10U_0805_6.3V6M
C274

C275

C276
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R306

1
100K_0402_5% D
1 2 2 1

1
1 2 2 Q84

2
G RHU002N06_SOT323
S

3
1
D 2 1 1 2
LAN_PHYPC 2 Q20
G BSS138_SOT23

1
S

3
1 2
R308 0_0402_5% LAN_CTRL_18

1
D

<33,36,38> ADP_PRES 2 Q21

G @ RHU002N06_SOT323
S
3

1
D
<22,26,28,33,35,36,38,41,42,44> SLP_S3# 2 Q22
G @ RHU002N06_SOT323
S
3

XTAL1

Y3
25MHZ_20P_1BG25000CK1A
C C
1 2 XTAL2

2 2
C277 C278
27P_0402_50V8J 27P_0402_50V8J
1 1
+V1.0M_LAN

U9
<22> GLAN_RXP C279 1 2 0.1U_0402_16V7K GLAN_RXP_C 52 26 LAN_MDI0N <25>
C280 1 GLAN_TXP MDI_N_0
<22> GLAN_RXN 2 0.1U_0402_16V7K GLAN_RXN_C 53 GLAN_TXN MDI_P_0 27 LAN_MDI0P <25>

C281

C282

C283

C284

C285

C286

C287
10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
<22> GLAN_TXP 55 GLAN_RXP MDI_N_1 22 LAN_MDI1N <25>
<22> GLAN_TXN 56 GLAN_RXN MDI_P_1 23 LAN_MDI1P <25> 2 2 2 2 2 2 1

MDI_N_2 20 LAN_MDI2N <25>

Add R309 back. 9/29 <21> GLAN_CLK 1 2 GLANCLK 45 JKCLK MDI_P_2 21 LAN_MDI2P <25>
R309 33_0402_5% 1 1 1 1 1 1 2
<21> LAN_RSTSYNC 50 JRSTSYNC
MDI_N_3 16 LAN_MDI3N <25>
<21> LAN_TXD0 42 JTXD_0 MDI_P_3 17 LAN_MDI3P <25>
<21> LAN_TXD1 43 JTXD_1
<21> LAN_TXD2 44 3 R310 1 2 0_0603_5% +3VM_LAN
JTXD_2 VDDO_33_3 +3VM_LAN_R
VDDO_33_46 46
<21> LAN_RXD0 47 JRXD_0 AVDD_33_28 28
+V1.0M_LAN

C288

C597

C598

C289
<21> LAN_RXD1 48 JRXD_1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z
<21> LAN_RXD2 49 JRXD_2 DVDD_10_5 5
DVDD_10_8 8 2 2 2 2 11/26
DVDD_10_33 33
DVDD_10_38 38 Add R597 close to pin3.
<22,25,33> LANLINK_STATUS# LANLINK_STATUS# 4 Add R598 close to pin46.
B LAN_ACT# LED_0 1 1 1 1 B
<25> LAN_ACT# 2 LED_1 AVDD_18_11 11
1 LED_2 AVDD_18_14 14
AVDD_18_19 19
AVDD_18_18 18
R312 2 1 4.99K_0402_1% 15 24 +1.8VM_LAN
RSET AVDD_18_24 +1.8VM_LAN
AVDD_18_25 25
AVDD_18_41 41
IEEE_TEST_P 12 54 R314
IEEE_TEST_P AVDD_18_54
1 2 IEEE_TEST_N 13 IEEE_TEST_N AVDD_18_32 32 0_0603_5%

C290

C291

C292

C293

C294

C295

C296
R313 @ 0_0402_5% 30 1 2 +1.8VM
AVDD_18_30

470P_0402_50V7K

470P_0402_50V7K

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 2 34 DIS_REG10
R315 1K_0402_5% 29 LAN_CTRL_18 2 2 2 2 2 1 1
LAN_PHYPC CTRL18
Change R315 to 1K and R316 to 10K. 10/10 <22,25,33> LAN_PHYPC 37 LAN_DISABLE_N CTRL10 31

R316 1 2 10K_0402_5% 36 51
TEST_EN RESERVED_NC 1 1 1 1 1 2 2
JTAG_TRST

JTAG_TMS

JTAG_TDO
JTAG_TCK

XTAL2
JTAG_TDI

9 XTAL2
XTAL1 10 57
XTAL1 GND_PAD

82567LF_QFN56_8X8~D
35
40
39
7
6

R617 1 2 @ 1K_0402_5% PAD T65

R618 1 2 @ 200_0402_5% PAD T67

+3VM_LAN R317 1 2 @ 200_0402_5% 2 1 +3VM_LAN

R318 @ 200_0402_5%
T68 PAD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 24 of 36
5 4 3 2 1
 5 4 3 2 1

Swap Q78A,B D & S pin. 2/22

Q78A
2N7002DW-T/R7_SOT363-6
<34> LAN_ACT#_DOCK 6 1 LAN_ACT#
D D

R615

2
10K_0402_5%
LAN_LINK_EN 1 2 +3VM_LAN
Q78B
2N7002DW-T/R7_SOT363-6
<34> LANLINK_STATUS#_DOCK 3 4 LANLINK_STATUS#

5
Delete all termination cause they are already inside BOAZMAN. 9/28

Pin Swap. 10/05

Swap P & N. 10/09
T69
<24> LAN_MDI0P 12 13 MDO0+
TD4- MX4-

C +1.8VM
Change design. 10/12 C

<24> LAN_MDI0N 11 14 MDO0- R319

TD4+ 1:1 MX4+ 75_0402_1%
2 1 TRM_CT 10 15 MCT0 C307 1 2 0.01U_0402_50V7K 2 1
C297 0.1U_0402_16V7K TCT4 MCT4
<24> LAN_MDI1P 9 16 MDO1+
TD3- MX3-

+1.8VM

<24> LAN_MDI1N 8 17 MDO1- R323

TD3+ 1:1 MX3+ 75_0402_1%
2 1 TRM_CT 7 18 MCT1 C308 1 2 0.01U_0402_50V7K 2 1
C299 0.1U_0402_16V7K TCT3 MCT3

<24> LAN_MDI2P 6 19 MDO2+

TD2- MX2-

+1.8VM

<24> LAN_MDI2N 5 20 MDO2- R329

TD21+ 1:1 MX2+ 75_0402_1%
2 1 TRM_CT 4 21 MCT2 C309 1 2 0.01U_0402_50V7K 2 1
C304 0.1U_0402_16V7K TCT2 MCT2
<24> LAN_MDI3P 3 22 MDO3+
TD1- MX1-

+1.8VM

<24> LAN_MDI3N 2 23 MDO3- R330

TD1+ 1:1 MX1+ 75_0402_1%
2 1 TRM_CT 1 24 MCT3 C310 1 2 0.01U_0402_50V7K 2 1 C306 1 2 1000P_1808_3KV7K
B C305 0.1U_0402_16V7K TCT1 MCT1 B
X'FORM_ NS692405 LAN_24P

JP11
V_3P3_LAN_LED 11 Yellow LED+
LAN_ACT# <24> LAN_ACT# LAN_ACT# R339 1 2 300_0603_5% 12 Yellow LED-
SHLD1 15 20 mil
LANLINK_STATUS# <34> MDO3- MDO3- 8 PR4- R89 +3VM_LAN V_3P3_LAN_LED
1 2 DETECT PIN1 13 1 2 @ 0_0402_5% LAN_PHYPC <22,24,33>
@ 680P_0402_50V7K C311 <34> MDO3+ MDO3+ 7 PR4+
3

<34> MDO1- MDO1- 6 PR2-

D
D44 20 mil 3 1
@ PACDN042_SOT23~D <34> MDO2- MDO2- 5 PR3-

1
Reserve to Modify JP11 footprint to
<34> MDO2+ MDO2+ Q23

G
4
prevent ESD issue same as Meson. 10/25
1

2
PR3+ R340 FDN338P_SOT23
as other project. <34> MDO1+ MDO1+ 3 PR2+
100K_0402_5%
1/18

2
<34> MDO0- MDO0- 2 PR1-

1
<34> MDO0+ MDO0+ D
1 PR1+
14 2 Q24
SHLD1 <22,34> PREP#
V_3P3_LAN_LED 9 G 2N7002_SOT23
Green LED+
S

3
<22,24,33> LANLINK_STATUS# LANLINK_STATUS# R341 1 2 300_0603_5% 10
A Green LED- A
SUYIN_100073FR014G303ZL_13P
CONN@
1 2
@ 680P_0402_50V7K C312

Swap connection of JP11 pin9 & pin10. 11/26

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 25 of 36
5 4 3 2 1
 A B C D E

JP12
Express Card Slot R342 1
1 GND-1
+3V_WLAN +1.5VS

<22> USB20_N2 2 0_0402_5% USBP2-_R 2 USB_D- Delete R407, R409, R522, R528, R529, & R530 of LPC for
R343 1 2 0_0402_5% USBP2+_R 3
+3VS_PEC <22> USB20_P2 USB_D+ layout improve. 2/21

0.01U_0402_16V7K

0.01U_0402_16V7K
0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z
NC_CP# 4 CPUSB#
5 RSV-5 1 1 1 1 1 1
6 RSV-6
Disconnect ICH_SMB_CLK & ICH_SMB_DATA 2/20 7 SMB_CLK

C315

C316

C317

C318

C319

C320
0.1U_0402_16V7K

4.7U_0805_10V4Z

8 SMB_DATA
R344 2 2 2 2 2 2
1 1 +1.5VS_PEC 9 +1.5V-9
0_0402_5% 10
+1.5VS_PEC +1.5V-10
<20> PCI_PME# 1 2 PCIE_PME#_R 11
+3V_PEC WAKE#
C322

C323

+3V_PEC 12 +3.3VAUX
1 2 2 PERST# 1
13 PERST#
+3VS_PEC 14 +3.3V-14
15 +3.3V-15
0.1U_0402_16V7K

4.7U_0805_10V4Z
CLKREQA# 16 Del R345 & improve
+1.5VS_PEC
1 1
<16> CLK_PCIE_EXP#
CPPE# 17
18
CLKREQ#
CPPE#
REFCLK-
Mini-Express Card +3V_WLAN. 12/11
+3V_WLAN

<16> CLK_PCIE_EXP 19 REFCLK+

C324

C325

20 JP13
2 2 C326 1 GND-20
<22> PCIE_RXN3 2 0.1U_0402_16V7K PCIE_RXN3_R 21 PERn0 <22> PCIE_WAKE# PCIE_WAKE# 1 1 2 2
<22> PCIE_RXP3 C327 1 2 0.1U_0402_16V7K PCIE_RX3P_R 22 PERp0 3 3 4 4 2/21
0.1U_0402_16V7K

4.7U_0805_10V4Z

23 GND-23 5 5 6 6 +1.5VS
1 1 24 <16> CLKREQ_WLAN# 7 8 LPC_FRAME# LPC_FRAME# <21,32,33>
<22> PCIE_TXN3 PETn0 7 8
25 9 10 LPC_AD3 LPC_AD3 <21,32,33>
<22> PCIE_TXP3 PETp0 9 10 LPC_AD2
26 GND-26 <16> CLK_PCIE_MCARD# 11 11 12 12 LPC_AD2 <21,32,33>
C328

C329

13 14 LPC_AD1 LPC_AD1 <21,32,33>

2 2 <16> CLK_PCIE_MCARD 13 14
27 29 15 16 LPC_AD0 LPC_AD0 <21,32,33>
GND-27 GND-29 PCI_RST# 15 16
Express Card Power Switch 28 GND-28 GND-30 30 2/21 <20,27> PCI_RST# 17 17 18 18
+3V_WLAN
19 20 XMIT_D_OFF#
<16> CLK_PCI_DEBUG 19 20
CONN@ SANTA_130832-1_LB 21 22 PLT_RST#
U11 R346 1 21 22 PLT_RST# <8,20,32>
<22> PCIE_RXN2 2 0_0402_5% PCIE_C_RXN2 23 23 24 24
TPS2231PWPR_PWP24 +3VS_PEC R347 1 2 0_0402_5% PCIE_C_RXP2 25 26
<22> PCIE_RXP2 25 26
27 27 28 28
C330 2 1 0.1U_0402_16V7K 5 7 +3VS 29 30 ICH_SMB_CLK
3.3Vin1 3.3Vout1 29 30 ICH_SMB_CLK <22>
+3VS 6 8 31 32 ICH_SMB_DATA
3.3Vin2 3.3Vout2 <22> PCIE_TXN2 31 32 ICH_SMB_DATA <22>
<22> PCIE_TXP2 33 33 34 34
+3VALW +3V_PEC 35 36
35 36 USB20_N3 <22>

2
Change Power rail same +3V_WLAN 37 38
37 38 USB20_P3 <22>
C331 2 1 0.1U_0402_16V7K 21 20 @ R348 39 40
3.3Vaux_in Aux_out 10K_0402_5% as pin2, 52. 8/16 41
39 40
42 WW_LED#
41 42 WL_LED#
43 43 44 44 WL_LED# <19>
C332 2 1 0.1U_0402_16V7K 18 16 +1.5VS_PEC CL_CLK1 R349 2 1 0_0402_5% 45 46 WP_LED#

1
1.5Vin1 1.5Vout1 CLKREQA# <22> CL_CLK1 CL_DATA1 R350 0_0402_5% 45 46
+1.5VS 19 1.5Vin2 1.5Vout2 17 CLKREQA# <16> <22> CL_DATA1 2 1 47 47 48 48
2 CL_RST#1 R351 0_0402_5% 2
<22> CL_RST#1 2 1 49 49 50 50
+3VALW 51 52
T77 PAD 51 52

6
NC_CP# 14 +3VALW
CPPE# CPUSB#
15 CPPE# OC# 23 53 GND1 GND2 54
4 Q25A @ resever for shirly WW_LED# R352 1 2 @ 0_0402_5% WL_LED#
<22,24,28,33,35,36,38,41,42,44> SLP_S3# STBY#
1 2 3 22 RCLKEN 2 2N7002DW-T/R7_SOT363-6
SHDN# RCLKEN peak issue 5/7

1
10K_0402_5%
R585 100K_0402_5% PLT_RST# 2 9 PERST# FOX_AS0B226-S40N-7F WP_LED# R353 1 2 @ 0_0402_5%
SYSRST# PERST#
RCLKEN have CONN@

1
Q66
GND

internal PU.
NC1
NC2
NC3
NC4
NC5

@ SI2305DS-T1-E3_SOT23-3 XMIT_D_OFF# 2 1

R605
XMIT_OFF# <22>
R606 D13 CH751H-40_SC76

3
Q25B @ 220K_0402_1% Add to prevent leakage issue.
11

1
10
12
13
24

<22> EXP_RST 5 2N7002DW-T/R7_SOT363-6 1 2 2

<33> MC2_DISABLE +3V_WLAN
1
Q25 & Q26 change to 2 in C615 Change Q66 from
4

add C615 1000pF per 1000P_0402_50V7K

1 package. 3/17 @ SI2301BDS to
HP request. 3/31

1
2 SI2305DS. 10/25

+3V_WWAN +3V_WWAN

Mini-Express Card--WWAN
Note2
ACCELEROMETER
Close to JP14

+3V_WWAN
Del R354 &
39P_0402_50V8J

39P_0402_50V8J

39P_0402_50V8J

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
DEL in 9/26 improve
Del BT_COMBO# in 10/12. JP14 1 1 1 1 1 1
+3V_WWAN.
PCIE_WAKE# 1 2 +3VS_ACL
1 2 12/11
3 3 4 4
2 2 2 2 2 2
C590

C591

C592

C333

C334

C335
5 5 6 6
3 UIM_PWR 3
<16> CLKREQG_WWAN# 7 7 8 8
9 10 UIM_DATA @ @ @
9 10 UIM_CLK
<16> CLK_PCIE_WAN# 11 11 12 12

10U_0805_6.3V6M
0.1U_0402_16V4Z
13 14 UIM_RST
<16> CLK_PCIE_WAN 13 14 +3VS +3VS_ACL +3VS_ACL_IO

C340

C341
15 16 UIM_VPP
15 16
T78 PAD 17 17 18 18 1 1
T79 PAD 19 20 M_WXMIT_OFF# U13 D14 R355
19 20 PLT_RST# CH751H-40_SC76 0_0603_5%
21 21 22 22 1 CH1 CH4 6
<22> PCIE_RXN4 23 23 24 24 +3V_WWAN 2 1 1 2
2 2
<22> PCIE_RXP4 25 25 26 26 2 Vn Vp 5 +3V_WWAN
Note1 27 27 28 28
29 30 ICH_SMB_CLK 3 4 U12
29 30 ICH_SMB_DATA CH2 CH3
31 32 LIS302DL
+3V_WWAN

<22> PCIE_TXN4 31 32 +3V_WWAN

33 34 @ S DIO(BR) NUP4301MR6T1 TSOP-6
<22> PCIE_TXP4 33 34
35 35 36 36 USB20_N7 <22> +3VS_ACL_IO 1 VDD_IO
R359 0_0603_5% 37 38 D15 +3VS_ACL 6 2
37 38 USB20_P7 <22> VDD GND
1 2 39 40 @ DAN217T146_SC59-3 4
39 40 WW_LED# JP15 GND
1 2 41 41 42 42 WW_LED# <19> 3 <20> ACCEL_INT# 8 INT 1 GND 5
R360 0_0603_5% 43 44 WL_LED# 4 1 UIM_PWR 1 9 10
43 44 UIM_VPP GND VCC UIM_RST INT 2 GND
45 45 46 46 5 VPP RST 2 2
47 48 UIM_DATA 6 3 UIM_CLK 12
47 48 I/O CLK SDO
49 49 50 50 7 DET 1 <4,22> ICH_SM_DA 13 SDA / SDI / SDO
18P_0402_50V8J
C336

T80 PAD 51 51 52 52 <4,22> ICH_SM_CLK 14 SCL / SPC

Add back 9/27 3 +3VS_ACL
RSVD
47K_0402_5%
2 R367

4.7U_0805_10V4Z

0.1U_0402_16V4Z

delete R362~R364, 53 54 +3VS_ACL R365 2 1 10K_0402_5% 7 11

GND1 GND2 2 CS RSVD
not support Clink GND 8 1 1
on 2008 products to CONN@ MOLEX_67910-5700 9 HP302DLTR8_LGA14_3X5
D16 GND
WWAN slot 5/22 L Must be placed in the center of the system.
C342

C343

1 2 M_WXMIT_OFF#
<22> WXMIT_OFF# @ 2 2
CH751H-40_SC76 @ Change U12 part description from
+3VALW
LIS302DLTR LGA to HP302DLTR8 as HP
1

4 CONN@ TAITW_PMPAT6-06GLBS7N14N0 4

Change value change list. 12/03

UIM_PWR Add in 9/27
to 47K. 9/27
1
10K_0402_5%

1
Note1
2/22 @ C603 Q67 Change Power rail same
R607

1000P_0402_50V7K @ SI2305DS-T1-E3_SOT23-3
2 R608 as pin2, 52. 8/16
Security Classification Compal Secret Data Compal Electronics, Inc.
2

220K_0402_1% Note2
<33> WMC1_DISABLE 1 2 2 Reserve for 800 & 900MHz Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
+3V_WWAN
Change Q67 from EMI issue. 8/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
resever for shirly SI2301BDS to AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
401554 B
peak issue 5/7 SI2305DS. 10/25 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 26 of 36
A B C D E
 5 4 3 2 1

+3VS
Layout Note: Place close to R5C833 Layout Note: Place close to R5C833 SD,MMC,MS,XD muti-function pin define
and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK MDIO SD Card MMC Card MS Card XD Card
U14

10U_0805_10V4Z
0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
<20> PCI_AD[0..31]
PCI_AD31 125 10 1 1 1 1 1 1
PIN Name PIN Name PIN Name PIN Name PIN Name
PCI_AD30 AD31 VCC_PCI3V
126 AD30 VCC_PCI3V 20 MDIO00 SDCD# MMCCD# XDCD0#
PCI_AD29 127 27
AD29 VCC_PCI3V

C344

C522

C534

C535

C536

C345
PCI_AD28 1 32 C346 MDIO01 MSCD# XDCD1#
PCI_AD27
PCI_AD26
2
3
AD28
AD27 R5C833 VCC_PCI3V
VCC_PCI3V 41
128
2 2 2 2 2 2 +3VS 1 2 R5C832XI
MDIO02 XDCE#
PCI_AD25 AD26 VCC_PCI3V 15P_0603_50V8J
5 AD25

2
PCI_AD24 6 61 MDIO03 SDWP# XDR/B#
PCI_AD23 AD24 VCC_RIN 24.576MHz_16P_3XG-24576-43E1
9 AD23
+3VS PCI_AD22 X1 MDIO04 SDPWR0 MMCPWR MSWR XDPWR

10U_0805_10V4Z
0.01U_0402_16V7K

0.01U_0402_16V7K
0.1U_0402_16V4Z
11 AD22 VCC_ROUT 16
CLK_PCI_1394 PCI_AD21 12 34 1 1 1 1 C347

1
D AD21 VCC_ROUT D
68K_0402_5%

PCI_AD20 14 64 1 2 R5C832XO MDIO05 SDPWR1 XDWP#

AD20 VCC_ROUT
1

10_0402_5%
PCI_AD19

0.01U_0402_16V7K

0.01U_0402_16V7K
15 114

0.47U_0603_16V4Z

0.47U_0603_16V4Z
AD19 VCC_ROUT
1
R369

C351
PCI_AD18 17 120 1 1 1 1 15P_0603_50V8J MDIO06 SDLED# MMCLED# MSLED# XDLED#
AD18 VCC_ROUT +3VS 2 2 2 2
R370
PCI_AD17 18 AD17

C348

C349

C350
PCI_AD16 19 67 MDIO07 MSEXTCK
PCI_AD15 AD16 VCC_3V
36
2

@ PCI_AD14 AD15 2 2 2 2
37 86 MDIO08 SDCCMD MMCCMD MSBS XDWE#
2

AD14 VCC_MD3V

C352

C353

C354

C355
CBS_GRST# PCI_AD13 38
PCI_AD12 AD13 +3V_PHY MDIO09 SDCCLK MMCCLK MSCCLK XDRE#

10U_0805_10V4Z
4.7P_0402_50V8C

0.01U_0402_16V7K
@ 39 AD12 AVCC_PHY3V 98
1 2 PCI_AD11 40 106 1 1
AD11 AVCC_PHY3V
C359

C358 PCI_AD10 42 110 MDIO10 SDCDAT0 MMCDAT MSCDAT0 XDCDAT0

1U_0603_10V4Z PCI_AD9 AD10 AVCC_PHY3V L6 +3V_PHY
43 AD9 AVCC_PHY3V 112

C357
PCI_AD8 44 BLM21A601SPT_0805 MDIO11 SDCDAT1 MSCDAT1 XDCDAT1
2 1 PCI_AD7 AD8 IEEE1394_TPBIAS0 2 2
46 AD7 TPBIAS0 113 +3VS 1 2

C356
PCI_AD6 47 MDIO12 SDCDAT2 MSCDAT2 XDCDAT2
PCI_AD5 AD6 IEEE1394_TPAP0

1000P_0402_50V7K

1000P_0402_50V7K
10U_0805_6.3V6M

0.01U_0402_16V7K

0.01U_0402_16V7K
48 AD5 TPAP0 109
@ PCI_AD4 49 108 IEEE1394_TPAN0 MDIO13 SDCDAT3 MSCDAT3 XDCDAT3
PCI_AD3 AD4 TPAN0
7/2: change R369 from 100K to 50 AD3 1 1 1 1 1

C360
PCI_AD2 51 105 IEEE1394_TPBP0 MDIO14 XDCDAT4
68K & reserve C358 AD2 TPBP0

C361

C362

C363

C364
PCI_AD1 52 104 IEEE1394_TPBN0
PCI_AD0 AD1 TPBN0
53 AD0 Add TP. 10/02 2 2 2 2 2
MDIO15 XDCDAT5
80 SD_CARD_DET#
MDIO00 MSCD#_XDCD1
MDIO01 79 PAD T118 MDIO16 XDCDAT6
PCI_CBE#3 7 78 XD_CE#
<20> PCI_CBE#3 C/BE3# MDIO02 PAD T119
PCI_CBE#2 21 77 SD_WP MDIO17 XDCDAT7
<20> PCI_CBE#2 C/BE2# MDIO03 Layout Note:
PCI_CBE#1 35 76 SDPWR0_MSPWR_XDPWR
<20> PCI_CBE#1 C/BE1# MDIO04
PCI_CBE#0 45 75 XDWP# Place these cap close to U14. MDIO18 XDCLE
<20> PCI_CBE#0 C/BE0# MDIO05 PAD T120
74 3IN1_LED#
MDIO06 PAD T121
73 TP_MSEXTCK MDIO19 XDALE
PCI_PAR MDIO07 SD_MMC_CMD
<20> PCI_PAR 33 PAR MDIO08 88 GND Layout Note:
PCI_FRAME# 23 84 SDCLK_MMCCLK
<20> PCI_FRAME# FRAME# MDIO09
PCI_TRDY# SDDATA0_MSDATA0
GND Add GND shield for SDCLK_MMCCLK.
<20> PCI_TRDY# 25 TRDY# MDIO10 82
C PCI_IRDY# 24 81 SDDATA1_MSDATA1 C
<20> PCI_IRDY# IRDY# MDIO11
R372 PCI_STOP# 29 93 SDDATA2_MSDATA2
<20> PCI_STOP# STOP# MDIO12
100_0402_5% PCI_DEVSEL# 26 90 SDDATA3_MSDATA3
<20> PCI_DEVSEL# DEVSEL# MDIO13
PCI_AD22 1 2 CBS_IDSEL 8 91 MMC_D4
PCI_PERR# 30
IDSEL MDIO14
89 MMC_D5 Function set pin define
<20> PCI_PERR# PERR# MDIO15
PCI_SERR# 31 92 MMC_D6 Add TP. 10/02 UDIO3 UDIO4 MSEN XDEN Function
<20,33> PCI_SERR# SERR# MDIO16
87 MMC_D7
MDIO17 XDCLE
MDIO18 85 PAD T122 Pull-up Pull-up Pull-down Pull-down Enable SD,MMC Card
PCI_REQ2# 124 83 XDALE
Layout Note: Add GND shield. <20> PCI_REQ2# PCI_GNT2# REQ# MDIO19 PAD T123
<20> PCI_GNT2# 123 GNT#
58 MSEN Layout Note: Shield GND for +3VS
MSEN XDEN
XDEN 55 CBS_CCLK_INTERNAL and CBS_CCLK
CLK_PCI_1394 121 UDIO3 R373 1 2 10K_0402_5%
<16> CLK_PCI_1394 PCICLK
119 94 R5C832XI UDIO4 R374 1 2 10K_0402_5%
<20,26> PCI_RST# PCIRST# XI
CBS_GRST# 71 95 R5C832XO UDIO5 R375 1 2 100K_0402_5%
R378 1 GBRST# XO
2@ 10K_0402_5% 117 CLKRUN#
R380 1 2 0_0402_5% 70 96 C365 1 2 0.01U_0402_16V7K MSEN R371 1 2 10K_0402_5%
<22,32,33> PM_CLKRUN# PME# FIL0
+3VS R381 1 2 10K_0402_5% PME# 101 XDEN R376 1 2 10K_0402_5%
REXT
VREF 100

10K_0603_1%
0.01U_0402_16V7K
<20> PCI_PIRQE# 115 INTA#

2
116 72 SIRQ 2
<20> PCI_PIRQG# INTB# UDIO0/SRIRQ# SIRQ <22,32,33>

C366
TP_UDIO1

R383
UDIO1 60 PAD T81
56 TP_UDIO2
UDIO2 PAD T82
R384 1 2 10K_0402_5% 69 65 UDIO3
+3VS HWSPND# UDIO3 1
66 59 UDIO4

1
TEST UDIO4 UDIO5
UDIO5 57
Modify to same as Meson. 9/13 +SD_MMC_3VCC
99 AGND GND 4
102 13 JP16
103
AGND GND
22
Layout Note: SDDATA0_MSDATA0 7 4
AGND GND Please them close to U14. SDDATA1_MSDATA1 D0 VDD
107 AGND GND 28 8 D1
SDDATA2_MSDATA2

4.7U_0805_10V4Z

0.1U_0402_16V4Z
111 AGND GND 54 9 D2
B B

150K_0402_5%

Near to JP9.
62 SDDATA3_MSDATA3 1
GND D3

2
63 MMC_D4 10 14 SD_WP 1
GND MMC_D5 D4 WP SD_CARD_DET#
97 RSV GND 68 11 D5 CD 15
118 MMC_D6 12
GND D6

R379

C548

C549
MMC_D7

100P_0402_50V8J
GND 122 13 D7 VSS2 6 2 2
3
270P_0402_50V7K

1
VSS1
1

1 5.1K_0402_1% 1 2 R377 @ 10_0402_5% SDCLK_MMCCLK 5 16

CLK VSS3
C367

C550
R5C833-TQFP128P_TQFP128_14X14~D C551 @ 22P_0402_50V8J 17
VSS4 1
R388

SD_MMC_CMD 2 CMD
2 CONN@ TAI_PSDBT0-16GNBS7N14N0_15P
2
2

2
56.2_0402_1%

56.2_0402_1%
R390

+SD_MMC_3VCC +SD_MMC_3VCC
R389

+3VS
Reserve them for test
if any EMI issue. 9/14 40mil
1

JP17 U15
GND CONN@ SUYIN_020115FB004S512ZL
IEEE1394_TPBN0 R546 1 2 0_0402_5% 1
IEEE1394_TPBP0 R547 0_0402_5% TPB- GND 5 SDPWR0_MSPWR_XDPWR
3 VIN VOUT 1
Layout Note: GND

10U_0805_10V4Z

0.1U_0402_16V4Z
1 2 2 TPB+ GND 6 4 VIN/CE VOUT 5
IEEE1394_TPAN0 R568 0_0402_5%

1U_0603_10V4Z
1 2 3 TPA- GND 7 1 1
Add GND shield for 1394.

150K_0402_5%
GND IEEE1394_TPAP0 R569 1 2 0_0402_5% 4 TPA+ GND 8

0.1U_0402_16V4Z
1 2 GND 1

C369
C368

C370

C371
RT9701CB_SOT25
R395 56.2_0402_1%

Layout Note: Shield GND for 2 2

2

2 2
56.2_0402_1%

R392
IEEE1394_TPA and TPB

2
R394

A A
1

IEEE1394_TPBIAS0
0.01U_0402_16V7K

0.33U_0603_16V4Z

1 1 Security Classification Compal Secret Data Compal Electronics, Inc.

C372

C373

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 27 of 36
5 4 3 2 1
 A B C D E

TPA6044 no longer needed. So delete BOM options & co-layout

components for TPA6044. SGND and SGND1 nets can also be
AMP. FOR INTERNAL
3/21
SPEAKER
deleted. Only TPA6041 will be supported. 9/5 3/21 GAIN1 GAIN0
+5VS

VDDA_CODEC +5VS
10dB 0 0

1
Modify in 3/26 12dB 0 1

1 R400

1 R401
VDDA_CODEC D18 Change gain to 12db. 15.6dB 1 0
@ PACDN042_SOT23~D R402 install.
R400 not install. 21.6dB 1 1 V
1

C374

C375

C376
3

2
R412
3/21

Close to Pin29

Close to Pin30
1 10K_0402_5% JP18 1
1 1 1
C402 R413 R_SPK+ 1 GAIN1 R402 2 1 @ 0_0402_5%

GAIN1 100K_0402_5% 2

GAIN0 100K_0402_5% 2
0.1U_0402_16V4Z 100K_0402_5% R_SPK- 1 +5VS
2
2

MONO_IN_HD 2 GAIN0 R403

1 2 1 2 1 2 3 G1 2 1 @ 0_0402_5%
C388 2 2 2
4 G2 VDDA_CODEC
1

D Change value. 9/28

100P_0402_50V8J
C378

10U_0805_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z
100P_0402_50V8J
R410

C391

C379
<22> SB_SPKR 2 Q33 1 1 ACES_85204-02001
G 2N7002_SOT23 CONN@ C377 1 2 2.2U_0603_16V6K HP_IN_L
S C380 1 2 2.2U_0603_16V6K HP_IN_R
3

1
2

HP_INR
HP_INL
2 2
SLP_S3# <22,24,26,33,35,36,38,41,42,44>
1

0.01U_0402_16V7K

33

32

31

30

29

28

27

26

25
10K_0402_5%
Change in 4/1 U16

VDD

SGND

HP_INR
TML

GAIN1

GAIN0

HP_INL

REG_EN
REG_OUT
Change in 3/28 Change in 3/28 TPA6041A4RHBR QFN 32P

LINE_OUTL 2 1 LINE_C_OUTR 1 2 R404 2 1 R405 1 2 1K_0402_1% 2 24 C383 2 1 0.47U_0402_6.3V6K_X5R

C381 1U_0603_10V4Z 2K_0402_1% C382 1U_0603_10V4Z SPKR_RIN+ BYPASS
LINE_OUTR 2 1 LINE_C_OUTL 1 2 R406 LINE_OUT 1 23 A_SD 3/21
C384 1U_0603_10V4Z 2K_0402_1% SPKR_RIN- SPKR_EN#
C385 2 1 0.47U_0402_6.3V6K 3 22 HP_EN 1 2 +5VS
SPKR_LIN+ HP_EN R408 @ 100K_0402_5%
C386 2 1 0.47U_0402_6.3V6K 4 21
SPKR_LIN- SPGND
5 20 R_SPK+
SPGND ROUT+
2 1 L_SPK+ 6 19 R_SPK- 3/21
C389 0.47U_0402_6.3V6K LOUT+ ROUT-
+3VS 2 1 L_SPK- 7 18
2 LOUT- SPVDD +5VS 2
R411 C390 0.47U_0402_6.3V6K

C392

C393
0_0805_5% 3/21 +5VS 8 17
VDDA_CODEC SPVDD HPVDD
2 1 1 1

C394

C395

HP_OUTR

HP_OUTL
+3VS_CODEC

CPGND
CPVDD

CPVSS

HPVSS
1 1

C1N
C1P
2 2

1U_0603_10V4Z

10U_0805_10V4Z
C396 C397 C398 C399 C400 Add in 3/28
1 1 1 1 1 2

MIC_BIAS_IN

10

11

12

13

14

15

16
C401 2 2 HP_EN

DVCORE

10U_0805_10V4Z

1U_0603_10V4Z
4.7U_0805_10V4Z
2 2 2 2 2 1

0.1U_0402_16V4Z
10U_0805_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
HP_OUTL <29> 1

C403

C404

1U_0603_10V4Z
HP_OUTR <29>
Adjust line-in attenuation from -6dB to -10dB by change 2 1

C611
25

38

33
R415, R418 = 6.04K and changing R417, R420 = 2.0k.

9
U17 2

DVCORE
MIC_BIAS_IN

DVIO

DVDD
AVDD1

AVDD2
2 @
C612 2 1@ 3300P_0402_50V7-K

R415 6.04K_0402_1% DLINE_IN_R_L 2 DLINE_IN_RC_L C406 1 2 47U_B2_6.3V-M R416 2 1 60.4_0402_1% 2 1 L7

+
<34> DOCK_LINE_IN_L 2 1 1 14 AUX1 LINE_OUT_L 35 DLINE_OUT_L <34>
R417 2 1 2K_0402_5% C405 1U_0603_10V4Z CHB1608B121YZF_0603
R418 6.04K_0402_1% DLINE_IN_R_R 2 DLINE_IN_RC_R C408 1 2 47U_B2_6.3V-M R419 2 1 60.4_0402_1% 2 1 L8

+
<34> DOCK_LINE_IN_R 2 1 1 15 AUX2 LINE_OUT_R 36 DLINE_OUT_R <34>
R420 2 1 2K_0402_5% C407 1U_0603_10V4Z CHB1608B121YZF_0603
LINE_OUTL 16 32 Correct net name. 10/02 R421 1 2 10K_0402_5%
VDDA_CODEC C613 2 AUX3 MONO_OUT
1@ 3300P_0402_50V7-K
LINE_OUTR 17 39 HP_IN_L R422 1 2 10K_0402_5% A_SD_D37
AUX4 HP_LOUT_L A_SD 3/26
1
20_0402_5%

<29> INT_MIC1 C409 1 2 1U_0603_10V4Z INT_MICL_C 23 41 HP_IN_R

LINE_IN_L HP_LOUT_R

3
R423

R424 2 1 @ 10_0402_5% C411 1 2 @ 10P_0402_25V8K D50

3 C410 1 2 1U_0603_10V4Z INT_MICR_C 24 PJDLC05_SOT23-3 +5VS 3
<29> INT_MIC2 LINE_IN_R
BIT_CLK 6 AC97_BITCLK_CODEC <21>
2

2
8 AC97_SDIN0_CODEC R425 2 1 33_0402_5% AC97_SDIN0 <21> SENSE_A_A
MIC_BIAS_IN SDATA_IN R426
Connect to GNDA. 3/20

1
100K_0402_5%

6
2 C412 1 2 1U_0603_10V4Z 19 C604 2 1 0.1U_0402_16V4Z
CD_GND R429
47

1
C413 MIC1_C GPIO_0/EAPD GPIO1 R427 2
<29> MIC1 1 2 21 MIC1 GPIO_1/MIC_BIASE-E 31 1 0_0402_5% EAPD <33> 0_0402_5% Q34A
4.7U_0805_10V4Z VDDA_CODEC C414 1U_0603_10V4Z 30 R571 1 2 15K_0402_1% ESD Request. 03/19 HP_EN 1 2 2 2N7002DW-T/R7_SOT363-6
1 GPIO_2 VDDA_CODEC
1 2 MIC2_C 22 2
<29> MIC2 C415 1U_0603_10V4Z MIC2 DM_1/DM_2 A_SD_D37 A_SD
4 2 1 A_SD <33> <29> HP_DET

1
R430 1 DM_3/DM_4
Place close to U14 2 2.67K_0402_1% SENSE_A 13 SENSE_A/SRC_B DM_CLK 46 D37 CH751H-40_SC76
R431 1 2 2.67K_0402_1% SENSE_B 34 Add R571, D37 in 9/26.
SENSE_B/SRC_A SENSE_A R432 1
<29> SENSE_A 2 39.2K_0402_1% SENSE_A_A
2 R642 1 4.7K_0402_5% Q34 & Q35 change to 2
+3VS
4.7K_0402_5%

VREF_FILT 27 AUD_REF 1 R433 1 2 20K_0402_1% SENSE_A_B in 1 package. 3/17

2

1
2 1 <21> AC97_RST#_CODEC 11 RESET#

3
1U_0603_10V4Z C418

C419
C416 0.1U_0805_25V7M 28 MIC_BIAS_B 1 1 R434 C417
MIC_BIAS_B
R639

<21> AC97_SYNC_CODEC 10 29 MIC_BIAS_C @ 0_0402_5% 1U_0603_10V4Z

SYNC MIC_BIAS_C 2 Q34B

0.1U_0402_16V4Z
2 1 <21> AC97_SDOUT_CODEC 5 12 MONO_IN_HD R435 2N7002DW-T/R7_SOT363-6 5 MIC_SENSE <29>
1

2
C420 0.1U_0805_25V7M @ SDATA_OUT PCBEEP 2 2 39.2K_0402_1%
1 18 SENSE_B 1 2 SENSE_A_C

4
GPIO1 C616 N/C
N/C 20
2 1 37 Q36
N/C

1
C421 0.1U_0805_25V7M 0.01U_0402_16V7K D 2N7002_SOT23
N/C 43 1
2
4.7K_0402_5%

44 C422 2 LINE_IN_SENSE <34>

N/C
2

48 40 1U_0603_10V4Z G
S/PDIF_OUT N/C

1
2 1 pull 4.7k to +3VS & 45 S 1

3
N/C 2
R640

C423 0.1U_0805_25V7M 0.01U to GND for ESD solution 49 R436 C426

NC 100K_0402_5% 0.1U_0402_16V4Z
2008/04/22 AVSS1 26
4 PIN42 4
7 42
1

@ DVSS AVSS2 2
2 1

2
R437 @ 0_1206_5% AD1984JCPZ-RL_LFCSP48_7X7
DVCORE

2 2
GND GNDA C424 C425
Add in 3/28 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 28 of 36
A B C D E
 A B C D E

Add C614 to provide some deglitching. 3/28 R438

5.1K_0603_1%
JP19 <28> SENSE_A 1 2
<28> HP_DET 5
Q37

1
R439 L9 D 2N7002_SOT23
4
60.4_0402_1% CHB1608B121YZF_0603 2 DOCK_HPS# <34>
1 2 1 2 3 G
<28> HP_OUTR
6 S

1
1 2 1 2 HP_OUT_L 2 2
<28> HP_OUTL
R440 L10 1 R441 C427

470P_0402_50V7K

470P_0402_50V7K
C428

C429

C614
0.01U_0402_16V7K
60.4_0402_1% CHB1608B121YZF_0603 100K_0402_5% 0.1U_0402_16V4Z

2
CONN@ FOX_JA6033L-B5S3-7F_6P
R442 R443 1
1 1 1

2
10K_0402_5% 10K_0402_5%
1 1

1
2 2 2

D19 Change R441 to 100K to make Q37 turn

3
on enough for SENSE_A. 11/26
Change R445 to 100K to reduce drain +5VS
1
2
and change pin 1 connection to +5VS
@ PACDN042_SOT23~D

1
R445 VDDA_CODEC CODEC_REF
Modify to same as Meson. 10/02 100K_0402_5%

1
2
JP20 R449
MIC_BIAS_B MIC_SENSE 5 47K_0402_5%
<28> MIC_SENSE
L11 4

2
CHB1608B121YZF_0603
1 2 EXT_MICB 1 2 3
R447 3.9K_0402_1% 6

1
1 2 EXT_MICA 1 2 2 1 1
R448 3.9K_0402_1% L12 1 C433 R451 C434

470P_0402_50V7K

470P_0402_50V7K
C430

C431

C432
0.1U_0402_16V4Z
CHB1608B121YZF_0603 47K_0402_5% @ 4.7U_0805_10V4Z
CONN@ FOX_JA6033L-B5S3-7F_6P 4.7U_0805_10V4Z
2 2
1 1 1

2
2 2 2
2
Connect to AGND. 11/26 2

EXTERNAL MICROPHONE/LINE OUT JACK

CODEC_REF
EXT_MICA_2 1
C435
2
100P_0402_50V8J AMP. FOR EXTERNAL MICROPHONE EXT_MICB_2
CODEC_REF
1
C436
2
100P_0402_50V8J
1 2
1 2 R452 100K_0402_5%
R453 100K_0402_5%
100P_0402_50V8J

100P_0402_50V8J
C437

C438
1 1
VDDA_CODEC VDDA_CODEC

2 2
4

4
L13 3 L14 5
P

P
HLC0603CSCCR10JT_0603 + MIC1 HLC0603CSCCR10JT_0603 + MIC2
OUT 1 MIC1 <28> OUT 7 MIC2 <28>
EXT_MICA 2 1 EXT_MICA_1 1 2 1 2 2 EXT_MICB 2 1 EXT_MICB_1 1 2 1 2 6
- -
G

G
C439 0.47U_0402_6.3V6K_X5R R454 10K_0402_5% U18A C440 0.47U_0402_6.3V6K_X5R R455 10K_0402_5% U18B
TLV2464_TSSOP14 TLV2464_TSSOP14
11

11
1 1
C441 C442
3 68P_0402_50V8J 68P_0402_50V8J 3

2 2

INT_MIC_2_4 C443 1 2 220P_0402_50V7K

1 2
INT_MIC_1_4 C444 1 2 220P_0402_50V7K AMP. FOR INTERNAL MICROPHONE CODEC_REF
R456
VDDA_CODEC
100K_0402_5%

1 2
R459 100K_0402_5%
CODEC_REF
MIC_BIAS_C VDDA_CODEC

100P_0402_50V8J
C445

0.1U_0402_16V4Z
1

C446
1
100P_0402_50V8J
C447

0.1U_0402_16V4Z

1 2
C448

1
2

4
2
R457 R458 2 L15 R462 12

P
3K_0402_5% 3K_0402_5% HLC0603CSCCR10JT_0603 10K_0402_5% +
14
OUT TLV2464_TSSOP14
4

2 INT_MIC_2_2 1 2INT_MIC_2_31 2 1 2 13 -

G
JP21 L16 10 C449 0.068U_0603_16V7K U18D
P
1

CONN@ ACES_85204-04001 HLC0603CSCCR10JT_0603 R465 +

8 1

11
4 INT_MIC_1_2 OUT 4
1 1 1 2INT_MIC_1_3 1 2 1 2 9 -
C452 <28> INT_MIC2
G

C450 0.068U_0603_16V7K 10K_0402_5% U18C 68P_0402_50V8J

2 2 INT_MIC_2_2 TLV2464_TSSOP14
3 3 1
11

C454 2
4 4
68P_0402_50V8J
G1 5 <28> INT_MIC1
G2 6
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 29 of 36
A B C D E
 SWITCH BOARD. INT_KBD CONN.
I2C_CLK
+3VL +3VS +3VL I2C_DAT KSO[0..11]
<33> KSO[0..11]
KSI[0..7]
<33> KSI[0..7]

2
5.1K_0402_5% R466

5.1K_0402_5% R467
D47

1
PACDN042_SOT23~D JP22 CP1 CP2
JP23 KSO11 1 KSO11 1 8 KSI_D_3 1 8
KSO0 1 KSO0 KSO3
1 2 2 7 2 7

1
1 KSO2 2 KSO2 KSO8
2 2 3 3 3 6 3 6
CAP_RST_EC 3 KSO5 4 KSO5 4 5 KSO4 4 5
<33> CAP_RST_EC

2
WL/BT_LED 3 KSI_D_14 4
<19> WL/BT_LED 4 4 5 5
5 KSI_D_8 6 @ 100P_1206_8P4C_50V8 @ 100P_1206_8P4C_50V8
I2C_CLK 5 KSI_D_12 6
<33> I2C_CLK 6 6 7 7
I2C_DAT 7 I2C_INT KSI_D_10 8 CP3 CP4
<33> I2C_DAT 7 8
I2C_INT 8 CAP_RST_EC KSI_D_0 9 KSI_D_14 1 8 KSO7 1 8
<33> I2C_INT 8 9
9 KSI_D_4 10 KSI_D_8 2 7 KSO6 2 7
STB_LED 9 KSI_D_2 10 KSI_D_12 KSO10
<19,34> STB_LED 10 10 11 11 3 6 3 6

2
KSI_D_1 12 KSI_D_10 4 5 KSO1 4 5
1
KSI_D_3 12
10K_0402_5%
13 13
D49 KSO3 14 @ 100P_1206_8P4C_50V8 @ 100P_1206_8P4C_50V8
PACDN042_SOT23~D KSO8 14
11 GND1 15 15
12 KSO4 16 CP5 CP6
GND2 16
R468

KSO7 17 KSI_D_0 1 8 KSI_D_5 1 8

2

1
ACES_87213-1000G KSO6 17 KSI_D_4 KSI_D_6
18 18 2 7 2 7
CONN@ KSO10 19 KSI_D_2 3 6 KSI7 3 6
KSO1 19 KSI_D_1 KSI_D_13
20 20 4 5 4 5
KSI_D_5 21
KSI_D_6 21 @ 100P_1206_8P4C_50V8 @ 100P_1206_8P4C_50V8
22 22
KSI7 23
KSI_D_13 23 CP7
24 24
KSI_D_11 25 KSI_D_11 1 8

MDC 1.5 Conn. +3VS +3VS

KSI_D_9
KSO9
26
27
28
25
26
27
28
KSI_D_9 2
KSO9 3
4
7
6
5
LEFT 29
JP24 RIGHT 29 @ 100P_1206_8P4C_50V8
30 30

1000P_0402_50V7K
C455

C456

C457
0.1U_0402_16V4Z

@ 4.7U_0805_10V4Z
CONN@ ACES_88025-120L_12P
1 1 2 2 1 1 1 31 GND1
AC97_SDOUT_MDC 3 3
<21> AC97_SDOUT_MDC 4 4 32 GND2
5 5 6 6
AC97_SYNC_MDC 7 7 CONN@ HRS_FH28-60(30)SB-1SH(86)
<21> AC97_SYNC_MDC 8 8 2 2 2
<21> AC97_SDIN1 1 2 AC97_SDIN1_MDC 9 9 10 10
R469 33_0402_5% 11 11 R470 2 1 0_0402_5%
12 12 AC97_BITCLK_MDC <21>
Change design at 12/03. +3VALW 1 2

GND
GND
GND
GND
GND
GND
C458 D20
@ 10P_0402_25V8K D21 2 KSI_D_3
5

U37 13 2 KSI_D_0 KSI3 1

14
15
16
17
18
1 KSI0 1 3 KSI_D_11
P

<21> AC97_RST#_MDC IN1

4 3 KSI_D_8
O DAP202U_SOT323-3
<20> MODEM_DISABLE# 2 IN2
G

DAP202U_SOT323-3 D22
SN74AHC1G08DCKR_SC70 D23 2 KSI_D_4
3

JP25
RJ-11 Conn. JP26
KSI1 1
2 KSI_D_1

3 KSI_D_9
KSI4 1
3 KSI_D_12

1 MOD_RING MOD_TIP 1 DAP202U_SOT323-3

1 MOD_TIP MOD_RING TIP DAP202U_SOT323-3 D24
2 2 2 RING
2 2 D25 2 KSI_D_5
C459 C460 2 KSI_D_2 KSI5 1
3 @ 220P_1808_3KV @ 220P_1808_3KV 3 KSI2 1 3 KSI_D_13
G1 GND KSI_D_10
G2 4 4 GND 3
1 1 DAP202U_SOT323-3
CONN@ ACES_88266-02001 CONN@ ACES_85204-02001_2P DAP202U_SOT323-3 D26
2 KSI_D_6
KSI6 1
3 KSI_D_14

DAP202U_SOT323-3

Power button
+3VL +3VL
+3VL
TrackPoint CONN. +5VS
T/P BOARD.
1

ACES_87151-04051_4P
2
100K_0402_5%

R471 JP27 JP28

1

D27 100K_0402_5% RIGHT 1 +5VS +5VS

1 1
R472

@ SF10402ML080C_0402 2 <33> TP_CLK

LEFT 2 2
3 1 <33> TP_DATA 1
2

SW1 3 C462 3 C461

ON/OFFBTN_KBC# <33> <33> SP_CLK 4 4 4
5

CONN@
1BT002-0121L_4P U20 <33> SP_DATA 5 0.1U_0402_16V4Z
2

5
1

SN74LVC1G14DCKR_SC70-5 D +3VALW 0.1U_0402_16V4Z

3 1 6
V

ON/OFF# 6 2 5 2
2 A Y 4 1 2 2 7 7 6
R473
NC

4 2 G +5VS 8 8
G

3
1 100K_0402_5% 1 S Q38 1 2
3

2N7002_SOT23 R474 100K_0402_5% ACES_87151-0807G D39

5
6

1
3

C463 C464 D28 CONN@ @ UESD3.3DT5G SOT-723

1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# <22>
2 2
CH751H-40_SC76

1
ON/OFF# <34>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 30 of 36
 5 4 3 2 1

BT Connector
+5VALW USB_VCCA
JP29
D D
1 +3VAUX_BT
2

2
USB20_P6_R R475 2 1 0_0402_5%
3 USB20_P6 <22>
R476 USB20_N6_R R477 2 1 0_0402_5%
+5VALW 4 USB20_N6 <22>
10K_0402_5% 5 BT_LED <19>
U21
6

1
JP30 7
1 GND OUT 8 W=100mils 8
2 IN OUT 7 1 1
3 6 2 CONN@ ACES_87213-0800G_8P
IN OUT <22> USB20_N0 2
S4_STATE# 4 5 3
EN# OC# <22> USB20_P0 3

0.1U_0402_16V4Z
220U 6.3V M F60
1 1 4 4

1000P_0402_50V7K

D29
PACDN042_SOT23~D
C465 1 1 5 GND

3
+

C466

C467

C468
G548A1P1U 6
4.7U_0805_10V4Z GND
2
(2A,100mils ,Via NO.=4) 7 GND +3VALW +3VAUX_BT
8 GND
2 2 2 Q39
CONN@ SUYIN_020173MR004S558ZL_4P SI2301BDS_SOT23

D
3 1

C471

C472
@

G
2
1
Change U21 to active
R480 1 1
high part. 12/11 10K_0402_5%

2
2 2

10U_0805_10V4Z
0.1U_0402_16V4Z
R482
<22> BT_OFF 1 2
C C
+5VALW 220K_0402_1%

JP31

USB20_N4 1
<22> USB20_N4 USB20_P4 2
U22, D30, R481, C474 ~ C477 will <22> USB20_P4 3 8
move to USB board side to save M/B S4_STATE# 4 7
space. 5
6
ACES_87213-0600G_6P

3.75A nominal with 3.5A minimum

+5VALW USB_VCCC
R483
B 0.01_2512_1% Q40 B
+3VALW
W=160mils
1 2 8 D S 1
2.2U_0805_16V4Z

0.1U_0402_16V4Z

7 2
USB CONNECTOR 3 D S

1000P_0402_50V7K
C480

C481

C482
0.1U_0402_16V4Z
1 1 6 D S 3 1

220U_D_6.3VM
5 D G 4 1 1
+
2

1
C478

C479

SI4800DY_SO8
R356 2 2 R484
2 2 2

0.1U_0402_16V4Z
100K_0402_5%
820_0805_1%
1
1

C483
U23 JP32
<22> S4_STATE# R628 1 2 10K_0402_5% S4_STATE#_R 13 8 1
FAULT ENABLE IN 1
11 FAULT <22> USB20_N5 2 2
USB_ISENSE1 2
12 10 3
0.47U_0402_10V7K 1K_0402_5%

PWRGD ISET <22> USB20_P5 3

1000P_0402_50V7K

4
0_0402_5%

4
1

82P_0402_50V7K
1U_0603_10V4Z

7 USB_ISENSE2 5
ISENSE GND

3
3 6
R485

TIMER GND
R629

PACDN042_SOT23~D D31
4 VREG GATE 1 7 GND
8 GND
2 14
2

DGND DISCH
0.1U_0402_16V4Z

6 CONN@ SUYIN_020173MR004S558ZL_4P
AGND
1 1 1 1 1 9 5

1
AGND VSENSE
TPS2331IPWRG4_TSSOP14
C321

2 2 2 2 2
C484

C485

C486

C487

A A

Change for SI1 to prevent USB power

short to GND cause system shutdown. 0130

Change C486 from 2200pF to 680pF.

Change C321 from 1000pF to 1uF.
Change R356 from 10K to 100K.
Change C484 from 1000pF to 0.47uF.
Security Classification Compal Secret Data Compal Electronics, Inc.
Change R484 from 1K to 820. Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

Currently power USB will not enable after OCP, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
Size Document Number Rev
so add R629 make it enable after OCP free. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 31 of 36
5 4 3 2 1
 5 4 3 2 1

+3VS +3VALW

Finger printer
TPM1.2 on board

C488

C489

C490

C491
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1

2 2 2 2

D D

+3VALW

24
19
10

5
U24

VSB
VDD
VDD
VDD
Q42 LPC_AD0 26
SI2301BDS_SOT23 LPC_AD1 LAD0
23 LAD1
JP33 LPC_AD2 20
S
USB20_N1_PWR +3VS LPC_AD3 LAD2 TPM_GPIO +3VS

D
3 1 1 1 17 LAD3 GPIO 6 PAD T83
<22> USB20_N8 2 LPC_FRAME# 22 2 TPM_GPIO2 PAD T84
2 LFRAME# GPIO2

C492

C563
<22> USB20_P8 3 PLT_RST# 16 Base I/O Address
3 LRESET#

1
R489 1 2 10K_0402_5% 0 = 02Eh
G

1 1 4 28
2

4 SIRQ LPCPD#
27 SERIRQ
1 =* 04Eh
2

2
CONN@ E&T_3801-04 <22> LPC_PD# R492 2 1 0_0402_5% <16> CLK_PCI_TCG 21 R490
LCLK

0.1U_0402_16V4Z

10U_0805_6.3V4Z
R486 R495 4.7K_0402_5%
2 2
10K_0402_5% D32 2 1
2 1 SLB 9635 TT 1.2 0_0402_5%

2
PACDN042_SOT23~D +3VS C493 R494 @ 10_0402_5% 15 8 2 1 2 1
@ 10P_0402_50V8K CLKRUN# TEST1
9
1

TESTB1/BADD R496
<22,27,33> PM_CLKRUN#

1
R487 7 @ 4.7K_0402_5%
220K_0402_1% PP
<22> FPR_OFF 1 2 R497 3
@ 4.7K_0402_5% TPM_XTALO NC
14 XTALO NC 12
1

2
TPM_XTALI NC
13 XTALI/32K IN

GND
GND
GND
GND
R498
0_0402_5% SLB 9635 TT 1.2_TSSOP28

25
18
11
4
C C

2
C494 2 1 18P_0402_50V8J TPM_XTALI

1
Y4
2 1 R499
NC IN 10M_0402_5%
3 NC OUT 4

2
32.768KHZ_12.5P_1TJS125BJ2A251

C495 2 1 18P_0402_50V8J TPM_XTALO

Add SIRQ and connect to

pin5. 10/08
+3VL
LPC Debug Port

100K_0402_5%
1
B+

R500
7/20

B
BIOS ROM +3VL B

2
Change Footprint. 12/13
&U1 8051_RECOVER# JP34
1 20mils 1 Ground
C496 U25 2
<16> CLK_PCI_DB LPC_PCI_CLK
8 VCC VSS 4 3 Ground
0.1U_0402_16V4Z 4
7/20 2 <21,26,33> LPC_FRAME# LPC_FRAME#
SPI_WP# 3 SIRQ 5
W <22,27,33> SIRQ +V3S
45@ SST25LF080A_SO8-200mil 6
<8,20,26> PLT_RST# LPC_RESET#
+3VL R501 1 2 3.3K_0402_5% SPI_HOLD#_0 7 7
HOLD +V3S
20mils <21,26,33> LPC_AD0 8 LPC_AD0
SPI_CS0# 1 9
<33> SPI_CS0# S <21,26,33> LPC_AD1 LPC_AD1
<21,26,33> LPC_AD2 10 LPC_AD2
SPI_CLK 6 11
<33> SPI_CLK C <21,26,33> LPC_AD3 LPC_AD3
12 VCC_3VA
SPI_SI 5 2 SPI_SO_R R502 1 2 15_0402_5% SPI_SO <33> 13
<33> SPI_SI D Q <33> 8051TX PWR_LED#
<33> 8051RX 14 CAPS_LED#
SPI_CS0#_JP34 R503 2 1 0_0402_5% SPI_CS0# WIESO_G6179-100000_8P 8051_RECOVER# 15
<33> 8051_RECOVER# NUM_LED#
<33,35,39> VCC1_PWRGD 16 VCC1_PWRGD
SPI_CLK_JP34 R504 1 2 0_0402_5% SPI_CLK 7/20 SPI_CLK_JP34 17
SPI_CS0#_JP34 SPI_CLK
20mils 18 SPI_CS#
SPI_SI_JP34 R507 1 2 0_0402_5% SPI_SI +3VL 1 2 SPI_WP# R506 1 2 @ 0_0402_5% SPI_SI_JP34 19
R505 3.3K_0402_5% SPI_SO_JP34 SPI_SI
Modify in 2/23. 20 SPI_SO
SPI_SO_JP34 R56 1 2 0_0402_5% SPI_SO_R SPI_HOLD#_0_JP34 21 SPI_HOLD#
<33> KBC_SPI_CS1#_R_JP34 22 Reserved
SPI_HOLD#_0_JP34 R632 1 2 0_0402_5% SPI_HOLD#_0 23 Reserved
24 Reserved
2/22
Pin3, 23 tie to GND. 10/10 ACES_87216-2404_24P
CONN@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 32 of 36
5 4 3 2 1
 +3VL
+3VL

2
100K_0402_5%
R513
1 1 1 1 1 R511 2 1 0_0402_5% +3VS

1
0.1U_0402_16V4Z
C499 C500 C501 C502 C503
G_BATLED# <21>

C498
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1
2 2 2 2 2 +3VL

1
D
GREEN_BATLED# 2 Q44
2 2N7002_SOT23
Del BATSELB_A# pin since only one G

2
S
battery. 10/18

3
R512

106

119
@ 100K_0402_5%

39
58
84

14

49
+3VL U26
128 15 C504 1 2 4.7U_0805_10V4Z

VCC1
VCC1
VCC1
VCC1
VCC1

VCC1

VCC2
<32> SPI_SI

1
FLDATAOUT CAP
<22> KBC_SPI_SI_R 127 HSTDATAOUT
RP18 R515 1
<32> SPI_CS0# 97 FLCS0# GPIO28 93 2 0_0402_5% PM_SLP_M# <22,36,40,41>
1 8 KSI0 96 98
<22> KBC_SPI_CS0#_R HSTCS0# GPIO29 SUS_PWR_ACK <22> +3VL
2 7 KSI3 95 99 Del D35 & @523 for
<32> SPI_SO FLDATAIN GPIO30 AC_PRESENT <22>
3 6 KSI2 94 100 R517 1 2 0_0402_5%
4 5 KSI1
<22> KBC_SPI_SO HSTDATAIN GPIO31
126
EAPD <28> power saving. 0130
GPIO32 PCI_SERR# <20,27>
<30> KSO[0..11] +3VL
@R519 for
10K_1206_8P4R_5% KSO0 21 124 KBC_PWR_ON ADP_PRES 1 2
KSO1 20
KSO0 OUT0
125 GREEN_BATLED#
KBC_PWR_ON <39> power saving. R523 @ 100K_0402_5%
RP19 KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# <19> 0130. CRACK_BGA
19 KSO2 1 2
1 8 KSI7 KSO3 18 123 R519 1 2@ 10K_0402_5% R525 100K_0402_5%

SMSC_1091-NU_TQFP-128P
KSI6 KSO4 KSO3 OUT7/SMI# KBRST# BATCON
2 7 17 KSO4 OUT8/KBRST 122 1 2 KB_RST# <21> 1 2

Keyboard/Mouse Interface
3 6 KSI5 KSO5 16 121 D33 R322 @ 100K_0402_5%
KSO5 OUT9/PWM2 LAN_DISABLE_N <22>
4 5 KSI4 KSO6 13 120 CH751H-40_SC76 THM_TRAVEL# 1 2

General Purpose I/O Interface

KSO7 KSO6 OUT10/PWM0 BAT_PWM_OUT <38> R320 100K_0402_5%
12 KSO7 OUT11/PWM1 118 CHGCTRL <38>
10K_1206_8P4R_5% KSO8 10
KSO9 KSO8 THM_TRAVEL# Swap BAT_PWM_OUT and LAN_DISABLE_N. 10/08 ADP_ID
9 KSO9 GPIO01 107 1 2
KSO10 8 79 ON/OFFBTN_KBC# <30> R624 10K_0402_5%
KSO11 KSO10 GPIO02
7 KSO11 GPIO03 80 LOW_BAT# <22>
+5VS 6 81 KSO14 Keep location as PR154. 12/4
KSO12/GPIO00/KBRST GPIO04/KSO14 PAD T85
5 83 KSO15 PAD T86 PM_RSMRST# <22>
KSO13/GPIO18 GPIO05/KSO15
1 2 TP_CLK <30> KSI[0..7] GPIO07/PWM3 85 PM_RSMRST# R604 1 2 10K_0402_5%
R521 10K_0402_5% KSI0 29 86 CRACK_BGA KBC_PWR_ON 1 2
KSI0 GPIO08/RXD CRACK_BGA <13,23>
KSI1 28 87 PAD T127 R622 10K_0402_5%
KSI2 KSI1 GPIO09/TXD
27 KSI2
1 2 TP_DATA KSI3 26 KSI3 GPIO11/AB2A_DATA 88 AB2A_DATA R526 1 2 0_0402_5% I2C_DAT <30> Add in 12/3.
R524 10K_0402_5% KSI4 25 89 AB2A_CLK R527 1 2 0_0402_5% I2C_CLK <30>
KSI5 KSI4 GPIO12/AB2A_CLK R279 1
24 KSI5 GPIO13/AB2B_DATA 90 2 0_0402_5% CELLS <38>
KSI6 23 91 R516 1 2 0_0402_5% +3VL
RP20 KSI6 GPIO14/AB2B_CLK A_SD <28>
KSI7 22 92 BATCON R630 1 2 0_0402_5% Add in 2/1. RP21
KSI7 GPIO15/FAN_TACH1 AC_AND_CHG <38>
1 8 SP_CLK 101 4.7K_1206_8P4R_5%
GPIO16/FAN_TACH2 BAT_ID# <37>
2 7 SP_DATA 102 SMB_EC_CK1 1 8
PS2_CLK TP_CLK GPIO17/A20M GATEA20 <21> SMB_EC_DA1 2
3 6 <30> TP_CLK 35 IMCLK 7
4 5 PS2_DATA TP_DATA 36 103 8051_RECOVER# AB1B_CLK 3 6
<30> TP_DATA IMDAT GPIO20/PS2CLK 8051_RECOVER# <32>
SP_CLK 38 105 AB1B_DATA 4 5
<30> SP_CLK KCLK GPIO21/PS2DAT SLP_S3# <22,24,26,28,35,36,38,41,42,44>
10K_1206_8P4R_5% SP_DATA 40 4
<30> SP_DATA KDAT GPIO24/KSO16
PS2_CLK 41 74 ADP_PRES
EMCLK GPIO27 ADP_PRES <24,36,38>
PS2_DATA 42
+3VS EMDAT

111 SMB_EC_DA1 SMB_EC_DA1 <37>

AB1A_DATA SMB_EC_CK1
AB1A_CLK 112 SMB_EC_CK1 <37>
Access Bus Interface
55 109 AB1B_DATA PGD_IN 1 2
<22,27,32> PM_CLKRUN#
57
CLKRUN# AB1B_DATA
110 AB1B_CLK
10/24 R532 10K_0402_5%
<22,27,32> SIRQ SER_IRQ AB1B_CLK
1 2 RUNSCI_EC# <16> CLK_PCI_EC
CLK_PCI_EC 54 PCI_CLK Power Mgmt/SIRQ
R533 10K_0402_5% RUNSCI_EC# 76 73 R534 1 2 0_0402_5%
<22> RUNSCI_EC# EC_SCI# PGM Strap/GPIO25 I2C_INT <30>
108 EA# R531 2 1 1K_0402_5% +3VL R535 1 2 @ 10_0402_5% C505 1 2 @ 10P_0402_25V8K
EA Strap#/GPIO26/KSO17 CLK_14M_KBC
<21,26,32> LPC_AD3 51 LAD[3] CLOCKI 59 CLK_14M_KBC <16>
50 75 32K_CLK R545 1 2 0_0402_5%
<21,26,32> LPC_AD2 LAD[2] 32KHZ_OUT/GPIO22 ADP_EN <44>
48 60 PGD_IN R543 2 1 2.2K_0402_5% PM_PWROK PM_PWROK <8,22,42,43>

Miscellaneous
<21,26,32> LPC_AD1 LAD[1] RESET_OUT#/GPIO06
delete R537 & 539 to clean up 46 LPC 78 PWR_GD
<21,26,32> LPC_AD0 LAD[0] PWRGD PWR_GD <35,42>
77 VCC1_PWRGD
CRY1 & CRY2 traces Bus VCC1_PWRGD VCC1_PWRGD <32,35,39>
<21,26,32> LPC_FRAME# 52 61 ADP_PS0 <44>
53
LFRAME# 24MHZ_OUT/GPIO19/WINDMON 9/21
<22> NPCI_RST# LRESET#
45 69 TEST R536 1 2 1K_0402_5%
<44> ADP_PS1 LPCPD#/GPIO23 TEST PIN
Change to 1K. 10/03 PM_PWROK 2 1 VCC1_PWRGD
D36 CH751H-40_SC76
CRY1 70 116 ADP_ID
CRY2 XTAL1 DMS_LED#/GPIO10
71 XTAL2 BAT_LED# 113 AMBER_BATLED# <19>
PWR_LED#/8051TX 115 8051TX <32>
+VCC0 68 VCC0 FDD_LED#/8051RX 114 8051RX <32> LANLINK_STATUS# no longer read by KBC. Add
R623 1 2 1 1 2
R333 between signal and pin 65. 10/08
<22,24,25> LAN_PHYPC GPIO40 +3VL
0_0402_5% 2 67 R538 100K_0402_5% Install R57. 10/08
<22> KBC_SPI_CLK_R HSTCLK NC
C506 22P_0402_50V8J

C507 22P_0402_50V8J

<32> SPI_CLK 3 FLCLK NC 66

30 65 R333 1 2 @ 0_0402_5%
<26> MC2_DISABLE GPIO39 GPIO33 LANLINK_STATUS# <22,24,25>
1

KBC_SPI_CS1#_R 31 64 R57 1 2 0_0402_5%

HSTCS1# GPIO34 LID_SW# <18,19,22>
32 63 R544 1 2 @ 0_0402_5%
IN

OUT

FLCS1# GPIO35 CAP_RST_EC <30>

<26> WMC1_DISABLE 33 GPIO38 GPIO36 62
1 1 SMSC guideline <22,36> LAN_WOL_EN 34 GPIO37
AGND

suggest to change 43
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC

NC

44 NC
18P to 22P
2 2 KBC1091-NU_TQFP128_14X14
2
2

72

11
37
47
56
104
82
117

C339
4.7U_0805_10V4Z
Y5 +RTCVCC
32.768KHZ_12.5P_1TJS125BJ2A251 1

Change in 10/08
1

Modify in 2/23.
R542
0_0402_5% 1 2 KBC_SPI_CS1#_R
<32> KBC_SPI_CS1#_R_JP34 KBC_SPI_CS1#_R <22>
R633 0_0402_5%
2

R520 1 2 +VCC0
@ 0_0402_5%
0.1U_0402_16V4Z

SMSC guideline suggest to change 0.1U to 0 ohm

1U_0603_10V4Z

1 1
AGND FILTER
2 2 C510
Security Classification Compal Secret Data Compal Electronics, Inc.
C528

C529

1 2
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 33 of 36
 DOCKING CONNECT
10/23
JP35

56
VA CONN@ FOX_QL0127L-C24E51-4F_54P-T
10/23

56
VA 53 53 54 54

51 51 52 52

C511

C512

C513

C514

C515

C516

C517

C518
<25> MDO0+ 49 49 50 50 MDO2+ <25>
1 1 1 1 1 1 1 1 <25> MDO0- 47 47 48 48 MDO2- <25>
<25> MDO1+ 45 45 46 46 MDO3+ <25>
<25> MDO1- 43 43 44 44 MDO3- <25>
2 2 2 2 2 2 2 2

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V

0.1U_0603_50V
+5VALW 37 37 38 38 +5VALW
35 35 36 36
+5VS 33 33 34 34
31 31 32 32 LANLINK_STATUS#_DOCK <25>
29 29 30 30 LAN_ACT#_DOCK <25>
<22> USB20_P9 27 27 28 28
<22> USB20_N9 25 25 26 26 ADP_SIGNAL <37,44> Change for can't charge issue. 10/24
23 23 24 24 ON/OFF# <30>
21 22 PREP#
T125 21 22 PREP# <22,25>
T126 19 19 20 20 D_DDCDATA <17>
<19,30> STB_LED 17 17 18 18 D_DDCCLK <17>
15 15 16 16 D_HSYNC <17>
<17> BLUE 13 13 14 14 D_VSYNC <17>
<17> GREEN 11 11 12 12
<17> RED 9 9 10 10
PREP# 7 8
7 8 LINE_IN_SENSE <28>
5 5 6 6 DOCK_HPS# <29>
<28> DLINE_OUT_L 3 3 4 4 DOCK_LINE_IN_L <28>
<28> DLINE_OUT_R 1 1 2 2 DOCK_LINE_IN_R <28>

55
55
Delete:
1. L21 ~ L23.
2. C605 ~ C610.
3. R635 ~ R637.
4. U27 ~ U29.
5. C519 ~ C521.
6. R548 ~ R550.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 34 of 36
Update per change list. 9/14
+3VS
R551
WWAN Card STANDOFF CPU support
1M_0402_5%
2 1 H3 H4 H22 H23 H24 H25

1
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
Change value for SI1. 01/30 R553
+5VALW 10K_0402_5%
<41> +1.5VS_PG 2 1

1
R554 3.3K_0402_5%

2
8
U30A
2 1 R556 2 1 10K_0402_5% 3

P
+5VS +
R555 113K_0603_1% 1 1 2
O PWR_GD <33,42>
2VREF_8734 2 1 2VREF_393 2 J6 SHORT PADS
-

G
+3VS 2 1 R558 30.1K_0402_5% LM393M_SO8
R559 75K_0402_1%

4
R479 2 1 44.2K_0402_1%
M_PWROK 1
D38
2 1
R560
2
3.3K_0402_5%
MDC STANDOFF
CH751H-40_SC76 1
D43 2 1 CH751H-40_SC76 C523 H5 H6 H27 H30 H31 H28
SLP_S3# <22,24,26,28,33,36,38,41,42,44>
1000P_0402_50V7K HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
+VCCP R478 1 2 23.7K_0402_1%
2
Change 10K to 3.3K, due to
M_PWROK too low (about 2.86V).

1
1

1
R561 03/28
28K_0402_1% C526 +3VALW
3300P_0402_50V7K

2
2
R562 2 1 1M_0402_5%

2
Del H1, H7 & H8. 1/18
R563
+5VALW 3.3K_0402_5%

1
8
U30B
R564 1 2 1K_0402_5% R565 2 1 10K_0402_5% 5 H9 H10 H11 H12 H13 H14 H15 H16

P
<41> M_PROK +
7 M_PWROK HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
O M_PWROK <8,22>
+3VM R566 1 2 49.9K_0603_1% 2VREF_393 6 -

G
R509 1 LM393M_SO8
+0.9V 2 13.7K_0402_1%

1
R386 1 2 1K_0402_5%
<40> DDR2_PG
Change value for SI1. 01/30
H17 H18 H19 H20 H21 H26
1

To reduce hysteresis on PWR_GD & M_PWROK, make HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

R567
154K_0402_1% C527 following changes:
0.033U_0402_16V7K R554=3.3k, R555=113k, R556=10k, R559=75k, R560=3.3k,
2

1
R478=23.7k, R561=28k, C526=3300pF; R566=49.9k,
2

R509=13.7k, R567=154k, R565=10k; remove R625, and

Change value for PV-R. 07/08 move D43 close to D38 and connect D43-2 to D38-2 and
C527=0.033UF, R564=1K, R385=1K D43-1 to SLP_S3#.
FM1 FM2 FM3 FM4
1 1 1 1
+3VL

R514 2 1 1M_0402_5% R611 1 2 10K_0402_5% +3VL

2

VL
R591
23.7K_0402_1%
1

U3A
R552 1 2 23.7K_0402_1% 3 JESD1 JESD2 JESD3 JESD4
KBC Power OK
P

+ CLIP PADCLIP PAD CLIP PADCLIP PAD

O 1 VCC1_PWRGD <32,33,39>
2200P_0402_50V7K

update KBC power good. 9/19 2 -

2

1 VL VL
LM393M_SO8
4

1
R592
1
100K_0402_5%
C216

51.1K_0402_1%
1

2 R510
1

R584

1M_0402_5%

Change value for DB2. 12/11

2

9/21
2

Change R555 from 169K to 365K.

Change R559 from 113K to 237K.
C215 Change R478 from 35.7K to 76.8K.
1

0.1U_0402_16V4Z D
2N7002_SOT23 Change R561 from 40.2K to 90.9K.
1 2 2
Q1
Change R566 from 76.8K to 158K.
G Change R509 from 21K to 43.2K.
S Change R567 from 187K to 499K.
3

2VREF_8734

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 35 of 36
 A B C D E

Modify at 7/31 after discuss with power team. +3VALW +3VM_WOL Discharge circuit-2 for V-M
+1.05VM to +VCCP Transfer +3VALW to +3VM_WOL Transfer U33 +1.05VM +3VM
To increase voltage B+ 8 1
D S
7 2
margin, change D S

1
+1.05VM +VCCP

C470

0.1U_0402_16V4Z
C218 1 6 3
D S

1
pull-up rail on B+ 10U_0805_10V4Z 5 4 R581
D G 1 1
Q51 R518 from +3VALW to R612 C473 R580 470_0402_5%
AO4430 1N SOIC-8 100K_0402_5% SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%

1
8 1 B+. 1/31 2

1 2

1 2
R518 2 2
7 2

2
100K_0402_5% 3VM_WOL_EN D D
6 3
5 LAN_EN# 2 LAN_EN# 2

1
C596

C542

C543

C497
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
G G

1
1 D R613 Q53 Q54 1
1 1 1 1 S S

3
Q47 LAN_WOL_EN# 2 Q76 470_0402_5% RHU002N06_SOT323 RHU002N06_SOT323
BSS138_SOT23 G BSS138_SOT23

1
D +3VALW S

2
2 2 RUNON 2 2 PM_SLP_M# +3VM_WOL
<22,33,40,41> PM_SLP_M# 2 1
G C469

1
S 0.01U_0402_25V7K

3
1

1
R576 2
R645 100K_0402_5% R614
820K_0402_5% 470_0402_5%

1
D
2

1 2
<22,33> LAN_WOL_EN 2 Q50
BSS138_SOT23 D
add 820k ohm divider G Add in 9/21

1
S LAN_WOL_EN# 2
with AC select 7/15

3
1

D R577 G
<24,33,38> ADP_PRES 2 Q85 @ 100K_0402_5% Q77 S

3
G 2N7002_SOT23 RHU002N06_SOT323
S
3

2
Add in 9/21

+3VALW +3VM
+3VALW to +3VM Transfer U32
+3VALW to +3VS Transfer To increase voltage B+ 8
7
D S 1
2
margin, change D S

C532

0.1U_0402_16V4Z
C531 1 6 3
D S

1
pull-up rail on R574 B+ 10U_0805_10V4Z 5 4
D G 1 1
+3VALW +3VS R573 C533
2 B+ U35
from +3VALW to B+. 100K_0402_5% SI4800DY_SO8 10U_0805_10V4Z 2

1
SI4800DY_SO8 1/31 2
R574 2 2
8 S 1

2
D
1

7 100K_0402_5% 3VM_EN
D S 2
10U_0805_10V4Z
0.1U_0402_16V4Z

1 6 D S 3

1
R578 5 G 4 1 1

2
D

1
330K_0402_5% C538 D R575
10U_0805_10V4Z Q49 LAN_EN# 2 Q48 470_0402_5%
2

2
C539

C540

BSS138_SOT23 G BSS138_SOT23

1
2 2 D
S

2
RUNON PM_SLP_M# 2 1
G C537
1

S 0.01U_0402_25V7K

3
J7
SHORT PADS R579 2
1 2

470_0402_5%
D
2

SLP_S3 2 Q52 1
G RHU002N06_SOT323 C541
S 0.01U_0402_25V7K
3

2 +3VL +3VL

1
R583 R582
+5VALW to +5VS Transfer Design Change at 9/14.
100K_0402_5% 100K_0402_5%

2
+5VALW +5VS
U36 SLP SLP SLP_S3
3 SI4800DY_SO8 3
8 D S 1
1

1
D D D
7 D S 2
0.1U_0402_16V4Z

1 6 D S 3 <22> SLP_S5# 2 <22,40> SLP_S4# 2 <22,24,26,28,33,35,38,41,42,44> SLP_S3# 2

5 G G G
C544 D G 4 1 1
C546 Q55 Q57 Q56
S S S
3

3
10U_0805_10V4M 10U_0805_10V4Z @ RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
2
C545

2 2
RUNON

Discharge circuit-1
Add in 1/31.
+3VS
+0.9V
+1.5VS +5VS +VCCP +1.8V
1
1

R587
1

1
R586
470_0402_5% R588 R589 R631 R590
470_0402_5%
2

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

1 2

1 2

1 2

1 2

1 2
1

D D
SLP SLP_S3 2 D D D D
2
G G SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP 2
S Q58 S Q59 G G G G
3

4 RHU002N06_SOT323 RHU002N06_SOT323 S Q60 S Q61 S Q82 S Q62 4

3

3
RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323

Del PWR_GD from Q59.1. 12/11

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4021P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401554 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 03, 2009 Sheet 36 of 36
A B C D E