CY62146ESL MoBL®

4-Mbit (256K × 16) Static RAM

4-Mbit (256K × 16) Static RAM

Features Functional Description

■ Very high speed: 45 ns The CY62146ESL is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V advanced circuit design to provide ultra low active current. This
■ Ultra low standby power is ideal for providing More Battery Life (MoBL®) in portable
❐ Typical Standby current: 1 A
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
❐ Maximum Standby current: 7 A
when addresses are not toggling. Placing the device into standby
■ Ultra low active power mode reduces power consumption by more than 99% when
❐ Typical active current: 2 mA at f = 1 MHz deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
■ Easy memory expansion with CE and OE features deselected (CE HIGH), the outputs are disabled (OE HIGH),
■ Automatic power down when deselected both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
■ Complementary metal oxide semiconductor (CMOS) for
To write to the device, take Chip Enable (CE) and Write Enable
optimum speed and power
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
■ Available in Pb-free 44-pin thin small outline package (TSOP) II from I/O pins (I/O0 through I/O7) is written into the location
package specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related documentation, click here.

Logic Block Diagram

DATA IN DRIVERS

A10
A9
A8
ROW DECODER

SENSE AMPS

A7
A6 256K × 16
A5
I/O0–I/O7
A4 RAM Array
A3
I/O8–I/O15
A2
A1
A0

COLUMN DECODER

BHE
WE
A11
A12
A13

CE
A15

A17
A14

A16

OE
BLE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-43142 Rev. *H Revised December 4, 2017
 CY62146ESL MoBL®

Contents
Pin Configurations ........................................................... 3 Ordering Information ...................................................... 12
Product Portfolio .............................................................. 3 Ordering Code Definitions ......................................... 12
Maximum Ratings ............................................................. 4 Package Diagram ............................................................ 13
Operating Range ............................................................... 4 Acronyms ........................................................................ 14
Electrical Characteristics ................................................. 4 Document Conventions ................................................. 14
Capacitance ...................................................................... 5 Units of Measure ....................................................... 14
Thermal Resistance .......................................................... 5 Document History Page ................................................. 15
AC Test Loads and Waveforms ....................................... 5 Sales, Solutions, and Legal Information ...................... 16
Data Retention Characteristics ....................................... 6 Worldwide Sales and Design Support ....................... 16
Data Retention Waveform ................................................ 6 Products .................................................................... 16
Switching Characteristics ................................................ 7 PSoC® Solutions ....................................................... 16
Switching Waveforms ...................................................... 8 Cypress Developer Community ................................. 16
Truth Table ...................................................................... 11 Technical Support ..................................................... 16

Document Number: 001-43142 Rev. *H Page 2 of 16

 CY62146ESL MoBL®

Pin Configurations
Figure 1. 44-pin TSOP II pinout (Top View) [1]

A4 1 44 A5
A3 2 43 A6
A2 3 42 A7
A1 4 41 OE
A0 5 40 BHE
CE 6 39 BLE
I/O0 7 38 I/O15
I/O1 8 37 I/O14
I/O2 9 36 I/O13
I/O3 10 35 I/O12
VCC 11 34 VSS
VSS 12 33 VCC
I/O4 13 32 I/O11
I/O5 14 31 I/O10
I/O6 15 30 I/O9
I/O7 16 29 I/O8
WE 17 28 NC
A17 18 27 A8
A16 19 26 A9
A15 20 25 A10
A14 21 24 A11
A13 22 23 A12

Product Portfolio
Power Dissipation

Speed Operating ICC, (mA)

Product Range VCC Range (V) [2] Standby, ISB2 (A)
(ns) f = 1MHz f = fmax
Typ [3] Max Typ [3] Max Typ [3] Max
CY62146ESL Industrial 2.2 V–3.6 V and 4.5 V–5.5 V 45 2 2.5 15 20 1 7

Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.

Document Number: 001-43142 Rev. *H Page 3 of 16

 CY62146ESL MoBL®

Maximum Ratings Output current into outputs (LOW) ............................. 20 mA

Static discharge voltage
Exceeding the maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) .................................. >2001 V
device. These user guidelines are not tested.
Latch up current ...................................................... >200 mA
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with Operating Range
power applied .......................................... –55 °C to +125 °C
Ambient
Supply voltage to ground potential ................–0.5 V to 6.0 V Device Range VCC[6]
Temperature
DC voltage applied to outputs
in High Z State [4, 5] ........................................–0.5 V to 6.0 V CY62146ESL Industrial –40 °C to +85 °C 2.2 V–3.6 V,
and
DC input voltage [4, 5] .....................................–0.5 V to 6.0 V 4.5 V–5.5 V

Electrical Characteristics
Over the Operating Range

45 ns
Parameter Description Test Conditions Unit
Min Typ [7] Max
VOH Output high voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – –
4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – –
VOL Output low voltage 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 V
2.7 < VCC < 3.6 IOL = 2.1mA – – 0.4
4.5 < VCC < 5.5 IOL = 2.1mA – – 0.4
VIH Input high voltage 2.2 < VCC < 2.7 1.8 – VCC + 0.3 V
2.7 < VCC < 3.6 2.2 – VCC + 0.3
4.5 < VCC < 5.5 2.2 – VCC + 0.5
VIL Input low voltage 2.2 < VCC < 2.7 –0.3 – 0.6 V
2.7 < VCC < 3.6 –0.3 – 0.8
4.5 < VCC < 5.5 –0.5 – 0.8
IIX Input Leakage Current GND < VI < VCC –1 – +1 A
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 – +1 A
ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCCmax – 15 20 mA
f = 1 MHz IOUT = 0 mA, – 2 2.5
CMOS levels
ISB1[8] Automatic CE Power down CE > VCC 0.2 V, – 1 7 A
Current – CMOS Inputs VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
ISB2[8] Automatic CE Power down CE > VCC – 0.2 V, – 1 7 A
Current – CMOS Inputs VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)

Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.

Document Number: 001-43142 Rev. *H Page 4 of 16

 CY62146ESL MoBL®

Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF

Thermal Resistance
Parameter [9] Description Test Conditions TSOP II Unit
JA Thermal resistance Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit 57.92 C/W
(junction to ambient) board
JC Thermal resistance 17.44 C/W
(junction to case)

AC Test Loads and Waveforms

Figure 2. AC Test Loads and Waveforms

R1 All Input Pulses

VCC VCC 90%
90%
Output 10% 10%
GND
30 pF R2 Rise Time = 1 V/ns Fall Time = 1 V/ns

Including
JIG and Equivalent to: Thé venin Equivalent
Scope RTH
OUTPUT V TH

Parameter 2.5 V 3.0 V 5.0 V Unit

R1 16667 1103 1800 
R2 15385 1554 990 
RTH 8000 645 639 
VTH 1.20 1.75 1.77 V

Note
9. Tested initially and after any design or process changes that may affect these parameters.

Document Number: 001-43142 Rev. *H Page 5 of 16

 CY62146ESL MoBL®

Data Retention Characteristics

Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR[11] Data retention current CE > VCC – 0.2 V, VCC = 1.5 V – 1 7 A
VIN > VCC – 0.2 V or
VIN < 0.2 V
tCDR [12] Chip deselect to data retention 0 – – ns
time
tR [13] Operation recovery time 45 – – ns

Data Retention Waveform

Figure 3. Data Retention Waveform

DATA RETENTION MODE

VCC VCC(min) VDR > 1.5 V VCC(min)
tCDR tR

CE

Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

Document Number: 001-43142 Rev. *H Page 6 of 16

 CY62146ESL MoBL®

Switching Characteristics
Over the Operating Range
45 ns
Parameter [14, 15] Description Unit
Min Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid – 45 ns
tDOE OE LOW to data valid – 22 ns
tLZOE OE LOW to Low Z [16] 5 – ns
tHZOE OE HIGH to High Z [16, 17] – 18 ns
tLZCE CE LOW to Low Z [16] 10 – ns
[16, 17] –
tHZCE CE HIGH to High Z 18 ns
tPU CE LOW to power up 0 – ns
tPD CE HIGH to power down – 45 ns
tDBE BLE/BHE LOW to data valid – 22 ns
[16] –
tLZBE BLE/BHE LOW to Low Z 5 ns
tHZBE BLE/BHE HIGH to High Z [16, 17] – 18 ns
[18, 19]
Write Cycle
tWC Write cycle time 45 – ns
tSCE CE LOW to write end 35 – ns
tAW Address setup to write end 35 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to Write Start 0 – ns
tPWE WE pulse width 35 – ns
tBW BLE/BHE LOW to write end 35 – ns
tSD Data Setup to write end 25 – ns
tHD Data Hold from write end 0 – ns
[16, 17] –
tHZWE WE LOW to High Z 18 ns
tLZWE WE HIGH to Low Z [16] 10 – ns

Notes
14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.

Document Number: 001-43142 Rev. *H Page 7 of 16

 CY62146ESL MoBL®

Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]

tRC
RC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]

ADDRESS

tRC
CE
tPD
tACE tHZCE
OE

tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
HIGH
HIGHIMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPU
ICC
VCC 50% 50%
SUPPLY ISB
CURRENT

Notes
20. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE, BHE, BLE transition LOW.

Document Number: 001-43142 Rev. *H Page 8 of 16

 CY62146ESL MoBL®

Switching Waveforms (continued)

Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24]

tWC

ADDRESS

tSCE
CE

tAW tHA
tSA tPWE
WE

tBW
BHE/BLE

tHD
tSD

DATA I/O NOTE 25 DATAIN

Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24]

tWC

ADDRESS

tSCE

CE

tSA
tAW tHA
tPWE
WE

BHE/BLE tBW

tSD tHD

DATA I/O NOTE 25 DATAIN

Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.

Document Number: 001-43142 Rev. *H Page 9 of 16

 CY62146ESL MoBL®

Switching Waveforms (continued)

Figure 8. Write Cycle No. 3 (BHE/BLE Controlled) [26]

tWC

ADDRESS

CE

tSCE
tAW tHA
tBW
BHE/BLE

tSA
tPWE
WE
tHZWE tHD
tSD

DATA I/O NOTE 27 DATAIN

tLZWE

Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW) [28]

tWC

ADDRESS

CE

tAW t HA
tSA
WE

tSD t HD

DATA I/O NOTE 27 DATA INVALID

t HZWE tLZWE

Notes
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
28. The minimum write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.

Document Number: 001-43142 Rev. *H Page 10 of 16

 CY62146ESL MoBL®

Truth Table
CE [29] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power down Standby (ISB)
L X X H H High-Z Output disabled Active (ICC)
L H L L L Data Out (I/O0–I/O15) Read Active (ICC)
L H L H L Data Out (I/O0–I/O7); Read Active (ICC)
I/O8–I/O15 in High-Z
L H L L H Data Out (I/O8–I/O15); Read Active (ICC)
I/O0–I/O7 in High-Z
L H H L L High-Z Output disabled Active (ICC)
L H H H L High-Z Output disabled Active (ICC)
L H H L H High-Z Output disabled Active (ICC)
L L X L L Data In (I/O0–I/O15) Write Active (ICC)
L L X H L Data In (I/O0–I/O7); Write Active (ICC)
I/O8–I/O15 in High-Z
L L X L H Data In (I/O8–I/O15); Write Active (ICC)
I/O0–I/O7 in High-Z

Note
29. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.

Document Number: 001-43142 Rev. *H Page 11 of 16

 CY62146ESL MoBL®

Ordering Information
Speed Package Operating
Ordering Code Package Type
(ns) Diagram Range
45 CY62146ESL-45ZSXI 51-85087 44-pin TSOP Type II (Pb-free) Industrial

Ordering Code Definitions

CY 621 4 6 E SL - 45 ZS X I

Temperature Range: I = Industrial

Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: SL = (3 V typical; 5 V typical)
Process Technology: E = 90 nm
Bus width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress

Document Number: 001-43142 Rev. *H Page 12 of 16

 CY62146ESL MoBL®

Package Diagram
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087

51-85087 *E

Document Number: 001-43142 Rev. *H Page 13 of 16

 CY62146ESL MoBL®

Acronyms Document Conventions

Acronym Description Units of Measure
BHE Byte High Enable Symbol Unit of Measure
BLE Byte Low Enable °C degree Celsius
CE Chip Enable MHz megahertz
CMOS Complementary Metal Oxide Semiconductor A microampere
I/O Input/Output mA milliampere

OE Output Enable ns nanosecond

 ohm
SRAM Static Random Access Memory
pF picofarad
TSOP Thin Small Outline Package
V volt
VFBGA Very Fine-Pitch Ball Grid Array
W watt
WE Write Enable

Document Number: 001-43142 Rev. *H Page 14 of 16

 CY62146ESL MoBL®

Document History Page

Document Title: CY62146ESL MoBL®, 4-Mbit (256K × 16) Static RAM
Document Number: 001-43142
Orig. of
Rev. ECN No. Issue Date Description of Change
Change
** 1875228 See ECN VKN / AESA New data sheet.
*A 2944332 06/04/2010 VKN Added Contents
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Truth Table:
Added Note 29 and referred the same note in CE column.
Updated Package Diagram.
Added Sales, Solutions, and Legal Information.
*B 3109186 12/13/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*C 3296704 06/29/2011 RAME Updated Functional Description:
Removed reference to AN1064 SRAM system guidelines.
Updated Electrical Characteristics:
Updated Note 8 (Added ISB1) and referred the same note in ISB1 parameter.
Updated Capacitance:
Added Note 9 and referred the same note in parameter column.
Updated Thermal Resistance:
Added Note 9 and referred the same note in parameter column.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Changed minimum value of tR parameter from tRC to 45 ns.
Updated Switching Characteristics:
Moved Note 14 to parameter column.
Added Units of Measure.
*D 3903350 02/13/2013 MEMJ Updated Switching Waveforms:
Updated Figure 6 (Removed OE signal).
Updated Figure 7 (Removed OE signal).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its reference
in Figure 6, Figure 7.
Removed the figure “Write Cycle 3: WE controlled, OE LOW”.
Updated Figure 8 (Removed “OE LOW” in caption only).
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *E.
*E 4100920 08/21/2013 VINI Updated Switching Characteristics:
Added Note 14 and referred the same note in “Parameter” column.
Updated to new template.
*F 4576406 01/16/2015 VINI Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Figure 9.
Added Note 28 and referred the same note in Figure 9.
*G 5169392 03/10/2016 VINI Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter from 77 C/W to 57.92 C/W.
Changed value of JC parameter from 13 C/W to 17.44 C/W.
Updated to new template.
Completing Sunset Review.
*H 5983493 12/04/2017 AESATMP9 Updated logo and copyright.

Document Number: 001-43142 Rev. *H Page 15 of 16

 CY62146ESL MoBL®

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

Products PSoC® Solutions

® ®
ARM Cortex Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive cypress.com/automotive
Cypress Developer Community
Clocks & Buffers cypress.com/clocks
Forums | WICED IOT Forums | Projects | Video | Blogs |
Interface cypress.com/interface Training | Components
Internet of Things cypress.com/iot
Technical Support
Memory cypress.com/memory
cypress.com/support
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless

© Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-43142 Rev. *H Revised December 4, 2017 Page 16 of 16

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Cypress Semiconductor:
CY62146ESL-45ZSXI CY62146ESL-45ZSXIT