A B C D E

LCFC Confidential
1 1

DY512 M/B Schematics Document

Intel Kabylake H-Processor with DDR4 + NV N17P-G0/G1 GPU
2 2

MB NM-B191
2016-11-25
3
REV:1.0 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 175 of
A B C D E
 A B C D E

NV N17P-G0 40W
NV N17P-G1 50W
PCI-Express 8x Gen3
1

VRAM 256/128*32 1GB/s * 8 Total 8GB/s

Intel CPU Memory BUS (DDR4 non-ECC) 1

Dual Channel
GDDR5*4 4GB/2GB Kaby Lake-H 45W DDR4-SO-DIMM X2
Page 12,13
Page 24~29 Page 30~33
1.2V DDR4 2400 MT/s
BGA-1440 19.2GB/s *2 Total 38.4GB/s UP TO 8G x 2
HDMI Conn. HDMI level shift
PS8203
TMDS 2.97Gbps
42mm*28mm
Page 35
Page 35
Page 5~11
eDP Conn eDP x2 Lane
FHD : 15" 1920*1080 2.7Gb/s * 2 Total 5.4Gb/s
Page 34 DMI *4
1GB/s * 4 Total 4GB/s
USB Right
DP Redriver DP x4Lane
USB 3.0 2x 5Gbps USB 3.0 Port1
Type C controller PS8330B 5.4Gb/s * 4 Total 21.6Gb/s USB 3.0 Port2

USB 2.0 2x 480Mbps

Typec CONN RTS5400 USB 3.0 1x 5Gbps USB 2.0 Port2
Page 37
USB2.0 1x 480Mbps Intel PCH USB 2.0 Port3
Page 43

2 Page 36~37 Kaby Lake-H 2

SATA HDD SATA Gen3 6Gbps USB Left

Page 42 SATA Port2
USB 2.0 1x 480Mbps
USB2.0 Port1

FCBGA PCIe 1x Gne1 250MGB/s

SSD
PCIE 4x Gen3 23mm*23mm LAN Realtek RJ45 Conn.
Optane memory RTL8111GUL(1000M)
1GB/s * 4 Total 4GB/s PCIe Port4
PCIe Port9~12 IO Board
Page 41 One M.2 CONN

USB 2.0 1x 480Mbps

NGFF Card
SD/MMC CardReader PCIe 1x Gne1 250MGB/s
PCIe 1x Gne1 250MGB/s WLAN&BT
Page 39 BH611FJ1LN PCIe Port3
USB2.0 Port11 Page 41
Page 39 PCIe Port2

Int. Camera
USB2.0 1x 480Mbps SPI BUS(17/33/48MHz) SPI ROM
Dual DMIC HD Audio(24MHz) 8MB Page 18
Page 34
Page 14~22
SPI ROM 4MB
3
LPC(24MHz) Page 18
3

DMIC Codec
Realtek ALC3248
Page 43

TPM
EC Z32H320TC
Page 46

SPK Conn. ITE IT8226-LQFP

HP&Mic Combo Conn. Page 45
Page 44
Sub-board
IO Board
IO Board (RJ45/USB2.0/Aduio combo jack)

Battery Touch Pad Int.KBD Thermal Sensor CPU FAN TP BUTTON Board (Only for Provence‐5R)
Page 58 Page 46 Page 46 Fintek F75303M GPU FAN
Page 40 Page 40

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 275 of
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VCCIO
VCCSTG S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+0.6VS
1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+3VALW
CPU_CORE
+3VALW_PCH +2.5V GFX S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
VCCSA
B+
+5VALW S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V +1.8V_AON
+1.8V_MAIN
+1.0VALW VCCST
State NVVDD
NVVDDS
+0.95VGS
BOM Structure Table
+1.35VGS
BOM Structure BTO Item
HSIO port Table
@ Not stuff
Port Description Function ME part(connector, hole)
ME@
S0 O OO O O 1 USB3#1 Left USB3
TPM@ For support TPM sku part
2 USB3#2 Left USB3 Cost down part
CD@
3 USB3#3 TypeC USB3 EMC part stuff
EMC@
S3 O O O O X 4 USB3#4
EMC_NS@ EMC part Not stuff
5 USB3#5 RF part stuff
2
RF@ 2

S3 6 USB3#6 RF part Not stuff

RF_NS@
Battery only O O O O X 7 USB3#7 / PCIE#1
8 USB3#8 / PCIE#2 CarderReader(PCIE)
9 USB3#9 / PCIE#3 WLAN(PCIE)
10
S5 S4/AC Only O O O X X 11
USB3#10 / PCIE#4
PCIE#5
LAN(PCIE)
OPT@ For GPU part
N16@ For N16 GPU part
12 PCIE#6 For N17 GPU part
S5 S4 N17@
O XX X X 13 PCIE#7
Battery only 14 PCIE#8
15 PCIE#9 / SATA#0
S5 S4 16 PCIE#10 / SATA#1
AC & Battery XX X X X 17 PCIE#11
PCIe x4 SSD
don't exist 18 PCIE#12
19 PCIE#13 / SATA#0
20 PCIE#14 / SATA#1
21 PCIE#15 / SATA#2 HDD(SATA3.0)
3
USB2.0 Port table 3

22 PCIE#16 / SATA#3 HDD cable(SATA3.0) Reserved

Port Function
23 PCIE#17 / SATA#4
1 Right USB2
24 PCIE#18 / SATA#5
2 Left USB3
25 PCIE#19 / SATA#6
3 Left USB3
26 PCIE#20 / SATA#6
4 TypeC USB2
5
6 Camera
7
8
9
10
11 BT
12
13
14
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 375 of
A B C D E
 5 4 3 2 1

+3.3V_LDO_RTS5400

2.2K
RTS5400
+3VALW RTS5400_SM_SCL
RTS5400_SM_SDA
D D

+3VALW
Dual MOS Control
2.2K

EC_SMB_CK0
EC_SMB_DA0

+3VALW_R

Battery JBATT2 Change IC PU102

2.2K
BQ24780SRUYR

EC
EC_SMB_CK1
IT8226 EC_SMB_DA1
C C

+3VS_AON +3VALW_PCH

2.2K 2.2K
NV GPU( UV1 ) PCH( UH1 )
+3VS VGA_SMB_CK2
SML1CLK
VGA_SMB_DA2
SML1DATA
Thermal sensor U1
Dual MOS
+3VS_AON
Control Dual MOS
+3VS
Control
F75303M
2.2K

EC_SMB_CK2
B EC_SMB_DA2 B

SMBUS Control Table

WLAN Thermal PCH TP
SOURCE VGA BATT IT8586E SODIMM WiMAX Sensor Module charger

DDR1 DDR2 WLAN TP

EC_SMB_CK1 IT8226 V
+3VALW_PCH +3VS EC_SMB_DA1 +3VALW X V +3VALW X X X X X V

EC_SMB_CK2 IT8226 V V V V
X X X X X
PCH
EC_SMB_DA2 +3VS +3VGS +3VS +3VS +3VALW_PCH

2.2K 2.2K PCH_SMB_CLK PCH

+3VS PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH
Control

Dual MOS EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

A
Device Address A
VGA_SMB_CK2 Device Device Address DDR DIMMA
PCH_SMBCLK 1010 000Xb
VGA_SMB_DA2 Smart Battery Thermal Sensor F75303M DDR DIMMB
PCH_SMBDATA 0X16 1001_100xb 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) WLAN Rsvd
PCH need to update
RTS5400 0xD4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank4
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Frid ay, November 25, 2016 Sheet 475 of
5 4 3 2 1
 5 4 3 2 1

24 PCIE_CRX_GTX_N[0..7]

24 PCIE_CRX_GTX_P[0..7]
I7 : SA00007HB20 VCCIO

PCIE_CTX_C_GRX_N[0..7] 24 I5 : SA00007HS10
PCIE_CTX_C_GRX_P[0..7] 24 PEG_COMP RC1 1 2 24.9_0402_1%
D D

UC1C SKYLAKE_HALO
CAD Note:
Trace width=12 mils ,Spacing=15mil
BGA1440 Max length= 400 mils.
E25 B25
D25 PEG_RXP[0] PEG_TXP[0] A25
PEG_RXN[0] PEG_TXN[0]
E24 B24
F24 PEG_RXP[1] PEG_TXP[1] C24
PEG_RXN[1] PEG_TXN[1]
E23 B23
Change PEG from X16 to X8 D23 PEG_RXP[2] PEG_TXP[2] A23
HLZ SDV 20160510 PEG_RXN[2] PEG_TXN[2]
Change PEG from X16 to X8
E22 B22
F22 PEG_RXP[3]
PEG_RXN[3]
PEG_TXP[3]
PEG_TXN[3]
C22 HLZ SDV 20160510
E21 B21
D21 PEG_RXP[4] PEG_TXP[4] A21
PEG_RXN[4] PEG_TXN[4]
E20 B20
F20 PEG_RXP[5] PEG_TXP[5] C20
PEG_RXN[5] PEG_TXN[5]
E19 B19
D19 PEG_RXP[6] PEG_TXP[6] A19
PEG_RXN[6] PEG_TXN[6]
E18 B18
F18 PEG_RXP[7] PEG_TXP[7] C18
PEG_RXN[7] PEG_TXN[7]
PCIE_CRX_GTX_P7 D17 A17 PCIE_CTX_GRX_P7 OPT@ CC24 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 E17 PEG_RXP[8] PEG_TXP[8] B17 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7
C PEG_RXN[8] PEG_TXN[8] C
PCIE_CRX_GTX_P6 F16 C16 PCIE_CTX_GRX_P6 OPT@ CC23 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 E16 PEG_RXP[9] PEG_TXP[9] B16 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6
PEG_RXN[9] PEG_TXN[9]
PCIE_CRX_GTX_P5 D15 A15 PCIE_CTX_GRX_P5 OPT@ CC22 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 E15 PEG_RXP[10] PEG_TXP[10] B15 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5
PEG_RXN[10] PEG_TXN[10]
PCIE_CRX_GTX_P4 F14 C14 PCIE_CTX_GRX_P4 OPT@ CC21 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 E14 PEG_RXP[11] PEG_TXP[11] B14 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4
PEG_RXN[11] PEG_TXN[11]
PCIE_CRX_GTX_P3 D13 A13 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 E13 PEG_RXP[12] PEG_TXP[12] B13 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3
PEG_RXN[12] PEG_TXN[12]
PCIE_CRX_GTX_P2 F12 C12 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 E12 PEG_RXP[13] PEG_TXP[13] B12 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2
PEG_RXN[13] PEG_TXN[13]
PCIE_CRX_GTX_P1 D11 A11 PCIE_CTX_GRX_P1 OPT@ CC18 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 E11 PEG_RXP[14] PEG_TXP[14] B11 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1
PEG_RXN[14] PEG_TXN[14]
PCIE_CRX_GTX_P0 F10 C10 PCIE_CTX_GRX_P0 OPT@ CC17 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0
PCIE_CRX_GTX_N0 E10 PEG_RXP[15] PEG_TXP[15] B10 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0
PEG_RXN[15] PEG_TXN[15]

PEG_COMP G2
PEG_RCOMP

DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
19 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP[0] DMI_TXP[0] DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 19
E8 A8
19 DMI_CRX_PTX_N0 DMI_RXN[0] DMI_TXN[0] DMI_CTX_PRX_N0 19
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
19 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP[1] DMI_TXP[1] DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 19
B F6 B6 B
19 DMI_CRX_PTX_N1 DMI_RXN[1] DMI_TXN[1] DMI_CTX_PRX_N1 19
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
19 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_RXP[2] DMI_TXP[2] DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 19
E5 A5
19 DMI_CRX_PTX_N2 DMI_RXN[2] DMI_TXN[2] DMI_CTX_PRX_N2 19
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
19 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP[3] DMI_TXP[3] DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 19
J9 B4
19 DMI_CRX_PTX_N3 DMI_RXN[3] DMI_TXN[3] DMI_CTX_PRX_N3 19
3 OF 14

SKYLAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (1/7) DMI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 575 of
5 4 3 2 1
 5 4 3 2 1

CFG STRAPS for CPU(Internal PH)

UC1E SKYLAKE_HALO

VCCST RC28 1 2 0_0402_5% CPU_BCLK B31 BGA1440 BN25 CFG0

17 PCH_CPU_BCLK RC29 1 CPU_BCLK# BCLKP CFG[0]
2 0_0402_5% A32 BN27 CFG1 @ PAD 1
H_THRMTRIP#_R 17 PCH_CPU_BCLK# BCLKN CFG[1] TC89
RC11 1 2 1K_0402_5% BN26 CFG2
RC15 1 CPU_PCIBCLK CFG[2]
H_CATERR# 17 PCH_CPU_PCIBCLK
2 0_0402_5%
CPU_PCIBCLK#
D35
PCI_BCLKP CFG[3]
BN28 CFG3
CFG3 42 St al l r es et s equence af t er PCU PLL l ock unt i l de- as s er t ed
RC174 1 @ 2 10K_0402_5% RC13 1 2 0_0402_5% C36 BR20 CFG4
17 PCH_CPU_PCIBCLK# PCI_BCLKN CFG[4] BM20 CFG5
RC17 1 2 0_0402_5% CPU_NSSC_CLK E31 CFG[5] BT20 CFG6
VCCST 17 PCH_CPU_NSSC_CLK
RC16 1 2 0_0402_5% CPU_NSSC_CLK# D31 CLK24P CFG[6] BP20 CFG7 　1 = (Default) Normal Operation; No stall.
17 PCH_CPU_NSSC_CLK# CLK24N CFG[7] BR23 CFG8 @ PAD 1 CFG0
VCCST CFG[8] TC77
BR22 CFG9 @ PAD 1 　0 = Stall.
CFG[9] BT23 1 TC78
1 CFG10 @ PAD
CFG[10] TC79
C925 BT22 CFG11 @ PAD 1

1K_0402_5%
CFG[11] TC80

1
.1U_0402_10V6-K BM19 CFG12 @ PAD 1
Res er ved conf i gur at i on l ane.

100_0402_1%
56.2_0402_1%

CFG[12] TC81
1

2
@ BR19 CFG13 @ PAD 1
D 2 CFG[13] TC82 D
BP19 CFG14 @ PAD 1

RC7
RC76

RC66
VR_SVID_ALRT#_R CFG[14] TC83
BH31 BT19 CFG15 @ PAD 1
VR_SVID_CLK VIDALERT# CFG[15] TC84
BH32
VIDSCK CFG1 N/A

2
VR_SVID_DAT BH29 BN23 @ PAD 1
VIDSOUT CFG[17] TC85
2

1 RC9 2 H_PROCHOT#_R BR30 BP23 @ PAD 1

49,65 H_PROCHOT# PROCHOT# CFG[16] TC86
499_0402_1% BP22 @ PAD 1
DDR_PG_CTRL CFG[19] TC87
BT13 BN22 @ PAD 1
VR_SVID_ALRT#_R DDR_VTT_CNTL CFG[18] TC88
RC65 1 2 220_0402_5%
65 SVID_ALERT#
RC3 1 2 0_0402_5% VR_SVID_CLK BR27 @ PAD 1
PCI Ex p r e s s * St a t i c x 1 6 La n e Numbe r i n g Re v e r s a l .
65 SVID_CLK VR_SVID_DAT BPM#[0] TC27
RC14 1 2 0_0402_5% BT27 @ PAD 1
65 SVID_DATA BPM#[1] TC28
BM31 @ PAD 1
VCCST_PWRGD H13 BPM#[2] BT30 1
TC29 　1 = Normal operation
VCCST_PWRGD BPM#[3]
@ PAD
TC42 CFG2
RC32 1 2 0_0402_5% VCCPW RGOOD_0_R BT31 　0 = Lane reserval
16 H_CPUPW RGD BUF_CPU_RST# PROCPWRGD
14 CPU_PLTRST# RC22 1 2 0_0402_5% BP35 BT28 XDP_TDO 42
H_PM_SYNC BM34 RESET# PROC_TDO BL32
14 H_PM_SYNC H_PM_DOWN_R PM_SYNC PROC_TDI XDP_TDI 42
RC33 1 2 20_0402_1% BP31 BP28
14 H_PM_DOWN EC_PECI BT34 PM_DOWN PROC_TMS BR28
XDP_TMS 42 Re s e r ve d c o n f i gu r a t i on l a ne .
14,49 EC_PECI H_THRMTRIP#_R PECI PROC_TCK XDP_TCK 42
RC34 1 2 0_0402_5% J31
14,24 H_THRMTRIP# THERMTRIP# BP30
PROC_TRST# XDP_TRST# 42
BR33 BL30
BN1 SKTOCC# PROC_PREQ# BP27 XDP_PREQ#
XDP_PRDY#
42
42
CFG3 N/A
PROC_SELECT# PROC_PRDY#
H_CATERR# BM30
CATERR# BT25
CFG_RCOMP
eDP enabl e

2
RC176

2
5 OF 14
RC175 51_0402_1%
SKYLAKE-H-CPU_BGA1440 49.9_0402_1%
　 1 = Disabled.
+1.2V
Add RC184 HLZ SIV 0811 @ 20150527_Mount CFG4

1
RC176 to enable

1
UC1K SKYLAKE_HALO DCI function 　0 = Enable
+3VALW +3VS
1

1K_0402_5%

BGA1440
100K_0402_5%

1 PAD @ D1 BM33 @ PAD 1

100K_0402_5%
RC184

TC100 RSVD_TP_1 RSVD_TP_7 TC90

2

C 1 PAD @ E1 BL33 @ PAD 1 C

TC101 RSVD_TP_2 RSVD_TP_8 TC91
1 PAD @ E3
PCI Expr es s * Bi f ur cat i on
RC178

TC102 RSVD_TP_3
2

1 PAD @ E2 BJ14 @ PAD 1

RC177

TC103 RSVD_TP_4 RSVD_TP_9 TC92

BJ13 @ PAD 1
RSVD_TP_10 TC93
@ 1 PAD @ BR1
TC104 RSVD_TP_5 　 00 = 1 x8, 2 x4 PCI Express*
1

1
2

1 PAD BT2 BK28

B

@
TC105 RSVD_TP_6 RSVD_43 BJ28
DDR_PG_CTRL 3 1 SM_PG_CTRL BN35 RSVD_44 　 01 = reserved
E

SM_PG_CTRL 61 RSVD_23 CFG[6:5]

C

BJ18
QC1 J24 VSS_447 　10 = 2 x8 PCI Express*
MMBT3904W H_SOT323-3 H24 RSVD_24 BJ16 @ PAD 1
RSVD_25 RSVD_TP_11 TC94
2

BN33 BK16 @ PAD 1

BL34 RSVD_26 RSVD_TP_12 TC95 　 11 = 1 x16 PCI Express*
RC179 RSVD_27
10K_0402_5% N29 BK24 @ PAD 1
RSVD_28 RSVD_TP_13 TC96
@ R14
RSVD_29 RSVD_TP_14
BJ24 @ PAD 1
TC97 PEG Tr ai ni ng
1

AE29
AA14 RSVD_30 BK21
RSVD_31 RSVD_45 BJ21
A36 RSVD_46 1 = (default) PEG Train immediately
A37 RSVD_32 BT17 following RESET# deassertion.
RSVD_33 RSVD_47
RSVD_48
BR17 CFG7
CPU_TRIGIN H23
22 CPU_TRIGIN PCH_TRIGIN RC4 1 2 CPU_TRIGOUT J23 PROC_TRIGIN BK18
0 = PEG Wait for BIOS for training.
22 PCH_TRIGIN PROC_TRIGOUT VSS_448
30_0402_1% F30 BJ34 @ PAD 1
RSVD_34 RSVD_TP_15 TC98
E30 BJ33 @ PAD 1
RSVD_35 RSVD_TP_16 TC99
B30
C30 RSVD_36 Re s e r ve d c o n f i gu r a t i on l a ne .
RSVD_37 G13
RSVD_49
G3
J3 RSVD_38 RSVD_50
AJ8
BL31
CFG[19:8] N/A
VCCST RSVD_39 RSVD_51
B2
NCTF_1 B38
NCTF_2 BP1
NCTF_3
1

+3VS +3VALW BR35 BR2

B
RC75 BR31 RSVD_40 NCTF_4 C1 B

1K_0402_5% BH30 RSVD_41 NCTF_5 C38 VCCIO

RSVD_42 11 OF 14 NCTF_6
2

R292 R291
2

SKYLAKE-H-CPU_BGA1440
10K_0402_5% 10K_0402_5%
@
@
RC50 1 2 60.4_0402_1% VCCST_PW RGD
1

1
1

1
RC139 RC140 RC141 RC142 RC143 RC144
1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%
1

Q2 D @ @
@ @
2 C929 @ @

2
2

2
G 330P_0402_50V8J
2

CFG7
S 2N7002KW _SOT323-3 CFG6
3
1

Q1 D CFG1 CFG5
2 VCCST CFG4
49,65 CPUCORE_ON G Add C929 HLZ SIV 0811 CFG2
CFG0
S 2N7002KW_SOT323-3
3

1
1

1
RC57
1

1K_0402_1% RC56 RC53 RC54 RC52 RC51 RC55

@ RC146 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%
1K_0402_5% @ @ @ @
2

2
2

2
2

XDP_PREQ#

@ C120 1 2 .1U_0402_10V6-K H_PROCHOT#_R

C52 1 2 .1U_0402_10V6-K H_CPUPWRGD

@ C126 1 2 .1U_0402_10V6-K H_THRMTRIP#

A A
C127 1 2 .1U_0402_10V6-K BUF_CPU_RST#
Change C52&C127 from @ to stuff HLZ SIV 0811
@ C133 1 2 .1U_0402_10V6-K H_PM_SYNC

@ C128 1 2 .1U_0402_10V6-K CPU_TRIGIN

Reserved Cap HLZ SDV 0616

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (2/7) PM, XDP, CLK, CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 675 of
5 4 3 2 1
 5 4 3 2 1

SKYLAKE_HALO UC1A SKYLAKE_HALO UC1B

DDRA_DQ[0..63] 12 DDRB_DQ[0..63] 13
AG1 BGA1440 BR6 DDRA_DQ0 AM9 BGA1440 BT11 DDRB_DQ0
12 DDRA_CLK0 DDR0_CKP[0] DDR0_DQ[0] DDRA_DQ1 13 DDRB_CLK0 DDR1_CKP[0] DDR1_DQ[0]/DDR0_DQ[16] DDRB_DQ1
AG2 BT6 AN9 BR11
12 DDRA_CLK0# DDR0_CKN[0] DDR0_DQ[1] DDRA_DQ2 13 DDRB_CLK0# DDR1_CKN[0] DDR1_DQ[1]/DDR0_DQ[17] DDRB_DQ2
AK1 BP3 AM8 BT8
12 DDRA_CLK1# AK2 DDR0_CKN[1] DDR0_DQ[2] BR3 DDRA_DQ3 13 DDRB_CLK1# AM7 DDR1_CKN[1] DDR1_DQ[2]/DDR0_DQ[18] BR8 DDRB_DQ3
12 DDRA_CLK1 DDR0_CKP[1] DDR0_DQ[3] DDRA_DQ4 13 DDRB_CLK1 DDR1_CKP[1] DDR1_DQ[3]/DDR0_DQ[19] DDRB_DQ4
AL3 BN5 AM11 BP11
AK3 DDR0_CLKP[2] DDR0_DQ[4] BP6 DDRA_DQ5 AM10 DDR1_CLKP[2] DDR1_DQ[4]/DDR0_DQ[20] BN11 DDRB_DQ5
AL2 DDR0_CLKN[2] DDR0_DQ[5] BP2 DDRA_DQ6 AJ10 DDR1_CLKN[2] DDR1_DQ[5]/DDR0_DQ[21] BP8 DDRB_DQ6
AL1 DDR0_CLKP[3] DDR0_DQ[6] BN3 DDRA_DQ7 AJ11 DDR1_CLKP[3] DDR1_DQ[6]/DDR0_DQ[22] BN8 DDRB_DQ7
DDR0_CLKN[3] DDR0_DQ[7] BL4 DDRA_DQ8 DDR1_CLKN[3] DDR1_DQ[7]/DDR0_DQ[23] BL12 DDRB_DQ8
D
AT1 DDR0_DQ[8] BL5 DDRA_DQ9 AT8 DDR1_DQ[8]/DDR0_DQ[24] BL11 DDRB_DQ9 D
12 DDRA_CKE0 DDR0_CKE[0] DDR0_DQ[9] DDRA_DQ10 13 DDRB_CKE0 DDR1_CKE[0] DDR1_DQ[9]/DDR0_DQ[25] DDRB_DQ10
AT2 BL2 AT10 BL8
12 DDRA_CKE1 DDR0_CKE[1] DDR0_DQ[10] DDRA_DQ11 13 DDRB_CKE1 DDR1_CKE[1] DDR1_DQ[10]/DDR0_DQ[26] DDRB_DQ11
AT3 BM1 AT7 BJ8
AT5 DDR0_CKE[2] DDR0_DQ[11] BK4 DDRA_DQ12 AT11 DDR1_CKE[2] DDR1_DQ[11]/DDR0_DQ[27] BJ11 DDRB_DQ12
DDR0_CKE[3] DDR0_DQ[12] BK5 DDRA_DQ13 DDR1_CKE[3] DDR1_DQ[12]/DDR0_DQ[28] BJ10 DDRB_DQ13
AD5 DDR0_DQ[13] BK1 DDRA_DQ14 AF11 DDR1_DQ[13]/DDR0_DQ[29] BL7 DDRB_DQ14
12 DDRA_CS0# DDR0_CS#[0] DDR0_DQ[14] DDRA_DQ15 13 DDRB_CS0# DDR1_CS#[0] DDR1_DQ[14]/DDR0_DQ[30] DDRB_DQ15
AE2 BK2 AE7 BJ7
12 DDRA_CS1# DDR0_CS#[1] DDR0_DQ[15] DDRA_DQ16 13 DDRB_CS1# DDR1_CS#[1] DDR1_DQ[15]/DDR0_DQ[31] DDRB_DQ16
AD2 BG4 AF10 BG11
AE5 DDR0_CS#[2] DDR0_DQ[16]/DDR0_DQ[32] BG5 DDRA_DQ17 AE10 DDR1_CS#[2] DDR1_DQ[16]/DDR0_DQ[48] BG10 DDRB_DQ17
DDR0_CS#[3] DDR0_DQ[17]/DDR0_DQ[33] BF4 DDRA_DQ18 DDR1_CS#[3] DDR1_DQ[17]/DDR0_DQ[49] BG8 DDRB_DQ18
DDRA_ODT0 AD3 DDR0_DQ[18]/DDR0_DQ[34] BF5 DDRA_DQ19 DDRB_ODT0 AF7 DDR1_DQ[18]/DDR0_DQ[50] BF8 DDRB_DQ19
12 DDRA_ODT0 DDRA_ODT1 AE4 DDR0_ODT[0] DDR0_DQ[19]/DDR0_DQ[35] DDRA_DQ20 13 DDRB_ODT0 DDRB_ODT1 DDR1_ODT[0] DDR1_DQ[19]/DDR0_DQ[51] DDRB_DQ20
BG2 AE8 BF11
12 DDRA_ODT1 DDR0_ODT[1] DDR0_DQ[20]/DDR0_DQ[36] DDRA_DQ21 13 DDRB_ODT1 DDR1_ODT[1] DDR1_DQ[20]/DDR0_DQ[52] DDRB_DQ21
AE1 BG1 AE9 BF10
AD4 DDR0_ODT[2] DDR0_DQ[21]/DDR0_DQ[37] BF1 DDRA_DQ22 AE11 DDR1_ODT[2] DDR1_DQ[21]/DDR0_DQ[53] BG7 DDRB_DQ22
DDR0_ODT[3] DDR0_DQ[22]/DDR0_DQ[38] BF2 DDRA_DQ23 DDR1_ODT[3] DDR1_DQ[22]/DDR0_DQ[54] BF7 DDRB_DQ23
AH5 DDR0_DQ[23]/DDR0_DQ[39] BD2 DDRA_DQ24 AH10 DDR1_DQ[23]/DDR0_DQ[55] BB11 DDRB_DQ24
12 DDRA_BA0 DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_DQ[24]/DDR0_DQ[40] DDRA_DQ25 13 DDRB_MA16_RAS# DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_DQ[24]/DDR0_DQ[56] DDRB_DQ25
AH1 BD1 AH11 BC11
12 DDRA_BA1 DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_DQ[25]/DDR0_DQ[41] DDRA_DQ26 13 DDRB_MA14_W E# DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_DQ[25]/DDR0_DQ[57] DDRB_DQ26
AU1 BC4 AF8 BB8
12 DDRA_BG0 DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_DQ[26]/DDR0_DQ[42] DDRA_DQ27 13 DDRB_MA15_CAS# DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_DQ[26]/DDR0_DQ[58] DDRB_DQ27
BC5 BC8
AH4 DDR0_DQ[27]/DDR0_DQ[43] BD5 DDRA_DQ28 AH8 DDR1_DQ[27]/DDR0_DQ[59] BC10 DDRB_DQ28
12 DDRA_MA16_RAS# DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_DQ[28]/DDR0_DQ[44] DDRA_DQ29 13 DDRB_BA0 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_DQ[28]/DDR0_DQ[60] DDRB_DQ29
AG4 BD4 AH9 BB10
12 DDRA_MA14_WE# AD1 DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_DQ[29]/DDR0_DQ[45] BC1 DDRA_DQ30 13 DDRB_BA1 AR9 DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_DQ[29]/DDR0_DQ[61] BC7 DDRB_DQ30
12 DDRA_MA15_CAS# DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_DQ[30]/DDR0_DQ[46] DDRA_DQ31 13 DDRB_BG0 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_DQ[30]/DDR0_DQ[62] DDRB_DQ31
BC2 BB7
12 DDRA_MA[0..9] DDRA_MA0 DDR0_DQ[31]/DDR0_DQ[47] DDRA_DQ32 13 DDRB_MA[0..9] DDRB_MA0 DDR1_DQ[31]/DDR0_DQ[63] DDRB_DQ32
AH3 AB1 AJ9 AA11
DDRA_MA1 AP4 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_DQ[32]/DDR1_DQ[0] AB2 DDRA_DQ33 DDRB_MA1 AK6 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_DQ[32]/DDR1_DQ[16] AA10 DDRB_DQ33
DDRA_MA2 AN4 DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_DQ[33]/DDR1_DQ[1] AA4 DDRA_DQ34 DDRB_MA2 AK5 DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_DQ[33]/DDR1_DQ[17] AC11 DDRB_DQ34
DDRA_MA3 AP5 DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_DQ[34]/DDR1_DQ[2] AA5 DDRA_DQ35 DDRB_MA3 AL5 DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_DQ[34]/DDR1_DQ[18] AC10 DDRB_DQ35
DDRA_MA4 AP2 DDR0_MA[3] DDR0_DQ[35]/DDR1_DQ[3] AB5 DDRA_DQ36 DDRB_MA4 AL6 DDR1_MA[3] DDR1_DQ[35]/DDR1_DQ[19] AA7 DDRB_DQ36
DDRA_MA5 AP1 DDR0_MA[4] DDR0_DQ[36]/DDR1_DQ[4] AB4 DDRA_DQ37 DDRB_MA5 AM6 DDR1_MA[4] DDR1_DQ[36]/DDR1_DQ[20] AA8 DDRB_DQ37
DDRA_MA6 AP3 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_DQ[37]/DDR1_DQ[5] AA2 DDRA_DQ38 DDRB_MA6 AN7 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_DQ[37]/DDR1_DQ[21] AC8 DDRB_DQ38
DDRA_MA7 AN1 DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_DQ[38]/DDR1_DQ[6] AA1 DDRA_DQ39 DDRB_MA7 AN10 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_DQ[38]/DDR1_DQ[22] AC7 DDRB_DQ39
DDRA_MA8 AN3 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_DQ[39]/DDR1_DQ[7] V5 DDRA_DQ40 DDRB_MA8 AN8 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_DQ[39]/DDR1_DQ[23] W8 DDRB_DQ40
DDRA_MA9 AT4 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_DQ[40]/DDR1_DQ[8] V2 DDRA_DQ41 DDRB_MA9 AR11 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_DQ[40]/DDR1_DQ[24] W7 DDRB_DQ41
DDRA_MA10_AP AH2 DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_DQ[41]/DDR1_DQ[9] U1 DDRA_DQ42 DDRB_MA10_AP AH7 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_DQ[41]/DDR1_DQ[25] V10 DDRB_DQ42
12 DDRA_MA10_AP DDRA_MA11 DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_DQ[42]/DDR1_DQ[10] DDRA_DQ43 13 DDRB_MA10_AP DDRB_MA11 DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_DQ[42]/DDR1_DQ[26] DDRB_DQ43
AN2 U2 AN11 V11
12 DDRA_MA11 DDRA_MA12 DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_DQ[43]/DDR1_DQ[11] DDRA_DQ44 13 DDRB_MA11 DDRB_MA12 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_DQ[43]/DDR1_DQ[27] DDRB_DQ44
AU4 V1 AR10 W11
12 DDRA_MA12 DDRA_MA13 DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_DQ[44]/DDR1_DQ[12] DDRA_DQ45 13 DDRB_MA12 DDRB_MA13 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_DQ[44]/DDR1_DQ[28] DDRB_DQ45
AE3 V4 AF9 W10
12 DDRA_MA13 DDRA_BG1 DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_DQ[45]/DDR1_DQ[13] DDRA_DQ46 13 DDRB_MA13 DDRB_BG1 DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_DQ[45]/DDR1_DQ[29] DDRB_DQ46
C AU2 U5 AR7 V7 C
12 DDRA_BG1 DDRA_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_DQ[46]/DDR1_DQ[14] DDRA_DQ47 13 DDRB_BG1 DDRB_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_DQ[46]/DDR1_DQ[30] DDRB_DQ47
AU3 U4 AT9 V8
12 DDRA_ACT# DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_DQ[47]/DDR1_DQ[15] DDRA_DQ48 13 DDRB_ACT# DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_DQ[47]/DDR1_DQ[31] DDRB_DQ48
R2 R11
DDRA_PARITY AG3 DDR0_DQ[48]/DDR1_DQ[32] P5 DDRA_DQ49 DDRB_PARITY AJ7 DDR1_DQ[48] P11 DDRB_DQ49
12 DDRA_PARITY DDRA_ALERT# DDR0_PAR DDR0_DQ[49]/DDR1_DQ[33] DDRA_DQ50 13 DDRB_PARITY DDRB_ALERT# DDR1_PAR DDR1_DQ[49] DDRB_DQ50
AU5 R4 AR8 P7
12 DDRA_ALERT# DDR0_ALERT# DDR0_DQ[50]/DDR1_DQ[34] DDRA_DQ51 13 DDRB_ALERT# DDR1_ALERT# DDR1_DQ[50] DDRB_DQ51
P4 R8
DDR0_DQ[51]/DDR1_DQ[35] R5 DDRA_DQ52 DDR1_DQ[51] R10 DDRB_DQ52
DDRA_DQS#0 BR5 DDR0_DQ[52]/DDR1_DQ[36] P2 DDRA_DQ53 13 DDRB_DQS#[0..7] DDRB_DQS#0 BP9 DDR1_DQ[52] P10 DDRB_DQ53
DDRA_DQS#1 BL3 DDR0_DQSN[0] DDR0_DQ[53]/DDR1_DQ[37] R1 DDRA_DQ54 DDRB_DQS#1 BL9 DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQ[53] R7 DDRB_DQ54
DDRA_DQS#2 BG3 DDR0_DQSN[1] DDR0_DQ[54]/DDR1_DQ[38] P1 DDRA_DQ55 DDRB_DQS#2 BG9 DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQ[54] P8 DDRB_DQ55
DDRA_DQS#3 BD3 DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQ[55]/DDR1_DQ[39] M4 DDRA_DQ56 DDRB_DQS#3 BC9 DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[55] L11 DDRB_DQ56
DDRA_DQS4 AB3 DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQ[56]/DDR1_DQ[40] M1 DDRA_DQ57 DDRB_DQS#4 AC9 DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[56] M11 DDRB_DQ57
DDRA_DQS5 V3 DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQ[57]/DDR1_DQ[41] L4 DDRA_DQ58 DDRB_DQS#5 W9 DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQ[57] L7 DDRB_DQ58
DDRA_DQS6 R3 DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQ[58]/DDR1_DQ[42] L2 DDRA_DQ59 DDRB_DQS#6 R9 DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQ[58] M8 DDRB_DQ59
DDRA_DQS7 M3 DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQ[59]/DDR1_DQ[43] M5 DDRA_DQ60 DDRB_DQS#7 M9 DDR1_DQSN[6] DDR1_DQ[59] L10 DDRB_DQ60
DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_DQ[60]/DDR1_DQ[44] M2 DDRA_DQ61 DDR1_DQSN[7] DDR1_DQ[60] M10 DDRB_DQ61
DDRA_DQS0 DDR0_DQ[61]/DDR1_DQ[45] DDRA_DQ62 13 DDRB_DQS[0..7] DDRB_DQS0 DDR1_DQ[61] DDRB_DQ62
BP5 L5 BR9 M7
DDRA_DQS1 BK3 DDR0_DQSP[0] DDR0_DQ[62]/DDR1_DQ[46] L1 DDRA_DQ63 DDRB_DQS1 BJ9 DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQ[62] L8 DDRB_DQ63
DDRA_DQS2 BF3 DDR0_DQSP[1] DDR0_DQ[63]/DDR1_DQ[47] DDRB_DQS2 BF9 DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQ[63]
DDRA_DQS3 BC3 DDR0_DQSP[2]/DDR0_DQSP[4] BA2 DDRB_DQS3 BB9 DDR1_DQSP[2]/DDR0_DQSP[6] AW11
DDRA_DQS#4 AA3 DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_ECC[0] BA1 DDRB_DQS4 AA9 DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_ECC[0] AY11
DDRA_DQS#5 U3 DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_ECC[1] AY4 DDRB_DQS5 V9 DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_ECC[1] AY8
DDRA_DQS#6 P3 DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_ECC[2] AY5 DDRB_DQS6 P9 DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_ECC[2] AW8
DDRA_DQS#7 L3 DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_ECC[3] BA5 DDRB_DQS7 L9 DDR1_DQSP[6] DDR1_ECC[3] AY10
DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_ECC[4] BA4 DDR1_DQSP[7] DDR1_ECC[4] AW10
AY3 DDR0_ECC[5] AY1 AW9 DDR1_ECC[5] AY7
BA3 DDR0_DQSP[8] DDR0_ECC[6] AY2 AY9 DDR1_DQSP[8] DDR1_ECC[6] AW7
DDR0_DQSN[8] DDR0_ECC[7] DDR1_DQSN[8] DDR1_ECC[7]

DDRA_DQS#[0..7] 12 DDR CHANNEL B

DDRA_DQS[0..7] 12
DDR CHANNEL RC1471 2 0_0402_5% +V_DDR_REFA_R BN13 G1 SM_RCOMP0
A +VREF_CA_DIMMA_R DDR_VREF_CA DDR_RCOMP[0]
PAD @ TC109 1 +VREF_DQ_DIMM_R RC36 1 2 0_0402_5% @ +V_DDR_REF_R BP13 H1 SM_RCOMP1
1 OF 14 RC37 1 2 0_0402_5% +V_DDR_REFB_R BR13 DDR0_VREF_DQ 2 OF 14 DDR_RCOMP[1] J2 SM_RCOMP2
+VREF_DQ_DIMMB_R DDR1_VREF_DQ DDR_RCOMP[2]
SKYLAKE-H-CPU_BGA1440 CAD Note: SKYLAKE-H-CPU_BGA1440
B @ Trace width= 20 mil, Spcing=20 mils @ B

DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A

DDR0_VREF_DQ : NC
DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B
DDR4 COMPENSATION SIGNALS
SM_RCOMP0 RC5 1 2 121_0402_1%

SM_RCOMP1 RC6 1 2 75_0402_1%

SM_RCOMP2 RC8 1 2 100_0402_1%

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (3/7) DDRVI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 775 of
5 4 3 2 1
 5 4 3 2 1

UC1D SKYLAKE_HALO

HDMI_TX2+ K36 BGA1440 D29 CPU_EDP_TX0+

36 HDMI_TX2+ HDMI_TX2- DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX0- CPU_EDP_TX0+ 35
HDMI D2 K37 E29
36 HDMI_TX2- HDMI_TX1+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX1+ CPU_EDP_TX0- 35
D J35 F28 D
36 HDMI_TX1+ HDMI_TX1- DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1- CPU_EDP_TX1+ 35
HDMI D1 36 HDMI_TX1- HDMI_TX0+
J34
DDI1_TXN[1] EDP_TXN[1]
E28
CPU_EDP_TX1- 35
H37 B29
36 HDMI_TX0+ HDMI_TX0- DDI1_TXP[2] EDP_TXN[2]
HDMI D0 36 HDMI_TX0- HDMI_TXC+
H36
DDI1_TXN[2] EDP_TXP[2]
A29
Delete eDP Lane2&3
J37 B28
HDMI CLK
36
36
HDMI_TXC+
HDMI_TXC-
HDMI_TXC- J38 DDI1_TXP[3]
DDI1_TXN[3]
EDP_TXN[3]
EDP_TXP[3]
C28 HLZ SDV 20160510
D27 C26 CPU_EDP_AUX
DDI1_AUXP EDP_AUXP CPU_EDP_AUX# CPU_EDP_AUX 35
E27 B26
Different to Y710 DDI1_AUXN EDP_AUXN CPU_EDP_AUX# 35
HLZ SDV 20160510 37 TYPE-C_DP_TXP0
TYPE-C_DP_TXP0 H34
DDI2_TXP[0]
TYPE-C_DP_TXN0 H33
37 TYPE-C_DP_TXN0 TYPE-C_DP_TXP1 DDI2_TXN[0] VCCIO
F37 A33
37 TYPE-C_DP_TXP1 TYPE-C_DP_TXN1 DDI2_TXP[1] EDP_DISP_UTIL
G38
37 TYPE-C_DP_TXN1 TYPE-C_DP_TXP2 DDI2_TXN[1]
F34
37 TYPE-C_DP_TXP2 TYPE-C_DP_TXN2 DDI2_TXP[2] EDP_COMP
Type C DP F35 D37 24.9_0402_1% 2 1 RC49
37 TYPE-C_DP_TXN2 TYPE-C_DP_TXP3 DDI2_TXN[2] EDP_RCOMP
E37
37 TYPE-C_DP_TXP3 TYPE-C_DP_TXN3 DDI2_TXP[3]
E36
37 TYPE-C_DP_TXN3 DDI2_TXN[3]
TYPE-C_DP_AUXP F26
COMPENSATION PU FOR eDP
37 TYPE-C_DP_AUXP TYPE-C_DP_AUXN DDI2_AUXP
E26
37 TYPE-C_DP_AUXN DDI2_AUXN CAD Note:Trace width=20 mils ,Spacing=25mil,
C34
DDI3_TXP[0]
Max length=100 mils.
D34
B36 DDI3_TXN[0]
B34 DDI3_TXP[1]
F33 DDI3_TXN[1]
E33 DDI3_TXP[2]
C33 DDI3_TXN[2]
B33 DDI3_TXP[3]
DDI3_TXN[3] G27 PROC_AUDIO_CLK_CPU
PROC_AUDIO_CLK PROC_AUDIO_CLK_CPU 16
A27 G25 PROC_AUDIO_SDO_CPU PROC_AUDIO_SDO_CPU 16
C B27 DDI3_AUXP PROC_AUDIO_SDI G29 PROC_AUDIO_SDI_CPU_R 20_0402_1% 1 2 RC180 C
DDI3_AUXN PROC_AUDIO_SDO PROC_AUDIO_SDI_CPU 16
4 OF 14
Place near CPU.
SKYLAKE-H-CPU_BGA1440 Need create 5% P/N
@

1
RH762
33_0402_5%
@

2
PROC_AUDIO_SDO_CPU CH14 1 2 10P_0402_50V8J @
1
CH264
10P_0402_50V8J
2 @
Reserved Cap HLZ SDV 0616

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (4/7) eDP, DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 875 of
5 4 3 2 1
 5 4 3 2 1

MAX 68A VCCGFXCORE

UC1N SKYLAKE_HALO
VCCCPUCORE UC1G SKYLAKE_HALO VCCCPUCORE VCCGFXCORE
AJ29 BGA1440
BGA1440 AJ30 VCCGT_ 109
AA13 V32 AJ31 VCCGT_ 110 AF29
AA31 VCC_1 VCC_64 V33 AJ32 VCCGT_ 111 VCCGTX_1 AF30
AA32 VCC_2 VCC_65 V34 AJ33 VCCGT_ 112 VCCGTX_2 AF31
AA33 VCC_3 VCC_66 V35 AJ34 VCCGT_ 113 VCCGTX_3 AF32
AA34
AA35
VCC_4
VCC_5
VCC_67
VCC_68
V36
V37
AJ35
AJ36
VCCGT_ 114
VCCGT_ 115
VCCGTX_4
VCCGTX_5
AF33
AF34
MAX 55A
AA36 VCC_6 VCC_69 V38 AK31 VCCGT_ 116 VCCGTX_6 AG13
AA37 VCC_7 VCC_70 W13 AK32 VCCGT_ 117 VCCGTX_7 AG14
AA38 VCC_8 VCC_71 W14 AK33 VCCGT_ 118 VCCGTX_8 AG31 VCCGFXCORE VCCGFXCORE
AB29 VCC_9 VCC_72 W29 AK34 VCCGT_ 119 VCCGTX_9 AG32
VCC_10 VCC_73 VCCGT_ 120 VCCGTX_10 CRB place to CPU
AB30 W30 AK35 AG33
AB31 VCC_11 VCC_74 W31 AK36 VCCGT_ 121 VCCGTX_11 AG34 VCCGFXCORE

VCCGT_SENSE
UC1H SKYLAKE_HALO
AB32 VCC_12 VCC_75 W32 AK37 VCCGT_ 122 VCCGTX_12 AG35
AB35 VCC_13 VCC_76 W35 AK38 VCCGT_ 123 VCCGTX_13 AG36 BG34 BGA1440 AV29
VCC_14 VCC_77 VCCGT_ 124 VCCGTX_14 VCCGT_1 VCCGT_55

1
AB36 W36 AL13 AH13 BG35 AV30 RC60
AB37 VCC_15 VCC_78 W37 AL29 VCCGT_ 125 VCCGTX_15 AH14 BG36 VCCGT_2 VCCGT_56 AV31 100_0402_1%
AB38 VCC_16 VCC_79 W38 AL30 VCCGT_ 126 VCCGTX_16 AH29 BH33 VCCGT_3 VCCGT_57 AV32
AC13 VCC_17 VCC_80 Y 29 AL31 VCCGT_ 127 VCCGTX_17 AH30 BH34 VCCGT_4 VCCGT_58 AV33
D AC14 VCC_18 VCC_81 Y 30 AL32 VCCGT_ 128 VCCGTX_18 AH31 BH35 VCCGT_5 VCCGT_59 AV34 D
VCC_19 VCC_82 VCCGT_ 129 VCCGTX_19 VCCGT_6 VCCGT_60

2
AC29 Y 31 AL35 AH32 BH36 AV35 RC40 1 2 0_0402_5% VCCGT_SENSE_R
VCC_20 VCC_83 VCCGT_ 130 VCCGTX_20 VCCGT_7 VCCGT_61 65 VCCGT_SENSE
AC30 Y 32 AL36 AJ13 BH37 AV36
AC31 VCC_21 VCC_84 Y 33 AL37 VCCGT_ 131 VCCGTX_21 AJ14 BH38 VCCGT_8 VCCGT_62 AW14 RC41 1 2 0_0402_5% VSSGT_SENSE_R
VCC_22 VCC_85 VCCGT_ 132 VCCGTX_22 VCCGT_9 VCCGT_63 65 VSSGT_SENSE
AC32 Y 34 AL38 BJ37 AW31
VCC_23 VCC_86 VCCGT_ 133 VCCGT_10 VCCGT_64

1
AC33 Y 35 AM 13 BJ38 AW32
AC34 VCC_24 VCC_87 Y 36 AM 14 VCCGT_ 134 BL36 VCCGT_11 VCCGT_65 AW33
AC35 VCC_25 VCC_88 L 14 AM 29 VCCGT_ 135 BL37 VCCGT_12 VCCGT_66 AW34 RC63
AC36 VCC_26 VCC_89 P29 AM 30 VCCGT_ 136 BM36 VCCGT_13 VCCGT_67 AW35 100_0402_1%
AD13 VCC_27 VCC_90 P30 AM 31 VCCGT_ 137 BM37 VCCGT_14 VCCGT_68 AW36
VCC_28 VCC_91 VCCGT_ 138 VCCGT_15 VCCGT_69

2
AD14 P31 AM 32 BN36 AW37
AD31 VCC_29 VCC_92 P32 AM 33 VCCGT_ 139 BN37 VCCGT_16 VCCGT_70 AW38
AD32 VCC_30 VCC_93 P33 AM 34 VCCGT_ 140 BN38 VCCGT_17 VCCGT_71 AY 29
AD33 VCC_31 VCC_94 P34 AM 35 VCCGT_ 141 BP37 VCCGT_18 VCCGT_72 AY 30
AD34 VCC_32 VCC_95 P35 AM 36 VCCGT_ 142 BP38 VCCGT_19 VCCGT_73 AY 31
AD35 VCC_33 VCC_96 P36 AN13 VCCGT_ 143 BR37 VCCGT_20 VCCGT_74 AY 32
AD36 VCC_34 VCC_97 R13 AN14 VCCGT_ 144 BT37 VCCGT_21 VCCGT_75 AY 35
AD37 VCC_35 VCC_98 R31 AN31 VCCGT_ 145 BE38 VCCGT_22 VCCGT_76 AY 36
AD38 VCC_36 VCC_99 R32 AN32 VCCGT_ 146 BF13 VCCGT_23 VCCGT_77 AY 37
AE13 VCC_37 VCC_100 R33 AN33 VCCGT_ 147 BF14 VCCGT_24 VCCGT_78 AY 38
AE14 VCC_38 VCC_101 R34 AN34 VCCGT_ 148 BF29 VCCGT_25 VCCGT_79 BA13
AE30 VCC_39 VCC_102 R35 AN35 VCCGT_ 149 BF30 VCCGT_26 VCCGT_80 BA14
AE31 VCC_40 VCC_103 R36 AN36 VCCGT_ 150 BF31 VCCGT_27 VCCGT_81 BA29
AE32 VCC_41 VCC_104 R37 AN37 VCCGT_ 151 BF32 VCCGT_28 VCCGT_82 BA30
AE35 VCC_42 VCC_105 R38 AN38 VCCGT_ 152 BF35 VCCGT_29 VCCGT_83 BA31 CRB place to CPU
AE36 VCC_43 VCC_106 T29 AP13 VCCGT_ 153 BF36 VCCGT_30 VCCGT_84 BA32
AE37 VCC_44 VCC_107 T30 AP14 VCCGT_ 154 BF37 VCCGT_31 VCCGT_85 BA33 VCCCPUCORE
AE38 VCC_45 VCC_108 T31 AP29 VCCGT_ 155 BF38 VCCGT_32 VCCGT_86 BA34
AF35
AF36
VCC_46
VCC_47
VCC_48
VCC_109
VCC_110
VCC_111
T32
T35
AP30
AP31
VCCGT_ 156
VCCGT_ 157
VCCGT_ 158
BG29
BG30
VCCGT_33
VCCGT_34
VCCGT_35
VCCGT_87
VCCGT_88
VCCGT_89
BA35
BA36
VCC_SENSE

1
AF37 T36 AP32 BG31 BB13 RC59
AF38 VCC_49 VCC_112 T37 AP35 VCCGT_ 159 BG32 VCCGT_36 VCCGT_90 BB14 100_0402_1%
K13 VCC_50 VCC_113 T38 AP36 VCCGT_ 160 BG33 VCCGT_37 VCCGT_91 BB31
K14 VCC_51 VCC_114 U29 AP37 VCCGT_ 161 BC36 VCCGT_38 VCCGT_92 BB32
L13 VCC_52 VCC_115 U30 AP38 VCCGT_ 162 BC37 VCCGT_39 VCCGT_93 BB33
VCC_53 VCC_116 VCCGT_ 163 VCCGT_40 VCCGT_94 CAD Note: RC38 SHOULD BE PLACED CLOSE TO CPU

2
N13 U31 AR29 BC38 BB34
N14 VCC_54 VCC_117 U32 AR30 VCCGT_ 164 BD13 VCCGT_41 VCCGT_95 BB35
N30 VCC_55 VCC_118 U33 AR31 VCCGT_ 165 BD14 VCCGT_42 VCCGT_96 BB36 RC38 1 2 0_0402_5% VCCSENSE_R
VCC_56 VCC_119 VCCGT_ 166 VCCGT_43 VCCGT_97 65 VCCCORE_SENSE
N31 U34 AR32 BD29 BB37
N32 VCC_57 VCC_120 U35 AR33 VCCGT_ 167 AH38 VCCGT_SENSE_R BD30 VCCGT_44 VCCGT_98 BB38
N35 VCC_58 VCC_121 U36 AR34 VCCGT_ 168 VCCGT_SENSE AH35 PAD 1 BD31 VCCGT_45 VCCGT_99 BC29
N36 VCC_59 VCC_122 V13 AR35 VCCGT_ 169 VSSGTX_SENSE AH37
@
VSSGT_SENSE_R TC60
BD32 VCCGT_46 VCCGT_100 BC30
CAD Note: RC39 SHOULD BE PLACED CLOSE TO CPU
N37 VCC_60 VCC_123 V14 AR36 VCCGT_ 170 VSSGT_SENSE AH36 @ PAD 1 BD33 VCCGT_47 VCCGT_101 BC31
VCC_61 VCC_124 VCCGT_ 171 VCCGTX_SENSE TC62 VCCGT_48 VCCGT_102 VSSSENSE_R
N38 V31 AT14 BD34 BC32 65 VSSCORE_SENSE RC39 1 2 0_0402_5%
P13 VCC_62 VCC_125 P14 AT31 VCCGT_ 172 BD35 VCCGT_49 VCCGT_103 BC35
VCC_63 VCC_126 AT32 VCCGT_ 173 BD36 VCCGT_50 VCCGT_104 BE33
VCCGT_ 174 VCCGT_51 VCCGT_105

1
AT33 BE31 BE34
AT34 VCCGT_ 175 BE32 VCCGT_52 VCCGT_106 BE35
AG37 VCCSENSE_R AT35 VCCGT_ 176 BE37 VCCGT_53 VCCGT_107 BE36 RC62
VCC_SENSE AG38 VSSSENSE_R AT36 VCCGT_ 177 VCCGT_54 VCCGT_108 100_0402_1%
C VSS_SENSE AT37 VCCGT_ 178 8 OF 14 C
VCCGT_ 179

2
AT38
7 OF 14 AU14 VCCGT_ 180 SKYLAKE-H-CPU_BGA1440
AU29 VCCGT_ 181
VCCGT_ 182 @
SKYLAKE-H-CPU_BGA1440 AU30
AU31 VCCGT_ 183
@ VCCGT_ 184
AU32
AU35 VCCGT_ 185
AU36 VCCGT_ 186
AU37 VCCGT_ 187
AU38 VCCGT_ 188
VCCGT_ 189 14 OF 14

SKYLAKE-H-CPU_BGA1440
@

SDV Cost down list:

10U 10Pcs
SIV Cost down list:
10U 9Pcs 10uF 35pcs
VCCGFXCORE 1U 28Pcs 1U 19Pcs

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CC108

CC107

CC110

CC106

CC104

CC102

CC103

CC109

CC111

CC119

CC116

CC120

CC115

CC112

CC113

CC118

CC128

CC123

CC127

CC125

CC121

CC124

CC131

CC134

CC132
B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @2 2 2 2 2 2 2 B
@ @ @ @ @ @ @ @
Cost down list:
VCCCPUCORE 10U 5Pcs
1U 19Pcs
10uF 28pcs
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD75 CD76
CC62

CC80

CC79

CC82

CC78

CC77

CC76

CC74

CC75

CC81

CC83

CC91

CC88

CC92

CC89

CC86

CC87

CC84

CC85

CC90

CC101

CC173

CC100

CC99

CC94

CC97

CC93

CC95

33P_0402_50V8J 33P_0402_50V8J
RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
@ @ @ @ @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD77 CD78

CH157

CH158

CH159

CH160

CH161

CH164

CH165

CH167

CH168

CH170

CH172

CH173

CH180

CH182

CH184
33P_0402_50V8J 33P_0402_50V8J
RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Near CPU @ @ @ @ @ @ @ @ @ @ @

Near CPU
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH93

CH94

CH95

CH96

CH97

CH98

CH99

CH100

CH101

CH102

CH103

CH104

CH105

CH106

CH107

CH108

CH109

CH110

CH111

CH112

CH113

CH114

CH115

CH116

CH117

CH118

CH119

CH120

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ @ @ @ @ @ @ @ @

CH185

CH187

CH186

CH188

CH191

CH190

CH192

CH195

CH194

CH197

CH196

CH201

CH200

CH203

CH204

CH202

CH206

CH205

CH208

CH210
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ @ @ @ @ @ @

1uF 68pcs
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH121

CH122

CH123

CH124

CH125

CH126

CH127

CH128

CH129

CH130

CH131

CH132

CH133

CH134

CH135

CH136

CH137

CH138

CH140

CH139

CH142

CH141

CH144

CH143

CH145

CH147

CH146

CH148

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
CH215

CH213

CH218

CH220

CH235
@ @ @ @ @ @ @
A A
2 2 2 2 2
@

1uF 64pcs Change CH109&CH110&CH135&CH140 from stuff to@

Change CH93&CH122&CH105&CH150 from @ to stuff
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1
HLZ SIV 0811
CH151

CH149

CH153

CH150

CH152

CH154

CH155

CH156

2 2 2 2 2 2 2 2
@ @
Security Classification LC Future Center Secret Data Title
Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: F riday, Novem ber 25, 2016 Sheet 975 of
5 4 3 2 1
 5 4 3 2 1

SKYLAKE_HALO

10uF 7pcs
VCCSA UC1J

VCCSA +1.2V BGA1440

MAX 11.1A UC1I SKYLAKE_HALO MAX 2.8A BJ17
VCCOPC_1
BJ19
VCCOPC_2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
J30 BGA1440 AA6 BJ20
K29 VCCSA_1 VDDQ_1 AE12 BK17 VCCOPC_3
VCCSA_2 VDDQ_2 1 1 1 1 1 1 1 1 1 VCCOPC_4
K30 AF5 CD79 CD80 BK19
K31 VCCSA_3 VDDQ_3 AF6 BK20 VCCOPC_5

CC136

CC141

CC140

CC142

CC139

CC138

CC137
33P_0402_50V8J 33P_0402_50V8J
K32 VCCSA_4 VDDQ_4 AG5 +1.2V RF_NS@ RF_NS@ BL16 VCCOPC_6
K33 VCCSA_5 VDDQ_5 AG9 2 2 2 2 2 2 2 2 2 BL17 VCCOPC_7
K34 VCCSA_6 VDDQ_6 AJ12 BL18 VCCOPC_8
K35 VCCSA_7 VDDQ_7 AL11 BL19 VCCOPC_9

10U_0603_6.3V6M
L31 VCCSA_8 VDDQ_8 AP6 BL20 VCCOPC_10
VCCSA_9 VDDQ_9 1 VCCOPC_11
L32 AP7 BL21
VCCSA_10 VDDQ_10 VCCOPC_12

CC172
L35 AR12 BM17
L36 VCCSA_11 VDDQ_11 AR6 BN17 VCCOPC_13

D
L37
L38
VCCSA_12
VCCSA_13
VCCSA_14
VDDQ_12
VDDQ_13
VDDQ_14
AT12
AW6
2
Near CPU BJ23
VCCOPC_14

RSVD_1
D

M29 AY6 BJ26

VCCSA_15 VDDQ_15 RSVD_2

1U_0402_6.3V6K

1U_0402_6.3V6K
M30 J5 1 1 BJ27
M31 VCCSA_16 VDDQ_16 J6 BK23 RSVD_3

1U_0402_6.3V6K
VCCSA_17 VDDQ_17 1 RSVD_4
M32 K12 BK26

CH222

CH223
M33 VCCSA_18 VDDQ_18 K6 BK27 RSVD_5

CH221
MAX 5.5A M34
M35
VCCSA_19
VCCSA_20
VCCSA_21
VDDQ_19
VDDQ_20
VDDQ_21
L12
L6
2
2
2
1uF 3pcs BL23
BL24
RSVD_6
RSVD_7
RSVD_8
VCCIO M36 R6 BL25
VCCSA_22 VDDQ_22 T6 BL26 RSVD_9
VDDQ_23 W6 BL27 RSVD_10
AG12 VDDQ_24 BL28 RSVD_11
G15 VCCIO_1 Y12 +1.2V BM24 RSVD_12
G17 VCCIO_2 VDDQC RSVD_13
G19 VCCIO_3 BH13 130mA
G21 VCCIO_4 VCCPLL_OC_1 G11 1 PAD BL15
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@
VCCIO_5 VCCPLL_OC_2 TC56 VCCOPC_SENSE
1 1 1 H15 1 PAD @ BM16
VCCIO_6 VCCST TC58 VSSOPC_SENSE
H16
H17 VCCIO_7 H30 BL22
CC147

CC148

CC149

1U_0402_6.3V6K

1U_0402_6.3V6K
60mA 1 1
H19 VCCIO_8 VCCST VCCSTG BM22 RSVD_14
2 2 2 VCCIO_9 RSVD_15

CC150

CH252
H20 H29 20mA
H21 VCCIO_10 VCCSTG_1
VCCIO_11 2 2

1U_0402_6.3V6K

1U_0402_6.3V6K
H26 G30 1 1 BP15
H27 VCCIO_12 VCCSTG_2 VCCST BR15 VCCEOPIO_1

1U_0402_6.3V6K
VCCIO_13 1 VCCEOPIO_2

CH249

CH250
J15 H28 150mA BT15
J16 VCCIO_14 VCCPLL_1 J28 VCCEOPIO_3

CH242
J17 VCCIO_15 VCCPLL_2 2 2 BP16
J19 VCCIO_16 2 BR16 RSVD_16
J20 VCCIO_17 M38 VCCSA_SENSE_R BT16 RSVD_17
J21 VCCIO_18 VCCSA_SENSE M37 VSSSA_SENSE_R RSVD_18
J26 VCCIO_19 VSSSA_SENSE
J27 VCCIO_20 H14 VCCIO_SENSE_R 1 PAD BN15

1U_0402_6.3V6K
1 @
VCCIO_21 VCCIO_SENSE TC75 VCCEOPIO_SENSE
J14 VSSIO_SENSE_R 1 PAD @ BM15
VSSIO_SENSE TC74 VSSEOPIO_SENSE

CH251
BP17
2 BN16 RSVD_19
RSVD_20
C C
1 PAD @ BM14
TC45 VCC_OPC_1P8_1
9 OF 14 1 PAD @ BL14
TC76 VCC_OPC_1P8_2
SKYLAKE-H-CPU_BGA1440 BJ35
BJ36 RSVD_21
@ RSVD_22

1 PAD @ AT13
TC47 1 PAD AW13 ZVM#
@
TC48 MSM#
+1.2V
VDDQ DECOUPLING 1 PAD @ AU13
TC49 ZVM2#
1 PAD @ AY13
TC51 MSM2#
1 PAD @ BT29
TC54 OPC_RCOMP
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 PAD @ BR25
TC53 OPCE_RCOMP
1 1 1 1 1 1 1 1 1 1 1 PAD @ BP25
TC52 OPCE_RCOMP2
CC51

CC52

CC53

CC54

CC55

CC56

CC57

CC58

CC59

CC60
10 OF 14
2 2 2 2 2 2 2 2 2 2 SKYLAKE-H-CPU_BGA1440
@
CC63
22U_0603_6.3V6-M

22U_0603_6.3V6-M
CC64
22U_0603_6.3V6-M

CC65
22U_0603_6.3V6-M

CC66

1 1 1 1

2 2 2 2

B B

CRB place to CPU CRB place to CPU

VCCSA VCCIO
VCCSA_SENSE VCCIO_SENSE
1

RC151 RC155
100_0402_1% 100_0402_1%

0_0402_5%
2

RC150 1 2 0_0402_5% VCCSA_SENSE_R RC154 1 @ 2 VCCIO_SENSE_R

65 VCCSA_SENSE 64 VCC_IO_SEN
RC148 1 2 0_0402_5% VSSSA_SENSE_R 1 @ 2 VSSIO_SENSE_R
65 VSSSA_SENSE 64 VSS_IO_SEN
RC152
1

0_0402_5%

RC149 RC153
For Merge
100_0402_1% 100_0402_1%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (6/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 10 of 75
5 4 3 2 1
 5 4 3 2 1

UC1M SKYLAKE_HALO
UC1F SKYLAKE_HALO UC1L SKYLAKE_HALO
D D
BB4 BGA1440 AK30
Y38 BGA1440 K1 C17 BGA1440 C25 BB3 VSS_300 VSS_378 AK29
Y37 VSS_1 VSS_78 J36 C13 VSS_154 VSS_239 C23 BB2 VSS_301 VSS_379 AK4
Y14 VSS_2 VSS_79 J33 C9 VSS_155 VSS_240 C21 BB1 VSS_302 VSS_380 AJ38
Y13 VSS_3 VSS_80 J32 BT32 VSS_156 VSS_241 C19 BA38 VSS_303 VSS_381 AJ37
Y11 VSS_4 VSS_81 J25 BT26 VSS_157 VSS_242 C15 BA37 VSS_304 VSS_382 AJ6
Y10 VSS_5 VSS_82 J22 BT24 VSS_158 VSS_243 C11 BA12 VSS_305 VSS_383 AJ5
Y9 VSS_6 VSS_83 J18 BT21 VSS_159 VSS_244 C8 BA11 VSS_306 VSS_384 AJ4
Y8 VSS_7 VSS_84 J10 BT18 VSS_160 VSS_245 C5 BA10 VSS_307 VSS_385 AJ3
Y7 VSS_8 VSS_85 J7 BT14 VSS_161 VSS_246 BM29 BA9 VSS_308 VSS_386 AJ2
W34 VSS_9 VSS_86 J4 BT12 VSS_162 VSS_247 BM25 BA8 VSS_309 VSS_387 AJ1
W33 VSS_10 VSS_87 H35 BT9 VSS_163 VSS_248 BM18 BA7 VSS_310 VSS_388 AH34
W12 VSS_11 VSS_88 H32 BT5 VSS_164 VSS_249 BM11 BA6 VSS_311 VSS_389 AH33
W5 VSS_12 VSS_89 H25 BR36 VSS_165 VSS_250 BM8 B9 VSS_312 VSS_390 AH12
W4 VSS_13 VSS_90 H22 BR34 VSS_166 VSS_251 BM7 AY34 VSS_313 VSS_391 AH6
W3 VSS_14 VSS_91 H18 BR29 VSS_167 VSS_252 BM5 AY33 VSS_314 VSS_392 AG30
W2 VSS_15 VSS_92 H12 BR26 VSS_168 VSS_253 BM3 AY14 VSS_315 VSS_393 AG29
W1 VSS_16 VSS_93 H11 BR24 VSS_169 VSS_254 BL38 AY12 VSS_316 VSS_394 AG11
V30 VSS_17 VSS_94 G28 BR21 VSS_170 VSS_255 BL35 AW30 VSS_317 VSS_395 AG10
V29 VSS_18 VSS_95 G26 BR18 VSS_171 VSS_256 BL13 AW29 VSS_318 VSS_396 AG8
V12 VSS_19 VSS_96 G24 BR14 VSS_172 VSS_257 BL6 AW12 VSS_319 VSS_397 AG7
V6 VSS_20 VSS_97 G23 BR12 VSS_173 VSS_258 BK25 AW5 VSS_320 VSS_398 AG6
U38 VSS_21 VSS_98 G22 BR7 VSS_174 VSS_259 BK22 AW4 VSS_321 VSS_399 AF14
U37 VSS_153 VSS_99 G20 BP34 VSS_175 VSS_260 BK13 AW3 VSS_322 VSS_400 AF13
U6 VSS_22 VSS_100 G18 BP33 VSS_176 VSS_261 BK6 AW2 VSS_323 VSS_401 AF12
T34 VSS_23 VSS_101 G16 BP29 VSS_177 VSS_262 BJ30 AW1 VSS_324 VSS_402 AF4
T33 VSS_24 VSS_102 G14 BP26 VSS_178 VSS_263 BJ29 AV38 VSS_325 VSS_403 AF3
T14 VSS_25 VSS_103 G12 BP24 VSS_179 VSS_264 BJ15 AV37 VSS_326 VSS_404 AF2
T13 VSS_26 VSS_104 G10 BP21 VSS_180 VSS_265 BJ12 AU34 VSS_327 VSS_405 AF1
T12 VSS_27 VSS_105 G9 BP18 VSS_181 VSS_266 BH11 AU33 VSS_328 VSS_406 AE34
T11 VSS_28 VSS_106 G8 BP14 VSS_182 VSS_267 BH10 AU12 VSS_329 VSS_407 AE33
T10 VSS_29 VSS_107 G6 BP12 VSS_183 VSS_268 BH7 AU11 VSS_330 VSS_408 AE6
T9 VSS_30 VSS_108 G5 BP7 VSS_184 VSS_269 BH6 AU10 VSS_331 VSS_409 AD30
T8 VSS_31 VSS_109 G4 BN34 VSS_185 VSS_270 BH3 AU9 VSS_332 VSS_410 AD29
T7 VSS_32 VSS_110 F36 BN31 VSS_186 VSS_271 BH2 AU8 VSS_333 VSS_411 AD12
T5 VSS_33 VSS_111 F31 BN30 VSS_187 VSS_272 BG37 AU7 VSS_334 VSS_412 AD11
T4 VSS_34 VSS_112 F29 BN29 VSS_188 VSS_273 BG14 AU6 VSS_335 VSS_413 AD10
T3 VSS_35 VSS_113 F27 BN24 VSS_189 VSS_274 BG6 AT30 VSS_336 VSS_414 AD9
C C
T2 VSS_36 VSS_114 F25 BN21 VSS_190 VSS_275 BF34 AT29 VSS_337 VSS_415 AD8
T1 VSS_37 VSS_115 F23 BN20 VSS_191 VSS_276 BF6 AT6 VSS_338 VSS_416 AD7
R30 VSS_38 VSS_116 F21 BN19 VSS_192 VSS_277 BE30 AR38 VSS_339 VSS_417 AD6
R29 VSS_39 VSS_117 F19 BN18 VSS_193 VSS_278 BE5 AR37 VSS_340 VSS_418 AC38
R12 VSS_40 VSS_118 F17 BN14 VSS_194 VSS_279 BE4 AR14 VSS_341 VSS_419 AC37
P38 VSS_41 VSS_119 F15 BN12 VSS_195 VSS_280 BE3 AR13 VSS_342 VSS_420 AC12
P37 VSS_42 VSS_120 F13 BN9 VSS_196 VSS_281 BE2 AR5 VSS_343 VSS_421 AC6
P12 VSS_43 VSS_121 F11 BN7 VSS_197 VSS_282 BE1 AR4 VSS_344 VSS_422 AC5
P6 VSS_44 VSS_122 F9 BN4 VSS_198 VSS_283 BD38 AR3 VSS_345 VSS_423 AC4
N34 VSS_45 VSS_123 F8 BN2 VSS_199 VSS_284 BD37 AR2 VSS_346 VSS_424 AC3
N33 VSS_46 VSS_124 F5 BM38 VSS_200 VSS_285 BD12 AR1 VSS_347 VSS_425 AC2
N12 VSS_47 VSS_125 F4 BM35 VSS_201 VSS_286 BD11 AP34 VSS_348 VSS_426 AC1
N11 VSS_48 VSS_126 F3 BM28 VSS_202 VSS_287 BD10 AP33 VSS_349 VSS_427 AB34
N10 VSS_49 VSS_127 F2 BM27 VSS_203 VSS_288 BD8 AP12 VSS_350 VSS_428 AB33
N9 VSS_50 VSS_128 E38 BM26 VSS_204 VSS_289 BD7 AP11 VSS_351 VSS_429 AB6
N8 VSS_51 VSS_129 E35 BM23 VSS_205 VSS_290 BD6 AP10 VSS_352 VSS_430 AA30
N7 VSS_52 VSS_130 E34 BM21 VSS_206 VSS_291 BC33 AP9 VSS_353 VSS_431 AA29
N6 VSS_53 VSS_131 E9 BM13 VSS_207 VSS_292 BC14 AP8 VSS_354 VSS_432 AA12
N5 VSS_54 VSS_132 E4 BM12 VSS_208 VSS_293 BC13 AN30 VSS_355 VSS_433 A30
N4 VSS_55 VSS_133 D33 BM9 VSS_209 VSS_294 BC6 AN29 VSS_356 VSS_434 A28
N3 VSS_56 VSS_134 D30 BM6 VSS_210 VSS_295 BB30 AN12 VSS_357 VSS_435 A26
N2 VSS_57 VSS_135 D28 BM2 VSS_211 VSS_296 BB29 AN6 VSS_358 VSS_436 A24
N1 VSS_58 VSS_136 D26 BL29 VSS_212 VSS_297 BB6 AN5 VSS_359 VSS_437 A22
M14 VSS_59 VSS_137 D24 BK29 VSS_213 VSS_298 BB5 AM38 VSS_360 VSS_438 A20
M13 VSS_60 VSS_138 D22 BK15 VSS_214 VSS_299 AM37 VSS_361 VSS_439 A18
M12 VSS_61 VSS_139 D20 BK14 VSS_215 AM12 VSS_362 VSS_440 A16
M6 VSS_62 VSS_140 D18 BJ32 VSS_216 AM5 VSS_363 VSS_441 A14
L34 VSS_63 VSS_141 D16 BJ31 VSS_217 AM4 VSS_364 VSS_442 A12
L33 VSS_64 VSS_142 D14 BJ25 VSS_218 AM3 VSS_365 VSS_443 A10
L30 VSS_65 VSS_143 D12 BJ22 VSS_219 AM2 VSS_366 VSS_444 A9
L29 VSS_66 VSS_144 D10 BH14 VSS_220 AM1 VSS_367 VSS_445 A6
K38 VSS_67 VSS_145 D9 BH12 VSS_221 C2 AL34 VSS_368 VSS_446
K11 VSS_68 VSS_146 D6 BH9 VSS_222 NCTFVSS_2 BT36 AL33 VSS_369
K10 VSS_69 VSS_147 D3 BH8 VSS_223 NCTFVSS_3 BT35 AL14 VSS_370 B37
K9 VSS_70 VSS_148 C37 BH5 VSS_224 NCTFVSS_4 BT4 AL12 VSS_371 NCTFVSS_8 B3
K8 VSS_71 VSS_149 C31 BH4 VSS_225 NCTFVSS_5 BT3 AL10 VSS_372 NCTFVSS_9 A34
K7 VSS_72 VSS_150 C29 BH1 VSS_226 NCTFVSS_6 BR38 AL9 VSS_373 NCTFVSS_10 A4
B
K5 VSS_73 VSS_151 C27 BG38 VSS_227 NCTFVSS_7 AL8 VSS_374 NCTFVSS_11 A3 B

K4 VSS_74 VSS_152 BG13 VSS_228 AL7 VSS_375 NCTFVSS_12

K3 VSS_75 D38 BG12 VSS_229 AL4 VSS_376
K2 VSS_76 NCTFVSS_1 BF33 VSS_230 VSS_377
VSS_77 6 OF 14 BF12 VSS_231 13 OF 14
BE29 VSS_232
SKYLAKE-H-CPU_BGA1440 BE6 VSS_233 SKYLAKE-H-CPU_BGA1440
BD9 VSS_234
@ VSS_235 @
BC34
BC12 VSS_236
BB12 VSS_237
VSS_238 12 OF 14

SKYLAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (6/7) PWR, VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 11 of 75
5 4 3 2 1
 5 4 3 2 1

+1.2V
DDR4 SO-DIMM A Change JDDRL1 from Foxconn to ARGOSY +1.2V +1.2V +1.2V +1.2V
HLZ SDV 20160510

1
RD5
+1.2V +1.2V +1.2V +1.2V JDDRL1B 240_0402_5%

RVS

2
JDDRL1A DDRA_MA3 131 132 DDRA_MA2 DDRA_EVENT#
7 DDRA_MA3 DDRA_MA1 A3 A2 DDRA_EVENT# DDRA_MA2 7
133 134
RVS 7 DDRA_MA1
135 A1
VDD_9
EVENT_n/NF
VDD_10
136
1 2 DDRA_CLK0 137 138 DDRA_CLK1
DDRA_DQ4 VSS_1 VSS_2 DDRA_DQ1 7 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t/NF DDRA_CLK1# DDRA_CLK1 7
3 4 139 140
7 DDRA_DQ4 5 DQ5 DQ4 6 DDRA_DQ1 7 7 DDRA_CLK0# 141 CK0_c CK1_c/NF 142 DDRA_CLK1# 7
DDRA_DQ0 7 VSS_3 VSS_4 8 DDRA_DQ5 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
7 DDRA_DQ0 DQ1 DQ0 DDRA_DQ5 7 7 DDRA_PARITY Parity A0 DDRA_MA0 7
9 10
DDRA_DQS#0 11 VSS_5 VSS_6 12
D 7 DDRA_DQS#0 DDRA_DQS0 DQS0_C DM0_n/DBI0_n/NC DDRA_BA1 DDRA_MA10_AP D
13 14 145 146
7 DDRA_DQS0 DQS0_t VSS_7 DDRA_DQ6 7 DDRA_BA1 BA1 A10/AP DDRA_MA10_AP 7
15 16 147 148
DDRA_DQ7 VSS_8 DQ6 DDRA_DQ6 7 DDRA_CS0# VDD_13 VDD_14 DDRA_BA0
17 18 149 150
7 DDRA_DQ7 DQ7 VSS_9 DDRA_DQ2 7 DDRA_CS0# DDRA_MA14_W E# CS0_n BA0 DDRA_MA16_RAS# DDRA_BA0 7
19 20 151 152
DDRA_DQ3 VSS_10 DQ2 DDRA_DQ2 7 7 DDRA_MA14_W E# WE_n/A14 RAS_n/A16 DDRA_MA16_RAS# 7
21 22 153 154
7 DDRA_DQ3 DQ3 VSS_11 DDRA_DQ9 DDRA_ODT0 VDD_15 VDD_16 DDRA_MA15_CAS#
23 24 155 156
DDRA_DQ13 VSS_12 DQ12 DDRA_DQ9 7 7 DDRA_ODT0 DDRA_CS1# ODT0 CAS_n/A15 DDRA_MA13 DDRA_MA15_CAS# 7
25 26 157 158
7 DDRA_DQ13 DQ13 VSS_13 DDRA_DQ8 7 DDRA_CS1# CS1_n A13 DDRA_MA13 7
27 28 159 160
DDRA_DQ12 VSS_14 DQ8 DDRA_DQ8 7 DDRA_ODT1 VDD_17 VDD_18
29 30 161 162
7 DDRA_DQ12 DQ9 VSS_15 DDRA_DQS#1 7 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMA
31 32 163 164
VSS_16 DQS1_c DDRA_DQS1 DDRA_DQS#1 7 VDD_19 VREFCA DDRA_SA2
33 34 165 166
DM1_n/DBl1_n/NC DQS1_t DDRA_DQS1 7 C1/CS3_n/NC SA2
35 36 167 168

.1U_0402_10V6-K
2.2U_0603_6.3V6K
DDRA_DQ15 37 VSS_17 VSS_18 38 DDRA_DQ10 DDRA_DQ33 169 VSS_53 VSS_54 170 DDRA_DQ36
7 DDRA_DQ15 DQ15 DQ14 DDRA_DQ10 7 7 DDRA_DQ33 DQ37 DQ36 DDRA_DQ36 7 1 1
39 40 171 172
DDRA_DQ14 41 VSS_19 VSS_20 42 DDRA_DQ11 DDRA_DQ37 173 VSS_55 VSS_56 174 DDRA_DQ32
7 DDRA_DQ14 DQ10 DQ11 DDRA_DQ11 7 7 DDRA_DQ37 DQ33 DQ32 DDRA_DQ32 7
43 44 175 176
DDRA_DQ21 45 VSS_21 VSS_22 46 DDRA_DQ16 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
7 DDRA_DQ21 DQ21 DQ20 DDRA_DQ16 7 7 DDRA_DQS#4 DDRA_DQS4 DQS4_c DM4_n/DBl4_n/NC
47 48 179 180

CD2

CD3
DDRA_DQ20 VSS_23 VSS_24 DDRA_DQ17 7 DDRA_DQS4 DQS4_t VSS_59 DDRA_DQ35
49 50 181 182
7 DDRA_DQ20 51 DQ17 DQ16 52 DDRA_DQ17 7 DDRA_DQ38 183 VSS_60 DQ39 184 DDRA_DQ35 7
DDRA_DQS#2 VSS_25 VSS_26 7 DDRA_DQ38 DQ38 VSS_61 DDRA_DQ34
53 54 185 186
7 DDRA_DQS#2 DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRA_DQ39 187 VSS_62 DQ35 188 DDRA_DQ34 7
7 DDRA_DQS2 DQS2_t VSS_27 DDRA_DQ19 7 DDRA_DQ39 DQ34 VSS_63 DDRA_DQ40
57 58 189 190
DDRA_DQ22 VSS_28 DQ22 DDRA_DQ19 7 DDRA_DQ44 VSS_64 DQ45 DDRA_DQ40 7
59 60 191 192
7 DDRA_DQ22 DQ23 VSS_29 DDRA_DQ23 7 DDRA_DQ44 DQ44 VSS_65 DDRA_DQ45
61 62 193 194
DDRA_DQ18 VSS_30 DQ18 DDRA_DQ23 7 DDRA_DQ41 VSS_66 DQ41 DDRA_DQ45 7
63 64 195 196
7 DDRA_DQ18 DQ19 VSS_31 DDRA_DQ24 7 DDRA_DQ41 DQ40 VSS_67 DDRA_DQS#5
65 66 197 198
DDRA_DQ29 VSS_32 DQ28 DDRA_DQ24 7 VSS_68 DQS5_c DDRA_DQS5 DDRA_DQS#5 7
67 68 199 200
7 DDRA_DQ29 DQ29 VSS_33 DDRA_DQ25 DM5_n/DBl5_n/NC DQS5_t DDRA_DQS5 7
69 70 201 202
DDRA_DQ28 VSS_34 DQ24 DDRA_DQ25 7 DDRA_DQ43 VSS_69 VSS_70 DDRA_DQ47
71 72 203 204
7 DDRA_DQ28 DQ25 VSS_35 DDRA_DQS#3 7 DDRA_DQ43 DQ46 DQ47 DDRA_DQ47 7
73 74 205 206
VSS_36 DQS3_c DDRA_DQS3 DDRA_DQS#3 7 DDRA_DQ46 VSS_71 VSS_72 DDRA_DQ42
75 76 207 208
DM3_n/DBl3_n/NC DQS3_t DDRA_DQS3 7 7 DDRA_DQ46 DQ42 DQ43 DDRA_DQ42 7
77 78 209 210
DDRA_DQ27 79 VSS_37 VSS_38 80 DDRA_DQ26 DDRA_DQ50 211 VSS_73 VSS_74 212 DDRA_DQ48
7 DDRA_DQ27 DQ30 DQ31 DDRA_DQ26 7 7 DDRA_DQ50 DQ52 DQ53 DDRA_DQ48 7
81 82 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ31 DDRA_DQ52 215 VSS_75 VSS_76 216 DDRA_DQ49
7 DDRA_DQ30 DQ26 DQ27 DDRA_DQ31 7 7 DDRA_DQ52 DQ49 DQ48 DDRA_DQ49 7
85 86 217 218
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220
C C
CB5/NC CB4/NC 7 DDRA_DQS#6 DDRA_DQS6 DQS6_c DM6_n/DBl6_n/NC
89 90 221 222
VSS_43 VSS_44 7 DDRA_DQS6 DQS6_t VSS_79 DDRA_DQ53
91 92 223 224
CB1/NC CB0/NC DDRA_DQ54 VSS_80 DQ54 DDRA_DQ53 7
93 94 225 226
VSS_45 VSS_46 7 DDRA_DQ54 DQ55 VSS_81 DDRA_DQ55
95 96 227 228
DQS8_c DBI8_n/DBI_n/NC DDRA_DQ51 VSS_82 DQ50 DDRA_DQ55 7
97 98 229 230
DQS8_t VSS_47 7 DDRA_DQ51 DQ51 VSS_83 DDRA_DQ56
99 100 231 232
101 VSS_48 CB6/NC 102 DDRA_DQ57 233 VSS_84 DQ60 234 DDRA_DQ56 7
CB2/NC VSS_49 7 DDRA_DQ57 DQ61 VSS_85 DDRA_DQ60
103 104 235 236
105 VSS_50 CB7/NC 106 DDRA_DQ61 237 VSS_86 DQ57 238 DDRA_DQ60 7
CB3/NC VSS_51 PCH_DRAMRST# 7 DDRA_DQ61 DQ56 VSS_87 DDRA_DQS#7
107 108 239 240
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 PCH_DRAMRST# 13,16 VSS_88 DQS7_c DDRA_DQS7 DDRA_DQS#7 7
7 DDRA_CKE0 109 110 241 242
CKE0 CKE1 DDRA_CKE1 7 DM7_n/DBl7_n/NC DQS7_t DDRA_DQS7 7
111 112 243 244
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# DDRA_DQ62 245 VSS_89 VSS_90 246 DDRA_DQ59
7 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 7 7 DDRA_DQ62 DQ62 DQ63 DDRA_DQ59 7
7 DDRA_BG0 115 116 247 248
BG0 ALERT_n DDRA_ALERT# 7 DDRA_DQ58 VSS_91 VSS_92 DDRA_DQ63
117 118 249 250
DDRA_MA12 VDD_3 VDD_4 DDRA_MA11 7 DDRA_DQ58 DQ58 DQ59 DDRA_DQ63 7
119 120 251 252
7 DDRA_MA12 DDRA_MA9 A12 A11 DDRA_MA7 DDRA_MA11 7 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
7 DDRA_MA9 121 122 1 RD18 13,16,45,50 SMB_CLK_S3 253 254
A9 A7 DDRA_MA7 7 DDRA_VDDSPD SCL SDA DDRA_SA0 SMB_DATA_S3 13,16,45,50
123 124 1 2 255 256
DDRA_MA8 VDD_5 VDD_6 DDRA_MA5 +3VS VDDSPD SA0
7 DDRA_MA8 125 126 CD69 257 258 +0.6VS
DDRA_MA6 A8 A5 DDRA_MA4 DDRA_MA5 7 0.1U_0402_10V7K VPP_1 Vtt DDRA_SA1
7 DDRA_MA6 127 128 0_0402_5% 1 1 259 260
A6 A4 DDRA_MA4 7 2 VPP_2 SA1
129 130 @
VDD_7 VDD_8 CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
2 2 ARGOS_D4AR0-26001-1P52
ARGOS_D4AR0-26001-1P52 ME@
ME@
RD20
1 2
+2.5V
0_0402_5% +1.2V
+3VS +3VS +3VS +VREF_CA_DIMMA_R
Change RD2 to 0ohm jump

1
Layout Note:
1

RD22 RD24 RD26

0_0402_5% 0_0402_5% 0_0402_5% Place near DIMM RD1
1K_0402_1%
B B
@ @ @

2
1 2 +VREF_CA_DIMMA
2

RD2

1
DDRA_SA0 DDRA_SA1 DDRA_SA2

.1U_0402_10V6-K
+2.5V 2_0402_5%
+0.6VS
MAX 0.5A

1K_0402_1%
1 1

CD21
MAX 0.5A
1

CD1
RD23 RD25 RD27 0.022U_0402_16V7-K

2
2 2

RD3
1U_0402_6.3V6K

1U_0402_6.3V6K
0_0402_5% 0_0402_5% 0_0402_5%

10U_0402_6.3V6M

10U_0402_6.3V6M

1
1 1 1 1
1U_0402_6.3V6K

RD4

CD59

CD60
CD57

CD58
10U_0402_6.3V6M

10U_0402_6.3V6M
2

1 1 1 24.9_0402_1%
CD23
CD25
CD24

2 2 2 2

2
2 2 2
Note:
VREF trace width:20 mils at least
SPD Address = 0H Layout Note: For EMC Spacing:20mils to other signal/planes
Place near DIMM Place near DIMM scoket

MAX 3A +1.2V
Change DDR4 220u to B2
HLZ SVD 0527
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

220U_B2_6.3VM_R25M
0.1U_0402_10V7K
0.1U_0402_10V7K

CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14

CD98 1 CD97 1 CD96 1 CD95 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD19 CD81 CD82

CD16

CD17

CD18

CD65

CD66

CD68
CD15

CD67
+ 33P_0402_50V8J 33P_0402_50V8J
RF@ RF@
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2 2
2
A A

Near JDDRL1
Change CD81 & CD82 from @ to stuff based on RF requirement
HLZ SIT 0924

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDRVI SO-DIMM A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 12 of 75
5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM B Change JDDRH1 from Foxconn to ARGOSY and RVS to STD
HLZ SDV 20160510
+1.2V
+1.2V +1.2V +1.2V +1.2V

1
+1.2V +1.2V +1.2V +1.2V
JDDRH1B RD6
240_0402_5%
JDDRH1A STD
DDRB_MA3 131 132 DDRB_MA2
STD 7 DDRB_MA3 A3 A2 DDRB_MA2 7

2
DDRB_MA1 133 134 DDRB_EVENT# DDRB_EVENT#
1 2 7 DDRB_MA1 135 A1 EVENT_n/NF 136
DDRB_DQ2 3 VSS_1 VSS_2 4 DDRB_DQ4 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
7 DDRB_DQ2 DQ5 DQ4 DDRB_DQ4 7 7 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t/NF DDRB_CLK1# DDRB_CLK1 7
5 6 139 140
DDRB_DQ5 VSS_3 VSS_4 DDRB_DQ0 7 DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# 7
7 8 141 142
D 7 DDRB_DQ5 DQ1 DQ0 DDRB_DQ0 7 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0 D
9 10 143 144
DDRB_DQS#0 VSS_5 VSS_6 7 DDRB_PARITY Parity A0 DDRB_MA0 7
11 12
7 DDRB_DQS#0 DDRB_DQS0 DQS0_C DM0_n/DBI0_n/NC
13 14
7 DDRB_DQS0 DQS0_t VSS_7 DDRB_DQ1 DDRB_BA1 DDRB_MA10_AP
15 16 145 146
DDRB_DQ6 VSS_8 DQ6 DDRB_DQ1 7 7 DDRB_BA1 BA1 A10/AP DDRB_MA10_AP 7
17 18 147 148
7 DDRB_DQ6 DQ7 VSS_9 DDRB_DQ7 DDRB_CS0# VDD_13 VDD_14 DDRB_BA0
19 20 7 DDRB_CS0# 149 150
DDRB_DQ3 VSS_10 DQ2 DDRB_DQ7 7 DDRB_MA14_W E# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 7
21 22 151 152
7 DDRB_DQ3 DQ3 VSS_11 DDRB_DQ8 7 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 7
23 24 153 154
DDRB_DQ10 VSS_12 DQ12 DDRB_DQ8 7 DDRB_ODT0 VDD_15 VDD_16 DDRB_MA15_CAS#
25 26 155 156
7 DDRB_DQ10 DQ13 VSS_13 DDRB_DQ9 7 DDRB_ODT0 DDRB_CS1# ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS# 7
27 28 7 DDRB_CS1# 157 158
DDRB_DQ14 VSS_14 DQ8 DDRB_DQ9 7 CS1_n A13 DDRB_MA13 7
29 30 159 160
7 DDRB_DQ14 DQ9 VSS_15 DDRB_DQS#1 DDRB_ODT1 VDD_17 VDD_18
31 32 161 162
VSS_16 DQS1_c DDRB_DQS1 DDRB_DQS#1 7 7 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
33 34 163 164
DM1_n/DBl1_n/NC DQS1_t DDRB_DQS1 7 VDD_19 VREFCA DDRB_SA2
35 36 165 166
DDRB_DQ12 37 VSS_17 VSS_18 38 DDRB_DQ11 167 C1/CS3_n/NC SA2 168
7 DDRB_DQ12 DQ15 DQ14 DDRB_DQ11 7 DDRB_DQ38 VSS_53 VSS_54 DDRB_DQ34

.1U_0402_10V6-K
39 40 169 170

2.2U_0603_6.3V6K
DDRB_DQ13 VSS_19 VSS_20 DDRB_DQ15 7 DDRB_DQ38 DQ37 DQ36 DDRB_DQ34 7
41 42 171 172 1 1
7 DDRB_DQ13 DQ10 DQ11 DDRB_DQ15 7 DDRB_DQ35 VSS_55 VSS_56 DDRB_DQ39
43 44 173 174
DDRB_DQ22 VSS_21 VSS_22 DDRB_DQ17 7 DDRB_DQ35 DQ33 DQ32 DDRB_DQ39 7
45 46 175 176
7 DDRB_DQ22 47 DQ21 DQ20 48 DDRB_DQ17 7 DDRB_DQS#4 177 VSS_57 VSS_58 178
DDRB_DQ18 VSS_23 VSS_24 DDRB_DQ16 7 DDRB_DQS#4 DDRB_DQS4 DQS4_c DM4_n/DBl4_n/NC 2 2
49 50 179 180
7 DDRB_DQ18 DQ17 DQ16 DDRB_DQ16 7 7 DDRB_DQS4 DQS4_t VSS_59

CD31
51 52 181 182 DDRB_DQ36

CD30
DDRB_DQS#2 VSS_25 VSS_26 DDRB_DQ33 VSS_60 DQ39 DDRB_DQ36 7
53 54 183 184
7 DDRB_DQS#2 DDRB_DQS2 DQS2_c DM2_n/DBl2_n/NC 7 DDRB_DQ33 DQ38 VSS_61 DDRB_DQ37
55 56 185 186
7 DDRB_DQS2 DQS2_t VSS_27 DDRB_DQ23 DDRB_DQ32 VSS_62 DQ35 DDRB_DQ37 7
57 58 187 188
DDRB_DQ20 VSS_28 DQ22 DDRB_DQ23 7 7 DDRB_DQ32 DQ34 VSS_63 DDRB_DQ44
59 60 189 190
7 DDRB_DQ20 DQ23 VSS_29 DDRB_DQ21 DDRB_DQ40 VSS_64 DQ45 DDRB_DQ44 7
61 62 191 192
DDRB_DQ19 VSS_30 DQ18 DDRB_DQ21 7 7 DDRB_DQ40 DQ44 VSS_65 DDRB_DQ45
63 64 193 194
7 DDRB_DQ19 DQ19 VSS_31 DDRB_DQ28 DDRB_DQ41 VSS_66 DQ41 DDRB_DQ45 7
65 66 195 196
DDRB_DQ27 VSS_32 DQ28 DDRB_DQ28 7 7 DDRB_DQ41 DQ40 VSS_67 DDRB_DQS#5
67 68 197 198
7 DDRB_DQ27 DQ29 VSS_33 DDRB_DQ25 VSS_68 DQS5_c DDRB_DQS5 DDRB_DQS#5 7
69 70 199 200
DDRB_DQ31 VSS_34 DQ24 DDRB_DQ25 7 DM5_n/DBl5_n DQS5_t DDRB_DQS5 7
71 72 201 202
7 DDRB_DQ31 DQ25 VSS_35 DDRB_DQS#3 DDRB_DQ42 VSS_69 VSS_70 DDRB_DQ47
73 74 203 204
VSS_36 DQS3_c DDRB_DQS3 DDRB_DQS#3 7 7 DDRB_DQ42 DQ46 DQ47 DDRB_DQ47 7
75 76 205 206
DM3_n/DBl3_n/NC DQS3_t DDRB_DQS3 7 DDRB_DQ46 VSS_71 VSS_72 DDRB_DQ43
77 78 207 208
DDRB_DQ30 VSS_37 VSS_38 DDRB_DQ26 7 DDRB_DQ46 DQ42 DQ43 DDRB_DQ43 7
79 80 209 210
7 DDRB_DQ30 DQ30 DQ31 DDRB_DQ26 7 DDRB_DQ52 VSS_73 VSS_74 DDRB_DQ54
81 82 211 212
DDRB_DQ24 VSS_39 VSS_40 DDRB_DQ29 7 DDRB_DQ52 DQ52 DQ53 DDRB_DQ54 7
C 83 84 213 214 C
7 DDRB_DQ24 DQ26 DQ27 DDRB_DQ29 7 DDRB_DQ48 VSS_75 VSS_76 DDRB_DQ55
85 86 215 216
VSS_41 VSS_42 7 DDRB_DQ48 DQ49 DQ48 DDRB_DQ55 7
87 88 217 218
89 CB5/NC CB4/NC 90 DDRB_DQS#6 219 VSS_77 VSS_78 220
VSS_43 VSS_44 7 DDRB_DQS#6 DDRB_DQS6 DQS6_c DM6_n/DBl6_n/NC
91 92 221 222
CB1/NC CB0/NC 7 DDRB_DQS6 DQS6_t VSS_79 DDRB_DQ53
93 94 223 224
VSS_45 VSS_46 DDRB_DQ50 VSS_80 DQ54 DDRB_DQ53 7
95 96 225 226
97 DQS8_c DBI8_n/DBI_n/NC 98 7 DDRB_DQ50 227 DQ55 VSS_81 228 DDRB_DQ49
DQS8_t VSS_47 DDRB_DQ51 VSS_82 DQ50 DDRB_DQ49 7
99 100 229 230
101 VSS_48 CB6/NC 102 7 DDRB_DQ51 231 DQ51 VSS_83 232 DDRB_DQ59
CB2/NC VSS_49 DDRB_DQ57 VSS_84 DQ60 DDRB_DQ59 7
103 104 233 234
VSS_50 CB7/NC 7 DDRB_DQ57 DQ61 VSS_85 DDRB_DQ62
105 106 235 236
CB3/NC VSS_51 PCH_DRAMRST# DDRB_DQ61 VSS_86 DQ57 DDRB_DQ62 7
107 108 237 238
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 PCH_DRAMRST# 12,16 7 DDRB_DQ61 DQ56 VSS_87 DDRB_DQS#7
109 110 239 240
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7 VSS_88 DQS7_c DDRB_DQS7 DDRB_DQS#7 7
111 112 241 242
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# DM7_n/DBl7_n/NC DQS7_t DDRB_DQS7 7
113 114 243 244
7 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT# DDRB_ACT# 7 DDRB_DQ56 VSS_89 VSS_90 DDRB_DQ63
115 116 245 246
7 DDRB_BG0 BG0 ALERT_n DDRB_ALERT# 7 7 DDRB_DQ56 DQ62 DQ63 DDRB_DQ63 7
117 118 1 247 248
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 DDRB_DQ60 249 VSS_91 VSS_92 250 DDRB_DQ58
7 DDRB_MA12 DDRB_MA9 A12 A11 DDRB_MA7 DDRB_MA11 7 7 DDRB_DQ60 DQ58 DQ59 DDRB_DQ58 7
121 122 CD70 251 252
7 DDRB_MA9 A9 A7 DDRB_MA7 7 0.1U_0402_10V7K SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
123 124 RD19 253 254
VDD_5 VDD_6 SMB_DATA_S3 12,16,45,50
DDRB_MA8 125 126 DDRB_MA5 2 @ 1 2 12,16,45,50 SMB_CLK_S3 DDRB_VDDSPD 255 SCL SDA 256 DDRB_SA0
7 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 7 +3VS VDDSPD SA0
127 128 1 1 257 258 +0.6VS
7 DDRB_MA6 A6 A4 DDRB_MA4 7 VPP_1 Vtt DDRB_SA1
129 130 0_0402_5% CD53 259 260
VDD_7 VDD_8 2.2U_0603_6.3V6K CD54 VPP_2 SA1
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
ARGOS_D4AS0-26001-1P52 ARGOS_D4AS0-26001-1P52
ME@ ME@

RD21
+3VS +3VS +3VS 1 2
+2.5V
0_0402_5% +VREF_DQ_DIMMB_R +1.2V
1

RD28 RD33
0_0402_5%
RD30
0_0402_5% Change RD12 to 0ohm jump
B
0_0402_5% B

1
@ @
Layout Note: RD11
2

1K_0402_1%
DDRB_SA0 DDRB_SA1 DDRB_SA2 Place near DIMM
1 2 +VREF_CA_DIMMB

2
RD12
1

RD31 2_0402_5%

1
RD29 RD32 +2.5V 1 1
0_0402_5% CD29
MAX 0.5A

.1U_0402_10V6-K
0_0402_5% 0_0402_5%
@ +0.6VS 0.022U_0402_16V7-K
MAX 0.5A

1K_0402_1%
2

2 2

2
1

CD47
1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M
RD14

RD13
1 1 1 1
24.9_0402_1%

CD61

CD62
1U_0402_6.3V6K

CD63

CD64
10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1
SPD Address = 2H CD49
CD50

CD51

2
2 2 2 2

2 2 2 CAD Note:
Trace width= 20 mil, Spcing=20 mils
Layout Note:
Place near DIMM For EMC

+1.2V Change CD83 & CD84 from @ to stuff based on RF requirement

MAX 3A HLZ SIT 0924

Add CD4 based on RF requirement

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

CD35 1 CD36 1 CD37 1 CD38 1 CD39 1 CD40 1 CD41 1 CD42 1 1 1 1 1 1 1 1 1 1 1 1

HLZ SIT 0924
CD83 CD84 CD4
CD45

CD71

CD74
CD43

CD44

CD46

CD72

CD73

33P_0402_50V8J 33P_0402_50V8J 33P_0402_50V8J

RF@ RF@ RF@
A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A

Near JDDRH1
Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDRVI SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 13 of 75
5 4 3 2 1
 5 4 3 2 1

D D

+3VS UH1C SPT-H_PCH

AV2 G31 PCIE_SATA_PRX_DTX_N9

CL_CLK PCIE9_RXN/SATA0A_RXN PCIE_SATA_PRX_DTX_P9 PCIE_SATA_PRX_DTX_N9 45
AV3 H31
CL_DATA PCIE9_RXP/SATA0A_RXP PCIE_SATA_PRX_DTX_P9 45
NGFF SSD

1
CLINK PCIE_SATA_PTX_DRX_N9
AW2 C31
CL_RST# PCIE9_TXN/SATA0A_TXN PCIE_SATA_PTX_DRX_P9 PCIE_SATA_PTX_DRX_N9 45
RH133 B31
PCIE9_TXP/SATA0A_TXP PCIE_SATA_PTX_DRX_P9 45
10K_0402_5% R44
R43 GPP_G8/FAN_PWM_0
U39 GPP_G9/FAN_PWM_1 G29 PCIE_PRX_DTX_N10
GPP_G10/FAN_PWM_2 PCIE10_RXN/SATA1A_RXN PCIE_PRX_DTX_N10 45

2
N42 E29 PCIE_PRX_DTX_P10
GPP_G11/FAN_PWM_3 PCIE10_RXP/SATA1A_RXP C32 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 45 NGFF SSD
FAN PCIE10_TXN/SATA1A_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 45
U43 B32
GPP_G0/FAN_TACH_0 PCIE10_TXP/SATA1A_TXP PCIE_PTX_DRX_P10 45
U42
EC_SCI# RH95 1 2 0_0402_5% U41 GPP_G1/FAN_TACH_1 F41
20,49 EC_SCI# GPP_G2/FAN_TACH_2 PCIE15_RXN/SATA2_RXN SATA_PRX_DTX_N2 46
M44 E41
GPP_G3/FAN_TACH_3 PCIE15_RXP/SATA2_RXP SATA_PRX_DTX_P2 46
U36 B39
SATA_PTX_DRX_N2 46
HDD
P44 GPP_G4/FAN_TACH_4 PCIE15_TXN/SATA2_TXN A39
GPP_G5/FAN_TACH_5 PCIE15_TXP/SATA2_TXP SATA_PTX_DRX_P2 46
T45
T44 GPP_G6/FAN_TACH_6 D43
GPP_G7/FAN_TACH_7 PCIE16_RXN/SATA3_RXN

PCIe/SATA
E42
PCIE_PTX_DRX_P11 B33 PCIE16_RXP/SATA3_RXP A41
Add Reserved HDD cable HDD Cable
45
45
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PTX_DRX_N11 C33 PCIE11_TXP PCIE16_TXN/SATA3_TXN A40 HLZ SDV 20160510
PCIE_PRX_DTX_P11 K31 PCIE11_TXN PCIE16_TXP/SATA3_TXP
NGFF SSD 45 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP
L31 H42
45 PCIE_PRX_DTX_N11 PCIE11_RXN PCIE17_RXN/SATA4_RXN H40
Delete HDD Cable SATA signal
AB33
GPP_F10/SCLOCK
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
E45 HLZ SDV 20160510
AB35 F45
AA44 GPP_F11/SLOAD PCIE17_TXP/SATA4_TXP
AA45 GPP_F13/SDATAOUT0 K37
GPP_F12/SDATAOUT1 PCIE18_RXN/SATA5_RXN G37
C B38 PCIE18_RXP/SATA5_RXP G45 C
C38 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN G44
D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
E37 PCIE14_RXN/SATA1B_RXN AD44 SATA_LED# RH15 1 2 10K_0402_5%
PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# +3VS
AG36 SSD_DET#
GPP_E0/SATAXPCIE0/SATAGP0 SSD_DET# 45
C36 AG35
B36 PCIE13_TXN/SATA0B_TXN GPP_E1/SATAXPCIE1/SATAGP1 AG39
G35 PCIE13_TXP/SATA0B_TXP GPP_E2/SATAXPCIE2/SATAGP2 AD35
E35 PCIE13_RXN/SATA0B_RXN GPP_F0/SATAXPCIE3/SATAGP3 AD31
PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 AD38
PCIE_PTX_DRX_P12 A35 GPP_F2/SATAXPCIE5/SATAGP5 AC43
45 PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP GPP_F3/SATAXPCIE6/SATAGP6
B35 AB44
45 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE12_TXN GPP_F4/SATAXPCIE7/SATAGP7
NGFF SSD H33
45 PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 PCIE12_RXP
G33
45 PCIE_PRX_DTX_N12 PCIE12_RXN W36
GPP_F21/EDP_BKLTCTL PCH_EDP_PWM 35
J45 W35
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_EDP_ENBKL 35
K44 W42
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_EDP_ENVDD 35
N38 HOST
N39 PCIE20_RXP/SATA7_RXP AJ3 PCH_THRMTRIP#_R RH34 1 2 620_0402_5% RH781
PCIE20_RXN/SATA7_RXN THERMTRIP# H_THRMTRIP# 6,24
H44 AL3 PCH_PECI RH35 1 2 13_0402_5% 1 @ 2
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC_R EC_PECI 6,49
H43 AJ4 RH13 1 2 30_0402_1%
PCIE19_TXN/SATA6_TXN PM_SYNC CPU_PLTRST# H_PM_SYNC 6
L39 AK2 0_0402_5%
PCIE19_RXP/SATA6_RXP PLTRST_PROC# H_PM_DOWN CPU_PLTRST# 6
L37 3 OF 12 AH2 H_PM_DOWN 6
PCIE19_RXN/SATA6_RXN PM_DOWN
SKYLAKE-H-PCH_FCBGA837
Change RH35 from 43 to 12.1 due to follow DG&CRB Add RH781_@ for PCH PECI
@
HLZ SDV 0601 HLZ SIV 0811

B B
CPU_PLTRST# CH263 1 2 0.1U_0402_25V6 EMC_NS@

H_PM_DOWN CH6 1 2 .1U_0402_10V6-K @

PCH_PECI CH7 1 2 .1U_0402_10V6-K @

Reserved Cap HLZ SDV 0616

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (1/9) PCIe/SATA/GPPFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 14 of 75
5 4 3 2 1
 5 4 3 2 1

+3VS
D UH1F SPT-H_PCH D

USB30_TX_N1 C11 AT22 LPC_AD0 KBRST# 10K_0402_5% 2 1 RH113

LPC/eSPI
47 USB30_TX_N1 USB30_TX_P1 USB3_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 49,50
B11 AV22
47 USB30_TX_P1 USB30_RX_N1 USB3_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 49,50 PCH_SMI#
B7 AT19 10K_0402_5% 2 @ 1 RH129
LEFT USB (3.0) 47 USB30_RX_N1 USB30_RX_P1 A7 USB3_1_RXN GPP_A3/LAD2/ESPI_IO2 BD16 LPC_AD3 LPC_AD2 49,50
47 USB30_RX_P1 USB30_TX_N2 USB3_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 49,50
B12
47 USB30_TX_N2 USB30_TX_P2 USB3_2_TXN/SSIC_1_TXN LPC_FRAME#
A12 BE16
47 USB30_TX_P2 USB30_RX_N2 USB3_2_TXP/SSIC_1_TXP GPP_A5/LFRAME#/ESPI_CS0# LPC_FRAME# 49,50 +3VS
C8 BA17 SERIRQ
47 USB30_RX_N2 USB30_RX_P2 USB3_2_RXN/SSIC_1_RXN GPP_A6/SERIRQ/ESPI_CS1# SERIRQ 49,50
B8 AW17
LEFT USB (3.0) 47 USB30_RX_P2 USB3_2_RXP/SSIC_1_RXP GPP_A7/PIRQA#/ESPI_ALERT0# AT17 KBRST# SERIRQ 10K_0402_5% 2 1 RH104
GPP_A0/RCIN#/ESPI_ALERT1# KBRST# 49
B15 BC18
C15 USB3_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
K15 USB3_6_TXP
3D Camera USB3_6_RXN CLK_PCI_EC_R CLK_PCI_EC

USB
K13 BC17 RH84 1 2 22_0402_5%
USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_TPM_R CLK_PCI_TPM CLK_PCI_EC 49
AV19 RH87 1 TPM@ 2 22_0402_5%
Delete 3D camera B14 GPP_A10/CLKOUT_LPC1 CLK_PCI_TPM 50
HLZ SDV 20160510 C14 USB3_5_TXN
USB3_5_TXP GPP_G19/SMI#
M45 PCH_SMI# 1 TC110 PAD @

10P_0402_50V8JCH266
G13 N43
USB3_5_RXN GPP_G18/NMI#

EMC_NS@
H13

10P_0402_50V8J
1 1

EMC_NS@
USB3_5_RXP

CH265
TYPE-C_USB3_TX_P3 D13 AE45
38 TYPE-C_USB3_TX_P3 TYPE-C_USB3_TX_N3 USB3_3_TXP/SSIC_2_TXP GPP_E6/DEVSLP2
C13 AG43
38 TYPE-C_USB3_TX_N3 TYPE-C_USB3_RX_P3 USB3_3_TXN/SSIC_2_TXN GPP_E5/DEVSLP1 DEVSLP0_R 2 2
A9 AG42 NGFF SSD
Type C USB3.0 38 TYPE-C_USB3_RX_P3 TYPE-C_USB3_RX_N3 B10 USB3_3_RXP/SSIC_2_RXP GPP_E4/DEVSLP0 AB39
DEVSLP0_R 45
38 TYPE-C_USB3_RX_N3 USB3_3_RXN/SSIC_2_RXN GPP_F9/DEVSLP7 AB36

SATA
B13 GPP_F8/DEVSLP6 AB43
A14 USB3_4_TXP GPP_F7/DEVSLP5 AB42
G11 USB3_4_TXN GPP_F6/DEVSLP4 AB41
Add TypeC USB3 E11 USB3_4_RXP 6 OF 12 GPP_F5/DEVSLP3
HLZ SDV 20160510 USB3_4_RXN
SKYLAKE-H-PCH_FCBGA837
C C
@

Add Port C/D strap

HLZ SDV 20160510 +3VS

Different to Y710 DDPC_DATA 2.2K_0402_5% 2 1 RH8

HLZ SDV 20160510 UH1E SPT-H_PCH

DDPD_DATA 2.2K_0402_5% 2 @ 1 RH10

BB3 DDPC_CLK PAD 1 @
GPP_I7/DDPC_CTRLCLK DDPC_DATA IT28
36 HDMI_HPD AW4 BD6
AY2 GPP_I0/DDPB_HPD0 GPP_I8/DDPC_CTRLDATA BA5 DDPB_CLK +3VS
37 TYPE-C_DP_HPD GPP_I1/DDPC_HPD1 GPP_I5/DDPB_CTRLCLK DDPB_CLK 36
AV4 BC4 DDPB_DATA HDMI
GPP_I2/DDPD_HPD2 GPP_I6/DDPB_CTRLDATA DDPD_CLK DDPB_DATA 36
BA4 BE5 PAD 1 @
GPP_I3/DDPE_HPD3 GPP_I9/DDPD_CTRLCLK DDPD_DATA IT36 DDPB_CLK
B BE6 2.2K_0402_5% 2 1 RH32 B
GPP_I10/DDPD_CTRLDATA
Y44
GPP_F14 V44 DDPB_DATA 2.2K_0402_5% 2 1 RH33
GPP_F23 W39
PCH_EDP_HPD BD7 GPP_F22
35 PCH_EDP_HPD GPP_I4/EDP_HPD L43
GPP_G23 L44
GPP_G22 DDPB_CTRLDATA
U35 The signal has a weak internal pull-down.
GPP_G21
GPP_G20
R35
BD36
* H Port B is detected.
GPP_H23 L Port B is not detected.
5 OF 12
DDPC_CTRLDATA
SKYLAKE-H-PCH_FCBGA837
The signal has a weak internal pull-down.
@ H Port C is detected.
* L Port C is not detected. (Default)
DDPD_CTRLDATA
The signal has a weak internal pull-down.
H Port D is detected.
* L Port D is not detected. (Default)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (2/9) USB3/GPPAEFGHI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 15 of 75
5 4 3 2 1
 5 4 3 2 1

RPH1

PCH_HDA_RST# 1 8 HDA_RST#
48 PCH_HDA_RST# PCH_HDA_SYNC HDA_SYNC
2 7
48 PCH_HDA_SYNC PCH_HDA_BIT_CLK HDA_BIT_CLK
3 6
48 PCH_HDA_BIT_CLK PCH_HDA_SDOUT HDA_SDOUT
4 5
48 PCH_HDA_SDOUT

1 33_0804_8P4R_5%

CH77
100P_0402_50V8J For EMC
2 EMC_NS@

ADD PM_CLKRUN# for Nuvoton TPM +1.2V

D HLZ SIT 0920 D

UH1D SPT-H_PCH

1
HDA_BIT_CLK BA9 BB17 RH756
HDA_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 PM_CLKRUN# 470_0402_5%
PCH_HDA_SDIN0 HDA_RST# GPP_A8/CLKRUN# PM_CLKRUN# 50
BE7
48 PCH_HDA_SDIN0 HDA_SDI0
BC8 AR15
HDA_SDI1 GPD11/LANPHYPC

2
RH91 2 0_0402_5% HDA_SDOUT BB7 AV13
49 ME_FLASH HDA_SYNC HDA_SDO GPD9/SLP_WLAN#
BD9
HDA_SYNC BC14 PCH_DRAMRST#
DRAM_RESET# PCH_DRAMRST# 12,13
BD1 BD23
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27
RSVD_BE2 GPP_B1 AR27
PROC_AUDIO_SDO_CPU RH754 2 1 30_0402_1% PROC_AUDIO_SDO_PCH AM1 AUDIO GPP_B0 N44
8 PROC_AUDIO_SDO_CPU DISPA_SDO GPP_G17/ADR_COMPLETE
PROC_AUDIO_SDI_CPU AN2 AN24
8 PROC_AUDIO_SDI_CPU PROC_AUDIO_CLK_CPU RH755 2 PROC_AUDIO_CLK_PCH AM2 DISPA_SDI GPP_B11 SYS_PWROK_R
1 30_0402_1% AY1 RH1931 2 0_0402_5% SYS_PWROK 42,49
8 PROC_AUDIO_CLK_CPU DISPA_BCLK SYS_PWROK
PLACE NEAR PCH AL42
GPP_D8/I2S0_SCLK WAKE#
BC13 WAKE#
SLP_A#
RH69 1 2 0_0402_5% PCIE_WAKE# 45,49
AN42 BC15 1 PAD @
AM43 GPP_D7/I2S0_RXD GPD6/SLP_A# AV15 SLP_LAN# 1 TH30
PAD @
GPP_D6/I2S0_TXD SLP_LAN# SLP_S0 TH31
AJ33 BC26 1 PAD @
GPP_D5/I2S0_SFRM GPP_B12/SLP_S0# PM_SLP_S3#_R TH32
AH44 AW15 RH70 1 2 0_0402_5%
GPP_D20/DMIC_DATA0 GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 49
AJ35 BD15 RH71 1 2 0_0402_5%
GPP_D19/DMIC_CLK0 GPD5/SLP_S4# PM_SLP_S5#_R1 PM_SLP_S4# 49
AJ38 BA13 PAD @
GPP_D18/DMIC_DATA1 GPD10/SLP_S5# TH33
AJ42
GPP_D17/DMIC_CLK1
GPD8/SUSCLK
AN15 SUSCLK
SUSCLK 45 CRB Reserve
BD13 BATLOW # SUSACK#_R
GPD0/BATLOW# BB19 SUSACK#_R RH66 2 @ 1 0_0402_5%
PCH_RTCRST# GPP_A15/SUSACK# SUSWARN#_R SUSACK# 49 SUSW ARN#_R
49 PCH_RTCRST# BC10 BD19 RH74 1 2 0_0402_5% RH745 1 2 0_0402_5%
PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSWARN# 49
BB10
SRTCRST#
RH12 1 2 0_0402_5% PCH_PW ROK_R AW11 BD11 PCH_LAN_W AKE#
42,49 PCH_PW ROK PCH_RSMRST#_R BA11 PCH_PWROK GPD2/LAN_WAKE# PCH_AC_PRESENT_R
RH14 1 2 0_0402_5% BB15 RH76 1 2 0_0402_5%
42,49 EC_RSMRST# RSMRST# GPD1/ACPRESENT PM_SLP_SUS#_R AC_PRESENT 49
RH2391 2 0_0402_5% BB13 RH77 1 @ 2 0_0402_5%
PCH_DPW ROK_R AV11 SLP_SUS# PM_PW RBTN#_R PM_SLP_SUS# 49
49 DPW ROK_EC RH68 1 @ 2 0_0402_5% AT13 RH75 1 2 0_0402_5% PBTN_OUT# 49
SMB_ALERT# BB41 DSW_PWROK GPD3/PWRBTN# AW1 SYS_RESET#
C C
PCH_SMBCLK GPP_C2/SMBALERT# SYS_RESET# PCH_BEEP SYS_RESET# 42
AW44 BD26

SMBUS
PCH_SMBDATA GPP_C0/SMBCLK GPP_B14/SPKR H_CPUPW RGD PCH_BEEP 48
BB43 AM3
SMB0_ALERT# GPP_C1/SMBDATA PROCPWRGD H_CPUPW RGD 6
BA40
SML0CLK AY44 GPP_C5/SML0ALERT# AT2
SML0DATA BB39 GPP_C3/SML0CLK ITP_PMODE AR3
Change RH56 from stuff to @ SMB1_ALERT# AT27 GPP_C4/SML0DATA
JTAG
JTAGX AR2
JTAGX 42
44 SMB1_ALERT#
HLZ SIV 0811 SML1CLK AW42 GPP_B23/SML1ALERT#/PCHHOT#
GPP_C6/SML1CLK
JTAG_TMS
JTAG_TDO
AP1 PCH_TMS
PCH_TDO
42
42
SML1DATA AW45 AP2
+3VALW _PCH GPP_C7/SML1DATA JTAG_TDI AN3 PCH_TDI 42
JTAG_TCK PCH_TCK 42
4 OF 12
RH56 1 @ 2 10K_0402_5% SUSW ARN#
SKYLAKE-H-PCH_FCBGA837
@
+3VALW
Change PM_PWRBTN#_R PWR
HLZ SDV 0606
RH17 1 2 10K_0402_5% PM_PWRBTN#_R
CMOS
RH58 1 2 10K_0402_5% PCH_AC_PRESENT_R W=20mils W=20mils Total Length 8000 mils
VCCRTC +RTCVCC
RH60 1 2 10K_0402_5% BATLOW # +RTCVCC
1

1
RH2 1 2 0_0402_5% CH4
RH80 1 2 1K_0402_5% W AKE# 1 1U_0402_6.3V6K @ JME1
CH1 SHORT PADS

2
RH747 1 2 20K_0402_5% PCH_LAN_W AKE# 1U_0402_6.3V6K 1 RH3 2 20K_0402_5% 2 PCH_SRTCRST#

2 CD@
PAD 1 @
+3VS TC111 Add Testpad for Box RTC discharge Hai SVT 1118
1 RH4 2 20K_0402_5% PCH_RTCRST#
RH67 1 2 10K_0402_5% SYS_RESET#
1

1
RH65 1 2 8.2K_0402_5% PM_CLKRUN# CH5 JCMOS1
1U_0402_6.3V6K @ SHORT PADS
RH16 1 2 100K_0402_5% SYS_PW ROK_R

2
B
RH54 2 1 10K_0402_5% PCH_PW ROK 2 B

RH59 1 2 10K_0402_5% PCH_RSMRST#_R

PCH_DPWROK_R
RH61 1 @ 2 100K_0402_5%
Place JUMPER under RAM door
+3VALW _PCH
AS EMC request
+3VALW _PCH
+3VALW _PCH RH28 1 @ 2 PCH_BEEP PCH_PW ROK SYS_PW ROK_R PCH_DPW ROK_R
1K_0402_5% RH25 1 @ 2 1K_0402_5% ME_FLASH
SPKR / GPP_B14
1 1 1
RH101 1
1
2 2.2K_0402_5%
2 2.2K_0402_5%
SML0CLK The s i gnal has a weak i nt er nal pul l - down.
0 = Di s abl e ¨ Top Swap mode . ( Def aul t)
* HDA_SDO This signal has a weak internal pull-down.
〃

RH102 SML0DATA CH83 CH84 CH85 0 = Enable security measures defined in the Flash Descriptor.
1 = Enabl e ¨ Top Swap mode . Thi s i nver t s a n addr es s .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K
1 = Disable Flash Descriptor Security (override). This
〃

* on acces s t o SPI and f i r mwar e hub, so t he pr oces sor

EMC_NS@ 2 EMC_NS@ 2 EMC_NS@ 2
strap should only be asserted high using external pull-
RH765 1 2 2.2K_0402_5% SMB_ALERT# RH768 1 @ 2 2.2K_0402_5% bel i eves i t f et ches t he al t er nat e boot bl ock i nst ead of up in manufacturing/debug environments ONLY.
RH766 1 @ 2 2.2K_0402_5% SMB0_ALERT# RH769 1 @ 2 2.2K_0402_5% t he or i gi nal boot - bl ock. PCH wi l l i nver t A16 ( def aul t )
RH767 1 @ 2 2.2K_0402_5% SMB1_ALERT# RH770 1 @ 2 2.2K_0402_5% +3VALW _PCH
f or cycl es goi ng t o t he upper t wo 64- KB bl ocks i n t he
Strap FWH or t he appr opr i at e addr es s l i nes ( A16, A17, or RH31 1 @ 2 1K_0402_5% HDA_SYNC
SMBALERT# / GPP_C2 A18) as s el ect ed i n Top Swap Bl ock si ze s of t st r ap
0 = Disable Intel ME Crypto Transport Layer Security ( handl ed t hr ough FI TC) .
(TLS) cipher suite (no confidentiality). (Default) +3VS
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
PCH is Master DIMM1, DIMM2, Mini CARD, TP PCH is salve GPU, EC, Thermal Sensor
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS. +3VS +3VS
+3VALW_PCH 1 RH121 2 2.2K_0402_5%

2
+3VALW_PCH 1 RH114 2 2.2K_0402_5% 2N7002KDWH 1 RH115 2 2.2K_0402_5%

G
2

SML0ALERT# / GPP_C5 Vth= min 1V, max 2.5V 1 RH122 2 2.2K_0402_5%

G

ESD 2KV
0 = LPC Is selected for EC. (Default) 1 RH116 2 2.2K_0402_5% 1 RH117 2 2.2K_0402_5%
1 = eSPI Is selected for EC.
SML1CLK 6 1 EC_SMB_CK2
EC_SMB_CK2 27,44,49

S
PCH_SMBCLK 6 1 SMB_CLK_S3

D
SML1ALERT# / PCHHOT#/GPP_B23 SMB_CLK_S3 12,13,45,50
S

5
QH2A 2N7002KDW H_SOT363-6
D

A This signal has an internal pull-down A

G
5

QH1A 2N7002KDW H_SOT363-6

G

SML1DATA 3 4 EC_SMB_DA2
EC_SMB_DA2 27,44,49

S
PCH_SMBDATA 3 4 SMB_DATA_S3

D
SMB_DATA_S3 12,13,45,50
S

@ .1U_0402_10V6-K 2 1 CH12 EC_RSMRST# QH2B 2N7002KDW H_SOT363-6

D

QH1B 2N7002KDW H_SOT363-6

@ .1U_0402_10V6-K 2 1 CH21 PROC_AUDIO_SDI_CPU

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (3/9) HDA,RTC,SMBUS,PM
Reserved Cap HLZ SDV 0616
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 16 of 75
5 4 3 2 1
 5 4 3 2 1

UH1G SPT-H_PCH
AR17
GPP_A16/CLKOUT_48
D G1 L1 D
6 PCH_CPU_NSSC_CLK F1 CLKOUT_CPUNSSC_P CLKOUT_ITPXDP L2
6 PCH_CPU_NSSC_CLK# CLKOUT_CPUNSSC CLKOUT_ITPXDP_P
G2 J1
6 PCH_CPU_BCLK CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK# 6
H2 J2
+1.0VALW 6 PCH_CPU_BCLK# CLKOUT_CPUBCLK CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK 6
+VCCCLK XTAL24_OUT A5 N7
XTAL24_IN A6 XTAL24_OUT CLKOUT_PCIE_N0 N8
XTAL24_IN CLKOUT_PCIE_P0
RH1981 2 0_0402_5% RH6 1 2 2.7K_0402_1% PCH_CLK_BIASREF E1 L7 CLK_PCIE_CR# CR
XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_CR CLK_PCIE_CR# 43
L5
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_CR 43
BC9
PCH_RTCX2 BD10 RTCX1 D3 CLK_PCIE_WLAN#
RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_WLAN CLK_PCIE_WLAN# 45
F2 WLAN
CLKOUT_PCIE_P2 CLK_PCIE_WLAN 45
BC24
CR_CLKREQ# AW24 GPP_B5/SRCCLKREQ0# E5 CLK_PCIE_LAN#
43 CR_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_LAN# 50
WLAN_CLKREQ# AT24 G4 CLK_PCIE_LAN LAN
45 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_LAN 50
LAN_CLKREQ# BD25
50 LAN_CLKREQ# GPP_B8/SRCCLKREQ3#
BB24 D5
BE25 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 E6
AT33 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4
SSD_CLKREQ# AR31 GPP_H0/SRCCLKREQ6# D8
45 SSD_CLKREQ# GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5
BD32 D7
Delete TBT CLK REQ BC32 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
HLZ SDV 20160510 BB31 GPP_H3/SRCCLKREQ9#
GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6
R8
24 GPU_CLKREQ# GPU_CLKREQ# BC33 R7
BA33 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AW33 GPP_H6/SRCCLKREQ12# U5 CLK_PCIE_SSD#
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 CLK_PCIE_SSD CLK_PCIE_SSD# 45
BB33 U7 M.2 SSD
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 CLK_PCIE_SSD 45
BD33
GPP_H9/SRCCLKREQ15# W10
R13 CLKOUT_PCIE_N8 W11
Delete TBT CLK
C +3VS R11 CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
CLKOUT_PCIE_P8 HLZ SDV 20160510 C
N3
P1 CLKOUT_PCIE_N9 N2
RH89 1 2 10K_0402_5% LAN_CLKREQ# R2 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
CLKOUT_PCIE_P14 P3
RH90 1 2 10K_0402_5% WLAN_CLKREQ# W7 CLKOUT_PCIE_N10 P2
Y5 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
RH91 1 2 10K_0402_5% CR_CLKREQ# CLKOUT_PCIE_P13 R3 CLK_PCIE_GPU#
CLKOUT_PCIE_N11 CLK_PCIE_GPU CLK_PCIE_GPU# 24
U2 R4 GPU
SSD_CLKREQ# CLKOUT_PCIE_N12 CLKOUT_PCIE_P11 CLK_PCIE_GPU 24
RH93 1 2 10K_0402_5% U3
CLKOUT_PCIE_P12 7 OF 12
RH94 1 2 10K_0402_5% GPU_CLKREQ#
SKYLAKE-H-PCH_FCBGA837
Delete TBT CLK REQ @
HLZ SDV 20160510

RH92 2 1 1M_0402_5% PCH_RTCX1

RH1
YH2 1 2 PCH_RTCX2
10M_0402_5%
2 3 XTAL24_IN
GND1 OSC2 YH1
XTAL24_OUT 1 4 1 2
OSC1 GND2
1 1
32.768KHZ_9PF_X1A0001410002
B CH9 24MHZ_6PF_7V24000032 CH10 1 1 B
3.9P_0402_50V8-B 3.9P_0402_50V8-B
2 2 CH2 CH3
10P_0402_50V8J 10P_0402_50V8J
2 2

Change CH9 & CH10 from 3.3P to 3.9P HLZ SIT 0921 Change CH2 & CH3 from 6.8P to 10P HLZ SIT 0921
Change CH9 & CH10 from 4.7P to 3.3P HLZ SIV 0811 Change YH1 based on common pool HLZ SIV 0811

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (3/9) CLOCK,GPPBH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 17 of 75
5 4 3 2 1
 5 4 3 2 1

UH1A SPT-H_PCH

BD17 BB27 PLT_RST#

GPP_A11/PME# GPP_B13/PLTRST# PLT_RST# 27,42,43,45,49,50

1
AG15
AG14 RSVD_1 P43 RH43
AF17 RSVD_2 GPP_G16/GSXCLK R39 100K_0402_5%
SPI_CLK_PCH_0 RH1051 2 33_0402_5% AE17 RSVD_3 GPP_G12/GSXDOUT R36
D 49 SPI_CLK_PCH_0 RSVD_4 GPP_G13/GSXSLOAD D
SPI_CLK_PCH_1 RH1061 2 33_0402_5% SPI_CLK_PCH R42
GPP_G14/GSXDIN

2
1 PAD @ AR19 R41
SPI_CS0#_R SPI_CS0# TC107 TP2 GPP_G15/GSXSRESET#
49 SPI_CS0#_R RH1071 2 0_0402_5% 1 PAD @ AN17
TC108 TP1
SPI_CS1#_R RH1081 2 0_0402_5% SPI_CS1# SPI_SI BB29 AF41
SPI_SO BE30 SPI0_MOSI GPP_E3/CPU_GP0 AE44
SPI_CS0# BD31 SPI0_MISO GPP_E7/CPU_GP1 BC23
SPI_SI_R0 RH1091 2 33_0402_5% SPI_CLK_PCH BC31 SPI0_CS0# GPP_B3/CPU_GP2 BD24
49 SPI_SI_R0 SPI_SI_R1 SPI_SI SPI_CS1# SPI0_CLK GPP_B4/CPU_GP3
RH1101 2 33_0402_5% AW31
SPI0_CS1# BC36
SPI_SO_R0 RH1111 2 33_0402_5% SPI_SO SPI_WP# BC29 GPP_H18/SML4ALERT# BE34
49 SPI_SO_R0 42 SPI_WP# SPI0_IO2 GPP_H17/SML4DATA GPP_H12
SPI_SO_R1 RH1121 2 33_0402_5% SPI_HOLD# BD30 BD39
AT31 SPI0_IO3 GPP_H16/SML4CLK BB36 +3VS This strap should sample LOW. There should NOT be any
SPI0_CS2# GPP_H15/SML3ALERT# BA35 on-board device driving it to opposite direction during
SPI_WP#_R0 RH2501 2 33_0402_5% AN36 GPP_H14/SML3DATA BC35 strap sampling.
SPI_WP#_R1 RH2491 2 33_0402_5% SPI_WP# AL39 GPP_D1/SPI1_CLK GPP_H13/SML3CLK BD35 RH753 1 @ 2 4.7K_0402_5%
AN41 GPP_D0/SPI1_CS# GPP_H12/SML2ALERT# AW35
SPI_CLK_PCH_0 SPI_HOLD#_R0 RH2521 2 33_0402_5% SPI_HOLD# AN38 GPP_D3/SPI1_MOSI GPP_H11/SML2DATA BD34
SPI_CLK_PCH_1 SPI_HOLD#_R1 RH2511 2 33_0402_5% AH43 GPP_D2/SPI1_MISO GPP_H10/SML2CLK
AG44 GPP_D22/SPI1_IO3 BE11 RH743 2 1 1M_0402_5%
GPP_D21/SPI1_IO2 INTRUDER# +RTCVCC
1 OF 12

1 1 SKYLAKE-H-PCH_FCBGA837
@
CH267 CH268
10P_0402_50V8J 10P_0402_50V8J
2 EMC_NS@ 2 EMC_NS@

500mA 500mA
+3VALW_PCH +3V_SPI
C C

RC171 1 2 0_0402_5%
+3VALW_PCH
+3VS
SPI_HOLD# RH771 1 @ 2 1K_0402_5%
RH123 1 2 1K_0402_5% SPI_WP# RC172 1 @ 2 0_0402_5%
RH125 1 2 1K_0402_5% SPI_HOLD#
RH772 1 @ 2 1K_0402_5% SPI_SO
RH773 1 @ 2 1K_0402_5% SPI_SI +3V_SPI
SPI0_MOSI 1. If support DS3, connect to +3VS and don't support EC mirror code;
SPI0_MISO
This signal has an internal pull-up.
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

This strap should sample HIGH. There should NOT be any

on-board device driving it to opposite direction during
strap sampling.

64Mb Flash ROM 250mA 32Mb Flash ROM 250mA

+3V_SPI
UC3 +3V_SPI
SPI_CS0#_R 1 8 UC7
SPI_SO_R0 CS# VCC SPI_HOLD#_R0
1
SPI_CS1#_R
For EMI
2 7 1 8 1 RH742
SPI_WP#_R0 3 DO HOLD# 6 SPI_CLK_PCH_0 CH13 SPI_SO_R1 2 CS# VCC 7 SPI_HOLD#_R1 SPI_CLK_PCH_1 1 2
4 WP# CLK 5 SPI_SI_R0 .1U_0402_10V6-K SPI_WP#_R1 3 DO HOLD# 6 SPI_CLK_PCH_1 CH246 10_0402_5%
GND DI 2 WP# CLK 1
4 5 SPI_SI_R1 .1U_0402_10V6-K EMC_NS@
W25Q64FVSSIQ_SO8 GND DI 2 CH247
B W25Q32FVSSIQ_SO8 10P_0402_50V8J B
2 EMC_NS@
Change UC3 Value from W25Q64FVSSIG_SO8 to W25Q64FVSSIQ_SO8
HLZ SIV 0811
RH119
SPI_CLK_PCH_0 1 2
10_0402_5% 1
EMC_NS@
CH11
10P_0402_50V8J
2 EMC_NS@

Delete socket
Delete socket

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (5/9) SPI,SMBUS,GPPBEGH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 18 of 75

5 4 3 2 1
 5 4 3 2 1

D D

UH1B SPT-H_PCH
DMI_CTX_PRX_N0 L27
5 DMI_CTX_PRX_N0 DMI_RXN0
DMI_CTX_PRX_P0 N27 AF5 USB20_N0
5 DMI_CTX_PRX_P0 DMI_RXP0 USB2N_1 USB20_N0 50
DMI_CRX_PTX_N0 C27 AG7 USB20_P0
5 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 B27 DMI_TXN0 USB2P_1 AD5 USB20_N1 USB20_P0 50 RIGHT USB (2.0)
5 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_TXP0 USB2N_2 USB20_P1 USB20_N1 47
5 DMI_CTX_PRX_N1 E24 AD7 LEFT USB (3.0)
DMI_CTX_PRX_P1 DMI_RXN1 USB2P_2 USB20_N2 USB20_P1 47
5 DMI_CTX_PRX_P1 G24 AG8
DMI_CRX_PTX_N1 DMI_RXP1 USB2N_3 USB20_P2 USB20_N2 47
B28 AG10 LEFT USB (3.0)
5 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_TXN1 USB2P_3 USB20_P2 47
A28 AE1
5 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_TXP1 USB2N_4 TYPE-C_PCH_USB20_N4 38
5 DMI_CTX_PRX_N2 G27 DMI AE2 Type C
DMI_CTX_PRX_P2 DMI_RXN2 USB2P_4 TYPE-C_PCH_USB20_P4 38
5 DMI_CTX_PRX_P2 E26 AC2
DMI_CRX_PTX_N2 B29 DMI_RXP2 USB2N_5 AC3
5 DMI_CRX_PTX_N2 DMI_TXN2 USB2P_5
Del TS HLZ SDV 20160510
DMI_CRX_PTX_P2 C29 AF2 USB20_N6
5 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_TXP2 USB2N_6 USB20_P6 USB20_N6 35
5 DMI_CTX_PRX_N3 L29 AF3 Camera
DMI_CTX_PRX_P3 DMI_RXN3 USB2P_6 USB20_P6 35
5 DMI_CTX_PRX_P3 K29 AB3
DMI_CRX_PTX_N3 B30 DMI_RXP3 USB 2.0
USB2N_7 AB2
5 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI_TXN3 USB2P_7
A30 AL8 Some PCH config not support USB port 6 & 7.
5 DMI_CRX_PTX_P3 DMI_TXP3 USB2N_8 AL7
RH741 1100_0402_1%
2 PCIE_RCOMN USB2P_8
CAD Note: B18
PCIE_RCOMPN USB2N_9
AA1 Del XBOX & Anti-ghost HLZ SDV 20160510
Trace width=15 mils,Spacing=15mil PCIE_RCOMP C17 AA2
PCIE_RCOMPP USB2P_9 AJ8 1 PAD @
Max length= N/A mils. USB2N_10 TH28 Debug port, reserved test point
C AJ7 1 PAD @ C
USB2P_10 USB20_N10 TH29
H15 W2
PCIE1_RXN/USB3_7_RXN USB2N_11 USB20_P10 USB20_N10 45
G15 W3 Buletooth
PCIE1_RXP/USB3_7_RXP USB2P_11 USB20_P10 45
A16 AD3
B16 PCIE1_TXN/USB3_7_TXN USB2N_12 AD2

PCIe/USB 3
CH2401 2 .1U_0402_10V6-K PCIE_PTX_DRX_N2 B19 PCIE1_TXP/USB3_7_TXP USB2P_12 V2
43 PCIE_PTX_C_DRX_N2 PCIE_PTX_DRX_P2 PCIE2_TXN/USB3_8_TXN USB2N_13
Cardreader CH2411 2 .1U_0402_10V6-K C19 V1
43 PCIE_PTX_C_DRX_P2 PCIE_PRX_DTX_N2 PCIE2_TXP/USB3_8_TXP USB2P_13
43 PCIE_PRX_DTX_N2 E17 AJ11
PCIE_PRX_DTX_P2 G17 PCIE2_RXN/USB3_8_RXN USB2N_14 AJ13
43 PCIE_PRX_DTX_P2 PCIE2_RXP/USB3_8_RXP USB2P_14
PCIE_PRX_DTX_N3 L17
45 PCIE_PRX_DTX_N3 PCIE3_RXN/USB3_9_RXN
PCIE_PRX_DTX_P3 K17
45 PCIE_PRX_DTX_P3 PCIE3_RXP/USB3_9_RXP
WLAN 45 PCIE_PTX_C_DRX_N3
CH17 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 B20
PCIE3_TXN/USB3_9_TXN
CH18 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 C20 AD43 USB_OC0#
45 PCIE_PTX_C_DRX_P3 PCIE_PRX_DTX_N4 PCIE3_TXP/USB3_9_TXP GPP_E9/USB2_OC0# USB_OC1#
50 PCIE_PRX_DTX_N4 E20 AD42 USB 3.0
PCIE_PRX_DTX_P4 PCIE4_RXN/USB3_10_RXN GPP_E10/USB2_OC1# USB_OC2# USB_OC1# 47
50 PCIE_PRX_DTX_P4 G19 AD39 USB 2.0
PCIE_PTX_DRX_N4 PCIE4_RXP/USB3_10_RXP GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 50
LAN CH15 1 2 .1U_0402_10V6-K B21 AC44 TypeC
50 PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PCIE4_TXN/USB3_10_TXN GPP_E12/USB2_OC3# USB_OC4# USB_OC3# 38
CH16 1 2 .1U_0402_10V6-K A21 Y43
50 PCIE_PTX_C_DRX_P4 PCIE4_TXP/USB3_10_TXP GPP_F15/USB2_OCB_4 USB_OC5#
K19 Y41
L19 PCIE5_RXN GPP_F16/USB2_OCB_5 W44 USB_OC6#
D22 PCIE5_RXP GPP_F17/USB2_OCB_6 W43 USB_OC7#
C22 PCIE5_TXN GPP_F18/USB2_OCB_7 Within 500 mils
G22 PCIE5_TXP
E22 PCIE6_RXN AG3 USB2_ COMP
B22 PCIE6_RXP USB2_COMP AD10
PCIE6_TXN USB2_VBUSSENSE
Thunderbolt A23
PCIE6_TXP RSVD_AB13
AB13
L22 AG2
x 4 PCIE7_RXN USB2_ID

2
K22
PCIE7_RXP

2
C23 RC182 RH127
B23 PCIE7_TXN RC183
PCIE7_TXP 1K_0402_5% 113_0402_1%
K24 BD14 1K_0402_5%
L24 PCIE8_RXN GPD7/RSVD
PCIE8_RXP

1
HLZ SDV 20160510 C24
PCIE8_TXN

1
B B24 B
PCIE8_TXP 2 OF 12

SKYLAKE-H-PCH_FCBGA837
@
+3VALW_PCH
RPH5

USB_OC4# 4 5
USB_OC7# 3 6
USB_OC6# 2 7
USB_OC3# 1 8

10K_1206_8P4R_5%
RPH6
USB_OC0# 4 5
USB_OC5# 3 6
USB_OC2# 2 7
USB_OC1# 1 8

10K_1206_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (5/9) DMI, PCIe, USB2, GPPEF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 19 of 75
5 4 3 2 1
 5 4 3 2 1

GSPI1_MOSI / GPP_B22 Bit 6 Boot BIOS

This field determines the destination of accesses to the Destination
+3VS BIOS memory range. Also controllable using Boot BIOS
Destination bit (Bus0, Device31, Function0, offset BCh, 0 SPI (Default)
RH160 2 1 10K_0402_5% PCH_BT_OFF# bit 6).
RH161 2 1 10K_0402_5% PCH_W LAN_OFF#
1 LPC

+3VALW _PCH SKU ID +3VALW +3VALW_PCH

UH1K SPT-H_PCH
RH750
1 @ 2 4.7K_0402_5% AT29
PCH_W LAN_OFF# AR29 GPP_B22/GSPI1_MOSI AL44 PCH_GPD9 RH152 RH155 RH153 RH163 RH774 RH776 RH778
D 45 PCH_W LAN_OFF# GPP_B21/GSPI1_MISO GPP_D9 PCH_GPD10 D
AV29 AL36
GPP_B20/GSPI1_CLK GPP_D10

1 NOBL@ 2

2
BC27 AL35 PCH_GPD11
Delete PCH_TS_ON# signal

10K_0402_5%

10K_0402_5%
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
GPP_B19/GSPI1_CS# GPP_D11 AJ39 PCH_GPD12
HLZ SDV 0606 GPP_B18_NO_REBOOT BD28 GPP_D12

1060M@
@ @ @ @
42 GPP_B18_NO_REBOOT GPP_B18/GSPI0_MOSI
BD27 AJ43
50 LAN_PW R_ON# GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
AW27 AL43
GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#

1
AR24 AK44
GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45
EC_SCI# @ GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA PCH_GPD9
14,49 EC_SCI# RH780 1 2 0_0402_5% AV44
PCH_BT_OFF# BA41 GPP_C9/UART0_TXD PCH_GPD10
45 PCH_BT_OFF# GPP_C8/UART0_RXD PCH_GPD11
AU44
AV43 GPP_C11/UART0_CTS# PCH_GPD12
Delete 3D_FR & PCH_CMOS_ON signal GPP_C10/UART0_RTS#
HLZ SDV 0606 AU41
GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL
BC38 PCH_GPA23
AT44 BB38 PCH_GPA22
AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA PCH_GPA21
24,27 VGA_PW RGD GPP_C13/UART1_TXD/ISH_UART1_TXD
2 1 VGA_ALERT_PCH# AU43 BD38
27 VGA_ALERT# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL
DV5 RB751V-40_SOD323-2 BE39 RH195
AN43 GPP_H21/ISH_I2C1_SDA RH157 RH158 RH159 RH775 RH777 RH779
@ GPP_C23/UART2_CTS#
AN44
GPP_C22/UART2_RTS#

2
PCH_UART2_TXD AR39

10K_0402_5%

10K_0402_5%
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
45 PCH_UART2_TXD PCH_UART2_RXD GPP_C21/UART2_TXD PCH_GPA23
AR45 BC22
45 PCH_UART2_RXD GPP_C20/UART2_RXD GPP_A23/ISH_GP5 PCH_GPA22

1 BL@
BD18

1050M@
@ @ @ @
PCH_GPIO52 AR41 GPP_A22/ISH_GP4 BE21 PCH_GPA21
Change RC10 from 1K to 0ohm HLZ SIV 0811 27 PCH_GPIO52 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
PXS_PWREN RC10 1 OPT@ 2 0_0402_5% PXS_PW REN_R AR44 BD22
27,28,70 PXS_PWREN GPP_C18/I2C1_SDA GPP_A20/ISH_GP2

1
PXS_RST# RC12 1 2 0_0402_5% PXS_RST#_R AR38 BD21
27 PXS_RST# PCH_GPIO53 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1
AT42 BB22
27 PCH_GPIO53 GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19
AM44 GPP_A17/ISH_GP7
AJ44 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL 11 OF 12
1

D
RC170 1 @ 2 2 QC13 SKYLAKE-H-PCH_FCBGA837
49 VGA_GATE# G
0_0402_5% 2N7002KW _SOT323-3 @
@
CC96
1
S 1. Add KB BL GPIO
3

C
.1U_0402_10V6-K
@ 2. Delete DZ510 / DY512 BOM structure C
2
HLZ SIT 0923

Function PCH_GPD9 PCH_GPD10 PCH_GPD11 PCH_GPD12 PCH_GPD21 PCH_GPD22 PCH_GPD23

DY512 X X X X XX X

DZ510 X X X X X X X

NV 1050M X 0 X X X X X

NV 1060M X 1 X X X X X

KB BL X X 0 X X X X

No KB BL X X 1 X X XX

PCIE SSD X X X 0 X XX

B Optane memory XXX X 1 X X B

RSV X X X X X X X

RSV XXXX XXX

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (6/9) GPPPABCD, I2C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 20 of 75
5 4 3 2 1
 5 4 3 2 1

+1.0VALW +VCCPRIM_1P0
Need short 4A
+1.0VALW 4A 1
JC2
1 2
2

+3VALW 0.225A JUMP_43X79

@

+3VALW_PCH 1.222A +VCCPRIM_1P0

Need short +1.0VS_VCCMPHY 0.885A
JC3 Total 0.685A
1 2
1 2 +3VS +3VALW _PCH
D D
JUMP_43X79
@

2
RH759 RH760
0_0805_5% 0_0805_5%
@

1
+VCCPFUSE_3P3
+VCCPRIM_1P0 Total 0.117A
UH1H SPT-H_PCH
RH220 1 2 0_0402_5%
Total 2.899A AA23 +VCCPRIM_1P0
AA26 VCCPRIM_1P0_1 +VCCPGPPD layout requirement RH760 do not change to R short
AA28 VCCPRIM_1P0_2 AL22 Total 2.899A
0.078A
AC23 VCCPRIM_1P0_3 VCCPRIM_1P0_17 1 2 0_0402_5%

CORE
RH221
AC26 VCCPRIM_1P0_4 BA24 Total 0.195A
VCCPRIM_1P0_5 VCCDSW_3P3_2 +VCCDSW +VCCPGPPA
AC28 BA31 0.082A +VCCPGPPA 0.082A
VCCPRIM_1P0_6 VCCPGPPA

VCCGPIO
AE23
AE26 VCCPRIM_1P0_7 BC42 0.229A RH222 1 2 0_0402_5%
VCCPRIM_1P0_8 VCCPGPPBCH_1 +VCCPGPPBCH
Y23 BD40
CH25 VCCPRIM_1P0_9 VCCPGPPBCH_2 +VCCPGPPBCH
Y25 AJ41 0.114A +VCCPGPPEF 0.229A
+VCCPRIM_1P0 1 2 DCPDSW _1P0 BA29 VCCPRIM_1P0_10 VCCPGPPEF_1 AL41
1U_0402_6.3V6K DCPDSW_1P0 VCCPGPPEF_2 AD41 0.065A RH223 1 2 0_0402_5%
VCCPGPPG +VCCPGPPG
N17 AN5 Total 0.117A +VCCPRIM_3P3 +VCCPRIM_1P0
R19 VCCCLK1_1 VCCPRIM_3P3 +VCCPGPPEF
0.242A U20 VCCCLK3_2 0.114A
V17 VCCCLK4_3 AD15 Total 2.899A RH224 1 2 0_0402_5%
R17 VCCCLK2_4 VCCPRIM_1P0_15 AD13 0.007A
VCCCLK2_5 VCCATS +V3.3A_VCCATS +VCCPGPPG
K2 BA20 0.35mA +VCCPRTCPRIM 0.065A
K3 VCCCLK5_6 VCCRTCPRIM_3P3 BA22 0.35mA
VCCCLK5_7 VCCRTC +VCCRTC_3P3
+1.0VS_VCCMPHY BA26 DCPRTC RH225 1 2 0_0402_5%
DCPRTC
2

.1U_0402_10V6-K
700mA U21 AJ20 +VCCPRIM_3P3
U23 VCCMPHY_1P0_1 VCCPRIM_1P0_11 AJ21 +VCCPRIM_1P0 Total 0.117A

MPHY

CH26
U25 VCCMPHY_1P0_2 VCCPRIM_1P0_12 AJ23 RH226 1 2 0_0402_5%
C C
+1.0VS_VCCMPHY +1.0VS_VCCMPHYPLL U26 VCCMPHY_1P0_3 VCCPRIM_1P0_13 AJ25 Total 2.899A 1
V26 VCCMPHY_1P0_4 VCCPRIM_1P0_14
RH199 1 2 0_0402_5% 0.08A+0.03A=0.11A A43 VCCMPHY_1P0_5
B43 VCCMPHYPLL_1P0_1 BE41 +3V_SPI
+1.0VS_VCCAPLLEBB C44 VCCMPHYPLL_1P0_2 VCCSPI_1 BE43
C45 VCCPCIE3PLL_1P0_1 VCCSPI_2 BE42 0.029A +VCCPRTCPRIM
VCCPCIE3PLL_1P0_2 VCCSPI_3 BC44
0.35mA
RH200 1 2 0_0402_5% 0.075A V28 VCCPGPPD_1 BA45 +VCCPGPPD RH746 1 2 0_0402_5%
AC17 VCCAPLLEBB_1P0 VCCPGPPD_2 BC45

USB
+VCCPRIM_1P0 Total 2.899A
VCCPRIM_1P0_16 VCCPGPPD_3

1U_0402_6.3V6K
+VCCUSBPLL_1P0 0.012A AJ5 BB45 0.078A
AL5 VCCUSB2PLL_1P0_1 VCCPGPPD_4
VCCUSB2PLL_1P0_2 1
0.033A AN19 BD3 +VCCPFUSE_3P3
+VCCHDAPLL_1P0 VCCHDAPLL_1P0 VCCPRIM_3P3_1
BA15 BE3

CH23
+VCCHDA 0.06A
Total 0.195A W15 VCCHDA VCCPRIM_3P3_2 BE4 Total 0.117A
+VCCDSW VCCDSW_3P3_1 VCCPRIM_3P3_3 2
8 OF 12

SKYLAKE-H-PCH_FCBGA837
@

+V3.3A_VCCATS +3VS +3VALW_PCH

0.007A
+VCCPRIM_1P0 0_0402_5% 1 2 RH219
+1.0VS_VCCMPHYPLL +1.0VS_VCCMPHY
NEAR PCH PIN NEAR
K2 0_0402_5% 1 @ 2 RH11
CH254
22U_0603_6.3V6-M

CH253
22U_0603_6.3V6-M

1U_0402_6.3V6K

1 1 1
CH257
22U_0603_6.3V6-M

CH256
22U_0603_6.3V6-M

1U_0402_6.3V6K

CH29
22U_0603_6.3V6-M

1U_0402_6.3V6K

1 1 1 1 1
CH22
CH255

CH30

2@ 2@ 2 +VCCPGPPA
@
2@ 2@ 2 2 2
@
+VCCPFUSE_3P3 +VCCPGPPD +VCCPRIM_3P3 +VCCPGPPG +VCCPGPPEF +VCCPGPPBCH +V3.3A_VCCATS

.1U_0402_10V6-K

.1U_0402_10V6-K
B 1 1 B

CH260

CH261

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K
1
@ @ 1 1 1 1 1 1

CH262

CH20

CH243

CH82

CH81

CH28

CH36
NEAR 2 2
NEAR
BA31 BA31 @ @ @ @
2
2 2 2 2 2 2
75ohm@100Mhz 200mA
+VCCPRIM_1P0
+VCCUSBPLL_1P0 +3VALW +VCCHDA

RH203 1 2 0_0805_5% LH1 +3VALW _PCH +VCCDSW VCCRTC +VCCRTC_3P3

1 2
+3VALW 1 2 0_0402_5%
1U_0402_6.3V6K

+VCCHDAPLL_1P0 1 BLM15GA750SN1D_2P RH216

LH2 +3VS RH206 1 @ 2 0_0402_5%
1 2
CH258

1U_0402_6.3V6K

.1U_0402_10V6-K
BLM15GA750SN1D_2P LH3 RH205 1 2 0_0402_5% 1 1
2 1 2
1U_0402_6.3V6K

CH245
1

CH244
75ohm@100Mhz 200mA BLM15GA750SN1D_2P 2 2
CH259

@ 2 2
CH248 CH80
2
.1U_0402_10V6-K 1U_0402_6.3V6K
1 1
@

Change CH248 from @ to stuff due to power noise test fail

HLZ SIV 0811

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 21 of 75
5 4 3 2 1
 5 4 3 2 1

UH1I SPT-H_PCH
UH1L SPT-H_PCH

AC18 AR5
C42 AB11 AN4 VSS_1 VSS_75 AR7
D10 VSS_149 VSS_217 AB7 AN10 VSS_2 VSS_76 U15
D12 VSS_150 VSS_218 AB14 BE14 VSS_3 VSS_77 AL4
D15 VSS_151 VSS_219 AB31 BE18 VSS_4 VSS_78 AE29
D16 VSS_152 VSS_220 AB32 BE23 VSS_5 VSS_79 AE4
D17 VSS_153 VSS_221 AB38 BE28 VSS_6 VSS_80 AE42
D19 VSS_154 VSS_222 AB4 BE32 VSS_7 VSS_81 AF18 UH1J SPT-H_PCH
D D21 VSS_155 VSS_223 AB5 BE37 VSS_8 VSS_82 AF20 D
D24 VSS_156 VSS_224 AC1 BE40 VSS_9 VSS_83 AF21
D25 VSS_157 VSS_225 AC20 BE9 VSS_10 VSS_84 AF23
D27 VSS_158 VSS_226 AC21 C10 VSS_11 VSS_85 AF25 BD2 AR22
D29 VSS_159 VSS_227 AC25 C2 VSS_12 VSS_86 AF26 BD45 VSS_286 RSVD_7 W13
D30 VSS_160 VSS_228 AC29 C28 VSS_13 VSS_87 AF28 BD44 VSS_287 RSVD_8 U13
D31 VSS_161 VSS_229 AC45 C37 VSS_14 VSS_88 AF29 BE44 VSS_288 RSVD_9 P31
D33 VSS_162 VSS_230 AB8 J7 VSS_15 VSS_89 AG11 D45 VSS_289 RSVD_10 N31
D35 VSS_163 VSS_231 AD11 K10 VSS_16 VSS_90 AG13 A42 VSS_290 RSVD_11
D36 VSS_164 VSS_232 AD14 K27 VSS_17 VSS_91 AG31 B45 VSS_291 P27
E13 VSS_165 VSS_233 AB15 K33 VSS_18 VSS_92 AG32 B44 VSS_292 RSVD_12 R27
E15 VSS_166 VSS_234 AD32 K36 VSS_19 VSS_93 AG33 A4 VSS_293 RSVD_13 N29
E31 VSS_167 VSS_235 AD33 K4 VSS_20 VSS_94 AG38 A3 VSS_294 RSVD_14 P29
E33 VSS_168 VSS_236 AD36 K42 VSS_21 VSS_95 AG4 B2 VSS_295 RSVD_15 AN29
F44 VSS_169 VSS_237 AD4 K43 VSS_22 VSS_96 AH1 A2 VSS_296 RSVD_16 R24
F8 VSS_170 VSS_238 AD8 L12 VSS_23 VSS_97 AH17 B1 VSS_297 RSVD_17 P24
G42 VSS_171 VSS_239 AE18 L13 VSS_24 VSS_98 AH18 BB1 VSS_298 RSVD_18
G9 VSS_172 VSS_240 AE20 L15 VSS_25 VSS_99 AH20 BC1 VSS_299 AT3
VSS_173 VSS_241 VSS_26 VSS_100 VSS_300 PREQ# PCH_PREQ# 42
H17 AE21 L4 AH21 A44 AT4
VSS_174 VSS_242 VSS_27 VSS_101 VSS_301 PRDY# PCH_PRDY# 42
H19 AE25 L41 AH23 AY5
VSS_175 VSS_243 VSS_28 VSS_102 CPU_TRST# CPU_TRST# 42
H22 AE28 L8 AH25 C1 AL2 PCH_TRIGOUT RH7581 2 30_0402_1% CPU_TRIGIN 6
H24 VSS_176 VSS_244 AL10 M35 VSS_29 VSS_103 AH26 D1 RSVD_5 PCH_TRIGOUT AK1
VSS_177 VSS_245 VSS_30 VSS_104 RSVD_6 PCH_TRIGIN PCH_TRIGIN 6
H27 AL11 M42 AH28
H29 VSS_178 VSS_246 AL13 N10 VSS_31 VSS_105 AH29 10 OF 12
C
H3 VSS_179 VSS_247 AL17 N15 VSS_32 VSS_106 AH45
C

H35 VSS_180 VSS_248 AL19 N19 VSS_33 VSS_107 AJ10 SKYLAKE-H-PCH_FCBGA837

J10 VSS_181 VSS_249 AL24 N22 VSS_34 VSS_108 AJ14
VSS_182 VSS_250 VSS_35 VSS_109 @
J11 AL29 N24 AJ15
J3 VSS_183 VSS_251 AL32 N35 VSS_36 VSS_110 AJ17
J39 VSS_184 VSS_252 AL33 N36 VSS_37 VSS_111 AJ18
J5 VSS_185 VSS_253 AL38 N4 VSS_38 VSS_112 AJ26
T42 VSS_186 VSS_254 AM15 N41 VSS_39 VSS_113 AJ28
U10 VSS_187 VSS_255 AM17 N5 VSS_40 VSS_114 AJ29
U11 VSS_188 VSS_256 AM19 P17 VSS_41 VSS_115 AJ31
U14 VSS_189 VSS_257 AM22 P19 VSS_42 VSS_116 AJ32 PCH_TRIGIN .1U_0402_10V6-K CH8 1 2 @
U17 VSS_190 VSS_258 AM24 P22 VSS_43 VSS_117 AJ36
U18 VSS_191 VSS_259 AM27 P45 VSS_44 VSS_118 AK4
U28 VSS_192 VSS_260 AM29 R10 VSS_45 VSS_119 AK42
U29 VSS_193 VSS_261 AM45 R14 VSS_46 VSS_120 AU7
U31 VSS_194 VSS_262 AN11 R22 VSS_47 VSS_121 AV17
U32 VSS_195 VSS_263 AN22 R29 VSS_48 VSS_122 AV24
Reserved Cap HLZ SDV 0616
U33 VSS_196 VSS_264 AN27 R33 VSS_49 VSS_123 AV27
U38 VSS_197 VSS_265 AN31 R38 VSS_50 VSS_124 AV31
U4 VSS_198 VSS_266 AN39 R5 VSS_51 VSS_125 AV33
U8 VSS_199 VSS_267 AN7 T1 VSS_52 VSS_126 AV6
V18 VSS_200 VSS_268 AN8 T2 VSS_53 VSS_127 AW13
V20 VSS_201 VSS_269 AP11 T4 VSS_54 VSS_128 AW19
V21 VSS_202 VSS_270 AP4 Y18 VSS_55 VSS_129 AW29
B B
V23 VSS_203 VSS_271 AR33 Y20 VSS_56 VSS_130 AW37
V25 VSS_204 VSS_272 AR34 Y21 VSS_57 VSS_131 AW9
V29 VSS_205 VSS_273 AR42 Y26 VSS_58 VSS_132 AY38
V3 VSS_206 VSS_274 AR9 Y28 VSS_59 VSS_133 AY45
V45 VSS_207 VSS_275 AT10 Y29 VSS_60 VSS_134 B25
W14 VSS_208 VSS_276 AT15 A18 VSS_61 VSS_135 B3
W31 VSS_209 VSS_277 AT36 A25 VSS_62 VSS_136 B37
W32 VSS_210 VSS_278 AT9 A32 VSS_63 VSS_137 B40
W33 VSS_211 VSS_279 AU1 A37 VSS_64 VSS_138 B6
W38 VSS_212 VSS_280 AU35 AA17 VSS_65 VSS_139 BA1
W4 VSS_213 VSS_281 AU36 AA18 VSS_66 VSS_140 BB11
W8 VSS_214 VSS_282 AU39 AA20 VSS_67 VSS_141 BB16
Y17 VSS_215 VSS_283 AU45 AA21 VSS_68 VSS_142 BB21
VSS_216 VSS_284 C4 AA25 VSS_69 VSS_143 BB25
VSS_285 AA29 VSS_70 VSS_144 BB30
AA4 VSS_71 VSS_145 BB34
AA42 VSS_72 VSS_146 BC2
12 OF 12 AB10 VSS_73 VSS_147 BD43
VSS_74 VSS_148
SKYLAKE-H-PCH_FCBGA837 9 OF 12
@ SKYLAKE-H-PCH_FCBGA837
@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 22 of 75
5 4 3 2 1
 5 4 3 2 1

STRAP2 STRAP1 STRAP0 RAMCFG[4:0] H=High: Tied to 1.8V

N17P-G1 GPIO M=Middle: Tied to 0.9V
L L L 00000
L=Low: Tied to 0V
GPIO I/O ACTIVE Function Description I/O Termination L H L 00010

GPIO0 OUT - PWM Output to control NVVDD L H H 00011

GPIO1 OUT - FB Enable for GC6 2.1 H H L 00110

GPIO2 IN - GPU wake signal for GC6 2.1 H H H 00111

D D

GPIO3 OUT - PWM Output to control the SRAM power supply

ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE
GPIO4 OUT - GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
L L L 1111 DEFAULT SOR0/1/2/3 ENABLE
GPIO5 IN N/A Active low Frame Lock
L L H 1110
GPIO6 OUT - Phase Shedding, NVVDD_PSI
L H L 1101
GPIO7 OUT N/A Panel Backlight enable
L H H 1100
GPIO8 OUT - Memory voltage Control
H L L 1011
GPIO9 I/O - Active Low Thermal Alert
H L H 1010
GPIO10 OUT - Memory VREF Control (100K pull Down)
H H L 1001
GPIO11 OUT - Panel Power enable
H H H 1000
GPIO12 IN - AC power detect or power supply overdraw input (10K pull High)
L L M 0111
GPIO13 OUT N/A LCD Panel Backlight Enable
L M L 0110
GPIO14 IN N/A Hot Plug Detect for IFPA
L M H 0101
C GPIO15 IN N/A Hot Plug Detect for IFPB C

L H M 0100
GPIO16 OUT - System side PCIe reset monitor
H L M 0011
GPIO17 IN N/A Hot Plug Detect for IFPD
H M L 0010
GPIO18 IN N/A Hot Plug Detect for IFPE
H M H 0001
GPIO19 OUT N/A 3D Vision L/R Signal
H H M 0000
GPIO20 N/A GC5_MODE

GPIO21 I/O N/A UNUSED

1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO22 I/O N/A UNUSED 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO23 OUT - GPU PCIe self-reset control 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO24 IN N/A Hot Plug Detect for IFPF
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO25 N/A UNUSED
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO26 N/A UNUSED
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
GPIO27 IN N/A Hot Plug Detect for IFPC 0:VGA_DEVICE DISABLE
B B
L M H 1 0 1 0

L M L 1 0 0 1

L L M 1 0 0 0

H H H 0 1 1 1
N17P-G1 Power Sequence
H H L 0 1 1 0

H L H 0 1 0 1

H L L 0 1 0 0

+1.8VS_AON NVVDDS/+1.0VGS L H H 0 0 1 1

+1.8VGS L H L 0 0 1 0
NVVDD
NVVDD L L H 0 0 0 1 DEFAULT

NVVDDS/+1.0VGS L L L 0 0 0 0

FBVDDQ

A A
1. All power rail ramp up time should be larger than 40us 1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
and is recommended to be less than 2ms. other power rails can ramp down together with NVVDD.
2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood) 2. All 3.3V devices that connect to the GPU must be
must NOT exceed 4ms. ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.
3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V 3. The previous power rail must ramp down to 10% before
leakage path before 1V8_AON present. the next power rail can start ramping down.
Security Classification LC Future Center Secret Data Title
4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.
Issued Date 2015/02/26 Deciphered Date 2016/02/26 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
DY512
Date: Friday, November 25, 2016 Sheet 23 of 75
5 4 3 2 1
 5 4 3 2 1

UV1A
1/17 PCI_EXPRESS
3A
D +1.0VGS D
2000mA
Under GPU(below 150mils) Near GPU Mid way
PEX_DVDD AG19
PLT_RST_VGA# AJ12 AG21

33P_0402_50V8J

33P_0402_50V8J
22U_0603_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
27 PLT_RST_VGA# PEX_RST PEX_DVDD 1 1 1 1 1 1 2 1 1 1
PEX_DVDD AG22
CLK_REQ_GPU# AK12 AG24
PEX_CLKREQ PEX_DVDD
AH21

RF_NS@
RF_NS@
PEX_DVDD
CLK_PCIE_GPU 2 2 2 2 2 2 1 2 2 2

OPT@
OPT@

OPT@

OPT@

OPT@
17 CLK_PCIE_GPU AL13 PEX_REFCLK PEX_DVDD AH25
CLK_PCIE_GPU#

OPT@

OPT@

OPT@
AK13

CV5
CV2

CV3

CV4

CV6

CV7

CV8

CV14

CD85

CD86
17 CLK_PCIE_GPU# PEX_REFCLK
PCIE_CRX_GTX_P0 CV12 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P0 AK14
5 PCIE_CRX_GTX_P0 PEX_TX0
PCIE_CRX_GTX_N0 CV13 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_N0 AJ14
5 PCIE_CRX_GTX_N0 PEX_TX0
PCIE_CTX_C_GRX_P0 AN12
5
5 PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N0 AM12
PEX_RX0
PEX_RX0 PEX_HVDD
PEX_HVDD
AG13
AG15
Near GPU 1A
PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P1 AH14 AG16
5 PCIE_CRX_GTX_P1 PEX_TX1 PEX_HVDD
PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_N1 AG14 AG18 VGA_MAIN_1.05V_1.8V VGA_MAIN_3V_1.8V
5 PCIE_CRX_GTX_N1 PEX_TX1 PEX_HVDD
PEX_HVDD AG25 Under GPU(below 150mils) Near GPU Mid way
PCIE_CTX_C_GRX_P1 AN14 AH15
5 PCIE_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD

2
PCIE_CTX_C_GRX_N1 AM14 AH18

10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
5 PCIE_CTX_C_GRX_N1 PEX_RX1 PEX_HVDD 1 1 1 1 1 1 2 2 1

22U_0603_6.3V6-M
PEX_HVDD AH26 RV29
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P2 AK15 AH27 0_0402_5%
5 PCIE_CRX_GTX_P2 PEX_TX2 PEX_HVDD
PCIE_CRX_GTX_N2 CV23 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_N2 AJ15 AJ27
5 PCIE_CRX_GTX_N2 PEX_TX2 PEX_HVDD
2 2 2 2 2 2 1 1 2 When VGA_PWRGD is work, CV66 is 100K

OPT@
OPT@

OPT@

OPT@
AK27 OPT@

OPT@
PEX_HVDD

1
PCIE_CTX_C_GRX_P2 AP14 VGA_MAIN_3V_1.8V

OPT@

OPT@

OPT@

OPT@
AL27 RV8 VGA_AON_3V_1.8V

CV303

CV302

CV304

CV305

CV306

CV307

CV9

CV10
5 PCIE_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD

CV18
PCIE_CTX_C_GRX_N2 AP15 AM28 1 2
5 PCIE_CTX_C_GRX_N2 PEX_RX2 PEX_HVDD 20,27 VGA_PWRGD
PEX_HVDD AN28

2
PCIE_CRX_GTX_P3 CV24 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P3 AL16 75K_0402_5%
5 PCIE_CRX_GTX_P3 PEX_TX3 1
PCIE_CRX_GTX_N3 PCIE_CRX_C_GTX_N3 AK16

2
5 PCIE_CRX_GTX_N3 CV25 1 2 0.22U_0402_10V6K OPT@ PEX_TX3 @ CV66
.1U_0402_10V6-K
PCIE_CTX_C_GRX_P3 AN15 @

10K_0402_5%
10K_0402_5%
5 PCIE_CTX_C_GRX_P3 PEX_RX3
PCIE_CTX_C_GRX_N3 AM15 2
5 PCIE_CTX_C_GRX_N3 PEX_RX3

1
1
PCIE_CRX_GTX_P4 PCIE_CRX_C_GTX_P4 AK17

OPT@
CV26 1 2 0.22U_0402_10V6K

RV31
OPT@

RV30
5 PCIE_CRX_GTX_P4 PEX_TX4
PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_N4 AJ17 @
5 PCIE_CRX_GTX_N4 PEX_TX4
MAX:100mA

2
PCIE_CTX_C_GRX_P4 AN17

G
5 PCIE_CTX_C_GRX_P4 PEX_RX4
PCIE_CTX_C_GRX_N4 AM17
5 PCIE_CTX_C_GRX_N4 PEX_RX4
1 3 CLK_REQ_GPU#
PCIE_CRX_GTX_P5 PCIE_CRX_C_GTX_P5 AH17 VGA_MAIN_3V_1.8V 17 GPU_CLKREQ#
CV28 1 2 0.22U_0402_10V6K OPT@ PEX_TX5 Near GPU

S
5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_C_GTX_N5 AG17
5 PCIE_CRX_GTX_N5 CV29 1 2 0.22U_0402_10V6K OPT@ PEX_TX5 N17 1.8V
PEX_PLL_HVDD
PEX_PLL_HVDD AH12 RV7 1 2 0_0402_5% QV5
PCIE_CTX_C_GRX_P5 AP17 LBSS139WT1G_SC70-3

0.1U_0402_10V7K
5 PCIE_CTX_C_GRX_P5 PEX_RX5
PCIE_CTX_C_GRX_N5 AP18

2
5 PCIE_CTX_C_GRX_N5 PEX_RX5 1 LBSS139WT1G OPT@
Vds=50V RV33
PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P6 AK18 10K_0402_5%
5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_C_GTX_N6 AJ18
PEX_TX6 Vgs= +-20V
5 PCIE_CRX_GTX_N6 CV34 1 2 0.22U_0402_10V6K OPT@ PEX_TX6 N16 3.3V Vgs(th)=0.5V--1V 1 2 @
2

OPT@
C RV35 C

1
PCIE_CTX_C_GRX_P6 AN18 0_0402_5%

CV31
5 PCIE_CTX_C_GRX_P6 PEX_RX6
PCIE_CTX_C_GRX_N6 AM18 @
5 PCIE_CTX_C_GRX_N6 PEX_RX6
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_P7 AL19
5 PCIE_CRX_GTX_P7 PEX_TX7
PCIE_CRX_GTX_N7 CV36 1 2 0.22U_0402_10V6K OPT@ PCIE_CRX_C_GTX_N7 AK19
5 PCIE_CRX_GTX_N7 PEX_TX7
PCIE_CTX_C_GRX_P7 AN20
5 PCIE_CTX_C_GRX_P7 PEX_RX7
PCIE_CTX_C_GRX_N7 AM20
5 PCIE_CTX_C_GRX_N7 PEX_RX7

AK20 PEX_TX8
AJ20 PEX_TX8

AP20 PEX_RX8
AP21 PEX_RX8

AH20 PEX_TX9
AG20 PEX_TX9 CV33 1 2 .1U_0402_10V6-K
OPT@
AN21 PEX_RX9
AM21 PEX_RX9 CV37 1 2 .1U_0402_10V6-K
OPT@
AK21
AJ21
PEX_TX1 0 MAX:250mA CV32 1 2 .1U_0402_10V6-K
DG Require 0.1U *3Pcs
PEX_TX1 0
OPT@
AN23 PEX_RX10
AM23 PEX_RX10 CV16 1 2 .1U_0402_10V6-K
VGA_MAIN_1.05V_1.8V OPT@ UV1O
AL22 PEX_TX1 1 30 ohms @100MHz (ESR=0.05) 11/17 XTAL_PLL
AK22 PEX_TX1 1 VGA_AON_3V_1.8V
1 2 CORE_PLLVDD RV4 1 2 0_0603_5% CORE_PLLVDD_GPU AD8 XS_PL L VDD
AP23 LV1 RV9 1 2 0_0603_5% GPCPLL_VDD H26
PEX_RX11 GPCPLL_AVD D
AP24 SBK160808T-300Y-N RV10 1 2 0_0603_5% +SP_PLLVDD AE8

22U_0805_6.3V6M
PEX_RX11 SP_PL L VDD
OPT@

4.7U_0603_6.3V6K
1 1
+VID_PLLVDD

2
AK23 PEX_TX1 2 RV11 1 2 0_0603_5% AD7 VID_ PLLVDD
AJ23 PEX_TX1 2 RV211
10K_0402_5%
Change PEG from X16 to X8 2 2

OPT@
AN24 @

CV11
PEX_RX12
HLZ SDV 20160510

OPT@
AM24

CV15
PEX_RX12

1
AH23 PEX_TX1 3 XTALSSIN H1 XTAL_ SSIN XTAL_O UTBUFF J4 XTALOUT
AG23 PEX_TX1 3

2
AN26 PEX_RX13 RV14 XTAL_IN H3 XTAL_ IN XTAL _OUT H2
XTAL_OUT

1
AM26 PEX_RX13 10K_0402_5%
OPT@ N17P-G1_FCBGA908 RV46
AK24 PEX_TX1 4 COMMON RV209 10K_0402_5%

1
AJ24 PEX_TX1 4 ? 1 2 OPT@
INS44015163 10M_0402_5%

2
AP26 PEX_RX14 @ OPT@
B B
AP27 PEX_RX14

AL25 YV1
PEX_TX1 5
AK25 PEX_TX1 5
XTAL_IN 1 4
AN27 PEX_TERMP OSC1 GND2
PEX_RX15 PEX_TERMP AP29 1 2
AM27 RV34 2 3 XTAL_OUT
PEX_RX15 GND1 OSC2
2.49K_0402_1%
OPT@ 1 1
27MHZ_10PF_7V27000050
CV262 OPT@ CV263
N17P-G1_FCBGA908 12P_0402_50V8-J 12P_0402_50V8-J
INS44014387 OPT@ 2 2 OPT@
?
COMMON
@

Change CV262&CV263 from 10P to 12P

HLZ SIT 0921

+1.0VALW TO +1.0VGS

1 2
WRST# 49
RV20

VGA_AON_3V_1.8V
0_0402_5%
@
For SWG mode
1 2
H_THRMTRIP# 6,14
RV1
1

0_0402_5%
RV2 @
1
For UMA mode
choose one 10K_0402_5%
@
D
CV1
.1U_0402_10V6-K
2@
3
2

5 QV1B LBSS138LT1G
G LBSS138DW1T1G_SOT363-6 Vds=50V
S @ Id=200mA
4

D Rdson=Max10ohm
6

OVERT# 2 QV1A
Vgs= +-20V
27 OVERT# Vgs(th)=0.5V--1V
G LBSS138DW1T1G_SOT363-6
S @
1

A A

D
1

1
PLT_RST_VGA# 1 2 2 QV2
RV3 G LBSS139WT1G_SC70-3 CV20
0_0402_5% S @ .1U_0402_10V6-K
3

@ 2@
1
CV21
.1U_0402_10V6-K
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_PEG I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Frid ay, No vem be r 2 5 , 2 016 Sheet 24 of 75
5 4 3 2 1
 5 4 3 2 1

UV1L UV1M
5/17 IFPAB 7/17 IFPEF

DVI HDMI DP

SL/DL

TXC/TXC IFPA_L3 AN6

D AM6 DVI HDMI DP D
TXC/TXC IFPA_L3
AJ8 IFPAB_RSET
SL/DL

TXD0/0 IFPA_L2 AN3 IFPE_AUX_SDA AB4

TXD0/0 IFPA_L2 AP3 IFPE_AUX_SCL AB3
AB8 IFPEF_PLLVDD
AH8 IFPAB_PLLVDD
TXD1/1 IFPA_L1 AM5 IFPE_L3 AC5
TXC/TXC
TXD1/1 IFPA_L1 AN5 AD6 IFPEF_RSET IFPE_L3 AC4
TXC/TXC

IFPE_L2 AC3
TXD0/0
TXD2/2 IFPA_L0 AK6 IFPE_L2 AC2
TXD0/0
IFPA_L0 AL6
TXD2/2
IFPE TXD1/1 IFPE_L1 AC1
IFPE_L1 AD1
TXD1/1
IFPA_AUX_SDA AH6
IFPA_AUX_SCL AJ6 IFPE_L0 AD3
TXD2/2
IFPE_L0 AD2
TXD2/2

TXC IFPB_L3 AH9

TXC IFPB_L3 AJ9

AG8 IFP_IOVDD
TXD0/3 IFPB_L2 AP5
AG9 IFP_IOVDD TXD0/3 IFPB_L2 AP6

TXD1/4 IFPB_L1 AL7

TXD1/4 IFPB_L1 AM7 DVI HDMI DP

SL/DL

TXD2/5 IFPB_L0 AM8 AC7 IFP_IOVDD

TXD2/5 IFPB_L0 AN8 IFPF_AUX_SDA AF2
IFPF_AUX_SCL AF3
AC8 IFP_IOVDD
IFPB_AUX_SDA AL8
IFPB_AUX_SCL AK8 TXC IFPF_L3 AF1
TXC IFPF_L3 AG1

IFPF_L2 AD5
IFPAB TXD0/3
IFPF_L2 AD4
IFPF TXD0/3
C N17P-G1_FCBGA908 AF5 C
TXD1/4 IFPF_L1
INS44016733 TXD1/4 IFPF_L1 AF4
?
COMMON TXD2/5 IFPF_L0 AE4
@ TXD2/5 IFPF_L0 AE3

UV1N
N17P-G1_FCBGA908
INS44016874
6/17 IFPCD ?
COMMON
@

AF8 IFPCD_RSET
UV1K
4/17 NC

AC6 NC
AG10 NC
DP AG12 NC
DVI HDMI
AG26 NC
SL/DL AG7 NC
AF7 IFPCD_PLLVDD IFPC_AUX_SDA AG2 AJ11 NC
IFPC_AUX_SCL AG3 AJ26 NC
AJ28 NC
AJ4 NC
IFPC_L3 AG4 AJ5 NC
TXC/TXC
IFPC_L3 AG5 AK26 NC
TXC/TXC
AK9 NC
IFPC_L2 AH4 AL10 NC
IFPC TXD0/0
TXD0/0 IFPC_L2 AH3 AL11 NC
AL9 NC
IFPC_L1 AJ2 AM9 NC
TXD1/1
IFPC_L1 AJ3 AN2 NC
TXD1/1
AN9 NC
B AJ1 AP8 B
TXD2/2
IFPC_L0 NC
IFPC_L0 AK1 C15 NC
TXD2/2
D19 NC
D20 NC
D23 NC
D26 NC
V32 NC

N17P-G1_FCBGA908
INS44016610
?
AF6 IFP_IOVDD COMMON
DVI HDMI DP
SL/DL @
AG6 IFP_IOVDD IFPD_AUX_SDA AK2
IFPD_AUX_SCL AK3

TXC IFPD_L3 AK5

TXC IFPD_L3 AK4

IFPD_L2 AL4
IFPD TXD0/3
TXD0/3 IFPD_L2 AL3

TXD1/4 IFPD_L1 AM4

TXD1/4 IFPD_L1 AM3

TXD2/5 IFPD_L0 AM2

TXD2/5 IFPD_L0 AM1

N17P-G1_FCBGA908
INS44016480
A ? A
COMMON
@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_DIGITAL OUT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 25 of 75

5 4 3 2 1
 5 4 3 2 1

MAX:250mA MAX:250mA
30ohms (ESR=0.01) Bead +FB_PLLAVDD
VGA_MAIN_1.05V_1.8V
P/N;SM010007W00
200mA GDDR5
1 2 +FB_PLLAVDD
LV7 Mode H - Mirror Mode Mapping
SBK160808T-300Y-N
OPT@
DATA Bus
Place close to BGA
UV1C Address 0..31 32..63
INS44017657
? FBx_CMD0 CS#
COMMON
D D
3/17 FBB FBx_CMD1 A3_BA3
UV1B FBx_CMD2 A2_BA0
INS44018303
32,33 FBC_D[0..63]
?
FBC_D0
FBx_CMD3 A4_BA2
COMMON G9 FBB_D0
FBC_D1
2/17 FBA
FBC_D2
E9 FBB_D1 FBx_CMD4 A5_BA1
G8 FBB_D2
FBC_D3
FBC_D4
F9 FBB_D3 FBx_CMD5 WE#
F11 FBB_D4
30,31 FBA_D[0..63] FBC_D5
FBA_D0 FBC_D6
G11 FBB_D5 FBx_CMD6 A7_A8
L28 FBA_D0 F12 FBB_D6
FBA_D1 M29 FBA_D1
FBC_D7 G12 FBB_D7 FBx_CMD7 A6_A11
FBA_D2 L29 +FB_PLLAVDD FBC_D8 G6
FBA_D2 FBB_D8
FBA_D3 FBC_D9
FBA_D4
M28 FBA_D3
FBC_D10
F5 FBB_D9 FBx_CMD8 ABI#
N31 FBA_D4 E6 FBB_D10
FBA_D5 FB_REFPLL_AVDD_GPU FBC_D11
FBA_D6
P29 FBA_D5 FB_REFPLL_AVDD K27 RV301 1 2 0_0603_5%
FBC_D12
F6 FBB_D11 FBx_CMD9 A12_RFU
R29 FBA_D6 F4 FBB_D12
FBA_D7 FBC_D13
FBA_D8
P28 FBA_D7
FBC_D14
G4 FBB_D13 FBx_CMD10 A0_A10
J28 FBA_D8 1 E2 FBB_D14
FBA_D9 FBC_D15
FBA_D10
H29 FBA_D9 CV172
FBC_D16
F3 FBB_D15 FBx_CMD11 A1_A9
J29 FBA_D10 0.1U_0402_10V7K C2 FBB_D16
FBA_D11 H28 OPT@ FBC_D17 D4 FBx_CMD12 RAS#
FBA_D11 FBB_D17
FBA_D12 G29 2 FBC_D18 D3
FBA_D12 FBB_D18
FBA_D13 E31 FBA_D13
FBC_D19 C1 FBB_D19 FBx_CMD13 RST#
FBA_D14 E32 FBC_D20 B3
FBA_D14 FBB_D20
FBA_D15 FBC_D21
FBA_D16
F30 FBA_D15
FBC_D22
C4 FBB_D21 FBx_CMD14 CKE#
C34 FBA_D16 B5 FBB_D22
FBA_D17 D32 FBA_D17 Under GPU FBC_D23 C5 FBB_D23 FBx_CMD15 CAS#
FBA_D18 B33 FBC_D24 A11
FBA_D18 FBB_D24
FBA_D19 C33 FBA_D19
FBC_D25 C11 FBB_D25 FBx_CMD16 CS#
FBA_D20 F33 FBC_D26 D11
FBA_D20 FBB_D26
FBA_D21 F32 FBA_D21
FBC_D27 B11 FBB_D27 FBx_CMD17 A3_BA3
FBA_D22 H33 FBC_D28 D8
FBA_D22 FBB_D28
FBA_D23 H32 FBC_D29 A8 FBx_CMD18 A2_BA0
FBA_D23 FBB_D29
FBA_D24 P34 FBC_D30 C8
FBA_D24 FBB_D30
FBA_D25 P32 FBC_D31 B8
FBA_D26
FBA_D25
FBC_D32
FBB_D31 FBx_CMD19 A4_BA2
P31 FBA_D26 F24 FBB_D32
FBA_D27 FBC_D33 FBC_CS#_L
FBA_D28
P33 FBA_D27
FBC_D34
G23 FBB_D33 FBB_CMD0 D13
FBC_MA3_BA3_L FBC_CS#_L 32 FBx_CMD20 A5_BA1
C L31 FBA_D28 E24 FBB_D34 FBB_CMD1 E14 C
FBA_D29 FBC_D35 FBC_MA2_BA0_L FBC_MA3_BA3_L 32
FBA_D30
L34 FBA_D29
FBC_D36
G24 FBB_D35 FBB_CMD2 F14
FBC_MA4_BA2_L FBC_MA2_BA0_L 32 FBx_CMD21 WE#
L32 FBA_D30 D21 FBB_D36 FBB_CMD3 A12
FBA_D31 FBC_D37 FBC_MA5_BA1_L FBC_MA4_BA2_L 32
FBA_D32
L33 FBA_D31
FBC_D38
E21 FBB_D37 FBB_CMD4 B12
FBC_WE#_L FBC_MA5_BA1_L 32 FBx_CMD22 A7_A8
AG28 FBA_D32 G21 FBB_D38 FBB_CMD5 C14
FBA_D33 FBA_CS#_L FBC_D39 FBC_MA7_MA8_L FBC_WE#_L 32
FBA_D34
AF29 FBA_D33 FBA_CMD0 U30
FBA_MA3_BA3_L FBA_CS#_L 30 FBC_D40
F21 FBB_D39 FBB_CMD6 B14
FBC_MA6_MA11_L FBC_MA7_MA8_L 32 FBx_CMD23 A6_A11
AG29 FBA_D34 FBA_CMD1 T31 G27 FBB_D40 FBB_CMD7 G15
FBA_D35 FBA_MA2_BA0_L FBA_MA3_BA3_L 30 FBC_D41 FBC_ABI#_L FBC_MA6_MA11_L 32
FBA_D36
AF28 FBA_D35 FBA_CMD2 U29
FBA_MA4_BA2_L FBA_MA2_BA0_L 30 FBC_D42
D27 FBB_D41 FBB_CMD8 F15
FBC_MA12_RFU_L FBC_ABI#_L 32 FBx_CMD24 ABI#
AD30 FBA_D36 FBA_CMD3 R34 G26 FBB_D42 FBB_CMD9 E15
FBA_D37 AD29 R33 FBA_MA5_BA1_L FBA_MA4_BA2_L 30 FBC_D43 E27 D15 FBC_MA0_MA10_L FBC_MA12_RFU_L 32
FBA_D38
FBA_D37 FBA_CMD4
FBA_WE#_L FBA_MA5_BA1_L 30 FBC_D44
FBB_D43 FBB_CMD10
FBC_MA1_MA9_L FBC_MA0_MA10_L 32 FBx_CMD25 A12_RFU
AC29 FBA_D38 FBA_CMD5 U32 E29 FBB_D44 FBB_CMD11 A14
FBA_D39 FBA_MA7_MA8_L FBA_WE#_L 30 FBC_D45 FBC_RAS#_L FBC_MA1_MA9_L 32
FBA_D40
AD28 FBA_D39 FBA_CMD6 U33
FBA_MA6_MA11_L FBA_MA7_MA8_L 30 FBC_D46
F29 FBB_D45 FBB_CMD12 D14
FBC_RST#_L FBC_RAS#_L 32 FBx_CMD26 A0_A10
AJ29 FBA_D40 FBA_CMD7 U28 E30 FBB_D46 FBB_CMD13 A15
FBA_D41 FBA_ABI#_L FBA_MA6_MA11_L 30 FBC_D47 FBC_CKE_L FBC_RST#_L 32
FBA_D42
AK29 FBA_D41 FBA_CMD8 V28
FBA_MA12_RFU_L FBA_ABI#_L 30 FBC_D48
D30 FBB_D47 FBB_CMD14 B15
FBC_CAS#_L FBC_CKE_L 32 FBx_CMD27 A1_A9
AJ30 FBA_D42 FBA_CMD9 V29 A32 FBB_D48 FBB_CMD15 C17
FBA_D43 FBA_MA0_MA10_L FBA_MA12_RFU_L 30 FBC_D49 FBC_CS#_H FBC_CAS#_L 32
FBA_D44
AK28 FBA_D43 FBA_CMD10 V30
FBA_MA1_MA9_L FBA_MA0_MA10_L 30 FBC_D50
C31 FBB_D49 FBB_CMD16 D18
FBC_MA3_BA3_H FBC_CS#_H 33 FBx_CMD28 RAS#
AM29 FBA_D44 FBA_CMD11 U34 C32 FBB_D50 FBB_CMD17 E18
FBA_D45 FBA_RAS#_L FBA_MA1_MA9_L 30 FBC_D51 FBC_MA2_BA0_H FBC_MA3_BA3_H 33
FBA_D46
AM31 FBA_D45 FBA_CMD12 U31
FBA_RST#_L FBA_RAS#_L 30 FBC_D52
B32 FBB_D51 FBB_CMD18 F18
FBC_MA4_BA2_H FBC_MA2_BA0_H 33 FBx_CMD29 RST#
AN29 FBA_D46 FBA_CMD13 V34 D29 FBB_D52 FBB_CMD19 A20
FBA_D47 FBA_CKE_L FBA_RST#_L 30 FBC_D53 FBC_MA5_BA1_H FBC_MA4_BA2_H 33
FBA_D48
AM30 FBA_D47 FBA_CMD14 V33
FBA_CAS#_L FBA_CKE_L 30 FBC_D54
A29 FBB_D53 FBB_CMD20 B20
FBC_WE#_H FBC_MA5_BA1_H 33 FBx_CMD30 CKE#
AN31 FBA_D48 FBA_CMD15 Y32 C29 FBB_D54 FBB_CMD21 C18
FBA_D49 FBA_CS#_H FBA_CAS#_L 30 FBC_D55 FBC_MA7_MA8_H FBC_WE#_H 33
FBA_D50
AN32 FBA_D49 FBA_CMD16 AA31
FBA_MA3_BA3_H FBA_CS#_H 31 FBC_D56
B29 FBB_D55 FBB_CMD22 B18
FBC_MA6_MA11_H FBC_MA7_MA8_H 33 FBx_CMD31 CAS#
AP30 FBA_D50 FBA_CMD17 AA29 B21 FBB_D56 FBB_CMD23 G18
FBA_D51 FBA_MA2_BA0_H FBA_MA3_BA3_H 31 FBC_D57 FBC_ABI#_H FBC_MA6_MA11_H 33
AP32 FBA_D51 FBA_CMD18 AA28 C23 FBB_D57 FBB_CMD24 G17
FBA_D52 AM33 AC34 FBA_MA4_BA2_H FBA_MA2_BA0_H 31 FBC_D58 A21 F17 FBC_MA12_RFU_H FBC_ABI#_H 33
FBA_D52 FBA_CMD19 FBA_MA4_BA2_H 31 FBB_D58 FBB_CMD25 FBC_MA12_RFU_H 33
FBA_D53 AL31 FBA_D53 FBA_CMD20 AC33 FBA_MA5_BA1_H FBC_D59 C21 FBB_D59 FBB_CMD26 D16 FBC_MA0_MA10_H
FBA_D54 FBA_WE#_H FBA_MA5_BA1_H 31 FBC_D60 FBC_MA1_MA9_H FBC_MA0_MA10_H 33
AK33 FBA_D54 FBA_CMD21 AA32 B24 FBB_D60 FBB_CMD27 A18
FBA_D55 AK32 AA33 FBA_MA7_MA8_H FBA_WE#_H 31 FBC_D61 C24 D17 FBC_RAS#_H FBC_MA1_MA9_H 33
FBA_D55 FBA_CMD22 FBA_MA7_MA8_H 31 FBB_D61 FBB_CMD28 FBC_RAS#_H 33
FBA_D56 AD34 Y28 FBA_MA6_MA11_H FBC_D62 B26 A17 FBC_RST#_H
FBA_D56 FBA_CMD23 FBA_MA6_MA11_H 31 FBB_D62 FBB_CMD29 FBC_RST#_H 33
FBA_D57 AD32 Y29 FBA_ABI#_H FBC_D63 C26 B17 FBC_CKE_H
FBA_D57 FBA_CMD24 FBA_ABI#_H 31 FBB_D63 FBB_CMD30 FBC_CKE_H 33
FBA_D58 AC30 W31 FBA_MA12_RFU_H E17 FBC_CAS#_H
FBA_D58 FBA_CMD25 FBA_MA12_RFU_H 31 FBB_CMD31 FBC_CAS#_H 33
FBA_D59 AD33 Y30 FBA_MA0_MA10_H G14
FBA_D59 FBA_CMD26 FBA_MA0_MA10_H 31 FBB_CMD32
FBA_D60 AF31 AA34 FBA_MA1_MA9_H FBC_DBI0# E11 G20
FBA_D60 FBA_CMD27 FBA_MA1_MA9_H 31 32 FBC_DBI0# FBB_DQM0 FBB_CMD33
FBA_D61 AG34 Y31 FBA_RAS#_H FBC_DBI1# E3 C12 FBB_DEBUG0 1 2 1.55V
FBA_D61 FBA_CMD28 FBA_RAS#_H 31 32 FBC_DBI1# FBB_DQM1 FBB_CMD34 FBVDDQ
FBA_D62 AG32 Y34 FBA_RST#_H FBC_DBI2# A3 C20 RV121
FBA_D62 FBA_CMD29 FBA_RST#_H 31 32 FBC_DBI2# FBB_DQM2 FBB_CMD35
FBA_D63 AG33 FBA_D63 FBA_CMD30 Y33 FBA_CKE_H FBC_DBI3# C9 FBB_DQM3 60.4_0402_1%
FBA_CAS#_H FBA_CKE_H 31 32 FBC_DBI3# FBC_DBI4#
FBA_CMD31 V31 F23 FBB_DQM4 @
FBA_CAS#_H 31 33 FBC_DBI4# FBC_DBI5# FBB_DEBUG1
FBA_CMD32 R28 F27 FBB_DQM5 1 2
FBA_DBI0# P30 AC28 33 FBC_DBI5# FBC_DBI6# C30 RV122
FBA_DQM0 FBA_CMD33 FBB_DQM6
30 FBA_DBI0# FBA_DBI1# F31 R32 FBA_DEBUG0 1 2 33 FBC_DBI6# FBC_DBI7# A24
B 30 FBA_DBI1# FBA_DQM1 FBA_CMD34 FBVDDQ 1.55V 33 FBC_DBI7# FBB_DQM7 60.4_0402_1%
B
FBA_DBI2# F34 AC32 RV119 @
FBA_DQM2 FBA_CMD35
30 FBA_DBI2# FBA_DBI3# M32 60.4_0402_1%
FBA_DQM3
30 FBA_DBI3# FBA_DBI4# AD31 @ FBC_EDC0 D10
31 FBA_DBI4# FBA_DQM4 32 FBC_EDC0 FBB_DQS_WP0
FBA_DBI5# AL29 FBA_DQM5
FBA_DEBUG1 1 2 FBC_EDC1 D5 FBB_DQS_WP1
31 FBA_DBI5# FBA_DBI6# AM32 RV120 32 FBC_EDC1 FBC_EDC2 C3 D12 FBC_CLK0
FBA_DQM6 FBB_DQS_WP2 FBB_CLK0
31 FBA_DBI6# FBA_DBI7# AF34 60.4_0402_1% 32 FBC_EDC2 FBC_EDC3 B9 E12 FBC_CLK0# FBC_CLK0 32
FBA_DQM7 FBB_DQS_WP3 FBB_CLK0
31 FBA_DBI7# @ 32 FBC_EDC3 FBC_EDC4 E23 E20 FBC_CLK1 FBC_CLK0# 32
FBB_DQS_WP4 FBB_CLK1
33 FBC_EDC4 FBC_EDC5 E28 F20 FBC_CLK1# FBC_CLK1 33
33 FBC_EDC5 FBB_DQS_WP5 FBB_CLK1 FBC_CLK1# 33
FBA_EDC0 M31 FBA_DQS_WP0
FBC_EDC6 B30 FBB_DQS_WP6 FBVDDQ
30 FBA_EDC0 FBA_EDC1 G31 33 FBC_EDC6 FBC_EDC7 A23
30 FBA_EDC1 FBA_DQS_WP1 33 FBC_EDC7 FBB_DQS_WP7
FBA_EDC2 E33 FBA_DQS_WP2 FBA_CLK0 R30 FBA_CLK0 FBVDDQ
30 FBA_EDC2 FBA_EDC3 M33 R31 FBA_CLK0# FBA_CLK0 30
30 FBA_EDC3 FBA_DQS_WP3 FBA_CLK0 FBA_CLK0# 30

1
FBA_EDC4 AE31 FBA_DQS_WP4 FBA_CLK1 AB31 FBA_CLK1 D9 FBB_DQS_RN0 FBB_WCK01 F8 FBC_WCK0
31 FBA_EDC4 FBA_EDC5 AK30 AC31 FBA_CLK1# FBA_CLK1 31 E4 E8 FBC_WCK0_N FBC_WCK0 32 RV309 RV308
31 FBA_EDC5 FBA_DQS_WP5 FBA_CLK1 FBA_CLK1# 31 FBB_DQS_RN1 FBB_WCK01 FBC_WCK0_N 32
FBA_EDC6 AN33 FBC_WCK1

1
FBA_DQS_WP6 B2 FBB_DQS_RN2 FBB_WCK23 A5 10K_0402_5% 10K_0402_5%
31 FBA_EDC6 FBA_EDC7 AF33 RV306 RV307 A9 A6 FBC_WCK1_N FBC_WCK1 32 OPT@ OPT@
FBA_DQS_WP7 FBB_DQS_RN3 FBB_WCK23
31 FBA_EDC7 10K_0402_5% 10K_0402_5% D22 D24 FBC_WCK2 FBC_WCK1_N 32
FBB_DQS_RN4 FBB_WCK45 FBC_WCK2 33

2
OPT@ OPT@ D28 FBB_DQS_RN5 FBB_WCK45 D25 FBC_WCK2_N FBC_CKE_L
M30 K31 FBA_WCK0 A30 B27 FBC_WCK3 FBC_WCK2_N 33 FBC_CKE_H
FBA_DQS_RN0 FBA_WC K01 FBA_WCK0 30 FBB_DQS_RN6 FBB_WCK67 FBC_WCK3 33

2
H30 FBA_DQS_RN1 FBA_WC K01 L30 FBA_WCK0_N FBA_CKE_L B23 FBB_DQS_RN7 FBB_WCK67 C27 FBC_WCK3_N
E34 H34 FBA_WCK1 FBA_WCK0_N 30 FBA_CKE_H FBC_WCK3_N 33 FBC_RST#_L
FBA_DQS_RN2 FBA_WC K23
M34 J34 FBA_WCK1_N FBA_WCK1 30 D6 FBC_RST#_H
FBA_DQS_RN3 FBA_WC K23 FBA_WCK1_N 30 FBB_WCKB01
AF30 FBA_DQS_RN4 FBA_WC K45 AG30 FBA_WCK2 FBA_RST#_L
FBB_WCKB01 D7
AK31 AG31 FBA_WCK2_N FBA_WCK2 31 FBA_RST#_H C6
FBA_DQS_RN5 FBA_WC K45 FBB_WCKB23
AJ34 FBA_WCK3 FBA_WCK2_N 31

1
AM34 FBA_DQS_RN6 FBA_WC K67 FBB_WCKB23 B6
AF32 AK34 FBA_WCK3_N FBA_WCK3 31 F26 RV125 RV126
FBA_DQS_RN7 FBA_WC K67 FBB_WCKB45
FBA_WCK3_N 31 E26 10K_0402_5% 10K_0402_5%
FBB_WCKB45
1

1
FBA_WCKB01 J30 FBB_WCKB67 A26 OPT@ OPT@
FBA_WCKB01 J31 RV123 RV124 FBB_WCKB67 A27

2
FBA_WCKB23 J32 10K_0402_5% 10K_0402_5%
J33 OPT@ OPT@ H17 FB_PLL_AVDD
FBA_WCKB23 FBB_PLL_AVDD
FBA_WCKB45 AH31
2

2
FBA_WCKB45 AJ31 1
FBA_WCKB67 AJ32 N17P-G1_FCBGA908

0.1U_0402_10V7K
FBA_WCKB67 AJ33 +FB_PLLAVDD @
H31 U27 FB_PLL_AVDD RV305 1 2 0_0603_5% 2
FB_VREF FBA_PLL_AVDD
22U_0603_6.3V6-M

OPT@
CV176
1 1 1
A N17P-G1_FCBGA908 A
0.1U_0402_10V7K

@
1U_0402_6.3V6K

OPT@

2 2 2
CV175
OPT@
CV173

CV174

@ Under GPU

Under GPU Near GPU

Security Classification LC Future Center Secret Data Title
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
DY512 1.0

Date: Friday, November 25, 2016 Sheet 26 of 75

5 4 3 2 1
 5 4 3 2 1

VGA_AON_3V_1.8V
VGA_AON_3V_1.8V

2
UV1P
INS44021881 RV130

2
? 0_0402_5% GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0
COMMON RV187 RV188 RV189
12/17 MISC2 100K_0402_5% 100K_0402_5% 100K_0402_5%

1
X76@ X76@ X76@ Samsung 8Gb K4G80325FB-HC28 0(0x0000) LLL

1
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) LL H
ROM_CS H6 @ PAD 1 ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE STRAP2
TC1

2
H5 ROM_SI
ROM _SI
ROM_SO
RV197 RV198 RV199 STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) LL H
ROM_SO H7 100K_0402_5% 100K_0402_5% 100K_0402_5% H H M 0000 SOR0/1/2/3 DISABLE
STRAP0 J2 H4 ROM_SCLK OPT@ OPT@ OPT@ STRAP0
STRAP0 ROM_SCLK
STRAP1 J7 STRAP1 Samsung 4Gb K4G41325FE-HC28 7(0x0111) HHH

1
D STRAP2 J6 STRAP2 D

2
STRAP3 J5 STRAP3
RV17 STRAP4 J3 STRAP4
ROM_SO RV192 RV193 RV194 4Gb Hynix 4Gb H5GC4H24AJR-R0C 6(0x0110) HHL
STRAP5 1 2 MULTI_STRAP J1 STRAP5 100K_0402_5% 100K_0402_5% 100K_0402_5%
ROM_SI X76@ X76@ X76@
1

0_0402_5% Micron 4Gb EDW4032BABG-70-F 8(0x1000) LLM

1
RV16 ROM_SCLK
40.2K_0402_1% BUF RST E1
@

1
2

2
RV203
10K_0402_5% RV200 RV201 RV202
@ 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ OPT@

1
N17P-G1_FCBGA908
@ E1 is FB_CLAMP of N16P VGA_AON_3V_1.8V

STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

+3VS

2
RV19 RV21 RV74 L L L 0 0 0 0
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @

2
+3VALW RV12 RV51

1
10K_0402_5% 1 2 1: SMB_ALT_ADDR ENABLE
PCH_GPIO52 20
OPT@ STRAP5
0_0402_5% 0: SMB_ALT_ADDR DISABLE

2
RV57 STRAP4

1
10K_0402_5%
OPT@ FB_GC6_EN_R STRAP3 1: DEVID_SEL REBRAND
0: DEVID_SEL ORIGNAL

1
D

2
5 QV7B
G LBSS138DW1T1G_SOT363-6 RV78 RV75 RV77 1: PCIE_CFG LOW POWER
S OPT@ 100K_0402_5% 100K_0402_5% 100K_0402_5%

4
OPT@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER
D

1
6
FB_GC6_EN 2 QV7A 1: VGA_DEVICE ENABLE
G LBSS138DW1T1G_SOT363-6
S OPT@ 0: VGA_DEVICE DISABLE

1
1
C C
RV313
10K_0402_5%
OPT@

2
VGA_AON_3V_1.8V

RV55 1 @ 2 0_0402_5% VGA_MAIN_3V_1.8V +3VS

VGA_AON_3V_1.8V Add RV13 for VGA_MAIN_3V_1.8V and change RV88 from stuff to ns +3VS
HLZ SIT 0922 BAT54AW
VF=0.32V @ IF=1mA

2
RV13 RV334
Reserve RV333 & DV9 & RV334 & RV335 for DG new sequence
2

0_0402_5% 82K_0402_1% RV104

RV5 RV6 Hai Y520 SVT @ OPT@ @ 10K_0402_5%
2.2K_0402_5% 2.2K_0402_5% BAT54AW_SOT323-3 OPT@

2
OPT@ OPT@

1
PXS_PWREN
5
G

RV220 2 @ 1 0_0402_5% 3 DV3

20,28,70 PXS_PWREN
1

1
VGA_SMB_CK2 1V8_MAIN_EN NVVDD_EN 29,71
4 3 2 RV49 2 1 0_0402_5% 2
EC_SMB_CK2 16,44,49 69 VDDQPWROK
VGA_AON_3V_1.8V 1
S

VGA_PWRGD 20,24

1
VGA_AON_3V_1.8V +3VS DV9 RV64 2 1 0_0402_5% 3
70 1.0VGS_PG
QV3B RV335
LBSS138DW1T1G_SOT363-6 100K_0402_1%
BAT54AW_SOT323-3

2
OPT@ @

1
RV59 RV333 1 @ 2 0_0402_5% OPT@

2
RV319 0_0402_5%

1
10K_0402_5%
2
G

OPT@ RV320

1
10K_0402_5% Add DV3 for VGA_PWRGD
2

VGA_SMB_DA2 1 6
EC_SMB_DA2 16,44,49
OPT@
ADD PXS_PWREN for NVVDDS & 1V0_MAIN_EN Power down VGA_AON_3V_1.8V +3VS HLZ SIT 0922
S

HLZ SIV 0725

2
2
G
RV318
QV3A PU AT EC SIDE, +3VS AND 4.7K GPU_EVENT# 3 1 GPU_EVENT#_R 1 2 DV8
LBSS138DW1T1G_SOT363-6 PCH_GPIO53 20
S

D
PXS_PWREN

1
OPT@ 0_0402_5% For Optimus Power OFF 1 2

2
QV8 RV331
LBSS139WT1G_SC70-3
OPT@
RB751V-40_SOD323-2
OPT@
RV89
10K_0402_5%
8.2K_0402_1%
OPT@ Use RV331 & RV330 and unstuff RV89 based on NV suggestion
@ HLZ SIV 0811

2
RV317 1 @ 2 0_0402_5%
DV7

1
1V8_MAIN_EN 2 RV95
For GC6 Power OFF 1 2 1
NVVDD_PWRGD NVVDDS_EN 72
For Power ON 3
71 NVVDD_PWRGD

1
0_0402_5%
BAT54AW_SOT323-3 RV330 RV98
B OPT@ 10K_0402_1% 2 1 B
1V0_MAIN_EN 29,70
OPT@

2
Delete RV40 & RV97 0ohm & RV54 (ns) Delete RV96(ns) 0_0402_5%

VGA_AON_3V_1.8V HLZ SIV 0725 HLZ SIT 0922

VGA_AON_3V_1.8V

1V8_MAIN_EN RV27 2 OPT@ 1 10K_0402_5%

UV1Q
INS44021236
?
COMMON
Delete FRM_LCK# DV4
FB_GC6_EN_R
2

10/17 MISC1 RV110 1 2 0_0402_5% 2

RV214 NVVDD_PSI RV28 1 @ 2 10K_0402_5%
100K_0402_5% 1
FBVDDQ_PWR_EN 29,69
OPT@
I2CS_SCL T4
VGA_SMB_CK2 VGA_AON_3V_1.8V VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5% 1.0VGS_PG RV325 1 OPT@ 2 0_0402_5% 3
1

I2CS_SDA T3
VGA_SMB_DA2 Internal Thermal Sensor VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%
VGA_EDID_CLK

1
24 OVERT# OVERT# M1 OVERT I2CC_ SCL R2 RV2121 2 2.2K_0402_5% OPT@ BAT54CW_SOT323-3
VGA_EDID_DATA
I2CC_SDA R3 RV2101 2 2.2K_0402_5% OPT@ RV112
TV5 @ 1 AP9 TS_V REF
Change signal from NVVDDS_PWRGD to 1.0VGS_PG OPT@
200K_0402_5%
I2CB_SCL R7
I2CB_SCL
I2CB_SDA
RV22 1 2 2.2K_0402_5% OPT@
SYS_PEX_RST_MON#
HLZ SIT 0922 OPT@
K4 THERMDN I2CB_SDA R6 RV25 1 2 2.2K_0402_5% OPT@ RV39 1 @ 2 10K_0402_5%

2
K3 THERMDP
GPU_PEX_RST_HOLD# RV18 1 @ 2 10K_0402_5%
GP IO0 P6 NVVDD_VID
FB_GC6_EN NVVDD_VID 71
TV1 @ 1 AM 10 JTA G_TCK GP IO1 M3
TV2 @ 1 AP11 JTA G_TMS GP IO2 L6 GPU_EVENT#
TV3 @ 1 AM 11 JTA G_TDI GP IO3 P5 NVVDDS_VID_GPU RV106 2 1 0_0402_5%
1V8_MAIN_EN NVVDDS_VID 72
TV4 @ 1 AP12 JTA G_TDO GP IO4 P7 UNUSED @DG-07875-001 V04
1V8_MAIN_EN 28 MEM_VREF +3VS
AN11 JTA G_TRST GP IO5 L7 RV32 2 OPT@ 1 100K_0402_5%
AK11 NVJT AG _SEL GP IO6 M7 NVVDD_PSI_GPU RV107 2 1 0_0402_5% Combine NVVDD_PSI&NVVDDS_PSI VGA_AON_3V_1.8V
NVVDD_PSI 71,72
2

GP IO7 N8 @DG-07875-001 V04 Delete 3D VISION RV38

RV37 L3 VRAM_VDDQ_ADJ 1 2 0_0402_5%
GP IO8 VRAM_VDDQ_ADJ 69
10K_0402_5% GP IO9 M2 VGA_ALERT# VGA_MAIN_3V_1.8V VGA_AON_3V_1.8V
MEM_VREF 1
2

OPT@ GPIO10 L1 MEM_VREF 30,32

2
RV24 GPIO11 M5 CV58
1

10K_0402_5% GPIO12 N3 VGA_AC_DET_R RV216 .1U_0402_10V6-K

OPT@ GPIO13 M4 10K_0402_5% 2 OPT@
GPIO14 N4 VGA_AON_3V_1.8V @
1

2
GPIO15 P2 RV322
UV2

1
GPIO16 R8 SYS_PEX_RST_MON#_R 1 2 SYS_PEX_RST_MON# RV52 RV50
GPIO17 M6 0_0402_5% 10K_0402_5% 10K_0402_5%
R1 @ VRAM_VDDQ_ADJ RV41 2 @ 1 10K_0402_5% PLT_RST# 1 5 @ @
GPIO18 18,42,43,45,49,50 PLT_RST# DV2
P3 B VCC
GPIO19

1
GPIO20 P4 GC5_MODE 1 @ TV7 2 GPU_PEX_RST_HOLD# 2
P1 RV43 2 OPT@ 1 10K_0402_5% 20 PXS_RST# A 1 PLT_RST_VGA#
GPIO21 PLT_RST_VGA# 24
P8 RV321 3 4 SYS_PEX_RST_MON# SYS_PEX_RST_MON# 3
GPIO22 G ND Y
A T8 GPU_PEX_RST_HOLD#_R 1 2 GPU_PEX_RST_HOLD# A
GPIO23

1
GPIO24 L2 0_0402_5%
R4 @ 74LVC1G08SE-7 SOT353-1-5 BAT54AW_SOT323-3 RV311
GPIO25
GPIO26 R5 RV217 OPT@ @ 100K_0402_5%
GPIO27 U3 100K_0402_5% @

1
OPT@

2
N17P-G1_FCBGA908 RV324 RV44 1 2 0_0402_5%
VGA_ALERT# 20
100K_0402_5%
@ GPIO24 is N16 BUFRST# OPT@
GPIO25 is N16 CRT SCL
GPIO26 is N16 CRT SDA

2
VGA_ALERT# 2 1
DV6 RB751V-40_SOD323-2
OPT@
VGA_AC_DET_R 2 1
VGA_AC_DET 49
DV1 RB751V-40_SOD323-2 Title
@ Security Classification LC Future Center Secret Data
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_GPIO,STRAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
DY512 1.0

Date: F riday, Novem ber 25, 2016 Sheet 27 of 75

5 4 3 2 1
 5 4 3 2 1

5A Peak 8A Cost down list: UV1E UV1F

FBVDDQ
1U 2Pcs INS44443631 INS44444235 1.8V Total 1A (AON+MAIN)
?
COMMON
?
COMMON 0.5A UV1G
INS44444384
14/17 FBVDDQ 17/17 VDD18/AON ?
Under GPU(below 150mils) VGA_AON_3V_1.8V NVVDDS COMMON
AA27 FBVDDQ Under GPU Near GPU 8/17 VDDS
AA30 RV65

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ
AB27 FBVDDQ 1V8_AON J8 +VDD_AON 2 1 AA12 VDDS
AB33 FBVDDQ 1V8_AON K8 AA16 VDDS

4.7U_0805_25V6-K
AC27 0_0603_5% AA19

0.1U_0402_10V7K

0.1U_0402_10V7K
FBVDDQ 1 1 1 1 VDDS
2 2 2 2 2 2 2 2 2 2 2 2

OPT@
OPT@

OPT@

OPT@
AD27 L8 AA23

1U_0603_10V6K
FBVDDQ VDD18 VDDS

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@
@

@
AE27 M8 AC14

CV99
CV114

CV105

CV106

CV115

CV112

CV100

CV101

CV102
CV103

CV104

CV113
FBVDDQ VDD18 VDDS
AF27 FBVDDQ AC21 VDDS
AG27 FBVDDQ
2 2 2 2 M14 VDDS

CV118
OPT@

OPT@

OPT@
B13 M21

OPT@
CV116

CV117
CV443
D FBVDDQ VDDS D
B16 FBVDDQ P12 VDDS
B19 FBVDDQ P16 VDDS
FBVDDQ E13 FBVDDQ P19 VDDS

Under GPU(below 150mils)

E16
E19
FBVDDQ
FBVDDQ 0.5A P23
T14
VDDS
VDDS
H10 FBVDDQ T21 VDDS
H11 VGA_MAIN_3V_1.8V U17

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 FBVDDQ VDDS
H12 FBVDDQ V18 VDDS
H13 FBVDDQ N17P-G1_FCBGA908 RV53 W14 VDDS
H14 FBVDDQ +VDD_MAIN 2 1 W21 VDDS
2 2 2 2 @
H15 FBVDDQ

OPT@

OPT@

OPT@

OPT@
H16

CV94

CV86

CV87

CV88
0_0603_5%

0.1U_0402_10V7K

4.7U_0603_6.3V6K
FBVDDQ 1 1 1 1

0.1U_0402_10V7K
H18

1U_0603_10V6K
FBVDDQ
H19 FBVDDQ VDDS_SENSE U1
H20 FBVDDQ
H21 2 2 2 2 GNDS_SENSE U2
only for N16 FBVDDQ

OPT@

OPT@

OPT@
H22

OPT@
CV119

CV122
CV120

CV121
FBVDDQ
H23 FBVDDQ
FBVDDQ H24 FBVDDQ N17P-G1_FCBGA908
Near GPU H8 FBVDDQ @
H9 FBVDDQ Under GPU Near GPU
Near GPU L27 FBVDDQ
M27 FBVDDQ 72 NVVDDS_VSS_SENSE

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
N27
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 2 2 1 1 1 1 FBVDDQ
P27
33P_0402_50V8J

33P_0402_50V8J

1 1 FBVDDQ 72 NVVDDS_VCC_SENSE
R27 FBVDDQ
T27 FBVDDQ CALIBRATION PIN GDDR5 trace width: 16mils
OPT@

OPT@

OPT@
1 1 1 1 2 2 2 2

OPT@
T30
RF_NS@

RF_NS@

FBVDDQ differential voltage sensing.

CV91

CV97

CV92

CV93
2 2
OPT@

OPT@

OPT@
OPT@

T33
CV95

CV89

CV96

CV90

FBVDDQ
19A Peak 42A Cost down list: differential signal routing.
V27 FB_CAL_x_PD_VDDQ 40.2Ohm
CD89

CD90

FBVDDQ
W27 FBVDDQ 4.7U 1Pcs
W30 FBVDDQ 1U 1Pcs
W33
Y27
FBVDDQ
FBVDDQ
FB_CAL_x_PU_GND 40.2Ohm NVVDDS

Near GPU
FB_CAL_xTERM_GND 60.4Ohm

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2 2 1 1 1

330U_D2_2.5VY_R9M
FBVDDQ_SENSE F1 FBVDDQ_SENSE_GPU RV90 1 OPT@ 2 0_0402_5%
+
POSCAP

OPT@
@

@
FBVDD_VCC_SENSE 69 1 1 2 2 2
@

CV430

CV431

CV432
C FBVDDQ_SENSE_GND_GPU RV91 1 2 C

OPT@

OPT@
PROBE_FB_GND F2 2 0_0402_5%

CV429
@

CV428
CV425
FB_CAL_PD_VDDQ J27 FBCAL_VDDQ 1 2
Add CV300 for RV92 40.2_0402_1%OPT@
FBVDDQ
power noise issue FB_CAL_PU_GND H27 FBCAL_GND 1 2
RV93 40.2_0402_1%OPT@
FB_CALTERM_GND H25 FBCAL_TERM 1 2
RV94 60.4_0402_1%OPT@
Under GPU
Place near balls
N17P-G1_FCBGA908
Delete CV300 330U

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@ 1 1 1 1 1 1 1 1 1 1
HLZ SDV 0610
FBVDDQ
2 2 2 2 2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@
OPT@

OPT@

OPT@
CV434

CV435

CV436

CV437

CV440

CV441

CV442
CV433

CV438

CV439
FBVDD_VCC_SENSE RV310 1 OPT@ 2 2_0402_5%

PLACE MIDWAY BETWEEN FBA AND FBB

Follow NV suggestion for NVVDDS Hai Y520 SVT

2A
AON7408L
Vds=30V
VGA_AON_3V_1.8V VGA_MAIN_3V_1.8V Ids=15A
V20B+ Rdson=28mohm@Vgs=4.66V
Delete +3.3V_AON QV16 =20mohm@Vgs=6V
=18mohm@Vgs>10V
AON7408L_DFN8-5
Vgs=+-20V

2
+3VS +5VALW RV42
1 Vgsth=1~3V
B 47K_0402_5% 5 S1 2 B
D S2
1

OPT@ 3
S3
2

RV108

1
G
RV109 47K_0402_5% +5VALW
2 1 1
10K_0402_5% OPT@ OPT@ CV73 RV85 CV74

4
OPT@ Vg=16.4V@AC CV72 0.01U_0402_25V7K 47_0603_5% 10U_0603_6.3V6M
2

1
Vg=7.38V@Battery 0.1U_0402_25V6 @ OPT@ OPT@
1

PXS_PWREN# RV86 1 @ 2 2
Change QV18 from LBSS138LT1G_SOT-23-3 to LBSS139WT1G_SC70-3 Hai Y520 SVT

2
47K_0402_5% 1 2
D OPT@ RV83
1

D 1K_0402_5% 2

1
2 QV18 OPT@
20,27,70 PXS_PWREN

1
G LBSS139WT1G_SC70-3 +1.8VGS_PWR_EN# 5 RV47 CV75 D
S OPT@ G 210K_0402_1% 0.1U_0402_25V6 +1.8VGS_PWR_EN# 2
3

1
1

LBSS138DW1T1G_SOT363-6
RV58 S QV9B OPT@ OPT@ QV20

4
LBSS138DW1T1G_SOT363-6
0_0402_5% D
OPT@ 2N7002KW_SOT323-3

2
6
RV115 OPT@ S OPT@

3
100K_0402_5% 2 1 2 QV9A
27 1V8_MAIN_EN G
@ OPT@
2

S
0.1U_0402_25V6

1
1

2
@

@
CV38

PD3 0_0402_5% RV84

3 PR4 1 2 100K_0402_5% Add +1.8V_MAIN discharger circuit
@
1 1 HLZ SIT 0928
2

0_0402_5% @
2 PR5 1 2

LBAT54SWT1G_SOT323-3
@
2A
+1.8VS_AON
Delete PD3503 and Reserve PD3/PR4/PR5/CV38 VGA_AON_3V_1.8V
+1.8VS_AON
HLZ SIT 0923
Add +1.8V-AON discharger circuit HLZ SIV 0811
1

RV101 1 2 0_0805_5%
RV66
470_0603_5%
OPT@
2

A
1.5A A
1

D
PXS_PWREN# 2 VGA_MAIN_1.05V_1.8V
G
QV13 VGA_MAIN_3V_1.8V
S 2N7002KW_SOT323-3
3

OPT@ RV116 1 2 0_0805_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 28 of 75

5 4 3 2 1
 5 4 3 2 1

UV1I UV1J UV1H 47A Peak90A Follow NV suggestion for NVVDD Hai Y520 SVT UV1D
INS44026444 INS44027230 INS44026127 INS44027501
? ? ? ?
COMMON COMMON COMMON COMMON
NVVDD NVVDD
NEAR GPU UNDER GPU
15/17 GND_1/2 16/17 GND_2/2 9/17 XVDD 13/17 NVVDD
A2 GND GND AM25
A33 GND GND AN1 N19 GND GND T28 CONFIGURABLE
D NVVDD D
AA13 GND GND AN10 N2 GND GND T32 POWER AA14 VDD
AA15 GND GND AN13 N21 GND GND T5 CHANNELS AA21 VDD
AA17 AN16 N23 T7 U4 AB13

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
GND GND GND GND XVDD 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD
AA18 AN19 N28 U12 U5 AB15

33P_0402_50V8J
33P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
GND GND GND GND XVDD 1 1 VDD
AA20 AN22 N30 U14 U6 AB17

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
GND GND GND GND XVDD VDD
AA22 GND GND AN25 N32 GND GND U16 XVDD U7 AB18 VDD
AB12 AN30 N33 U19 U8 2 2 2 2 2 2 2 2 2 2 2 2 2 AB20

RF_NS@

RF_NS@
GND GND GND GND XVDD VDD
2 2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@
AB14 AN34 N5 U21 V1 AB22

CV148

CV139

CV145
CV135

CV136

CV147

CV138

CV146
GND GND GND GND XVDD VDD

OPT@

OPT@

OPT@

OPT@

OPT@
AB16 AN4 N7 U23 V2 AC12

CV141

CV142

CV144
CV140

CV143
CD94

CD93
GND GND GND GND XVDD VDD
AB19 GND GND AN7 P13 GND GND V12 XVDD V3 AC16 VDD
AB2 GND GND AP2 P15 GND GND V14 XVDD V4 AC19 VDD
AB21 GND GND AP33 P17 GND GND V16 AC23 VDD
AB23 GND GND B1 P18 GND GND V19 M12 VDD
AB28 GND GND B10 P20 GND GND V21 XVDD V5 M16 VDD
AB30 GND GND B22 P22 GND GND V23 XVDD V6 M19 VDD

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AB32 B25 R12 W13 V7 M23

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M
GND GND GND GND XVDD 1 1 1 1 1 1 1 VDD

4.7U_0603_6.3V6K
AB5 GND GND B28 R14 GND GND W15 XVDD V8 N13 VDD
AB7 GND GND B31 R16 GND GND W17 XVDD W2 N15 VDD
AC13 B34 R19 W18 W3 N17

OPT@

OPT@
GND GND GND GND XVDD

OPT@
VDD
AC15 B4 R21 W20 W4 2 2 2 2 2 2 2 N18

CV151

CV152

CV153

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND GND GND GND XVDD 1 1 1 1 1 1 1 1 VDD

CV137

CV134

CV149

OPT@

OPT@
OPT@
AC17 B7 R23 W22 W5 N20

OPT@
CV150
GND GND GND GND XVDD VDD
AC18 GND GND C10 T13 GND GND W28 XVDD W7 N22 VDD
AC20 GND GND C13 T15 GND GND Y12 P14 VDD
AC22 C19 T17 Y14 2 2 2 2 2 2 2 2 P21
GND GND GND GND VDD

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@
AE2 C22 T18 Y16 W8 R13

CV156

CV157
CV154

CV155

CV158

CV159

CV160

CV161
GND GND GND GND XVDD VDD
AE28 GND GND C25 T2 GND GND Y19 XVDD Y1 R15 VDD
AE30 GND GND C28 T20 GND GND Y21 XVDD Y2 R17 VDD
AE32 GND GND C7 T22 GND GND Y23 XVDD Y3 R18 VDD
AE33 GND GND D2 AG11 GND GND AH11 XVDD Y4 R20 VDD
C AE5 GND GND D31 XVDD Y5 1 R22 VDD C

330U_D2_2.5VY_R9M
AE7 GND GND D33 XVDD Y6 T12 VDD
AH10 E10 Y7 + T16
GND GND XVDD VDD
AH13 E22 Y8 T19
AH16
AH19
GND
GND
GND
GND E25
E5
XVDD
2
@ POSCAP T23
U13
VDD
VDD

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND GND 1 1 1 1 1 1 1 VDD
AH2 E7 AA1 U15

CV162
GND GND XVDD VDD
AH22 GND GND F28 XVDD AA2 U18 VDD
AH24 GND GND F7 XVDD AA3 U20 VDD
AH28 G10 AA4 2 2 2 2 2 2 2 U22
GND GND XVDD VDD

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@
AH29 G13 AA5 V13

CV165

CV166

CV168

CV169
CV164

CV167

CV170
GND GND XVDD VDD
AH30 GND GND G16 XVDD AA6 V15 VDD
AH32 GND GND G19 XVDD AA7 V17 VDD
AH33 GND GND G2 GND_OPT C16 XVDD AA8 V20 VDD
AH5 GND GND G22 GND_OPT W32 V22 VDD
AH7 GND GND G25 W 12 VDD
AJ7 GND GND G28 Optional CMD GNDs (2) W 16 VDD
AK10 GND GND G3 NC for 4-Lyr cards W 19 VDD
AK7 GND GND G30 W 23 VDD
AL12 GND GND G32 N17P-G1_FCBGA908 Y13 VDD
AL14 GND GND G33 @ Y15 VDD
AL15 GND GND G5 Y17 VDD
AL17 GND GND G7 N17P-G1_FCBGA908 Y18 VDD
AL18 GND GND K2 @ Y20 VDD
AL2 GND GND K28 Y22 VDD
AL20 GND GND K30
AL21 GND GND K32
AL23 GND GND K33
AL24 GND GND K5
AL26 GND GND K7
B B
AL28 GND GND M13
AL30 GND GND M15 NVVDD
AL32 GND GND M17 FBVDDQ
AL33 GND GND M18
Change NVVDDS & +1.0VGS discharge circuit

1
AL5 GND GND M20 +5VALW
HLZ SIV 0725

1
AM13 GND GND M22 +5VALW RV36
AM16 GND GND N12 RV61 470_0603_5%

1
AM19 GND GND N14 470_0603_5% @

1
AM22 GND GND N16 @ RV62 VDD_SENSE L4

2
NVVDDS +1.0VGS RV48 47K_0402_5%

LBSS138DW 1T1G_SOT363-6
47K_0402_5% REV@
REV@
D GND_SENSE L5

3
N17P-G1_FCBGA908

3
5

QV4B

REV@
@ D QV6B
5 G N17P-G1_FCBGA908
2N7002KDW H_SOT363-6

LBSS138DW 1T1G_SOT363-6
G
15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%
15_0805_1%

15_0805_1%

15_0805_1%

S @

4
RV332 1

RV45 1

RV326 1

RV327 1

RV63 1

RV328 1

RV329 1

NVVDD_VSS_SENSE
Add RV332 for NVVDDS discharge Hai Y520 SVT REV@
D 71 NVVDD_VSS_SENSE

6
OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

4
6
2 NVVDD_VCC_SENSE

QV4A
QV6A

REV@
D
+5VALW 27,71 NVVDD_EN 71 NVVDD_VCC_SENSE
2 G
27,69 FBVDDQ_PWR_EN G 2N7002KDW H_SOT363-6 S
2

1
REV@ trace width: 16mils
1

S
RV60 1
differential voltage sensing.
47K_0402_5% differential signal routing.
1

OPT@
D

D
2

2 2
G G
A A
LBSS139W T1G_SC70-3

QV11 QV29 QV12

D
1

AO3402_SOT-23-3 AO3402_SOT-23-3
3

3
OPT@

2
27,70 1V0_MAIN_EN G OPT@ OPT@
S
Security Classification LC Future Center Secret Data Title
3

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_POWER,GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 29 of 75

5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 64 bits(MF=0) UV4

MF=0 MF=1 MF=1 MF=0

FBA_D0 FBA_D[0..7] 26 BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0

A4
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1
26 FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1 FBA_D2
C13 B4
26 FBA_EDC1 FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3
26 FBA_EDC2 FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4
R2 E4
26 FBA_EDC3 EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
DQ29 DQ5 F4 FBA_D6
FBA_DBI0# DQ30 DQ6 FBA_D7
26 FBA_DBI0# FBA_DBI1#
D2
DBI0# DBI3# DQ31 DQ7
F2
FBA_D8 FBA_D[8..15] 26 BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D13 A11
26 FBA_DBI1# FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D9
P13 A13
26 FBA_DBI2# FBA_DBI3# P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
D 26 FBA_DBI3# DBI3# DBI0# DQ18 DQ10 D
B13 FBA_D11
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12
26 FBA_CLK0 FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13
26 FBA_CLK0# FBA_CKE_L CK# DQ21 DQ13 FBA_D14
J3 F11
26 FBA_CKE_L CKE# DQ22 DQ14 FBA_D15
DQ23 DQ15
F13
FBA_D16 FBA_D[16..23] 26 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
U11
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17
26 FBA_MA2_BA0_L FBA_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18
K10 T11
26 FBA_MA5_BA1_L FBA_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19
26 FBA_MA4_BA2_L FBA_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
H10 N11
26 FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
DQ13 DQ21 M11 FBA_D22
FBA_MA7_MA8_L DQ14 DQ22 FBA_D23
26 FBA_MA7_MA8_L FBA_MA1_MA9_L
K4
A8/A7 A10/A0 DQ15 DQ23
M13
FBA_D24 FBA_D[24..31] 26 BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
H5 U4
26 FBA_MA1_MA9_L FBA_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBA_D25
H4 U2
26 FBA_MA0_MA10_L FBA_MA6_MA11_L K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
26 FBA_MA6_MA11_L FBA_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBA_D27
J5 T2
26 FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 N4 FBA_D28
A5 DQ4 DQ28 N2 FBA_D29
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31
DQ7 DQ31
RV127 2 1 1K_0402_1% OPT@ J1 FBVDDQ
2 1 1K_0402_1% J10 MF
RV129
RV131 2 1 121_0402_1%
OPT@
OPT@ J13 SEN B1
Cost down list:
ZQ VDDQ1
VDDQ2
D1 2A Peak 3A 22U 2Pcs
Follow DG FBA_ABI#_L VDDQ3
F1
J4 M1
26 FBA_ABI#_L FBA_RAS#_L ABI# VDDQ4
G3 P1
FBA_CLK0 1 2 26 FBA_RAS#_L FBA_CS#_L G12 RAS# CAS# VDDQ5 T1
26 FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ6
RV133
26 FBA_CAS#_L
L3
CAS# RAS# VDDQ7
G2 FBVDDQ UV4 SIDE
40.2_0402_1% FBA_WE#_L L12 L2
26 FBA_WE#_L WE# CS# VDDQ8
1

OPT@ B3
RV134 VDDQ9 D3
80.6_0402_1% VDDQ10 F3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
VDDQ11 2 2 2 2 2 2 2 2 2
FBA_WCK0_N
@ D5 H3
GDDR5

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
26 FBA_WCK0_N FBA_WCK0 D4 WCK01# WCK23# VDDQ12 K3
C 26 FBA_WCK0 C
WCK01 WCK23 VDDQ13
2

FBA_CLK0#

OPT@
1 2
FBA_WCK1_N VDDQ14
M3
1 1 1 1 1 1 1 1 1 Mode H - Mirror Mode Mapping

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@
RV135 P5 P3
26 FBA_WCK1_N FBA_WCK1 WCK23# WCK01# VDDQ15
P4 T3

CV188

CV308

CV309

CV310

CV311

CV312

CV313

CV314

CV315
40.2_0402_1% 1 26 FBA_WCK1 WCK23 WCK01 VDDQ16 E5
OPT@
0.01U_0402_25V7K

VDDQ17
VDDQ18
N5 DATA Bus
A10 E10
2 VREFD1 VDDQ19
U10
VREFD2 VDDQ20
N10 Address 0..31 32..63
+FBA_VREFC0
OPT@

J14
VREFC VDDQ21
B12 AROUND DRAM CLOSE TO DRAM
D12 FBx_CMD0 CS#
CV177

VDDQ22 F12
VDDQ23
VDDQ24
H12 FBx_CMD1 A3_BA3
FBA_RST#_L J2 K12

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
26 FBA_RST#_L RESET# VDDQ25 2 2 2 2 2 2 2

1
M12 FBx_CMD2 A2_BA0

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDQ26 P12
VDDQ27
VDDQ28
T12 FBx_CMD3 A4_BA2

2
1 1 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

OPT@

OPT@

OPT@
G13

CV316

CV317

CV318

CV319

CV320
VDDQ29
H1 L13 FBx_CMD4 A5_BA1

CV321

CV322

CV323

CV324

CV325

CV326

CV327
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31
B5
VSS3 VDDQ32
D14 FBx_CMD5 WE#
G5 F14
VSS4 VDDQ33
L5
VSS5 VDDQ34
M14 FBx_CMD6 A7_A8
T5
VSS6 VDDQ35
P14 AROUND DRAM CLOSE TO DRAM
B10
VSS7 VDDQ36
T14 FBx_CMD7 A6_A11
D10
VSS8
G10
VSS9
FBx_CMD8 ABI#
L10 A1
VSS10 VSSQ1
P10
VSS11 VSSQ2
C1 FBx_CMD9 A12_RFU
T10 E1
VSS12 VSSQ3
H14
VSS13 VSSQ4
N1 FBx_CMD10 A0_A10
K14 R1
VSS14 VSSQ5
FBVDDQ
VSSQ6
U1 FBVDDQ FBx_CMD11 A1_A9
VSSQ7
H2 UNDER DRAM
G1
VDD1 VSSQ8
K2 FBx_CMD12 RAS#
L1 A3
VDD2 VSSQ9
G4
VDD3 VSSQ10
C3 2 2 2 2 FBx_CMD13 RST#
L4 E3

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDD4 VSSQ11
B C5
VDD5 VSSQ12
N3 FBx_CMD14 CKE# B
R5 R3
VDD6 VSSQ13 1 1 1 1 FBx_CMD15 CAS#

OPT@

OPT@

OPT@
OPT@
C10 U3
R10 VDD7 VSSQ14 C4

CV357

CV350

CV351

CV352
VDD8 VSSQ15
D11
VDD9 VSSQ16
R4 FBx_CMD16 CS#
G11 F5
VDD10 VSSQ17
L11
VDD11 VSSQ18
M5 FBx_CMD17 A3_BA3
P11 F10
VDD12 VSSQ19
G14
VDD13 VSSQ20
M10 FBx_CMD18 A2_BA0
L14
VDD14 VSSQ21
C11 UNDER DRAM
VSSQ22
R11 FBx_CMD19 A4_BA2
A12
VSSQ23
VSSQ24
C12 2 2 2 2 FBx_CMD20 A5_BA1
E12

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ25
VSSQ26
N12 FBx_CMD21 WE#
R12
VSSQ27 1 1 1 1 FBx_CMD22 A7_A8

OPT@

OPT@

OPT@
OPT@
170-BALL U12
VSSQ28 H13

CV358

CV354

CV355

CV356
VSSQ29
SGRAM GDDR5
VSSQ30
K13 FBx_CMD23 A6_A11
A14
VSSQ31
VSSQ32
C14 FBx_CMD24 ABI#
E14
VSSQ33
VSSQ34
N14 FBx_CMD25 A12_RFU
FBVDDQ R14
VSSQ35
VSSQ36
U14 FBx_CMD26 A0_A10
X76@ FBx_CMD27 A1_A9
1

RV136 H5GC2H24BFR-T2C_BGA170 FBx_CMD28 RAS#

549_0402_1%
OPT@
16 mil FBx_CMD29 RST#
2

1 2 +FBA_VREFC0
+FBA_VREFC0 31 FBx_CMD30 CKE#
RV137
1

931_0402_1% RV138 1 FBx_CMD31 CAS#

OPT@ 1.33K_0402_1% CV178
OPT@ 820P_0402_25V7
A OPT@ A
2
2

D
1

2
27,32 MEM_VREF G QV26
S LBSS138LT1G_SOT-23-3
3

OPT@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 30 of 75
5 4 3 2 1
 5 4 3 2 1

Memory Partition A- Upper 64 bits(MF=0)

UV6
MF=0 MF=1 MF=1 MF=0

FBA_D32 FBA_D[32..39] 26 BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2

A4
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
26 FBA_EDC4 FBA_EDC5 EDC0 EDC3 DQ25 DQ1 FBA_D34
C13 B4
26 FBA_EDC5 FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
26 FBA_EDC6 FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
R2 E4
26 FBA_EDC7 EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D38
FBA_DBI4# DQ30 DQ6 FBA_D39
26 FBA_DBI4# FBA_DBI5#
D2
DBI0# DBI3# DQ31 DQ7
F2
FBA_D40 FBA_D[40..47] 26 BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
D13 A11
26 FBA_DBI5# FBA_DBI6# DBI1# DBI2# DQ16 DQ8 FBA_D41
P13 A13
26 FBA_DBI6# FBA_DBI7# P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
D 26 FBA_DBI7# DBI3# DBI0# DQ18 DQ10 D
B13 FBA_D43
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D44
26 FBA_CLK1 FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45
26 FBA_CLK1# FBA_CKE_H CK# DQ21 DQ13 FBA_D46
J3 F11
26 FBA_CKE_H CKE# DQ22 DQ14 FBA_D47
DQ23 DQ15
F13
FBA_D48 FBA_D[48..55] 26 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
U11
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49
26 FBA_MA2_BA0_H FBA_MA5_BA1_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50
K10 T11
26 FBA_MA5_BA1_H FBA_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D51
26 FBA_MA4_BA2_H FBA_MA3_BA3_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
26 FBA_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
N13
DQ13 DQ21 FBA_D54
DQ14 DQ22
M11 BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
FBA_MA7_MA8_H K4 M13 FBA_D55
26 FBA_MA7_MA8_H FBA_MA1_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBA_D56 FBA_D[56..63] 26
H5 U4
26 FBA_MA1_MA9_H FBA_MA0_MA10_H A9/A1 A11/A6 DQ0 DQ24 FBA_D57
H4 U2
26 FBA_MA0_MA10_H FBA_MA6_MA11_H K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
26 FBA_MA6_MA11_H FBA_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBA_D59
J5 T2
26 FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D60
Follow DG DQ4 DQ28
N4
FBA_D61
A5 N2
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
FBA_CLK1 1 2 VPP/NC2 DQ6 DQ30 M2 FBA_D63
RV148 DQ7 DQ31
40.2_0402_1% RV143 2 1 1K_0402_1% OPT@ J1 FBVDDQ
OPT@ RV145 2 1 1K_0402_1% OPT@ J10 MF
SEN
1

RV147 2 1 121_0402_1% OPT@ J13 B1

RV149 ZQ VDDQ1 D1
80.6_0402_1% VDDQ2 F1
@ FBA_ABI#_H J4 VDDQ3 M1
26 FBA_ABI#_H FBA_RAS#_H ABI# VDDQ4
G3 P1
26 FBA_RAS#_H RAS# CAS# VDDQ5
2

FBA_CLK1# 1 2 FBA_CS#_H G12 T1

26 FBA_CS#_H FBA_CAS#_H CS# WE# VDDQ6
RV150
40.2_0402_1%
26 FBA_CAS#_H FBA_WE#_H
L3
L12 CAS# RAS# VDDQ7
G2
L2
Cost down list: GDDR5
2A Peak 3A
0.01U_0402_25V7K

1 26 FBA_WE#_H WE# CS# VDDQ8 22U 2Pcs

OPT@
VDDQ9
VDDQ10
B3
D3 Mode H - Mirror Mode Mapping
F3
2 FBA_WCK2_N VDDQ11
OPT@

D5 H3
26 FBA_WCK2_N FBA_WCK2 WCK01# WCK23# VDDQ12
D4 K3 DATA Bus
CV196

C 26 FBA_WCK2 C
WCK01 WCK23 VDDQ13
FBA_WCK3_N VDDQ14
M3 FBVDDQ UV6 SIDE
26 FBA_WCK3_N
P5
WCK23# WCK01# VDDQ15
P3 Address 0..31 32..63
FBA_WCK3 P4 T3
26 FBA_WCK3 WCK23 WCK01 VDDQ16
VDDQ17
E5 FBx_CMD0 CS#
N5

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDQ18 2 2 2 2 2 2 2 2 2
A10 E10 FBx_CMD1 A3_BA3

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
U10 VREFD1 VDDQ19 N10
+FBA_VREFC0 VREFD2 VDDQ20
J14
VREFC VDDQ21
B12
1 1 1 1 1 1 1 1 1
FBx_CMD2 A2_BA0

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@
D12
VDDQ22 F12 FBx_CMD3 A4_BA2

CV329

CV330

CV331

CV332

CV334

CV333

CV335

CV336

CV337
VDDQ23 H12
VDDQ24
26 FBA_RST#_H
FBA_RST#_H J2
RESET# VDDQ25
K12 FBx_CMD4 A5_BA1
M12
VDDQ26
VDDQ27
P12 FBx_CMD5 WE#
VDDQ28
T12 AROUND DRAM CLOSE TO DRAM
VDDQ29
G13 FBx_CMD6 A7_A8
H1 L13
VSS1 VDDQ30
K1
VSS2 VDDQ31
B14 FBx_CMD7 A6_A11
B5 D14

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
VSS3 VDDQ32 2 2 2 2 2 2 2

1
G5 F14 FBx_CMD8 ABI#

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
L5 VSS4 VDDQ33 M14
VSS5 VDDQ34
T5
VSS6 VDDQ35
P14 FBx_CMD9 A12_RFU

2
1 1 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@
16 mil

@
B10 T14

CV338

CV339

CV340

CV341

CV342
VSS7 VDDQ36
D10 FBx_CMD10 A0_A10

CV343

CV345

CV344

CV346

CV347

CV348

CV328
G10 VSS8
VSS9
L10
VSS10 VSSQ1
A1 FBx_CMD11 A1_A9
+FBA_VREFC0 P10 C1
30 +FBA_VREFC0 VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 FBx_CMD12 RAS#
1 H14
VSS13 VSSQ4
N1 AROUND DRAM CLOSE TO DRAM
K14
VSS14 VSSQ5
R1 FBx_CMD13 RST#
CV197 FBVDDQ U1
VSSQ6
820P_0402_25V7
2 OPT@ VSSQ7
H2 FBx_CMD14 CKE#
G1 K2
VDD1 VSSQ8
L1
VDD2 VSSQ9
A3 FBx_CMD15 CAS#
G4 C3
VDD3 VSSQ10
L4
VDD4 VSSQ11
E3 FBx_CMD16 CS#
B C5 N3 FBVDDQ B
VDD5 VSSQ12
R5
VDD6 VSSQ13
R3 UNDER DRAM FBx_CMD17 A3_BA3
C10 U3
VDD7 VSSQ14
R10
VDD8 VSSQ15
C4 FBx_CMD18 A2_BA0
D11 R4 2 2 2 2
VDD9 VSSQ16
G11 F5 FBx_CMD19 A4_BA2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
L11 VDD10 VSSQ17 M5
VDD11 VSSQ18
P11
VDD12 VSSQ19
F10
1 1 1 1
FBx_CMD20 A5_BA1

OPT@

OPT@

OPT@
OPT@
G14 M10
VDD13 VSSQ20
L14 C11 FBx_CMD21 WE#

CV365

CV360

CV359

CV361
VDD14 VSSQ21 R11
VSSQ22
VSSQ23
A12 FBx_CMD22 A7_A8
C12
VSSQ24
VSSQ25
E12 FBx_CMD23 A6_A11
N12
VSSQ26
VSSQ27
R12 UNDER DRAM FBx_CMD24 ABI#
170-BALL U12
VSSQ28
VSSQ29
H13 FBx_CMD25 A12_RFU
SGRAM GDDR5 K13 2 2 2 2
VSSQ30 A14 FBx_CMD26 A0_A10

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ31 C14
VSSQ32
VSSQ33
E14
1 1 1 1
FBx_CMD27 A1_A9

OPT@

OPT@

OPT@
OPT@
N14
VSSQ34 R14 FBx_CMD28 RAS#

CV366

CV362

CV363

CV364
VSSQ35 U14
VSSQ36
FBx_CMD29 RST#
X76@
FBx_CMD30 CKE#
H5GC2H24BFR-T2C_BGA170
FBx_CMD31 CAS#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 31 of 75
5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Lower 32 bits(MF=0)

UV8

MF=0 MF=1 MF=1 MF=0

FBC_D0 FBC_D[0..7] 26 BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0

A4
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1
26 FBC_EDC0 FBC_EDC1 EDC0 EDC3 DQ25 DQ1 FBC_D2
C13 B4
26 FBC_EDC1 FBC_EDC2 EDC1 EDC2 DQ26 DQ2 FBC_D3
R13 B2
26 FBC_EDC2 FBC_EDC3 EDC2 EDC1 DQ27 DQ3 FBC_D4
R2 E4
26 FBC_EDC3 EDC3 EDC0 DQ28 DQ4 FBC_D5
E2
DQ29 DQ5 F4 FBC_D6
FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7
26 FBC_DBI0# FBC_DBI1# DBI0# DBI3# DQ31 DQ7 FBC_D8 FBC_D[8..15] 26 BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D D13 A11 D
26 FBC_DBI1# FBC_DBI2# DBI1# DBI2# DQ16 DQ8 FBC_D9
P13 A13
26 FBC_DBI2# FBC_DBI3# DBI2# DBI1# DQ17 DQ9 FBC_D10
P2 B11
26 FBC_DBI3# DBI3# DBI0# DQ18 DQ10 FBC_D11
B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_D12
26 FBC_CLK0 FBC_CLK0# CK DQ20 DQ12 FBC_D13
J11 E13
26 FBC_CLK0# FBC_CKE_L CK# DQ21 DQ13 FBC_D14
J3 F11
26 FBC_CKE_L CKE# DQ22 DQ14 FBC_D15
F13 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
DQ23 DQ15 FBC_D16 FBC_D[16..23] 26
U11
FBC_MA2_BA0_L H11 DQ8 DQ16 U13 FBC_D17
26 FBC_MA2_BA0_L FBC_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D18
K10 T11
26 FBC_MA5_BA1_L FBC_MA4_BA2_L BA1/A5 BA3/A3 DQ10 DQ18 FBC_D19
K11 T13
26 FBC_MA4_BA2_L FBC_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBC_D20
26 FBC_MA3_BA3_L H10 N11
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21
DQ13 DQ21 M11 FBC_D22
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23
26 FBC_MA7_MA8_L FBC_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBC_D24 FBC_D[24..31] 26 BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
Follow DG H5 U4
26 FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D25
26 FBC_MA0_MA10_L FBC_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBC_D26
K5 T4
FBC_CLK0 26 FBC_MA6_MA11_L FBC_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBC_D27
1 2 26 FBC_MA12_RFU_L J5 T2
RV163 A12/RFU/NC DQ3 DQ27 N4 FBC_D28
40.2_0402_1% A5 DQ4 DQ28 N2 FBC_D29
OPT@ U5 VPP/NC1 DQ5 DQ29 M4 FBC_D30
VPP/NC2 DQ6 DQ30
1

M2 FBC_D31
RV164 DQ7 DQ31
80.6_0402_1% RV157 2 1 1K_0402_1% OPT@ J1 FBVDDQ
@ RV159 2 1 1K_0402_1% OPT@ J10 MF
RV161 2 1 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1
2

D1
VDDQ2 F1
FBC_CLK0# 1 2 FBC_ABI#_L J4 VDDQ3 M1
26 FBC_ABI#_L FBC_RAS#_L ABI# VDDQ4
RV165 G3 P1
40.2_0402_1% 26 FBC_RAS#_L FBC_CS#_L G12 RAS# CAS# VDDQ5 T1
OPT@
1 26 FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ6 G2
Cost down list:
2A Peak 3A
0.01U_0402_25V7K

26
26
FBC_CAS#_L
FBC_WE#_L
FBC_WE#_L L12 CAS# RAS# VDDQ7 L2 22U 2Pcs
WE# CS# VDDQ8 B3
2 VDDQ9 D3
VDDQ10
OPT@

C
FBC_WCK0_N D5 VDDQ11
F3
H3 GDDR5 C
CV215

26 FBC_WCK0_N FBC_WCK0 WCK01# WCK23# VDDQ12

26 FBC_WCK0
D4
WCK01 WCK23 VDDQ13
VDDQ14
K3
M3
FBVDDQ UV8 SIDE Mode H - Mirror Mode Mapping
FBC_WCK1_N P5 P3
26 FBC_WCK1_N FBC_WCK1 WCK23# WCK01# VDDQ15
P4 T3
26 FBC_WCK1 WCK23 WCK01 VDDQ16 E5 DATA Bus

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDQ17 2 2 2 2 2 2 2 2 2
N5

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDQ18
A10
VREFD1 VDDQ19
E10 Address 0..31 32..63
U10 N10
+FBC_VREFC0 VREFD2 VDDQ20 1 1 1 1 1 1 1 1 1 FBx_CMD0 CS#

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
J14 B12
VREFC VDDQ21 D12

CV368

CV369

CV371

CV370

CV373

CV372

CV374

CV375

CV376
VDDQ22
VDDQ23
F12 FBx_CMD1 A3_BA3
H12
FBC_RST#_L VDDQ24
26 FBC_RST#_L
J2
RESET# VDDQ25
K12 FBx_CMD2 A2_BA0
M12
VDDQ26
VDDQ27
P12 AROUND DRAM CLOSE TO DRAM FBx_CMD3 A4_BA2
T12
VDDQ28
VDDQ29
G13 FBx_CMD4 A5_BA1
H1 L13
VSS1 VDDQ30
K1 B14 FBx_CMD5 WE#

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
VSS2 VDDQ31 2 2 2 2 2 2 2

1
B5 D14

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSS3 VDDQ32
G5
VSS4 VDDQ33
F14 FBx_CMD6 A7_A8
L5 M14
VSS5 VDDQ34

2
1 1 1 1 1 1 1 FBx_CMD7 A6_A11

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
T5 P14

CV377

CV378

CV379

CV380

CV381
B10 VSS6 VDDQ35 T14

CV382

CV384

CV383

CV385

CV386

CV387

CV367
VSS7 VDDQ36
D10
VSS8
FBx_CMD8 ABI#
G10
VSS9
L10
VSS10 VSSQ1
A1 FBx_CMD9 A12_RFU
P10 C1
VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 AROUND DRAM CLOSE TO DRAM FBx_CMD10 A0_A10
H14 N1
VSS13 VSSQ4
K14
VSS14 VSSQ5
R1 FBx_CMD11 A1_A9
U1
FBVDDQ VSSQ6
VSSQ7
H2 FBx_CMD12 RAS#
G1 K2
VDD1 VSSQ8
L1
VDD2 VSSQ9
A3 FBx_CMD13 RST#
B G4 C3 B
VDD3 VSSQ10
L4
VDD4 VSSQ11
E3 FBVDDQ FBx_CMD14 CKE#
C5 N3 UNDER DRAM
VDD5 VSSQ12
R5
VDD6 VSSQ13
R3 FBx_CMD15 CAS#
C10 U3
VDD7 VSSQ14
R10
VDD8 VSSQ15
C4 2 2 2 2 FBx_CMD16 CS#
D11 R4

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDD9 VSSQ16
G11
VDD10 VSSQ17
F5 FBx_CMD17 A3_BA3
L11 M5
VDD11 VSSQ18 1 1 1 1 FBx_CMD18 A2_BA0

OPT@

OPT@

OPT@

OPT@
P11 F10
G14 VDD12 VSSQ19 M10

CV394

CV388

CV389

CV390
VDD13 VSSQ20
L14
VDD14 VSSQ21
C11 FBx_CMD19 A4_BA2
R11
VSSQ22
VSSQ23
A12 FBx_CMD20 A5_BA1
C12
VSSQ24
VSSQ25
E12 FBx_CMD21 WE#
N12 UNDER DRAM
VSSQ26
VSSQ27
R12 FBx_CMD22 A7_A8
170-BALL U12
VSSQ28
VSSQ29
H13 2 2 2 2 FBx_CMD23 A6_A11
SGRAM GDDR5 K13

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ30
VSSQ31
A14 FBx_CMD24 ABI#
C14
FBVDDQ VSSQ32 1 1 1 1 FBx_CMD25 A12_RFU

OPT@

OPT@

OPT@

OPT@
E14
VSSQ33 N14

CV395

CV391

CV393

CV392
VSSQ34
VSSQ35
R14 FBx_CMD26 A0_A10
U14
VSSQ36
1

FBx_CMD27 A1_A9
RV166
549_0402_1%
16 mil X76@
FBx_CMD28 RAS#
OPT@ H5GC2H24BFR-T2C_BGA170
FBx_CMD29 RST#
2

1 2 +FBC_VREFC0
+FBC_VREFC0 33
RV167 FBx_CMD30 CKE#
1

931_0402_1% 1
OPT@ RV168 CV216 FBx_CMD31 CAS#
1.33K_0402_1% 820P_0402_25V7
A OPT@ OPT@ A
2
2

D
1

2
27,30 MEM_VREF G QV28
S LBSS138LT1G_SOT-23-3
3

OPT@
Security Classification LC Future Center Secret Data Title
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM B Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, N ovem ber 25, 2016 Sheet 32 of 75
5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Upper 32 bits(MF=0)

UV10
MF=0 MF=1 MF=1 MF=0

FBC_D32 FBC_D[32..39] 26 BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2

A4
FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
26 FBC_EDC4 FBC_EDC5 EDC0 EDC3 DQ25 DQ1 FBC_D34
C13 B4
26 FBC_EDC5 FBC_EDC6 EDC1 EDC2 DQ26 DQ2 FBC_D35
R13 B2
26 FBC_EDC6 FBC_EDC7 EDC2 EDC1 DQ27 DQ3 FBC_D36
R2 E4
26 FBC_EDC7 EDC3 EDC0 DQ28 DQ4 FBC_D37
E2
DQ29 DQ5 F4 FBC_D38
FBC_DBI4# D2 DQ30 DQ6 F2 FBC_D39
26 FBC_DBI4# FBC_DBI5# DBI0# DBI3# DQ31 DQ7 FBC_D40 FBC_D[40..47] 26 BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
D13 A11
26 FBC_DBI5# FBC_DBI6# DBI1# DBI2# DQ16 DQ8 FBC_D41
D P13 A13 D
26 FBC_DBI6# FBC_DBI7# DBI2# DBI1# DQ17 DQ9 FBC_D42
P2 B11
26 FBC_DBI7# DBI3# DBI0# DQ18 DQ10 FBC_D43
B13
FBC_CLK1 J12 DQ19 DQ11 E11 FBC_D44
26 FBC_CLK1 FBC_CLK1# CK DQ20 DQ12 FBC_D45
J11 E13
26 FBC_CLK1# FBC_CKE_H CK# DQ21 DQ13 FBC_D46
J3 F11
26 FBC_CKE_H CKE# DQ22 DQ14 FBC_D47
F13 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
DQ23 DQ15 FBC_D48 FBC_D[48..55] 26
U11
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49
26 FBC_MA2_BA0_H FBC_MA5_BA1_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D50
26 FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51
Follow DG 26 FBC_MA4_BA2_H FBC_MA3_BA3_H BA2/A4 BA0/A2 DQ11 DQ19 FBC_D52
H10 N11
26 FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53
FBC_CLK1 1 2 DQ13 DQ21 M11 FBC_D54
FBC_MA7_MA8_H DQ14 DQ22 FBC_D55
BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
RV178 K4 M13
26 FBC_MA7_MA8_H FBC_MA1_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBC_D56 FBC_D[56..63] 26
40.2_0402_1% H5 U4
OPT@ 26 FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D57
26 FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25
1

FBC_MA6_MA11_H K5 T4 FBC_D58
RV179 26 FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_D59
80.6_0402_1% 26 FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 N4 FBC_D60
@ A5 DQ4 DQ28 N2 FBC_D61
U5 VPP/NC1 DQ5 DQ29 M4 FBC_D62
VPP/NC2 DQ6 DQ30
2

M2 FBC_D63
DQ7 DQ31
FBC_CLK1# 1 2 RV172 2 1 1K_0402_1% OPT@ J1 FBVDDQ
RV180 RV174 2 1 1K_0402_1% OPT@ J10 MF
40.2_0402_1% RV175 2 1 121_0402_1% OPT@ J13 SEN B1
0.01U_0402_25V7K

1 ZQ VDDQ1
OPT@ D1
VDDQ2 F1
FBC_ABI#_H J4 VDDQ3 M1
2 26 FBC_ABI#_H FBC_RAS#_H ABI# VDDQ4 Cost down list:
OPT@

G3 P1
26 FBC_RAS#_H FBC_CS#_H G12 RAS# CAS# VDDQ5 T1 2A Peak 3A 22U 2Pcs
CV234

26 FBC_CS#_H FBC_CAS#_H CS# WE# VDDQ6

L3 G2
26 FBC_CAS#_H FBC_WE#_H CAS# RAS# VDDQ7
L12 L2
26 FBC_WE#_H WE# CS# VDDQ8
VDDQ9
VDDQ10
B3
D3 GDDR5
C 26 FBC_WCK2_N
FBC_WCK2_N D5
WCK01# WCK23#
VDDQ11
VDDQ12
F3
H3
FBVDDQ UV10 SIDE Mode H - Mirror Mode Mapping C
FBC_WCK2 D4 K3
26 FBC_WCK2 WCK01 WCK23 VDDQ13 M3
FBC_WCK3_N VDDQ14
P5 P3 DATA Bus

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
26 FBC_WCK3_N WCK23# WCK01# VDDQ15 2 2 2 2 2 2 2 2 2
FBC_WCK3 P4 T3

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
26 FBC_WCK3 WCK23 WCK01 VDDQ16
VDDQ17
E5 Address 0..31 32..63
N5
VDDQ18 1 1 1 1 1 1 1 1 1 FBx_CMD0 CS#

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
A10 E10
U10 VREFD1 VDDQ19 N10

CV397

CV398

CV400

CV399

CV402

CV401

CV404

CV403

CV405
+FBC_VREFC0 VREFD2 VDDQ20
J14
VREFC VDDQ21
B12 FBx_CMD1 A3_BA3
D12
VDDQ22
VDDQ23
F12 FBx_CMD2 A2_BA0
H12
FBC_RST#_H VDDQ24
26 FBC_RST#_H J2
RESET# VDDQ25
K12 AROUND DRAM Cost down CLOSE TO DRAM FBx_CMD3 A4_BA2
M12
VDDQ26
VDDQ27
P12 FBx_CMD4 A5_BA1
T12
VDDQ28 G13 FBx_CMD5 WE#

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
VDDQ29 2 2 2 2 2 2 2

1
H1 L13

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSS1 VDDQ30
K1
VSS2 VDDQ31
B14 FBx_CMD6 A7_A8
B5 D14
VSS3 VDDQ32

2
1 1 1 1 1 1 1 FBx_CMD7 A6_A11

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
G5 F14

CV406

CV408

CV407

CV409

CV410
L5 VSS4 VDDQ33 M14

CV412

CV413

CV411

CV414

CV415

CV416

CV396
VSS5 VDDQ34
T5
VSS6 VDDQ35
P14 FBx_CMD8 ABI#
16 mil B10
D10 VSS7 VDDQ36
T14
FBx_CMD9 A12_RFU
G10 VSS8
VSS9
L10
VSS10 VSSQ1
A1 AROUND DRAM CLOSE TO DRAM FBx_CMD10 A0_A10
+FBC_VREFC0 P10 C1
32 +FBC_VREFC0 VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 FBx_CMD11 A1_A9
1 H14 N1
VSS13 VSSQ4
CV235 K14
VSS14 VSSQ5
R1 FBx_CMD12 RAS#
820P_0402_25V7 FBVDDQ U1
VSSQ6
2
OPT@
VSSQ7
H2 FBx_CMD13 RST#
G1 K2
VDD1 VSSQ8
L1
VDD2 VSSQ9
A3 FBVDDQ FBx_CMD14 CKE#
G4 C3 UNDER DRAM
VDD3 VSSQ10
B L4
VDD4 VSSQ11
E3 FBx_CMD15 CAS# B
C5 N3
VDD5 VSSQ12
R5
VDD6 VSSQ13
R3 2 2 2 2 FBx_CMD16 CS#
C10 U3

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDD7 VSSQ14
R10
VDD8 VSSQ15
C4 FBx_CMD17 A3_BA3
D11 R4
VDD9 VSSQ16 1 1 1 1 FBx_CMD18 A2_BA0

OPT@

OPT@

OPT@

OPT@
G11 F5
L11 VDD10 VSSQ17 M5

CV423

CV417

CV419

CV418
VDD11 VSSQ18
P11
VDD12 VSSQ19
F10 FBx_CMD19 A4_BA2
G14 M10
VDD13 VSSQ20
L14
VDD14 VSSQ21
C11 FBx_CMD20 A5_BA1
R11
VSSQ22
VSSQ23
A12 FBx_CMD21 WE#
C12 UNDER DRAM
VSSQ24
VSSQ25
E12 FBx_CMD22 A7_A8
N12
VSSQ26
VSSQ27
R12 2 2 2 2 FBx_CMD23 A6_A11
170-BALL U12

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ28
VSSQ29
H13 FBx_CMD24 ABI#
SGRAM GDDR5 K13
VSSQ30 1 1 1 1 FBx_CMD25 A12_RFU

OPT@

OPT@

OPT@

OPT@
A14
VSSQ31 C14

CV424

CV421

CV422

CV420
VSSQ32
VSSQ33
E14 FBx_CMD26 A0_A10
N14
VSSQ34
VSSQ35
R14 FBx_CMD27 A1_A9
U14
VSSQ36
FBx_CMD28 RAS#
X76@
FBx_CMD29 RST#
H5GC2H24BFR-T2C_BGA170
FBx_CMD30 CKE#
FBx_CMD31 CAS#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM B Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, N ovem ber 25, 2016 Sheet 33 of 75
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: F riday, Novem ber 25, 2016 Sheet 34 of 75
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

V20B+ +LED_VDD
1A Inrush 2A

+LCD_VDD 1A Inrush 2A 2A 80 mil 2A 80 mil

R17 1 2 0_0805_5%

4.7U_0805_25V6K
+3VS

0.1U_0402_25V6
1 1
C15
U9 AO3401A_SOT23-3 EMC@

C14
R22 1 2 0_0603_5% 1 5

CD@
OUT IN Q33 3 1 @ 2 2

D
2

.1U_0402_10V6-K
EMI Request
4.7U_0603_6.3V6K
C7

C8
GND
1 1
D 2 1 3 4 D

G
OCB EN

2
CD@
R275
0_0402_5% R179 1 @ 2 LEDVDD_EN#
2 2 V20B+
@ SY6288C20AAC_SOT23-5 100K_0402_5%

1
Change U9 to Common pool main source HLZ SIV 0811 R180
100K_0402_5%
@

1 2
14 PCH_EDP_ENVDD R6 1 2 0_0402_5%
PCH_EDP_ENVDD R181 1 @
0_0402_5%
2 2
G
Q34 D
For Battery Life test
1

.1U_0402_10V6-K
1 1
R7 C132 @ S

3
100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3

C23

CD@
@
2 2 2

1. EDP CONN pin define change

Reserve for power consumption test
2. Delete CMOS camera CONN
HLZ SDV 20160510

EMI request
Update eDP CONN based on ME CONN list
DMIC_CLK DISPOFF# INVT_PWM
Update eDP CONN based on ME CONN list HLZ SIV 07/26

470P_0402_50V7K
470P_0402_50V7K
C12

C13
1 1 1 JEDP1
R299 1 2 0_0402_5% ENBKL 2A 80 mil

EMC_NS@
14 PCH_EDP_ENBKL ENBKL 49
C11 1

EMC_NS@
C +LED_VDD 1 C
R10 2 1 100K_0402_5% 10P_0402_50V8J 2
2 EMC@ 2 2 3 2
4 3
5 4
1A Inrush 2A 5
R12 1 2 0_0402_5% DISPOFF# +LCD_VDD 6
49 BKOFF# 6
7
DISPOFF# 8 7
Change C11 from ns to stuff INVT_PWM 9 8
HLZ SIT 0922 PCH_EDP_HPD 10 9
11 10
+3VS 12 11
13 12
CPU_EDP_TX1- C16 1 2 .1U_0402_10V6-K EDP_TX1- 14 13
8 CPU_EDP_TX1- 14
2

CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 15

8 CPU_EDP_TX1+ 15
R18 16
1K_0402_5% CPU_EDP_TX0- C18 1 2 .1U_0402_10V6-K EDP_TX0- 17 16
8 CPU_EDP_TX0- CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 18 17
@
8 CPU_EDP_TX0+ 18
19
19
1

CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 20

INVT_PWM PCH_EDP_HPD 8 CPU_EDP_AUX CPU_EDP_AUX# C21 EDP_AUX# 20
R19 1 2 0_0402_5% 1 2 .1U_0402_10V6-K 21
14 PCH_EDP_PWM PCH_EDP_HPD 15 8 CPU_EDP_AUX# 21
22
2 1 0_0603_5% +3VS_DMIC 23 22
+3VS 0.5A R3
23
1

R23 1 2 0_0402_5% DMIC_DATA 24

48 DMIC_DATA_R 24
1

R20 DMIC_CLK 25
48 DMIC_CLK 25
100K_0402_5% 26
R57 27 26
100K_0402_5% R24 1 @ 2 0_0402_5% USB20_P6_R 28 27
19 USB20_P6 28
2

R260 1 @ 2 0_0402_5% USB20_N6_R 29 31

19 USB20_N6 29 GND1
2

R261 2 1 0_0603_5% +3VS_CMOS 30 32

+3VS 30 GND2
0.5A 2
HIGHS_FC5AF301-3181H
C24 ME@
0.047U_0402_16V7K
1
CD@
B B

DMIC_DATA
EMC@ For EMI
EXC24CH900U_4P

10P_0402_50V8J
1

EMC_NS@
USB20_P6 USB20_P6_R

CH19
4 3
4 3

USB20_N6 1 2 USB20_N6_R 2
1 2
L7

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 35 of 75
5 4 3 2 1
 5 4 3 2 1

HDMI_TX0+ 1 2 0.1U_0402_10V7K HDMI_TX0+_REIN

8 HDMI_TX0+ CRE1
ISET
HDMI_TX0- CRE3 1 2 0.1U_0402_10V7K HDMI_TX0-_REIN
8 HDMI_TX0-
HDMI_TX1+ CRE5 1 2 0.1U_0402_10V7K HDMI_TX1+_REIN H Increase +13%
8 HDMI_TX1+
HDMI_TX1- 1 2 0.1U_0402_10V7K HDMI_TX1-_REIN
8 HDMI_TX1- CRE7
L default
HDMI_TX2+ CRE9 1 2 0.1U_0402_10V7K HDMI_TX2+_REIN
8 HDMI_TX2+
HDMI_TX2- CRE11 1 2 0.1U_0402_10V7K HDMI_TX2-_REIN M Reduce -13%
8 HDMI_TX2-
HDMI_TXC+ 1 2 0.1U_0402_10V7K HDMI_TXC+_REIN
8 HDMI_TXC+ CRE13
EQ
D HDMI_TXC- HDMI_TXC-_REIN D
8 HDMI_TXC- CRE14 1 2 0.1U_0402_10V7K
H EQ for channel loss up to 4.3 dB
DDPB_CLK
15 DDPB_CLK DDPB_DATA
15 DDPB_DATA L EQ for channel loss up to 12.4 dB
HDMI_HPD
15 HDMI_HPD
R262 1 2 100K_0402_5%
M EQ for channel loss up to 8.6 dB
PRE
H 1.6dB pre-emphasis
L no pre-emphasis
M 2.5dB pre-emphasis

+3VS
HDMI Repeater 100mA
DDCBUF
Follow Vendor suggestion to stuff REE2 +3VS
HLZ SDV 0601 URE1
H active DDC buffer with default threshold
RRE1 2 @ 1 4.7K_0402_5% DCIN_EN PS8203TQFN32GTR-A3_TQFN32_3X6 R55
VDDIO_PS8203 2 1
30 VDDIO_PS8203
RRE2 2 1 4.7K_0402_5% EQ_PS8203 HDMI_TX2+_REIN 1 VDDIO 0_0603_5%
L default,passive DDC pass-through

1U_0402_16V6K

.01U_0402_16V7-K
HDMI_TX2-_REIN 2 IN_D2P 32 DDPB_DATA 1

CRE12
IN_D2N SDA_SRC 1
HDMI_HPD 3 31 DDPB_CLK
M active DDC buffer without default threshold

CRE2
RRE4 @ HDMI_TX1+_REIN HPD_SRC SCL_SRC
2 1 4.7K_0402_5% 4
HDMI_TX1-_REIN 5 IN_D1P 29 HDMI_DAT_CON
IN_D1N SDA_SNK 2
HDMI_TX0+_REIN 6 28 HDMI_CLK_CON 2
RRE3 2 1 4.7K_0402_5% PRE_PS8203 HDMI_TX0-_REIN 7 IN_D0P SCL_SNK I2C_CTL_EN
DCIN_EN 8 IN_D0N 27 HDMI_TX2+_D
DCIN_EN OUT_D2P
C
RRE18 2 @
1 4.7K_0402_5%
HDMI_TXC+_REIN
HDMI_TXC-_REIN
9
10 IN_CKp OUT_D2N
26
25
HDMI_TX2-_D
HDMI_HPD_CON H I2C control is selected C

IN_CKn HPD_SNK 24 HDMI_TX1+_D

OUT_D1P
VDD_PS8203 11
VDD OUT_D1N
23
22
HDMI_TX1-_D
HDMI_TX0+_D L Pin control is selected
Change RRE3 from @ to stuff due to 4K*2K Eye-diagram fail @ 1 PAD 12 OUT_D0P 21 HDMI_TX0-_D
IT11
HLZ SIT 0920 EQ_PS8203 13 PD#
EQ
OUT_D0N
CFG
20 PAD 1 @
IT12 CFG
19 HDMI_CLK+_D
PRE_PS8203 15 OUT_CKp 18 HDMI_CLK-_D
16 PRE OUT_CKn
REXT 17
H HDMI ID enable

EPAD
100mA

GND
CEXT
1

+3VS RRE5
L HDMI ID disable

0.1U_0402_10V7K
R56 4.99K_0402_1% 1

14

33
2 1 VDD_PS8203 CRE17
DCIN_EN
.01U_0402_16V7-K

.01U_0402_16V7-K

0_0603_5%
1U_0402_16V6K

2
1 1 1
H DC coupling input
CRE16

CRE4
CRE15

2 2 2
L default,AC coupling input
Change RRE5 from 5.9K to 4.99K due to 4K*2K Eye-diagram fail
HLZ SIT 0920 PD#
H Normal operation
L Chip power down

D3 Modify HDMI fuse based on PUR requirement

HDMI_HPD_CON 1 1 10 9 HDMI_HPD_CON
200mA 200mA
B HDMI_DAT_CON HDMI_DAT_CON B
2 2 9 8
+5VS Delete diode +5VS_HDMI_F +5VS_HDMI
HDMI_CLK_CON 4 4 7 7 HDMI_CLK_CON
F1
+5VS_HDMI 5 5 6 6 +5VS_HDMI 1 2

3 3 0.5A_6V_1206L050YRHF

8
For EMC

AZ1045-04F_DFN2510P10E-10-9
0427 Kerry Del Q25B 1 3 Q22

S
EMC_NS@
LP2301ALT1G_SOT23-3 1
C34

G
2
EMC@ .1U_0402_10V6-K

4
3
D6 HDMI_CLK-_D 4 3 HDMI_CLK-_CON
HDMI_CLK+_CON HDMI_CLK+_CON 4 3 R59 820_0402_5% 53 SUSP 2
1 1 10 9 @
HDMI_CLK-_CON 1 2 HDMI_CLK+_CON RP1
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_CLK+_D 1 2 HDMI_CLK+_CON NEW
1 2 2.2K_0404_4P2R_5% HLZ SDV 0601

1
2
HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON L2 EXC24CH900U_4P R10023 colay with C26,C27 pin1 R151 1 @ 2 27K_0402_5%
JHDMI1
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON EMC@ R60 @ 820_0402_5% HDMI_HPD_CON 19
HDMI_TX0-_D 4 3 HDMI_TX0-_CON HDMI_TX0-_CON 1 2 HDMI_TX0+_CON 18 HP_DET
3 3 4 3 17 +5V
HDMI_DAT_CON DDC/CEC_GND
R10023 colay with C28,C29 pin1 16
SDA
8 HDMI_TX0+_D 1 2 HDMI_TX0+_CON HDMI_CLK_CON 15
1 2 R61 @ 820_0402_5% 14 SCL
For EMC L3 HDMI_TX1-_CON1 HDMI_TX1+_CON Utility
EXC24CH900U_4P 2 13 20
AZ1045-04F_DFN2510P10E-10-9 HDMI_CLK-_D R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC GND1
CK-
EMC_NS@ EMC@ R10023 colay with C30,C31 pin1 11
CK_shield GND2
21
HDMI_TX1-_D 4 3 HDMI_TX1-_CON HDMI_CLK+_D R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10
4 3 HDMI_TX0-_D R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 CK+ 22
D7 R62 @ 820_0402_5% 8 D0- GND3
HDMI_TX1-_CON 1 1 HDMI_TX1-_CON HDMI_TX1+_D HDMI_TX1+_CON HDMI_TX2-_CON 1 HDMI_TX2+_CON HDMI_TX0+_D HDMI_TX0+_CON D0_shield
10 9 1 2 2 R46 2 @ 1 0_0402_5% 7 23
1 2 HDMI_TX1-_D R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6 D0+ GND4
HDMI_TX1+_CON HDMI_TX1+_CON L4 D1-
A 2 2 9 8 EXC24CH900U_4P R10023 colay with C32,C33 pin1 5
D1_shield
A
HDMI_TX1+_D R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4
HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON EMC@ HDMI_TX2-_D R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3 D1+
HDMI_TX2-_D 4 3 HDMI_TX2-_CON 2 D2-
HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON 4 3 HDMI_TX2+_D R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
D2+
3 3 HDMI_TX2+_D 1 2 HDMI_TX2+_CON
1 2 ALLTO_C128V7-K1939-L
8 L5 EXC24CH900U_4P ME@
For EMC
For EMC Security Classification LC Future Center Secret Data Title
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ Issued Date 2015/02/26 Deciphered Date 2016/02/26 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 36 of 75
5 4 3 2 1
 5 4 3 2 1

DP Redriver
500mA
+3VS U5_VDD33
R352
1 2 0_0805_5%

.01U_0402_16V7-K
0.1U_0402_10V7K
1 1

C33

C35
U5_VDD33
2 2
D D

2
R34
4.7K_0402_5%
@

12
25
32
36

1
1
6
U5 U5_CFG1

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6

2
C272 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXP0 38 23 TBT_SNK0_DP0P_Driver C6 1 2 0.1U_0402_10V7K R35
8 TYPE-C_DP_TXP0 IN0p OUT0p TYPE-C_DP_RE_TXP0 38
C273 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXN0 39 22 TBT_SNK0_DP0N_Driver C22 1 2 0.1U_0402_10V7K 4.7K_0402_5%
8 TYPE-C_DP_TXN0 IN0n OUT0n TYPE-C_DP_RE_TXN0 38
C274 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXP1 41 20 TBT_SNK0_DP1P_Driver C26 1 2 0.1U_0402_10V7K @
8 TYPE-C_DP_TXP1 IN1p OUT1p TYPE-C_DP_RE_TXP1 38
C275 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXN1 42 19 TBT_SNK0_DP1N_Driver C27 1 2 0.1U_0402_10V7K
8 TYPE-C_DP_TXN1 IN1n OUT1n TYPE-C_DP_RE_TXN1 38

1
C276 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXP2 44 17 TBT_SNK0_DP2P_Driver C28 1 2 0.1U_0402_10V7K
8 TYPE-C_DP_TXP2 IN2p OUT2p TYPE-C_DP_RE_TXP2 38
C277 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXN2 45 16 TBT_SNK0_DP2N_Driver C29 1 2 0.1U_0402_10V7K
8 TYPE-C_DP_TXN2 IN2n OUT2n TYPE-C_DP_RE_TXN2 38
C278 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXP3 47 14 TBT_SNK0_DP3P_Driver C30 1 2 0.1U_0402_10V7K
8 TYPE-C_DP_TXP3 IN3p OUT3p TYPE-C_DP_RE_TXP3 38
C279 1 2 0.1U_0402_10V7K TYPE-C_SRC_DP_TXN3 48 13 TBT_SNK0_DP3N_Driver C31 1 2 0.1U_0402_10V7K
8 TYPE-C_DP_TXN3 IN3n OUT3n TYPE-C_DP_RE_TXN3 38
U5_VDD33
R21 1 2 0_0402_5% U5_I2C_ADDR 3 40 U5_CFG1
I2C_ADDR CFG1

2
U5_PEQ 4 46 R16 1 2 10K_0402_5%
U5_CFG0 SCL_CTL/PEQ NC1 U5_VDD33
5 R4
SDA_CTL/CFG0 35 U5_RST# C32 1 2 2.2U_0603_6.3V6K 4.7K_0402_5%
RST#
@ 1 PAD 26 10 U5_CAD_SNK R37 1 2 1M_0402_5%
IT13 PD# CAD_SNK

1
R8 1 2 4.99K_0402_1% 7 U5_PEQ
REXT 11 TBT_SNK0_HPD_SINK R15 1 2 0_0402_5%
HPD_SINK TYPE-C_DP_RE_HPD 38

2
8 R5
CAD_SRC R38 1 2 100K_0402_5% 4.7K_0402_5%
R9 1 2 0_0402_5% CPU_SNK0_HPD_R 9 28 R85 1 2 0_0402_5%
15 TYPE-C_DP_HPD HPD_SRC AUX_SNKP TYPE-C_DP_RE_AUXP 38
R11 1 2 10K_0402_5% 27 R170 1 2 0_0402_5%
AUX_SNKN TYPE-C_DP_RE_AUXN 38

1
R39 1 2 100K_0402_5% U5_VDD33
@ 1 PAD 33 R174 1 @ 2 100K_0402_5%
IT14
@ 1 PAD 34 SCL_DDC +3.3V_LDO_RTS5400 Follow Vendor suggestion to stuff R4 & R5
IT15 SDA_DDC 2 C5 1 2 2.2U_0603_6.3V6K Reserve R174 for Power leakage concern HLZ SDV 0601
CEXT 15
C2 1 2 0.1U_0402_10V7K CPU_SNK0_AUXP_C 30 NC2 21 U5_VDD33
C 8 TYPE-C_DP_AUXP C
C4 1 2 0.1U_0402_10V7K CPU_SNK0_AUXN_C 29 AUX_SRCP NC3 37
8 TYPE-C_DP_AUXN AUX_SRCN NC4 43
NC5

2
R25

GND1
GND2
GND3
4.7K_0402_5%

EPAD
@

1
U5_CFG0

18
24
31
49
PS8330BQFN48GTR2-A0_QFN48_7X7

2
R26
4.7K_0402_5%
@

1
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDI Redriver PS8330

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 37 of 75
5 4 3 2 1
 4 3 2 1

Reserved for EXT-XTAL Mode

R2079 2 @ 1 1M_0402_5%

Y1

2 3 RTS5400_24M_XTLI
GND1 OSC2
RTS5400_24M_XTLO 1 4
OSC1 GND2
1 1
D C918 24MHZ_6PF_7V24000032 C919 D
4.7P_0402_50V8-J @ 4.7P_0402_50V8-J
@ 2 2 @ U4
Connect this pin to GND to disable dead battery
Leave this pin floating to enable dead battery
49 R108 1 2 0_0402_5%
RTS5400_24M_XTLI 50 DB_CFG TYPE-C_CC1 C44 2 1 220P_0402_50V7K
XTLI 46 TYPE-C_CC1
RTS5400_24M_XTLO 51 CC1 40 TYPE-C_CC2 TYPE-C_CC1 39 CC TYPE-C_CC2 C51 2 1 220P_0402_50V7K
XTLO CC2 TYPE-C_CC2 39

+1.2V_LDO_RTS5400 TYPE-C_USB3_RX_P3 1 47 TYPE-C_RTS5400_TX2_P C9 1 2 .1U_0402_10V6-K

15 TYPE-C_USB3_RX_P3 TYPE-C_USB3_RX_N3 SSRX_P C_TX2_P TYPE-C_RTS5400_TX2_N TYPE-C_TX2_P 39
2 48 C10 1 2 .1U_0402_10V6-K
15 TYPE-C_USB3_RX_N3 SSRX_N C_TX2_N TYPE-C_TX2_N 39
USB3.0 15 TYPE-C_USB3_TX_P3
TYPE-C_USB3_TX_P3 4 45 TYPE-C_RX2_P
TYPE-C_RX2_P 39
R14 1 2 100K_0402_5% TYPE-C_DP_RE_TXP0 TYPE-C_USB3_TX_N3 5 SSTX_P C_RX2_P 44 TYPE-C_RX2_N
R27 1 2 100K_0402_5% TYPE-C_DP_RE_TXN0 15 TYPE-C_USB3_TX_N3 SSTX_N C_RX2_N TYPE-C_RX2_N 39 TX & RX
TYPE-C_DP_RE_TXP0 7 41 TYPE-C_RTS5400_TX1_P C42 1 2 .1U_0402_10V6-K
TYPE-C_DP_RE_TXP1 37 TYPE-C_DP_RE_TXP0 TYPE-C_DP_RE_TXN0 DP0_P C_TX1_P TYPE-C_RTS5400_TX1_N TYPE-C_TX1_P 39
R28 1 2 100K_0402_5%
37 TYPE-C_DP_RE_TXN0
8 42 C43 1 2 .1U_0402_10V6-K
TYPE-C_DP_RE_TXN1 DP0_N C_TX1_N TYPE-C_TX1_N 39
R30 1 2 100K_0402_5%
TYPE-C_DP_RE_TXP1
10Gbps 3:2 MUX TYPE-C_RX1_P
10 39
TYPE-C_DP_RE_TXP2 37 TYPE-C_DP_RE_TXP1 TYPE-C_DP_RE_TXN1 DP1_P C_RX1_P TYPE-C_RX1_N TYPE-C_RX1_P 39
R31 1 2 100K_0402_5% 37 TYPE-C_DP_RE_TXN1 11 38 TYPE-C_RX1_N 39
R32 1 2 100K_0402_5% TYPE-C_DP_RE_TXN2 DP1_N C_RX1_N
TYPE-C_DP_RE_TXP2 13
TYPE-C_DP_RE_TXP3 37 TYPE-C_DP_RE_TXP2 TYPE-C_DP_RE_TXN2 DP2_P
R33 1 2 100K_0402_5% 14
R40 1 2 100K_0402_5% TYPE-C_DP_RE_TXN3 DP 37 TYPE-C_DP_RE_TXN2 DP2_N
37 TYPE-C_DP_RE_TXP3
TYPE-C_DP_RE_TXP3 16 Reserved in the future +3.3V_LDO_RTS5400
TYPE-C_DP_RE_TXN3 17 DP3_P
37 TYPE-C_DP_RE_TXN3 DP3_N RTS5400_SPI_WP# R120 1 2 10K_0402_5%
RTS5400_SPI_HOLD# R113 1 2 10K_0402_5%
TYPE-C_DP_RE_AUXP 28 30 TYPE-C_SBU1 RTS5400_SPI_CS# R115 1 2 10K_0402_5%
37 TYPE-C_DP_RE_AUXP TYPE-C_DP_RE_AUXN AUX_P SBU1 TYPE-C_SBU2 TYPE-C_SBU1 39 RTS5400_SPI_CLK
37 TYPE-C_DP_RE_AUXN 29
AUX_N Low Speed MUX SBU2
31
TYPE-C_SBU2 39 SBU RTS5400_SPI_MOSI
R118 1 @ 2 20K_0402_5%
R117 1 @ 2 20K_0402_5%

64
37 TYPE-C_DP_RE_HPD HPD/GPIO5 Strap pin SPI_CS#
R2 1 2 100K_0402_5% 0:Execute codes from internal ROM .Optionally loadconfigurable futures from the external EEPROM.
@ 1 PAD 18 22 TYPE-C_USB20_A6_P4 1:Execute codes from Serial Flash.
IT19 1 PAD 19 ALT_DP0/MGPIO1/HS_DP MGPIO5/C_HS_TP 23 TYPE-C_USB20_A7_N4 TYPE-C_USB20_A6_P4 39
@
IT20 ALT_DN0/MGPIO3/HS_DN TYPE-C_USB20_A7_N4 39
C
USB2.0 2:2 MUXMGPIO7/C_HS_TN TYPE-C_USB20_B6_P4 USB2 C
20 24
19 TYPE-C_PCH_USB20_P4 21 ALT_DP1/MGPIO0 MGPIO4/C_HS_BP 25 TYPE-C_USB20_B7_N4 TYPE-C_USB20_B6_P4 39
+3.3V_LDO_RTS5400 USB2.0 19 TYPE-C_PCH_USB20_N4 ALT_DN1/MGPIO2 MGPIO6/C_HS_BN TYPE-C_USB20_B7_N4 39 Flash ROM +3.3V_LDO_RTS5400

RTS5400_SM_INT 57 U115
R109 2 1 4.7K_0402_5% RTS5400_SM_INT RTS5400_SM_SDA 58 SM_INT/GPIO13 56 RTS5400_SPI_CS# RTS5400_SPI_CS# 1 8
SM_SDA/GPIO12 SCS_N CS# VCC 1
RTS5400_SM_SCL 59 RTS5400 55 RTS5400_SPI_CLK RTS5400_SPI_MISO 2 7 RTS5400_SPI_HOLD#
SM_SCL/GPIO11 SCK 54 RTS5400_SPI_MOSI +3.3V_LDO_RTS5400 RTS5400_SPI_WP# 3 DO HOLD# 6 RTS5400_SPI_CLK C917
R110 1 2 2.2K_0402_5% RTS5400_SM_SDA MOSI 53 RTS5400_SPI_MISO 4 WP# CLK 5 RTS5400_SPI_MOSI .1U_0402_10V6-K
27 MISO GND DI 2
R112 1 2 2.2K_0402_5% RTS5400_SM_SCL 26 BB_DP/MGPIO8 63 RTS5400_I2C_EN R121 2 @ 1 4.7K_0402_5% 8M W25Q80JVSSIQ SOIC 8P
BB_DM/MGPIO9 GPIO7/I2C_EN 62 RTS5400_I2C_INT R122 2 @ 1 4.7K_0402_5%
6.2K_0402_1% 1 2 R41 34 GPIO8/I2C_INT 61 RTS5400_I2C_SCL R123 2 @ 1 4.7K_0402_5%
REXT GPIO9/I2C_SCL 60 RTS5400_I2C_SDA R124 2 @ 1 4.7K_0402_5%
Change U115 from 32M to 8M ROM
+3.3V_LDO_RTS5400 69
E-PAD
GPIO10/I2C_SDA HLZ SIT 0920
3 67 VBUS_DISCHG
6 AV33_0 GPIO0 66 PAD 1 @
VBUS_P0
.1U_0402_10V6-K

.1U_0402_10V6-K
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0402_6.3V6M

9 AV33_1 GPIO1 52 GPIO14_RTS5400 IT17 +5VALW

2 2 2 2 2 2 AV33_2 GPIO14/CC1_VNE
12 65 PAD 1 @
AV33_3 GPIO6/CC2_VNE IT18
15
C72

C73

C82
C54

C71

C83
AV33_4
1 1 1 1 1 1 32 35 LP_VMON
3V3_OUT LOC_PWR
37
1V2_OUT

1
36 VMON R51
+1.2V_LDO_RTS5400 33 VMON R42 200K_0402_1%
5V_IN 200K_0402_1% @
43 68 IMON R104 1 @ 2 100_0402_1% PAD 1 @
VCON_IN IMON IT9
4.7U_0402_6.3V6M 2 1 C84

2
For Cost dowm Not stuff

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
5V_IN_RTS5400 VMON LP_VMON
1 1 1
100mA RTS5400-GR_QFN68_8X8 C87 C88 C90

1
@ R54
10U_0603_6.3V6M

2 2 @2 R53 10K_0402_1%
.1U_0402_10V6-K

1 2
VCONN_IN 10K_0402_1% @
Change C85 from 0805 to 0603 due to LED placement
500mA
C85

C86

HLZ SIV 0811

2
2 1
10U_0805_10V6K

.1U_0402_10V6-K

1 2
C101
C102

B B

2 1 +5VALW VBUS_P0
VBUS_P0
100mA 100mA 3A
3A

1
1
+5VALW 5V_IN_RTS5400 J9 Add J9 for current test HLZ SIV 0811

1
+ C89 JUMP_43X79
150U_B2_6.3VM_R35M

1
500mA 500mA

2
R103
2
@
1 2 R171

2
+5VALW VCONN_IN 470_0603_5%
U6
1 0_0603_5%
C103 @

2
2

1U_0402_6.3V6K R105 1 2 0_0603_5% A1 A3

B1 VIN1 VOUT1 B3
@
2 U7
R136
C1 VIN2 VOUT2 C3
High enable discharge
100K_0402_5%
5 1 @ R131 VIN3 VOUT3 Low disable discharge
IN OUT

1
RTS5400_I2C_EN VBUS_EN USB_OC3# D

GND1
GND2
GND3
1 3 1 2 D3 D1 R172 Q19
D

ON OC_FLAGB USB_OC3# 19
1

2 D2 VBUS_DISCHG 1 2 2
GND Q8 0_0402_5% ISET G
1

2
4 3 LP2301ALT1G_SOT23-3 0_0402_5%
49 RTS5400_PWR_EN
G

ENB OCB
2

A2
B2
C2

2
R2078 R132 FPF2595UCX_WLCSP12 S 2N7002KW_SOT323-3

3
1

1
47K_0402_5% 100K_0402_5% R173
1

SY6288D20AAC_SOT23-5 R106 R149 100K_0402_5%

R154 @ 442_0402_1% 1.07K_0402_1%
2

1
100K_0402_5% GPIO14_RTS5400

1
@

2
Low
2

+3VALW HiZ

Change R106 from 499ohm to 442ohm

2

1
Q13 D
R2080 49 VBUS_OC_EN
2
G HLZ SIT 0920
0_0402_5% Change EC side SMbus power level HLZ SIV 0811
S 2N7002KW_SOT323-3
VBUS_OC_EN=H OC is 3A
1

3
VBUS_OC_EN=L OC is 1A
A A
Address 0xD4
Add R149 1.07K & R106 499ohm(vendor suggest 495) & Q13 to adjust OC
2
G

HLZ SDV 0531

R139 1 2 0_0402_5% 1 6 RTS5400_SM_SCL
S

49 EC_SMB_CK0
D
5
G

Q10A
EC 2N7002KDWH_SOT363-6

R140 1 2 0_0402_5% 4 3 RTS5400_SM_SDA

LC Future Center Secret Data Title
S

49 EC_SMB_DA0 Security Classification

D

Q10B 2N7002KDWH
Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB TYPE-C Controller
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
ESD 2KV AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 38 of 75

4 3 2 1
 4 3 2 1

3A
VBUS_P0
TYPE-C_CC1
38 TYPE-C_CC1
TYPE-C_CC2
38 TYPE-C_CC2

TYPE-C_SBU1
38 TYPE-C_SBU1
TYPE-C_SBU2
D 38 TYPE-C_SBU2 D

R133 1 @ 2 0_0402_5%
NEW
L22 HLZ SDV 0601
1 2 TYPE-C_USB20_A7_N4_C
38 TYPE-C_USB20_A7_N4 1 2

4 3 TYPE-C_USB20_A6_P4_C

28
27
38 TYPE-C_USB20_A6_P4 4 3 JUSBC1
EXC24CH900U_4P 24 1

GND8
GND7
GND_B12 GND_A1
EMC@
TYPE-C_RX1_P_C 23 2 TYPE-C_TX1_P_C
SSRXp1_B11 SSTXp1_A2
R134 1 @ 2 0_0402_5% TYPE-C_RX1_N_C 22 3 TYPE-C_TX1_N_C
SSRXn1_B10 SSTXn1_A3
21 4
R63 1 @ 2 0_0402_5% VBUS_B9 VBUS_A4
TYPE-C_SBU2 20 5 TYPE-C_CC1
SBU2_B8 CC1_A5
EMC@ TYPE-C_USB20_B7_N4_C TYPE-C_USB20_A6_P4_C
19 6
EXC24CH900U_4P Dn2_B7 Dp1_A6
4 3 TYPE-C_USB20_B7_N4_C TYPE-C_USB20_B6_P4_C 18 7 TYPE-C_USB20_A7_N4_C
38 TYPE-C_USB20_B7_N4 4 3 Dp2_B6 Dn1_A7
TYPE-C_CC2 17 8 TYPE-C_SBU1
1 2 TYPE-C_USB20_B6_P4_C CC2_B5 SBU1_A8
38 TYPE-C_USB20_B6_P4 1 2 16 9
L6 VBUS_B4 VBUS_A9
TYPE-C_TX2_N_C 15 10 TYPE-C_RX2_N_C
SSTXn2_B3 SSRXn2_A10
R81 1 @ 2 0_0402_5% TYPE-C_TX2_P_C 14 11 TYPE-C_RX2_P_C
SSTXp2_B2 SSRXp2_A11

GND6
GND5
13 12
GND_B1 GND_A12
R84 1 @ 2 0_0402_5% HIGHS_UB11246-25A0C-1H
C C

26
25
ME@

L1
1 2 TYPE-C_TX1_N_C
38 TYPE-C_TX1_N 1 2

4 3 TYPE-C_TX1_P_C
38 TYPE-C_TX1_P 4 3
EXC24CH900U_4P
EMC@

R86 1 @ 2 0_0402_5% VBUS_P0

R89 1 @ 2 0_0402_5%

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K
AZ4520-01F.R7G_DFN1610P2E2

10U_0603_25V6-M
1 1 1 1 1
L12

C922

C921

C53
C920
1
TYPE-C_TX2_N_C

C924
1 2

EMC_NS@
38 TYPE-C_TX2_N 1 2
2 2 2 2 2

D18
TYPE-C_TX2_P_C

2
38 TYPE-C_TX2_P 4 3 @
4 3

2
EXC24CH900U_4P
EMC@

R91 1 @ 2 0_0402_5%
Change D18 from NXP to AZ HLZ SIT 0922
Change D18 from stuff to@ HLZ SIV 0811
R92 1 @ 2 0_0402_5%
B B

EMC@
EXC24CH900U_4P
4 3 TYPE-C_RX1_N_C
38 TYPE-C_RX1_N 4 3

1 2 TYPE-C_RX1_P_C D5 D8
38 TYPE-C_RX1_P 1 2 TYPE-C_USB20_B6_P4_C TYPE-C_USB20_B6_P4_C TYPE-C_USB20_A6_P4_C TYPE-C_USB20_A6_P4_C
9 10 1 1 9 10 1 1
L13
TYPE-C_USB20_B7_N4_C 8 9 2 2 TYPE-C_USB20_B7_N4_C TYPE-C_USB20_A7_N4_C 8 9 2 2 TYPE-C_USB20_A7_N4_C

TYPE-C_SBU1 7 7 4 4 TYPE-C_SBU1 TYPE-C_RX2_N_C 7 7 4 4 TYPE-C_RX2_N_C

R98 1 @ 2 0_0402_5%
TYPE-C_SBU2 6 6 5 5 TYPE-C_SBU2 TYPE-C_RX2_P_C 6 6 5 5 TYPE-C_RX2_P_C

3 3 3 3

8 8

R100 1 @ 2 0_0402_5% AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@

EMC@
EXC24CH900U_4P Change D5&D8&D19&D20 from stuff to@ HLZ SIV 0811
4 3 TYPE-C_RX2_N_C
38 TYPE-C_RX2_N 4 3
D19
1 2 TYPE-C_RX2_P_C TYPE-C_TX1_N_C 9 10 1 1 TYPE-C_TX1_N_C D20
38 TYPE-C_RX2_P 1 2 TYPE-C_TX2_P_C TYPE-C_TX2_P_C
9 10 1 1
L21 TYPE-C_TX1_P_C 8 9 2 2 TYPE-C_TX1_P_C
TYPE-C_TX2_N_C 8 9 2 2 TYPE-C_TX2_N_C
TYPE-C_RX1_P_C 7 7 4 4 TYPE-C_RX1_P_C
R101 1 @ 2 0_0402_5% TYPE-C_CC1 7 4 TYPE-C_CC1
7 4
TYPE-C_RX1_N_C 6 6 5 5 TYPE-C_RX1_N_C
TYPE-C_CC2 6 6 5 5 TYPE-C_CC2
A 3 3 A
3 3
8
8
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB TYPE-C Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 39 of 75
4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB TYPE-C Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 40 of 75

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Anti-ghost KB
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 41 of 75
5 4 3 2 1
 5 4 3 2 1

JTAGX R591 1 2 0_0402_5% XDP_TCK

16 JTAGX

PCH_TMS XDP_TMS 18 SPI_WP#

R593 1 2 0_0402_5%
TABLE : CPU ITP DEBUG REPORT 16 PCH_TMS

1
PCH_TDI R594 1 2 0_0402_5% XDP_TDI
16 PCH_TDI
R597
Individual DCI 2.0 CPU_TRST# R595 1 2 0_0402_5% XDP_TRST# 1K_0402_1%
No use Port w/o connector 22 CPU_TRST#
@
PCH_TDO R596 1 2 0_0402_5% XDP_TDO
16 PCH_TDO

2
D D

R591 NO ASM NO ASM ASM PCH_PRDY# R657 1 2 0_0402_5% XDP_PRDY#

22 PCH_PRDY#
R593 NO ASM NO ASM ASM PCH_PREQ# R658 1 2 0_0402_5% XDP_PREQ# Reference Intel document 546884 SKL PHG
22 PCH_PREQ#
R594 NO ASM NO ASM ASM
R595 NO ASM NO ASM ASM
R596 NO ASM NO ASM ASM
R657 NO ASM NO ASM ASM
R658 NO ASM NO ASM ASM Delete R93
VCCST
R102 NO ASM ASM NO ASM
R597 NO ASM ASM NO ASM
R9907 NO ASM ASM ASM

2
R168 R169
JXDP1 NO ASM ASM NO ASM 51_0402_1% 51_0402_1%
@ @
C70 NO ASM ASM NO ASM

1
R96 NO ASM ASM NO ASM
R101 NO ASM ASM NO ASM XDP_TMS
PCH_TDI R217 1 @ 2 0_0402_5% TDI
R9909 NO ASM ASM ASM XDP_TDI +3VALW +1.0VALW
C PCH_TDO R218 1 @ 2 0_0402_5% TDO C
R9910 NO ASM ASM ASM
VCCST
R9916 NO ASM ASM ASM
R99 NO ASM ASM ASM 2 @
C70
R9912 NO ASM ASM ASM

2
0.1U_0402_25V6
R233 @ 1
R9934 NO ASM ASM ASM 51_0402_1% 1K_0402_5%
R234
R9930 NO ASM ASM ASM

1
R9931 NO ASM ASM ASM R99 1 @ 2 0_0402_5%
16 PCH_TCK @
R219 1 2 0_0402_5% PAD 1 @
R9932 NO ASM ASM ASM 6 XDP_TCK IT21
PCH_TMS R220 1 @ 2 0_0402_5%
R9933 NO ASM ASM ASM R221 1 @ 2 0_0402_5% PAD 1 @
6 XDP_TMS @ IT22
R222 1 2 0_0402_5% TDI PAD 1 @
6 XDP_TDI @ IT23
R223 1 2 0_0402_5% PAD 1 @
6 XDP_TRST# @ IT24
6 XDP_TDO R224 1 2 0_0402_5% TDO PAD 1 @
IT25
LOGIC PAD 1 @
16 SYS_RESET# @ IT26
R225 1 2 1K_0402_5% PAD 1 @
18,27,43,45,49,50 PLT_RST# @ IT27
R226 1 2 1K_0402_5%
TABLE : PCH ITP DEBUG REPORT 16,49 PCH_PWROK

R228 1 @ 2 0_0402_5% PAD 1 @

No use Individual DCI 2.0 16,49 SYS_PWROK IT29
Port w/o connector @
EC_RSMRST# R229 1 2 1K_0402_5% PAD 1 @
16,49 EC_RSMRST# IT30
B R230 1 @ 2 0_0402_5% PAD 1 @ B
R93 NO ASM ASM NO ASM 6 CFG3 IT31

JXDP1 NO ASM ASM NO ASM

R9917 NO ASM ASM NO ASM
R231 1 @ 2 0_0402_5% PAD 1 @
R101 NO ASM ASM NO ASM 6 XDP_PRDY#
R232 1 @ 2 0_0402_5% PAD 1 @
IT32
6 XDP_PREQ# IT33
R9908 NO ASM ASM NO ASM

1
R9911 NO ASM ASM NO ASM R322
1K_0402_1%
R9913 NO ASM ASM NO ASM @ Change XDP CONN to Test Point
R9915 NO ASM ASM NO ASM HLZ SVD 0527

2
LOGIC +3VS
GPP_B18_NO_REBOOT
* 0 = Di s abl e ¨ No Reboot mode . ( Def aul t)
〃

1 = Enabl e ¨ No Reboot mode ( PCH wi l l di s abl e t he

〃

TABLE : Functional Strap TCO

1

GPP_B18/GSPI0_MOSI (No Reboot) R563 Ti mer s ys t em r eboot f eat ur e) . Thi s f unct i on i s us ef ul

R563 when r unni ng I TP/ XDP.
HIGH Enable "No Reboot" Mode ASM 1K_0402_5% Place near PCH
@
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC
2

A A
GPP_B18_NO_REBOOT GPP_B18_NO_REBOOT 20

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 42 of 75
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_CR
500mA RW1
1 2

0_0603_5%

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K
2
2 2
500mA

CW1

CW2

CW3
1
D
1 1 +CARD_3V SD / MMC D

NEW
JREAD1
4 HLZ SDV 0601
VID;1217 VDD

.1U_0402_10V6-K
SD_D0 7
Close Pin9&Pin11 Close Pin16 Close Pin28 DID:8621 @
1
CW5
SD_D1
SD_D2
8
9
DAT0
DAT1
UW 1 SD_D3 1 DAT2
2 CD/DAT3
1 28 +3VS_CR SD_CD# 11
17 CLK_PCIE_CR# PE_REFCLKM PE_33VCCAIN SD_WP C/D
10
2 27 LDO_V12 CW 6 2 1 .1U_0402_10V6-K W/P
17 CLK_PCIE_CR PE_REFCLKP PE_PDLL_12VCCAIN SD_CMD
SD_D2_R
Close to Connector SD_CLK
2
CMD
R13 1 2 191_0402_1% 3 26 5
PE_REXT SD_D2 CLK
PCIE_PTX_C_DRX_N2 4 25 SD_D3_R 3 12
19 PCIE_PTX_C_DRX_N2 PE_RXM SD_D3 VSS1 GND_1
6 13
PCIE_PTX_C_DRX_P2 5 24 SD_CMD_R VSS2 GND_2
19 PCIE_PTX_C_DRX_P2 PE_RXP SD_CMD
C CW7 2 1 .1U_0402_10V6-K PCIE_PRX_C_DTX_P2 6
BH611FJ1LN 23 SD_CLK_R
DEREN_434277101101RHF_NR
C
ME@
19 PCIE_PRX_DTX_P2 PE_TXP 28-QFN SD_CLK
CW8 2 1 .1U_0402_10V6-K PCIE_PRX_C_DTX_N2 7 22 SD_D0_R
19 PCIE_PRX_DTX_N2 PE_TXM SD_D0
CW9 2 1 4.7U_0603_6.3V6K LDO_V12 8 21 SD_D1_R
LDO_12VOUT SD_D1
+3VS_CR 9 20
LDO_VIN1 CLKREQ# CR_CLKREQ# 17
CW 10 2 1 1U_0402_10V6K 10 19 SD_WP
LDO_CAP SD_WPI
11 18 SD_CD#
LDO_VIN2 SD_CD#
12 17
MAIN_LDO_EN SD_IO_LDO_CAP
PLT_RST# 13 16 +3VS_CR FOR EMI

.1U_0402_10V6-K
18,27,42,45,49,50 PLT_RST# PE_RST# SD_IO_SKT_33VIN
2 2
14 15 +CARD_3V
GND SD_SKT_33VOUT SD_D0_R RW2 2 1 0_0402_5% SD_D0

CW12
CW11
29 4.7U_0603_6.3V6K CW13 1 2 5.6P_0402_50V8-D
Exposed_Pad 1 1 EMC_NS@
2
SD_D1_R RW3 2 1 0_0402_5% SD_D1
CW182,CW183 Close to CPU. BH611FJ1LN_QFN28_4X4 CW4 CW14 1 2 5.6P_0402_50V8-D
B 1U_0402_6.3V6K EMC_NS@ B
1 SD_D2_R RW4 2 1 0_0402_5% SD_D2
CW15 1 2 5.6P_0402_50V8-D
EMC_NS@
SD_D3_R RW5 2 1 0_0402_5% SD_D3
CW16 1 2 5.6P_0402_50V8-D
Close to pin15 SD_CMD_R
EMC_NS@
SD_CMD
RW7 2 1 0_0402_5%
Delete SD_WP & SD_CD# connect 0ohm CW17 1 2 5.6P_0402_50V8-D
HLZ SVD 0527 EMC_NS@
SD_CLK_R RW8 2 1 0_0402_5% SD_CLK
PLT_RST# CW18 1 2 5.6P_0402_50V8-D
EMC_NS@

1
C928 Close to UW1 Placement
1000P_0402_50V7K
2 For micro SD 插槽
SDW P signal

Add C928 due to signal waveform abnormal

A HLZ SIV 0811 A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2016/02/26 Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 43 of 75
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

4.7K_0402_5%

4.7K_0402_5%
Fintek thermal sensor

2
100mA REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

R881

R882
placed near DIMM Trace width/space:10/10 mil
+3VS @ @
U1 Trace length:<8"

1
D D
EC_SMB_CK2_R 2 0_0402_5%
1
VCC SCL
10 R183 1 @
EC_SMB_CK2 1 6,2 7,49 Near CPU core
REMOTE1+ 2 9 EC_SMB_DA2_R R184 1 @ 2 0_0402_5% REMOTE1+
Near GPU&VRAM REMOTE2+
1 DP1 SDA EC_SMB_DA2 1 6,2 7,49 1

1
C
1

1
C47 REMOTE1- 3 8 THEM_ALERT# R301 1 @ 2 0_0402_5% C C46 2 Q16
.1U_0 402_10V6-K DN1 ALERT# SMB1 _ALERT# 16
C45 2 Q15 3300P_0402_50V7-K B MMBT390 4W H_SOT323-3
CD@ 2 REMOTE2+ 4 7 THERM_L 3300P_0402_ 50V7-K B MMBT3904W H_SOT323-3 @ 2 E
DP2 THERM#

3
@ 2 E REMOTE2-

3
REMOTE2- 5 6 REMOTE1-
DN2 GND

F75303M_MSOP10

Address 1001_101xb

Near GPU&VRAM Near CPU

+5VLP +5VLP
+5VLP

HW thermal sensor

2
+3VALW
2

C25 4 R29 R36 +3VALW

C 0.1U_0603_25V7-M 21.5K_04 02_1% 21.5K_0402_1% C
@ @ @
1

1
1

1
R17 8
U18 13.7K_0 402_1% R182
1 8 TMSNS1 R88 1 @ 2 0_0402_5% NTC_V1_GPU 13.7K_04 02_1%
VCC TMSNS1 NTC_V1_GPU 49

2
2 7 PHYST1 R175 1 @ 2 10K_040 2_5% NTC_V1 _GPU
GND RHYST1

2
NTC_V2_CPU

1
3 6 TMSNS2 R176 1 @ 2 0_0402_5% NTC_V2_CPU
OT1 TMSNS2 NTC_V2_CPU 49
RT2

1
4 5 PHYST2 R177 1 @ 2 10K_040 2_5% 100K_0402_1%_NCP15 W F104F03RC
49,60 EC_ON OT2 RHYST2 RT3
G718TM1U_SOT23-8 100K_0402_1%_NCP15W F104F03 RC

2
@

2
over temperature threshold:

2
RSET=3*RTMH R18 6
0_0402_5%
92+/-30C
Hysteresis temperature threshold.

1
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

for layout optimized, change the EC_AGND to GND

Near DIMM
+3VALW
1

B B
R380
13.7K_0402_1% FAN Conn
Update FAN CONN based on ME SDV CONN list
2

Update FAN CONN based on ME SIT CONN list

NTC_V3_DIMM
49 NTC_V3_DIMM 0.5A +5VS JFAN1
R52
1 2 0_0603_5% +5VS_FAN1 8
8
1

1 1 49 EC_FAN1_SPEED 7
RT1 C50 6 7
49 EC_FAN1_PW M 6
100 K_0402_1%_NCP15W F104F03RC C49 .1U_0402_10V6-K 5 10
10U_0805_10V6K @ 4 5 GND2
2 2 3 4
49 EC_FAN2_PW M 3
2

49 EC_FAN2_SPEED 2 9
2 GND1
0.5A +5VS
1
1
2

R75 ACES_50228-00871-001
R187 R188 1 2 0_0603_5% +5VS_FAN2 ME@
0_0402_5% 0 _0402_ 5%
@ 1 1
C60
1

C81 .1U_0402_10V6-K
10U_0805_10V6K @
2 2

EC_AGND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 44 of 75

5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) JW LAN2

Update WLAN CONN based on ME conn list
HLZ SDV 0601 +3VS_WLAN +3VS

1 2
1A +3VS Need short +3VS_W LAN
19 USB20_P10
3 GND1 3.3VAUX1 4
J3 @ 5 USB_D+ 3.3VAUX2 6 1 @ T1

49.9K_0402_1%

49.9K_0402_1%
19 USB20_N10 USB_D- LED1#
1 2 7 8
1 2 GND2 PCM_CLK/I2S_SCK

1
9 10
JUMP_43X79 11 SDIO_CLK PCM_SYNC/I2S_WS 12
1

R344

R345
C110 13 SDIO_CMD PCM_IN/I2S_SD_IN 14
1U_0402_10V6K 15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T2
@ 17 SDIO_DATA1 LED#2 18
SDIO_DATA2 GND11

2
2 19 20
21 SDIO_DATA3 UART_WAKE# 22 PCH_UART2_RXD
SDIO_WAKE# UART_RXD PCH_UART2_RXD 20
23
SDIO_RESET#
1 Change AOAC option 1
HLZ SDV 0606
KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 PCH_UART2_TXD
GND3 UART_TXD PCH_UART2_TXD 20
35 34
19 PCIE_PTX_C_DRX_P3 PETP0 UART_CTS
37 36
19 PCIE_PTX_C_DRX_N3 PETN0 UART_RTS EC_TX_RSVD EC_TX
39 38 R2075 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R2067 1 @ 2 0_0402_5% EC_RX
19 PCIE_PRX_DTX_P3 PERP0 VENDOR_DEFINED2
WLAN 19 PCIE_PRX_DTX_N3
43
PERN0 VENDOR_DEFINED3
42
45 44
47 GND5 COEX3 46 BT_OFF# R77 1 2 0_0402_5%
17 CLK_PCIE_W LAN REFCLKP0 COEX2 EC_RX 49
49 48
17 CLK_PCIE_W LAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R2076 1 2 0_0402_5%
WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 16
53 52
CLKREQ0# PERST0# BT_OFF# PLT_RST# 18,27,42,43,49,50
R167 1 @ 2 0_0402_5% 55 54 R2070 1 2 1K_0402_5%
16,49 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_BT_OFF# 20
57 56 R2066 1 2 0_0402_5%
GND7 W_DISABLE1# PCH_WLAN_OFF# 20
R2071 1 @ 2 0_0402_5%
49,50 LAN_WAKE#
59 58 SMB_DATA_S3_R R2068 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA SMB_CLK_S3_R SMB_DATA_S3 12,13,16,50
61 60 R2069 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 12,13,16,50
63 62
65 GND8 ALERT# 64 EC_TX_R R2074 1 2 0_0402_5%
RSRVD/PERP1 RSRVD EC_TX 49
67 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_W LAN
71 GND9 UIM_POWER_SNK/CLKREQ1# 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
RSRVD/REFCLKN1 3.3VAUX3

1
75 74
Change AOAC option GND10 3.3VAUX4 R2073
HLZ SDV 0606 77
GND15 GND14
76 100K_0402_5% PLT_RST#

2
1
2 ARGOS_NASE0-S6701-TS40 C926 2
ME@ 1000P_0402_50V7K

R80 1 2 0_0402_5% W LAN_CLKREQ_Q# 2

17 WLAN_CLKREQ#

If support AOAC, NC R80;

Add C926 due to signal waveform abnormal
if not support AOAC, stuff R80. HLZ SIV 0811

NEW
M.2 SSD(SATA/PCIE) 1
JSSD1 HLZ SDV 0601
2
+3.3V_NGFF

3 GND_1 3.3V_1 4
+3VS PCIE_PRX_DTX_N12 5 GND_2 3.3V_2 6
J1 2A PCIE_PRX_DTX_P12 7 PERN3
PERP3
N/C_2
N/C_3
8
2
1 2 9 10 C238
1 2 +3.3V_NGFF PCIE_PTX_DRX_N12_C GND_3 DAS/DSS#/LED1#
11 12 .1U_0402_10V6-K
JUMP_43X79 PCIE_PTX_DRX_P12_C 13 PETN3 3.3V_3 14 1
22U_0603_6.3V6-M

4.7U_0402_6.3V6M

1 1 PETP3 3.3V_4
@ 15 16 +3.3V_NGFF
.1U_0402_10V6-K

1 GND_4 3.3V_5
PCIE_PRX_DTX_N11 17 18
C239

C240

CD@

PCIE_PRX_DTX_P11 19 PERN2 3.3V_6 20

C241

CD@

2 2 21 PERP2 N/C_4 22
2 PCIE_PTX_DRX_N11_C GND_5 N/C_5
Change 0805 to Jump HLZ SDV 0616 23
PETN2 N/C_6
24

2
PCIE_PTX_DRX_P11_C 25 26
27 PETP2 N/C_7 28 R95
PCIE_PRX_DTX_N10 29 GND_6 N/C_8 30 10K_0402_5%
PCIE_PRX_DTX_P10 31 PERN1 N/C_9 32 @
33 PERP1 N/C_10 34
GND_7 N/C_11

1
PCIE_PTX_DRX_N10_C 35 36
PCIE_PTX_DRX_P10_C 37 PETN1 N/C_12 38 DEVSLP0
39 PETP1 DEVSLP 40
PCIE_SATA_PRX_DTX_P9 41 GND_8 N/C_13 42
3 PCIE_SATA_PRX_DTX_N9 43 PERN0/SATA-B+ N/C_14 44 3
PERP0/SATA-B- N/C_15

2
45 46
PCIE_SATA_PTX_DRX_N9_C 47 GND_9 N/C_16 48 R97
PCIE_SATA_PTX_DRX_P9_C 49 PETN0/SATA-A- N/C_17 50 PLT_RST#
PETP0/SATA-A+ PERST# 10K_0402_5%
51 52 SSD_CLKREQ#
CLK_PCIE_SSD# GND_10 CLKREQ# SSD_CLKREQ# 17
53 54 1
17 CLK_PCIE_SSD# REFCLKN PEWAKE#

1
CLK_PCIE_SSD 55 56
17 CLK_PCIE_SSD REFCLKP NC18
57 58 TP76
GND_11 NC19 @
59 NC NC 60
61 NC NC 62 +3.3V_NGFF
63 NC NC 64
65 NC NC 66

1
67 68 +3.3V_NGFF
SSD_DET 69 N/C_1 SUSCLK 70 R274
71 PEDET 3.3V_7 72 10K_0402_5%
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9 76
GND_14 PEG2 1 1

2
77

22U_0603_6.3V6-M
.1U_0402_10V6-K

.1U_0402_10V6-K
PEG1 1
C106

C107
SSD_DET R249 1 2 0_0402_5% SSD_DET#
C237

2 2 SSD_DET# 14
ARGOS_NASM0-S6701-TS20
2
ME@
PEDET (PE_DTCT)

1
R290 SATA Device GND
10K_0402_5% PCIe Device Open
PCIE_SATA_PRX_DTX_N9 @
PCIE_SATA_PRX_DTX_P9 PCIE_SATA_PRX_DTX_N9 14 For optane Memory
PCIE_SATA_PRX_DTX_P9 14 Add C927 due to signal waveform abnormal SSD_DET#

2
PCIE_SATA_PTX_DRX_N9_C 0.22U_0402_10V6K 1 2 CC39 PCIE_SATA_PTX_DRX_N9
PCIE_SATA_PTX_DRX_P9_C 0.22U_0402_10V6K 1 2 CC165 PCIE_SATA_PTX_DRX_P9 PCIE_SATA_PTX_DRX_N9
PCIE_SATA_PTX_DRX_P9
14
14
HLZ SIV 0811 0 ‐ SATA
PLT_RST#
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_N10 14
1 ‐ PCIE
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10_C PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 14
0.22U_0402_10V6K 1 2 CC166 1
PCIE_PTX_DRX_P10_C PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 14
0.22U_0402_10V6K 1 2 CC167 C927
PCIE_PTX_DRX_P10 14
1000P_0402_50V7K
4 PCIE_PRX_DTX_N11 4
PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 14 2 DEVSLP0_R
DEVSLP0 1 2 R96
PCIE_PTX_DRX_N11_C PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 14 DEVSLP0_R 15
0.22U_0402_10V6K 1 2 CC168 0_0402_5%
PCIE_PTX_DRX_P11_C PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 14
0.22U_0402_10V6K 1 2 CC169 @
PCIE_PTX_DRX_P11 14
Ac coupling-Cap place near NGFF CONN within 500mil
PCIE_PRX_DTX_N12
PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 14
PCIE_PTX_DRX_N12_C 1 2 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 14
0.22U_0402_10V6K CC170
PCIE_PTX_DRX_P12_C PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 14
0.22U_0402_10V6K 1 2 CC171
PCIE_PTX_DRX_P12 14

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 45 of 75
A B C D E
 A B C D E F G H

Reserved
SATA HDD Cable

1
Delete C74&C75&C76&C77&C78 1
HLZ SIT 0922 Delete C66&C67&C68&C69&R342&JHDD1
HLZ SIT 0922

SATA HDD Conn.

NEW
1A JHDD2 HLZ SDV 0601
+5VS 1
SATA_PTX_DRX_P2 C1 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P2 2 GND_1
14 SATA_PTX_DRX_P2 SATA_PTX_DRX_N2 SATA_PTX_C_DRX_N2 A+
14 SATA_PTX_DRX_N2 C3 1 2 .01U_0402_16V7-K 3
4 A-
SATA_PRX_DTX_N2 C25 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N2 5 GND_2
1 1 1 1 1 14 SATA_PRX_DTX_N2 B-
C37 C38 C39 C40 C41 SATA_PRX_DTX_P2 C36 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P2 6
1000P_0402_50V7K .1U_0402_10V6-K 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K 14 SATA_PRX_DTX_P2 7 B+
2 2
@ @ @ @ GND_3
2 2 2 2 2
8
9 V33_1
10 V33_2
11 V33_3
12 GND_4
For EMC GND_5
13
R1 1 2 0_0805_5% 14 GND_6
+5VS V5_1
15
16 V5_2
17 V5_3
R191 1 @ 2 0_0402_5% 18 GND_7
19 DAS/DSS
20 GND_8 23
21 V12_1 GND1 24
22 V12_2 GND2
V12_3

Reserve R191 ns for WD HDD post need long time Hai Y520 SVT ALLTO_C16839-12239-L
ME@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 HDD/XBOX CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 46 of 75
A B C D E F G H
 A B C D E

1A +USB_VCCA

LEFT SIDE USB3.0 PORT X2 C55 1 2 100U_1206_6.3V6M

2A @
2A U2 +USB_VCCA C56 1 2
+5VALW @ 1U_0603_25V6M
1 8
GND VOUT3 C57 1 2
2 7 @ 470P_0402_50V7K
VIN1 VOUT2
NEW
@ C58 1 2 1U_0402_16V6K 3 6
VIN2 VOUT1 JUSB1 HLZ SDV 0601
USB_ON# 4 5 USB_OC1# USB30_TX_P2 C79 1 2 .1U_0402_10V6-K USB30_TX_C_P2 R74 1 @ 2 0_0402_5% USB30_TX_R_P2 9
49,50 USB_ON# EN/EN FLAG USB_OC1# 19 15 USB30_TX_P2 StdA_SSTX+
1
1 USB30_TX_N2 C80 1 2 .1U_0402_10V6-K USB30_TX_C_N2 R76 1 @ 2 0_0402_5% USB30_TX_R_N2 8 VBUS 1
1 15 USB30_TX_N2 StdA_SSTX-
SY6288D10CAC MSOP 8P C61 USB20_P2 R64 1 @ 2 0_0402_5% USB20_P2_R 3
19 USB20_P2 D+
1000P_0402_50V7K 7
@ USB20_N2 R65 1 @ 2 0_0402_5% USB20_N2_R 2 GND_DRAIN 10
Low Active 2A 2 19 USB20_N2 USB30_RX_P2 R79 1 @ 2 0_0402_5% USB30_RX_R_P2 6 D- GND_1 11
15 USB30_RX_P2 StdA_SSRX+ GND_2
4 12
USB30_RX_N2 R78 1 @ 2 0_0402_5% USB30_RX_R_N2 5 GND_5 GND_3 13
15 USB30_RX_N2 StdA_SSRX- GND_4
Change USB3.0 PWR SW from BCD to SILERGY due to BCD will EOL ALLTO_C190Y2-1-0939-L
HLZ SIT 0920 ME@

USB20_P2_R
D24
USB30_RX_R_N2 9 10 1 1USB30_RX_R_N2 USB20_N2_R +USB_VCCA

AZC199-02S.R7G_SOT23-3
L15 EMC@

2
USB30_RX_P2 1 2 USB30_RX_R_P2 USB30_RX_R_P2 8 9 2 2 USB30_RX_R_P2
1 2

AZ5425-01F.R7GR_DFN1006P2E

1
USB30_TX_R_N2 7 7 4 4 USB30_TX_R_N2 D11
USB30_RX_N2 4 3 USB30_RX_R_N2

1
4 3 USB30_TX_R_P2 6 5 USB30_TX_R_P2
6 5

EMC_NS@
EXC24CH900U_4P

U116
3 3

2
L16 EMC@
USB30_TX_C_P2 1 2 USB30_TX_R_P2 EMC_NS@
1 2

2
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

1
USB30_TX_C_N2 4 3 USB30_TX_R_N2
4 3
EXC24CH900U_4P
USB20_P1_R

USB20_N2 4
EMC@
3 USB20_N2_R
D12
USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N1_R Change USB2 ESD from single to 2in1
4 3 Change U116 & U117 & D11 from stuff to @
HLZ SIV 0811

2
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

AZC199-02S.R7G_SOT23-3
USB20_P2 1 2 USB20_P2_R
1 2 USB30_TX_R_N1 7 4 USB30_TX_R_N1
2 7 4 2
L8 EXC24CH900U_4P

EMC_NS@
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

U117
3 3

AZ1045-04F_DFN2510P10E-10-9
EMC_NS@
1A
Change C59 from D2 to ShuiTong Cap

1
+USB_VCCA HLZ SIT 0926
L9 EMC@ For EMC
USB30_RX_P1 1 2 USB30_RX_R_P1
1 2
C59 220U_6.3V_M
USB30_RX_N1 4 3 USB30_RX_R_N1 1 2

+
4 3
EXC24CH900U_4P
C62 1 2
@ 1U_0603_25V6M
L10 EMC@
USB30_TX_C_P1 1 2 USB30_TX_R_P1 C63 1 2
1 2 @ 470P_0402_50V7K

USB30_TX_C_N1 USB30_TX_R_N1
NEW
4 3
4 3 JUSB2 HLZ SDV 0601
EXC24CH900U_4P USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
15 USB30_TX_P1 StdA_SSTX+
1
EMC@ USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
USB20_N1 USB20_N1_R 15 USB30_TX_N1 USB20_P1 USB20_P1_R StdA_SSTX-
4 3 R70 1 @ 2 0_0402_5% 3
4 3 19 USB20_P1 D+
7
USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
USB20_P1 USB20_P1_R 19 USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_1
1 2 R72 1 @ 2 0_0402_5% 6 11
1 2 15 USB30_RX_P1 4 StdA_SSRX+ GND_2 12
L11 EXC24CH900U_4P USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
15 USB30_RX_N1 StdA_SSRX- GND_4
ALLTO_C190Y2-1-0939-L
3 3
ME@
For EMC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB2.0/USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 47 of 75
A B C D E
 5 4 3 2 1

Y700 A+A is 1.5V

100mA 100mA
+3VS R235 1 2 0_0402_5% DVDD-IO DVDD-IO +5VS R300 1 2 0_0402_5% AVDD1 AVDD1

C223 2 1 4.7U_0603_6.3V6K
C146 2 1 .1U_0402_10V6-K

C149 2 1 .1U_0402_10V6-K GNDA

R236 1 2 0_0402_5% DVDD DVDD 100mA

C145 1 2 .1U_0402_10V6-K RL21 1 2 0_0402_5% AVDD2
+3VS AVDD2

C217 1 2
60ohm@100Mhz 1.7A
1U_0402_10V6K
Y700 A+A is 1.5V C224 1 1U_0402_10V6K
2A 2 GNDA

C111 2 1 .1U_0402_10V6-K GNDA

D L23 D

+5VS 1 2 EMC@
BLM15PD600SN1D_2P

R166 1 @ 2 0_0805_5% PVDD PVDD

C147 2 1 .1U_0402_10V6-K PVDD

DVDD-IO AVDD1
C148 2 1 .1U_0402_10V6-K
DVDD AVDD2
LINE1-VREFO-R
C218 2 1 10U_0402_6.3V6M
U114 LINE1-VREFO-L

41

46

26

40
1

9
C219 2 1 10U_0402_6.3V6M

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
@

1
4.7K_0402_5%
4.7K_0402_5%
LINE1_L 22 43 SPK_L- Change RA1&RA2 from 49ohm to 75ohm
LINE1_R 21 LINE1-L(PO RT-C-L) SPK-OUT-L- 42 SPK_L+ HLZ SIT 0928

RA37

RA38
LINE1-R(PORT-C-R) SPK-OUT-L+
24 45 SPK_R+ 1U_0402_10V6K 2 1 C225 LINE1_R
LINE2-L(PO RT-E-L) SPK-OUT-R+

2
23 44 SPK_R-
Change CH269 from ns to stuff LINE2-R(PORT-E-R) SPK-OUT-R- LINE1_L Tr ace wi dt h i s 10 mil s
1U_0402_10V6K 2 1 C226
DMIC_CLK HLZ SIT 0922 Tr ace wi dt h i s 70 mil s
A_RING2_CONN 17 32 HP_OUTL RA1 1 2 75_0402_1%
50 A_RING2_CONN A_SLEEVE M IC2-L(PO RT-F-L)/RING HPOUT-L (PORT-I-L) HP_OUTR A_HP_OUTL_R 50
10P_0402_50V8J

1 50 A_SLEEVE
18 33 RA2 1 2 75_0402_1% A_HP_OUTR_R 50
EMC@

M IC2-R(PORT-F-R)/SLEEVE HPOUT-R(PORT-I-R)
CH269

RH5 1 2 2.2K_0402_5% LINE1-VREFO-L 31 10 PCH_HDA_SYNC

MIC2_VREF LINE1-VREFO-L SY NC PCH_HDA_BIT_CLK PCH_HDA_SYNC 16
RH7 1 2 2.2K_0402_5% LINE1-VREFO-R 30 6
2 LINE1-VREFO-R BCLK PCH_HDA_BIT_CLK 16
5 PCH_HDA_SDOUT
DMIC_DATA_R SDATA-O UT PCH_HDA_SDIN0_R PCH_HDA_SDIN0 PCH_HDA_SDOUT 16
2 8 RC2 2 1 33_0402_5%
35 DMIC_DATA_R RC181 2 DMIC_CLK_R GPIO0/DM IC-DATA SDATA-IN PCH_HDA_SDIN0 16
35 DMIC_CLK 1 33_0402_5% 3
GPIO1/DM IC-CLK 48
R102 1 2 1K_0402_5% 47 SPDIF-O UT/GPIO2
49 EC_MUTE#
R238 1 2 10K_0402_5%
16 PCH_HDA_RST#
PCH_HDA_RST# 11 PDB
RESETB
ALC3248 MONO-O UT
16
Delete MONO-OUT & CODEC_WF_MUTE# signal
HLZ SDV 0603
29 MIC2_VREF
PC_BEEP 12 M IC2-VREFO
PCBEEP
+3VS R239 1 2 100K_0402_5% 13 7 C228 1 2 4.7U_0603_6.3V6K
R240 1 2 200K_0402_5% 14 HP/LINE1_ JD(JD1) LDO3-CAP 39 C229 1 2 4.7U_0603_6.3V6K
50 HPOUT_JD M IC2/LINE2_JD(JD2) LDO2-CAP 27 C230 1 2 4.7U_0603_6.3V6K
LDO1-CAP R246 1 2 2.2K_0402_5%
C220 1 2 1U_0402_6.3V6K 37 @
35 CBP
C CBN GNDA C

+3VS 36 28 C231 1 2 1U_0402_6.3V6K

C221 1 2 4.7U_0603_6.3V6K CPVDD VREF GNDA

+3VALW R241 1 @ 2 0_0402_5% 20 15

VD33_STB SPDIFO/FRONT_JD(JD3)/GPIO3 34 C232 1 2 1U_0402_6.3V6K
R242 1 2 0_0402_5% C222 1 2 4.7U_0603_6.3V6K 19 CPVEE
+3VL M IC_CAP
To solve the background noise while combojack connecting to an R107 1 @ 2 0_0402_5% 4
DC_DET
49 25
active speaker and system entry into S3/S4/S5 without analog power. Therma l_PAD AVSS1 38
GNDA AVSS2

ALC3248-CG_MQFN48_6X6 GNDA

Change SPK CON from 5pin to 4pin HLZ SDV 0615

Update SPK CONN based on ME SIT CONN list HLZ SIT 0922

80ohm@100Mhz 2.3A JSPK1

Tr a c e wi d t h i s 3 0 mi l s 6
5 G2
SPK_R+ L17 1 EMC@ 2 BLM15PX800SN1D_2P SPK_R+_CONN 4 G1
SPK_R-
SPK_L-
L18
L19
1
1
EMC@ 2 BLM15PX800SN1D_2P
EMC@ 2 BLM15PX800SN1D_2P
SPK_R-_CONN
SPK_L-_CONN
3
2
4
3 2W
SPK_L+ L20 1 EMC@ 2 BLM15PX800SN1D_2P SPK_L+_CONN 1 2
1
Bead modify symbol HIGHS_WS32040-S0471-HF
ME@

1 1 1 1 Del et e SPK ESD

EMC@
1000P_0402_50V7K
CA31

EMC@
1000P_0402_50V7K
CA32

EMC@
1000P_0402_50V7K
CA33

EMC@
1000P_0402_50V7K
CA34

Foll ow Y700 A+A

2 2 2 2

PCH_HDA_RST#
B B
PCH_HDA_SYNC

PCH_HDA_SDOUT

RA7 1 EMC@ 2 PCH_HDA_BIT_CLK

0_0402_5%
PCH_HDA_SDIN0
SPK_L+ 1 EMC_NS@
2 15_0402_5% 1 2 220P_0402_50V7K EMC_NS@
RA3 CA1
CA6

CA9
CA7

CA8

SPK_L- Change RA7&CA8 from @ to stuff due to power noise test fail
68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

15P_0402_50V8J

33P_0402_50V8J

1 EMC_NS@
2 15_0402_5% 1 2 220P_0402_50V7K EMC_NS@
RA4 CA2 1 1 1 1 1 HLZ SIV 0811
SPK_R- 1 EMC_NS@
2 15_0402_5% 1 2 220P_0402_50V7K EMC_NS@
CA5

RA5 CA3
SPK_R+ 1 EMC_NS@
2 15_0402_5% 1 2 220P_0402_50V7K EMC_NS@
RA6 CA4 2 2 2 2 2
Delete WF AMP
EMC_NS@

EMC_NS@
EMC_NS@

EMC_NS@

HLZ SDV 0603

EMC@

For EMI For EMI

PC‐BEEP R296 1 2 0_0402_5%

DA1 R297 1 2 0_0402_5%

BEEP# 2 STUFF for power consumption test
49 BEEP# CA35
RA10
1 1 2 PC_BEEP_C 1 2 PC_BEEP R298 1 2 0_0402_5% 2015/07/06 ADD
PCH_BEEP
1

3 0_0402_5%
16 PCH_BEEP 0.1U_0402_10V7K
RA11 C108 1 2 .1U_0402_10V6-K
BAT54CW_SOT323-3 10K_0402_5% EMC_NS@

C109 1 2 .1U_0402_10V6-K
2

EMC_NS@

GNDA

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Codec_CX20752
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: F riday, Novem ber 25, 2016 Sheet 48 of 75
5 4 3 2 1
 5 4 3 2 1

+3VALW_R +VFSPI RE1 1 2 0_0603_5%

For EMI +3VL 0.5A

+3VALW RE75 1 @ 2 0_0402_5% RE3 1 2 0_0603_5% +3VALW

@
2 @ 1 RE2 CLK_PCI_EC
+3VALW _R +3VALW _R +3VALW _EC
10_0402_5% RE97 1 2 0_0402_5%
1
RE4 1 2 0_0603_5%
CE2
For SPI ROM Mirror +3VALW _R All capacitors close to EC
10P_0402_50V8J 1 1
2 @ CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
.1U_0402_10V6-K
EMC_NS@ 220P_0402_50V7K 2 1 CE24 LPC_FRAME# Close EC +3VS
+VFSPI 1
CE6
1
CE7
1
CE8
1
CE9
1
CE10
1
CE11
CE5
1000P_0402_50V7K
+3VALW_EC RE6 1 2 0_0603_5% 2 EC_AGND 2
D LPC_AD3 D
EMC_NS@ 220P_0402_50V7K 2 1 CE25 CE3 CD@ @ @
PLT_RST# 1 2 VCOREVCC 2 2 2 2 2 2
EMC_NS@ 220P_0402_50V7K 2 1 CE26 LPC_AD2
1 .1U_0402_10V6-K EC_AGND
CE1 EMC_NS@ 220P_0402_50V7K 2 1 CE27 LPC_AD1 +3VS
1000P_0402_50V7K For Cost down
EMC_NS@ 220P_0402_50V7K 2 1 CE28 LPC_AD0
2 minimum trace width 12 mil

114
121
127

106
12

11

74
26
50
92
UE1 EC_FAN2_SPEED RE66 1 2 10K_0402_5%
Reserved Cap HLZ SDV 0616

VCORE

VCC

VSTBY1
VSTBY2
VSTBY3
VSTBY4

VSTBY6

AVCC
VFSPI
VSTBY(PLL)5
EC_FAN2_PW M RE65 1 @ 2 10K_0402_5%
change CE1 from @ to stuff due to signal waveform abnormal EC_FAN1_SPEED RE10 1 2 10K_0402_5%
HLZ SIV 0811
EC_FAN1_PW M RE11 1 @ 2 10K_0402_5%
24 W RST# PW R_LED1#
KBRST# 4 24
+3VALW_R 15 KBRST# KBRST#/GPB6 PWM0/GPA0 BATT_CHG_LED# PW R_LED1# 50 LPC_FRAME#
SERIRQ 5 25 RE7 1 @ 2 10K_0402_5%
15,50 SERIRQ LPC_FRAME# ALERT#/SERIRQ/GPM6 PWM1/GPA1 BATT_LOW_LED# BATT_CHG_LED# 50
6 28
15,50 LPC_FRAME# LPC_AD3 ECS#/LFRAME#/GPM5 PWM2/GPA2 LED_KB_PW M BATT_LOW_LED# 50
7 29 ENBKL RE9 1 @ 2 100K_0402_5%
1 2 15,50 LPC_AD3 LPC_AD2 8 EIO3/LAD3/GPM3 PWM3/GPA3 30 EC_FAN2_PWM LED_KB_PWM 50
DE1 @
15,50 LPC_AD2 EIO2/LAD2/GPM2 PWM PWM4/GPA4 EC_FAN2_PW M 44
LPC_AD1 9 31 EC_FAN1_PWM
15,50 LPC_AD1 LPC_AD0 10 EIO1/LAD1/GPM1 PWM5/GPA5 32 EC_FAN1_PW M 44
BEEP#
RB751V-40_SOD323-2 15,50 LPC_AD0 CLK_PCI_EC EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 VCCIO_PG BEEP# 48
15 CLK_PCI_EC
13
ESCK/LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7
34 VCCIO_PG 53,64
RTS5400_PW R_EN
RE8 1 2 100K_0402_5% W RST#
PM_SLP_SUS#
14
15 WRST# GPC4
120
124 SUSP#
RTS5400_PW R_EN 38 Change CHG_MOD1 to RTS5400_PWR_EN +3VS
1
16 PM_SLP_SUS#
45 EC_RX
EC_RX 16 PLTRST#/ECSMI#/GPD4 GPC6 SUSP# 53,61,64 HLZ SDV 0613
EC_TX 17 SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 66 NTC_V1_GPU
45 EC_TX SOUT0/LPCPD#/GPE6 ADC0/GPI0 NTC_V1_GPU 44

2
CE12 PLT_RST# NTC_V2_CPU
1U_0402_6.3V6K 18,27,42,43,45,50 PLT_RST# EC_SCI#
22
23 ERST#/LPCRST#/GPD2 ADC1/GPI1
67
68 BATT_TEMP
NTC_V2_CPU 44 Change to NTC_V1_GPU & NTC_V2_CPU RE99
2
53
14,20 EC_SCI#
PCH_PW R_EN
PCH_PW R_EN 126 ECSCI#/GPD3
ADC
ADC2/GPI2 69 BATT_I BATT_TEMP 58,59
BATT_I 59
HLZ SDV 0613 0_0402_5%
GA20/GPB5 ADC3/GPI3
change GPB5 from PCHCMOSP to PCH_PWR_EN IT8226E-128/BX ADC4/GPI4
ADC5/DCD1#/GPI5
70
71
ENBKL
ADP_I ENBKL
ADP_I
35
59

1
ADAPTER_ID
HLZ SIV 0811 72 Change CHG_MOD2 to NTC_V3_DIMM
50 KSI[0..7]
KSI[0..7]
KSI0 58
LQFP128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 NTC_V3_DIMM ADAPTER_ID
NTC_V3_DIMM
58,59
44
HLZ SDV 0613 TP_CLK RE12 2 1 4.7K_0402_5%
KSO[0..17] KSI1 59 KSI0/STB# 78 CPU_PW RGD
+3VALW _R 50 KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 CPU_PWRGD 65 TP_DATA
KSI2 60 79 MAINPWON RE13 2 1 4.7K_0402_5%
KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC MAINPW ON 60
C KSI3 61
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
80 C
KSI4 62 81 EC_RTCRST#_ON
RPE2 KSI5 63 KSI4 DAC5/RIG0#/GPJ5
EC_SMB_CK1 KSI5 VBUS_OC_EN
1
2
4
3 EC_SMB_DA1
KSI6
KSI7
64
65 KSI6 PS2CLK0/TMB0/CEC/GPF0
85
86 PBTN_OUT# VBUS_OC_EN 38 Change CHG_MOD3 to VBUS_OC_EN +5VALW
1
C112 KSO0 36 KSI7 PS2DAT0/TMB1/GPF1 87 EC_SMB_CK0 PBTN_OUT#
EC_SMB_CK0
16
38
HLZ SDV 0531
KSO1 37 KSO0/PD0 SMCLK0/GPF2 EC_SMB_DA0 USB_ON#
2.2K_0404_4P2R_5% 1 15P_0402_50V8J
KSO1/PD1 Int. K/B PS2 SMDAT0/GPF3
88
EC_SMB_DA0 38 Add SMBUS0 for RTS5400 RE15 1 2 100K_0402_5%
C113 @ KSO2 38 89 TP_CLK SYSON_VDDQ RE64 1 @ 2 100K_0402_5%
2 KSO2/PD2 Matrix PS2CLK2/GPF4 TP_DATA TP_CLK 50 HLZ SIV 0811
15P_0402_50V8J KSO3 39 90
40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 50
@ KSO4
+3VS 2 KSO4/PD4 VGA_GATE#
KSO5 41
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
96
VGA_GATE# 20
+3VALW_R
KSO6 42 97 CPUCORE_ON
KSO6/PD6 GPH4/ID4 ME_FLASH CPUCORE_ON 6,65
RPE3 KSO7 43 98
EC_SMB_CK2 KSO7/PD7 GPH5/ID5 SYS_PW ROK ME_FLASH 16
1 4 KSO8 44 99
EC_SMB_DA2 KSO8/ACK# GPH6/ID6 SYS_PWROK 16,42
2 3 1 KSO9 45 SUSP# RE18 1 @ 2 100K_0402_5%
C117 KSO10 46 KSO9/BUSY 101 EC_SPI_CS0#
2.2K_0404_4P2R_5% 15P_0402_50V8J KSO11 51 KSO10/PE FSCE# 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
1 KSO11/ERR# FMOSI
C118 @ KSO12 52 SPI Flash ROM 103 EC_SPI_SO
+3VALW 15P_0402_50V8J 2 KSO13 53 KSO12/SLCT FMISO 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
@ KSO14 54 KSO13 FSCK
2 KSO15 55 KSO14 CPUCORE_ON RE14 1 2 100K_0402_5%
RPE4
IT34 DEL 0727 KSO16 56 KSO15 108 ACIN#
EC_SMB_CK0 KSO16/SMOSI/GPC3 AC_IN#/GPB0 LID_SW#
2 3 KSO17 57
KSO17/SMISO/GPC5 UART LID_SW#/GPB1
109
LID_SW # 50
1 4 EC_SMB_DA0 Add SMBUS0 for RTS5400
2.2K_0404_4P2R_5%
HLZ SIV 0811
ON/OFF 110 82 EC_MUTE# Mount RE30 Reserve for VGA_AC_DET
50 ON/OFF EC_ON PWRSW/GPB3 EGAD/GPE1 EC_MUTE# 48
RE96 2 @ 1 0_0402_5% 111 83 RE92 1 2 0_0402_5%
EC_SMB_CK1 XLP_OUT/GPB4 EGCS#/GPE2 ADAPTER_ID_ON# EC_ON 44,60
RE98 115 84
58,59 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 ADAPTER_ID_ON# 59 VGA_AC_DET
0_0402_5% 116 RE30 1 2 0_0402_5%
58,59 EC_SMB_DA1 SMDAT1/GPC2 VGA_AC_DET 27
2 @ 1 6,14 EC_PECI RE24 1 2 33_0402_5% PECI_EC 117 SM Bus 77 PM_SLP_S4#
PM_SLP_S4# 16
16 SUSACK# DPWROK_EC SMCLK2/PECI/GPF6 GPJ1
118 100 GPG2
16 DPW ROK_EC EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
16,27,44 EC_SMB_CK2 EC_SMB_DA2
94
95 CRX1/SIN1/SMCLK3/GPH1/ID1 GPIO SSCE1#/GPG0
125
119 SUSW ARN#
Delete AOAC_ON#
16,27,44 EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 122 LAN_W AKE# SUSW ARN# 16 HLZ SDV 0606
DTR1#/SBUSY/GPG1/ID7 113 BKOFF#
Change SUSACK# from GPF2 to GPF7 CRX0/GPC0 123 PCH_PW ROK BKOFF# 35
HLZ SIV 0811 +3VL 112
VSTBY0
CTX0/TMA0/GPB2
RI1#/GPD0
18 PM_SLP_S3# PCH_PWROK
PM_SLP_S3# 16
16,42
Delete EC_WF_MUTE#
NOVO# 107 WAKE UP 21 EC_ON_1V
50 NOVO#
B GPE4/BTN# RI2#/GPD1 76 SYSON
EC_ON_1V 63 HLZ SDV 0531 ADAPTER_ID C119 1 2 .1U_0402_10V6-K B
TACH2/GPJ0 EC_FAN2_SPEED SYSON 53,62
48 EC_FAN2_SPEED 44
TACH1A/TMA1/GPD7 47 EC_FAN1_SPEED SYSON CE13 1 2 .1U_0402_10V6-K EMC_NS@
TACH0A/GPD6 EC_FAN1_SPEED 44
USB_ON# 33 19 RE76 1 2 0_0402_5%
Change USB_CHG_EN to SYSON_VDDQ 47,50 USB_ON# SYSON_VDDQ 35 GINT/CTS0#/GPD5
GPIO
L80HLAT/BAO/GPE0 20 RE77 1 2 0_0402_5%
CAPS_LED# 50
HLZ SDV 0531 61
16,42
SYSON_VDDQ
EC_RSMRST#
EC_RSMRST# 93 RTS1#/GPE5
CLKRUN#/GPH0/ID0
L80LLAT/GPE7
GPH7
3 EC_ON_5V
EC_ON_5V 60
NUM_LED# 50

16,45 PCIE_W AKE#

RE29 1 2 0_0402_5% 2
GPJ7 Clear CMOS issue
Clock
AC_PRESENT 128 Change RE30 to 0ohm jump
+3VL 16 AC_PRESENT GPJ6/THERMTRIP_SHUTDOWN#
Delete 2nd RTCRST#
RE95 1 2 10K_0402_5% EC_ON HLZ SDV 0606
MIRROR@ RE34 1 2 0_0402_5% H_PROCHOT# 6,65
59 VR_HOT#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5

RE36 1 @ 2 10K_0402_5% BKOFF#

1
EC_SMB_CK1 PAD 1 @ QE1 D 1
IT1
RE38 2 1 100K_0402_5% LID_SW # EC_SMB_DA1 PAD 1 @ H_PROCHOT#_EC 2 CE14
IT2 PCH_RTCRST# 16
1

91
27
49

75
104

PAD 1 @ G 47P_0402_50V8J
IT3
PAD 1 @ IT8226E-128-BX_LQFP128_14X14 @
IT4 2

1
PAD 1 @ 2N7002KW _SOT323-3 S QE3 D
IT5

3
EC_RTCRST#_ON 2
RE40 1 2 100K_0402_5% BKOFF# G

KSI7 PAD 1 @ EC_AGND S 2N7002KW _SOT323-3

IT6

3
1
KSI6 PAD 1 @ @
IT7 PECI_EC
W RST# PAD 1 @ CE15 1 2 47P_0402_50V8J EMC_NS@ RE50
IT8
100K_0402_5%
BATT_TEMP CE16 1 2 100P_0402_50V8J EMC_NS@ @
For factory EC flash +3VL
Unmount QE3,QE4,RE99,RE50 by

2
ACIN# CE17 1 2 100P_0402_50V8J EMC_NS@
same net name with PCH ON/OFF CE18 1 2 1U_0402_6.3V6K EMC_NS@ +3VS
Intel request

1
EC_SPI_CS0# RE45 1 2 0_0402_5%
SPI_CS0#_R 18 RE42
+3VALW _R EC_SPI_SI RE47 1 2 0_0402_5% 100K_0402_5% +3VALW _R
SPI_SI_R0 18 1
A CE19 A
EC_SPI_SO RE48 1 2 0_0402_5% NOVO# C48 1 2 .01U_0402_16V7-K @ .1U_0402_10V6-K
SPI_SO_R0 18

1
GPG2 RE44 2 1 10K_0402_5% ACIN# RE94 1 2 0_0402_5%
EC_SPI_CLK PM_SLP_S3# 2 ACIN 59
MIRROR@ RE49 2 1 0_0402_5% C134 1 2 .01U_0402_16V7-K @ RE5
GPG2 RE46 2 1 10K_0402_5% SPI_CLK_PCH_0 18 10K_0402_5%
NOMIRROR@ PM_SLP_S4# C135 1 2 .01U_0402_16V7-K @
Delete MOS
when mirror, GPG2 pull high

2
LAN_W AKE#
Reserved Cap HLZ SDV 0616 Reserved Cap HLZ SDV 0616 LAN_WAKE# 45,50
when no mirror, GPG2 pull low EC_SPI_CS0# CE20 1 2 .01U_0402_16V7-K @
Security Classification LC Future Center Secret Data Title
EC_SPI_SI CE21 1 2 .01U_0402_16V7-K @

EC_SPI_SO CE22 1 2 .01U_0402_16V7-K @

Issued Date 2015/02/26 Deciphered Date 2016/02/26 ITE8371LQFP
EC_SPI_CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CE23 1 2 .01U_0402_16V7-K @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 49 of 75
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW NOVO Button KSO16 1 @ T11

K/B Connector KSO17 1 @ T7
K/B BL Connector
KB_PIN32

2
KSI[0..7] KSO9 R400 1 2 0_0402_5%
KSI[0..7] 49 KB_PIN31
R82 R83 KSI7 R418 1 2 0_0402_5%
100K_0402_5% 100K_0402_5% KSO[0..17]
@
KSO[0..17] 49 Add 0ohm

1
NOVO# R899 1 2 0_0402_5% NOVO_BTN# Change KB CONN Pin31&32 design HLZ SIV 0811 R190
49 NOVO# LED_KB_C
1 2
change NOVO button from MB to DB +3VS
HLZ SDV 20160510 0_0603_5%
1
Delete D15 D
HLZ SDV 20160510 JKB1 Update KB CONN based on ME CONN list 49 LED_KB_PWM 2

1
Layout Note: R885 R90
G
S
Top & Bottom side need 1Pcs KB_PIN32

2
300_0402_5% 300_0402_5% 32 33
KB_PIN31 31 32 GND1 34 R116 3 Q121
30 31 GND2 PJA138K_SOT23-3
100K_0402_5%
+3VL 30

2
J5 1 2 @ +3VALW 29 BL@ BL@
D PWR_NUM_LED 28 29 D
28

1
SHORT PADS NUM_LED# 27
49 NUM_LED# PWR_CAPS_LED 27

2
26
J6 1 2 @ R111 R114 CAPS_LED# 25 26

SHORT PADS
100K_0402_5% 100K_0402_5%
@
PWR LED Chnage LED HLZ SDV 0615
49 CAPS_LED#
KSO15
KSO14
24
23
25
24
KSO12 22 23
Chnage LED value from B1101BS--05P-000233_WHITE to B1101BS--05P-000733_WHITE 22

1
KSO10 21
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF
ON/OFF 49
HLZ SDV 0615 U118
3
KSO11
KSO6
20
19
21
20
0.5A
KSO8 18 19 +5VS
LED1 KSO4 17 18 Update KB BL CONN based on ME CONN list
PWR_LED1# 1 2 R142 1 2 390_0402_5% 1 KSO2 16 17
49 PWR_LED1# +3VALW 16
KSO5 15 R189 JKBL1
KSO13 14 15 1 2 1
14 1

0.1U_0402_10V6K
B1101BS--05P-000733_WHITE 2 KSI0 13 2
12 13 LED_KB_C 2

C141
KSI3 0_0603_5% 2 3
ON/OFFBTN# KSO1 11 12 4 3
AZC199-02S.R7G_SOT23-3 KSI2 10 11 5 4
EMC@ KSI4 9 10 @ 6 GND1
KSO3 8 9 1 GND2
PWR_LED1# 8
1

KSI5 7 ACES_50578-0040N-001
Change U118 ESD from ns to stuff KSI6 6 7
ME@
HLZ SIT 0922
1

6
1

D1 KSO9 5

AZ5425-01F.R7GR_DFN1006P2E
AZ5123-01F.R7GR_DFN1006P2X2 KSI7 4 5
4

1
EMC@ 2 Change USB2 ESD from single to 2in1 and ns KSI1 3
SW5 C208 KSO0 2 3
HLZ SIV 0811

1
1 2
2

T4BJB16_4P D36 220P_0402_50V7K KSO7

EMC_NS@ 1
R116 & R190 & Q121 & R189 add KB_BL BOM structure
2

EMC_NS@ 1
Change D1 from AZ5215 to AZ5123 Hai Y520 SVT CVILU_CF32321D0RONH

New KB & new KB matrix HLZ SIT 0920

2

ME@

2
PUR change material

2
TP_PWR
0.5A +3VS

Touchpad R141 1 2 0_0402_5% TP_PWR

USB I/O Connector

.1U_0402_10V6-K
C
1 Right Side USB2.0 Port X 1 (USB/B) C

C114
Different pin defien to Y710
2 Change U3 from Silegy to GMT +USB_VCCB HLZ SDV 20160510 JUSB3
HLZ SIT 0926
R67 1 2 0_0402_5% 1A 40
39 40
+5VALW 0.5A U3
+USB_VCCB
0.5A EMC_NS@
+3VALW
R153 1 @ 2 0_0402_5%
38
37
39
38 GND2
42
41
5 1 EXC24CH900U_4P 1A 20 LAN_PWR_ON#
36 37 GND1
IN OUT 3 4 USB20_P0_CONN 35 36
1 19 USB20_P0 3 4 35
C91 2 +3VS 34
1U_0402_6.3V6K GND 33 34
USB_OC2# USB20_N0_CONN 49 BATT_LOW_LED# 33
4 3 2 1 32
2 47,49 USB_ON# ENB OCB USB_OC2# 19 19 USB20_N0 2 1 Modify RTC battery from MB to DB 49 BATT_CHG_LED#
31 32
18,27,42,43,45,49 PLT_RST#
G517E2T11U_SOT23-5 1 L14 HLZ SDV 0615 45,49 LAN_WAKE#
30 31
C92 29 30
1000P_0402_50V7K 20mils 17 LAN_CLKREQ# 28 29
Low Active 2A @ R66 1 2 0_0402_5% RTC_VCC 27 28
JTP1 2 26 27
SMB_DATA_S3 17 CLK_PCIE_LAN# 26
1 25
12,13,16,45 SMB_DATA_S3 SMB_CLK_S3 1 17 CLK_PCIE_LAN 25
2 24
12,13,16,45 SMB_CLK_S3 2 24
3 19 PCIE_PTX_C_DRX_N4
23
TP_DATA 4 3 22 23
49 TP_DATA TP_CLK 4 19 PCIE_PTX_C_DRX_P4 22
5 21
49 TP_CLK TP_PWR 5 21
6 19 PCIE_PRX_DTX_N4 20
TP_CLK 6 20
100P_0402_50V8J
100P_0402_50V8J

@1 @1 7 19
G1 8
Change U3 from USB charger to Power SW 19 PCIE_PRX_DTX_P4
18 19
TP_DATA G2 HLZ SDV 20160510 USB20_P0_CONN 17 18
USB20_N0_CONN 16 17
2 2 16
3

C115

15
C116

ME@ 15
DT1 14
49 LID_SW# 14
+3VL 13
CVILU_CF31061D0R4-10-NH_6P NOVO_BTN# 12 13
11 12
A_RING2_CONN 10 11
48 A_RING2_CONN 10
9
8 9
A_HP_OUTL_R 7 8
48 A_HP_OUTL_R A_HP_OUTR_R 7
6
48 A_HP_OUTR_R HPOUT_JD 6
5
48 HPOUT_JD 5
AZC199-02S.R7G_SOT23-3 4
4
1

EMC_NS@ 3
For EMC A_SLEEVE 2 3
48 A_SLEEVE 2
1
GNDA 1

pin number 6 7 8 4 HRS_FH52E-40S-0P5SH_40P-T

ME@

pin name CTL1 CTL2 CTL3 ILM_SEL

B B

PLT_RST#
S0 CDP
Nationz TPM Nuvoton TPM 1 1 1 1
1. Add R93 for NationZ TPM Charge port 1
2. Add R94 & +3VALW for Nuvoton TPM Pin5 Enable S3 DCP
C140
H for all 0 1 1 0/1
1000P_0402_50V7K
3. Add R163 PD & R185 for PM_CLKRUN# of Nuvoton TPM R626 Stuff NC 2
HLZ SIT 0920 S4/S5 DCP
0 0 1 0/1
R93 Stuff NC Reserved Cap HLZ SDV 0616
S0 SDP1 0/1
Normal port 10 1 Change C140 from @ to stuff due to signal waveform abnormal
Pin5 Enable HLZ SIV 0811
R94 NC Stuff H for S0/S3
0.5A TPM L for S4/S5 S3 SDP1 0 0/1
1 0
+3VS

+3VS_TPM S4/S5 Disable 0 0 0 0/1

R227 1 TPM@ 2 0_0603_5%
1 1 1 SDP2 (No Discharge from/to CDP)
C176 C177 C178
SDP1(Discharge from/to any charging state including CDP)
.1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K
2 TPM@ 2 TPM@ 2 TPM@

+3VS_TPM

UTPM1
for Nationz TPM
1
2 NC_1 VDD3
24
10 LID Hall Sensor 3D Camera
3 NC_2 VDD1
NC_3
for Nationz TPM
R93 1 TPMZ@ 2 0_0402_5% 7 28 R626 1 TPMZ@ 2 10K_0402_5%
PP LPCPD# 27
SERIRQ SERIRQ 15,49
6 26
NC_4 LAD0 LPC_AD0 15,49
A 9 23 A
NC_7 LAD1 LPC_AD1 15,49
22
LFRAM E# LPC_FRAME# 15,49
4 20
GND_1 LAD2 LPC_AD2 15,49
11 17 LPC_AD3 15,49
+3VALW 18 GND_2 LAD3
GND_3 25 +3VS_TPM
R94 1 TPMN@ 2 0_0603_5% 5 GND_4 21
NC_5 LCLK CLK_PCI_TPM 15
8 19
12 NC_6 VDD2 15 R185 1 @ 2 0_0402_5%
NC_8 CL K_RUN# PM_CLKRUN# 16
for Nuvoton TPM 13
NC_9 PLT_RST#
2

14 16 R127 1 TPM@ 2 0_0402_5% Reserved for Nuvoton TPM

NC_10 LRESET# R163
0_0402_5%
Z32H320TC_TSSOP28
TPM@
Change Hall Sensor from MB to DB Delete 3D camera
1

TPM@
HLZ SDV 20160510 HLZ SDV 20160510 Security Classification Title
LC Future Center Secret Data
Issued Date 2015/02/26 Deciphered Date 2016/02/26 KBD/PWR/IO/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: F riday, Novem ber 25, 2016 Sheet 50 of 75
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 ITE8371LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 51 of 75
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 RGB KBD LED CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
DY512 1.0

Date: Friday, November 25, 2016 Sheet 52 of 75

5 4 3 2 1
 A B C D E

+5VALW to +5VS
+5VLP +5VALW

+0.6VS
5A +5VALW

1
3VS_CT2 R161 R157
1

1000P_0402_50V7K
C121 +5VS 5A 1
100K_0402_5% @ 100K_0402_5% R159
47_0603_5%

C125

@
1U_0402_16V6K U56 @

2
2 1 14
IN1_1 OUT1_2 1

2
2 13 C216 SUSP
IN1_2 OUT1_1 .1U_0402_10V6-K 2 36 SUSP

1
1 SUSP# R263 1 2 0_0402_5% 3 12 5VS_CT1 CD@ D 1
EN1 CT1 2 2 SUSP
4 11 G Q18
VBIAS GND

1
D 2N7002KW _SOT323-3
R264 1 2 0_0402_5% 5 10 3VS_CT2 2 S
EN2 CT2
+3VS
8A 49,61,64 SUSP# SUSP# @

3
+3VALW 5VS_CT1 G Q6
6 9

1000P_0402_50V7K
1 8A 7 IN2_1 OUT2_2 8 1 1
S
2N7002KW _SOT323-3
IN2_2 OUT2_1

3
C123

C124

@
1 C215
0.01UF_0402_25V7-K 15 .1U_0402_10V6-K
@ 2 C122 GPAD CD@
1U_0402_10V6K G5016KD1U_TDFN14_2X3 2 2
2

1.5A 1.5A
+1.0VALW Open 210mA VCCST
Add VCCST & VCCSTG Level shift
+3VALW Need short +3VALW _PCH HLZ SDV 20160530 1
J2 @
2
1 2
J7
JUMP_43X79
AO3402_SOT-23-3
1 2 Vds=30V
1 2
Q5 Ids=4A
JUMP_43X79
LP2301ALT1G Rds=50mohm@Vgs=4V
Vds=-20V AO3402_SOT-23-3
@ Vgs=20V
Ids=-1.6A VGS(th)=0.5--1.5V
2 +5VALW 1 3 2
Rdson=100mohm@Vgs=3V D S
LP2301ALT1G_SOT23-3 Vgs=+-8V
+5VALW
Vgsth=-0.4~-1 1 1

G
Q29 3 1 +5VALW C245 C246

D
R146 .1U_0402_10V6-K 0.01U_0402_25V7K

2
1

1 @ 1 47K_0402_5% @
2 2

1
C129 C130

G
2
R155 .1U_0402_10V6-K 0.01U_0402_25V7K R147 R148

2
100K_0402_5% @ @ 47K_0402_5% 1 2
@ 2 2
2

0_0402_5% 1

3
PCH_PW R_EN# R156 1 @ 2 100K_0402_5% PCH_PW R_EN#_R D C247
5 .1U_0402_10V6-K
G Q12B @
1 2
1

1
D C131
PCH_PW R_EN 2 R87 .1U_0402_10V6-K S Change C246 from @ to stuff due to slew rate test fail
49 PCH_PW R_EN
HLZ SIV 0811

4
6
G 100K_0402_5% @ D 2N7002KDW H_SOT363-6
Q30 @ 2 R150 1 2 0_0402_5% 2
S 2N7002KW _SOT323-3 49,62 SYSON G
3

2
1

0.1U_0402_10V6-K
@ Q12A
S

1
1

1M_0402_5%
R162 C105 2N7002KDW H_SOT363-6

R152
100K_0402_5%
@
2

2
@
@

1
120mA
+1.0VALW Open VCCSTG

J4 @
3 1 2 3
1 2
AO3402_SOT-23-3
+1.0VALW TO VCCIO JUMP_43X79
6A PUR change material AON6764_DFN
Vds=30V
Delete +1.2VS for HDMI Repeater PS8407 VCCIO_H Q7 Ids=4A
HLZ SDV 20160510
+1.0VALW Vds=30V
Ids=85A
6A AO3402_SOT-23-3
Rds=50mohm@Vgs=4V
Vgs=20V
Q3 +5VALW
Rds=3.5mohm@Vgs=4V VCCIO VGS(th)=0.5--1.5V
1 3
AON6764_DFN8-5 Vgs=12V Need short D S
VGS(th)=1.1--1.9V

1
1 J8 +5VALW
1 1

G
2 1 2 R135 C248 C249
+5VALW 5 3 1 2 .1U_0402_10V6-K
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
47K_0402_5% 0.01U_0402_25V7K

2
1
@ @
JUMP_43X79 2 2
1

1
+3VALW
0.01U_0402_25V7K

R137 R138

2
1

+5VALW @ 47K_0402_5% 1 2
C94

C96
C93

C95
1 1
4

R129 C97
2

2
47K_0402_5% C100 R255 1 @ 2 100K_0402_5% 0_0402_5%

2
1

3
.1U_0402_10V6-K @ D
R125 R130 2 @ 2 5
2

47K_0402_5% 1 2 SYSON R145 1 @ 2 1K_0402_1% G Q11B

1
0_0402_5% S C251
1
2

4
3

6
D C99 D 2N7002KDW H_SOT363-6 .1U_0402_10V6-K
VCCIO_PW R_EN 5 .1U_0402_10V6-K SUSP# R143 1 2 0_0402_5% 2 @
G Q9B G 2
2

0.1U_0402_10V6-K
+3VALW Q11A
S S
4

1
6

2
VCCIO

1M_0402_5%
D 2N7002KDW H_SOT363-6 Change net to SUSP# for PWR sequence C104 2N7002KDW H_SOT363-6
+3VL
1

SUSP# R126 1 2 0_0402_5% 2

R144
G R164

2
0.1U_0402_10V6-K

Q9A 47K_0402_5% @
1

4 S @ 4
@
1

1
1

1M_0402_5%

C98 2N7002KDW H_SOT363-6 R160 R58

2

47K_0402_5% R165 1 @ 2 0_0402_5% 470_0603_5%

R128

VCCIO_PG 49,64
@ @
2

D
@
2

@ 2
1

G Q4
1

VCCIO 2N7002KW _SOT323-3 D

Security Classification LC Future Center Secret Data Title
1

C S @ VCCIO_PW R_EN 2
3

1 2 2 G
B
Q17 Q168
Issued Date 2015/02/26 Deciphered Date 2016/02/26 DC V TO VS INTERFACE
R158 MMBT3904W H_SOT323-3 2N7002KW _SOT323-3
1K_0402_1% E @ S REV@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
3

@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DY512 1.0

Date: Friday, November 25, 2016 Sheet 53 of 75

A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Virtual symbol
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Custom
DZ510/DY512 1.0

Date: Friday, November 25, 2016 Sheet 54 of 75

5 4 3 2 1
 5 4 3 2 1

H2 H1 Delete H11 HLZ SDV 0615

HOLEA H19
HOLEA
HOLEA

H5 H6
For USB3 shielding Clip
HOLEA HOLEA
1

1
1
Delete SH1 SH2 SH3 SH4 SH5 SH6 0726

1
pad_r6p4x8p0d2p8-offl0p8 pad_r6p4x6p5d2p8-offl0p8 pad_r6p4x8p0d2p8-offl0p8
D D
pad_o2p5x3p5d2p5x3p5n pad_o2p5x3p5d2p5x3p5n

Update footprint name HLZ SDV 0615

H12 H13 H14 H15 H16

HOLEA HOLEA HOLEA HOLEA HOLEA
H3 H4
HOLEA HOLEA

1
1

pad_c4p0d4p0n pad_c4p0d4p0n pad_c4p0d4p0n pad_c4p0d4p0n pad_c4p0d4p0n

pad_C6p0d3p2 PAD_ST8P0CB8P0D2p5

H18
Update H3 footprint name HLZ SIT 0923 HOLEA

C Update footprint name HLZ SDV 0616 C

1
H7
HOLEA
PAD_C2P5D2P5N For DDR4 shielding Clip

SH8
1

ME@
SH7 ME@ SH9 ME@
pad_st6p0cb6p0d2p5 1
1 1 1
1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P
H8 H9 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
HOLEA HOLEA
SH12 ME@
SH10 ME@ SH11 ME@
1

1
1 1 1
pad_st8p0cb6p0d2p5 pad_st8p0cb6p0d2p5 1 1
B B
SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

H17 H20
HOLEA HOLEA
SH15 ME@
SH13 ME@ SH14 ME@
1
1
1

1 1
1 1
pad_shapet8p0x8p0cb8p0d2p5 pad_cb6p0d2p5
SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
Delete H10 HLZ SDV 0618
FD1 FD2 FD3 FD4 FD5 FD6
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: Friday, November 25, 2016 Sheet 55 of 75
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DY512
Date: F riday, Novem ber 25, 2016 Sheet 56 of 75
5 4 3 2 1
 5 4 3 2 1

B+ +5VLP/ 100mA
Silergy
Richtek SY8868QMC +1.0VGS/3A
Adaptor +5VALW/8A
D
EC_ON EN
RT6585BGQW PGOOD Switch Mode D

ALW_PWRGD FOR GPU PGOOD 1.0VGS_PG

135W/20V EN_VGA EN
Switch Mode Page 70

FOR SYSTEM +3VLP/ 100mA

Page 60
+3VALW/ 8A APNEC
APL5930CKAI-TRG +2.5V/600mA
SYSON EN LDO
FOR DDR PGOOD

MPS Page 62
+1.2V/10A
NB685GQ-Z
Converter +0.6VS/1A
SYSON S5 FOR DDR APNEC
SM_PG_CTRL S3 Page 61 PGOOD 1.2V_PGD +1.8VGS/1A
APL5930CKAI-TRG
EN_VGA EN LDO
FOR GPU PGOOD

Richtek Page 70
TI RT8237EZQW-2 +1.0VALW/ 10.5A
C
BQ24780SRUYR Switch Mode C

EN FOR PCH PGOOD

EC_ON Page 63
Battery Charger
Switch Mode
Page 59 Richtek
RT8237EZQW-2 +1.35VS_VGA/ 11A
Switch Mode
FBVDDQ_PWR_EN EN PGOOD VDDQPWROK
FOR GPU
Page 69
SMBus

Silergy
SY8288RAC VCCIO/ 5.5A
Converter
SUSP# EN FOR CPU PGOOD VCCIO_PG
Page 64

ON VCC_CORE/56A/68A

B
NCP81205MNTXG VCCGT/39A/55A B
Switch Mode
FOR CPU Core VCCSA/10A
VR_ON Page 65-68
EN PGOOD
CPU_PWRGD

Richtek
RT8816A NVVDD/47A/90A
Switch Mode
EN_VGA EN FOR GPU NVVDD PGOOD GPU_PWRGD
Page 71
Battery
Li-ion Richtek
RT8816A NVVDDS/19A/42A
3S1P/45WH Switch Mode
EN_VGA EN FOR GPU NVVDDS PGOOD GPU_PWRGD
Page 72

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Power Diagram
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Custom
DZ510/DY512 1 .0

Date: Friday, November 25, 2016 Sheet 57 of 75

5 4 3 2 1
 5 4 3 2 1

+3VL
PL101 EMC@
HCB2012KF-121T50_0805
VIN

1
1 2
D
PL102
EMC@ PR101
1.5K_0603_1% VCCRTC D
JDCIN1 PF101
HCB2012KF-121T50_0805
1 APDIN 1 2 APDIN1 1 2
1 RTC_VCC

2
2 PR103
2 PD101
3 12A_24V_F1206HB12V024T/M 47K_0402_1% PR102
3 4 2 1VCCRTC_D_R 1 2 VCCRTC_D
3
4 5

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
5

PC101 EMC@

EMC@

PC104 EMC@
1

EMC@
0_0603_5%

1
PC102

PC103
ADAPTER_ID 49,59 RTC_VCC_R
CVILU_CI2105P2HR1-NH 1 2 2
ME@

2
PR104
1K_0603_5% BAT54CW_SOT323-3

1
PC105
1U_0402_10V6K
@

2
C C
16 PL103 EMC@
GND4
GND3 15 HCB2012KF-121T50_0805
Change JRTC1 based on ME CONN list
GND2 14 1 2 HLZ SDV 0530
GND1 13
12
VMB2 VMB BATT+
12
11 11 PF102 PL104 EMC@
10 10 15A_24V_F1206HB15V024T/M HCB2012KF-121T50_0805
9 9 1 2 1 2
8 8 EC_SMCA
7 7 EC_SMDA
6 PL105 EMC@
Chnage RTC battery from MB to DB HLZ SDV 0615
6 5 HCB2012KF-121T50_0805
5
3

1
4 PC106 1 2 PC107
4 3 1000P_0402_50V7K 0.01U_0402_25V7K
3 2
2 EMC@ EMC@

2
1
1
1

100_0402_1%

JBATT1
SUYIN_125022HB012M200ZL
PR105
1

100_0402_1%

ME@
PR106

2
2

B PD103 EC_SMB_CK1 49,59 B

AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 49,59

PR107 1 2 100K_0402_1% +3VALW

BATT_TEMP_IN 1 2
BATT_TEMP 49,59 A/D
PR108
10K_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-DCIN/BATT/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 58 of 75
5 4 3 2 1
 5 4 3 2 1

PQ201 PQ202
AON6366E 1N DFN AON6414AL_DFN8-5
P2 PR201 V20B+
VIN 1 1 P3 @ 0.01_1206_1%
2 2 PJ201
5 3 3 5 2 1 1 4
2 1
2 3
JUMP_43X118

EMC_NS@

EMC_NS@
10U_0805_25V6K
10U_0805_25V6K
4

4
D D

2
PC203

PC204
1

1
PC202
PC201 PR202 0.022U_0402_25V7K

1
4.7_0603_5%

2
470P_0402_50V7K

5
2
PQ203
AON6414AL_DFN8-5
1 2

PC205 780s_BATDRV 4

1
PC206 0.1U_0402_25V6

1
1U_0603_25V6K PC207
0.1U_0402_25V6

1
2

3
2
1
1
PR203
499K_0402_1% PC208
VIN BATT+ 0.01U_0402_25V7K

2
2
780s_ACDRV_R

3
PD201 Change PC209 from ns to Stuff Hai Y520 SVT V20B+
BAT54CW_SOT323-3

1780s_VCC_R
1

10U_0805_25V6-K

10U_0805_25V6K
0.1U_0402_25V6
VIN
1

2
EMC@

PC211
4.02K_0603_1%

4.02K_0603_1%

ACN
ACP
PR207
PR206

PC212
BQ24780S_VDD

PC209
2

1
1

5
PR209
2

1
PR208 PC213 10_1206_5% PQ205

D
6.2K_0603_1% 39K_0603_1% 1U_0603_25V6K AON7408L_DFN8-5

ACP

ACN
C 1 2 C

2
PR210 1 2 780s_VCC 28 24 1 2
VCC REGN

2
2.2U_0603_10V6-K PC214 4
2 1 780s_ACDET 6 PC216 G
PC215 ACDET 0.047U_0603_16V7K

S3
S2
S1
0.1U_0402_25V6 25 780s_BS
1 2780s_BS_R
2 1
BTST PR211 PR213
BATT+

3
2
1
2.2_0603_5% 0.01_1206_1%
780s_CMSRC 3 26 780s_HG PL201
CMSRC HIDRV 1 2 1 4
780s_ACDRV 4 4.7UH_PCMB063T-4R7MS_5.5A_20%
ACDRV 2 3

1
27 780s_LX

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
PHASE

EMC_NS@
PR216

1
PR215 1 2 0_0402_5% 780s_ACOK 5 PQ206 4.7_0805_5%

PC221

PC217

PC218
49 ACIN ACOK PU201 AON7408L_DFN8-5 EMC@
PR217 1 2 0_0402_5% 780s_SDA 11
SDA

2
49,58 EC_SMB_DA1 23 780s_LG 4

780s_SN
LODRV G
PR218 1 2 0_0402_5% 780s_SCL 12 22

S3
S2
S1
SCL GND

1
49,58 EC_SMB_CK1
PC222

3
2
1
PR219 1 2 0_0402_5% 780s_IADP 7 29 1000P_0402_50V9-J

0.1U_0402_25V6

0.1U_0402_25V6
49 ADP_I IADP PAD

2
EMC@

1
PR220 1 2 0_0402_5% 780s_IDCHG 8 18 780s_BATDRV

PC223

PC224
49 BATT_I IDCHG BATDRV
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

PR221 1 2 0_0402_5% 780s_PMON 9

65 PSYS PMON

2
17 780s_BATSRC 1 2 780s_BATSRC_R
BATSRC PR222 10_0603_5%
20 780s_SRP 1 2 780s_SRP_R
10 SRP PR224 10_0603_5%
49 VR_HOT# PROCHOT#

1
1

13 PC228
CMPIN
0.1U_0402_25V6

2
BATPRES#
TB_STAT#
14
PC226

PC227
PC225

CMPOUT
2

19 780s_SRN 1 2 780s_SRN_R
780s_ILIM 21 SRN PR225 10_0603_5%
ILIM
B B
2

PR226

780s_TB#16

15
0_0402_5% BQ24780SRUYR_QFN28_4X4

+3VALW VIN
1

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 49,58
PR227 PR228
1

143K_0402_1% 32.4K_0402_1%
1

PR230
1

PC229 100K_0402_1%
PR229 PR231 0.1U_0402_25V6
2

750_0603_1% 1M_0402_5%
2

@
2

IchargeLIM=7A
2

ADAPTER_ID_R
IDischargeLIM=10A
2

D
PR232 2 ADAPTER_ID_ON#_G
0_0402_5% G

S PQ207A @
1

L2N7002KDW 1T1G_SOT363-6

ADAPTER_ID 49,58
1

D
680P_0402_50V7K

5 ADAPTER_ID_ON# 49
AZ5123-01F.R7GR_DFN1006P2X2
1

PR233 G
@ 1M_0402_5%
0.1U_0402_25V6

@ S PQ207B @
2

4
1

L2N7002KDW1T1G_SOT363-6
PC230

PC231

PD203

@
A A
2

2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 59 of 75
5 4 3 2 1
 5 4 3 2 1

D D

PJ601 @

12A
2 1
+3VALWP 2 1 +3VALW
JUMP_43X118

PJ602 @

+5VALWP
2
2
JUMP_43X118
1
1
+5VALW 12A
3V5V_VIN
PJ604
+5VLP 2 1
+3VLP 2 1 +3VL 1A

27K_0402_1%
0.1U_0402_25V7-K
JUMP_43X39

30.1K_0402_1%

4.7U_0603_6.3V6K
3V5V_VIN

1
@

PC602

4.7U_0603_6.3V6K
2

0_0603_5%
V20B+

1
PC601

PC603
PR602
3V5V_VIN

2
PJ603 @

2
2 1 1 2
2 1 +3VALW

1
PR604
+3V5V_CS22

+3V5V_CS12
JUMP_43X118 PR619

PR601

+5V_LDO
0_0603_5% Vout=5V+-5%
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

2
EMC_NS@

PC610
PC609

PC611

+3VLP

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
Vset=5.06V+-1.5%

1
PC605

PC606

PC607

EMC_NS@
PR605
FSW=400KHz
2

Vout=3.3V+-5% 100K_0402_1%

2
C @ TDC=10A OCP=15A C

13
12
Vset=3.3V+-1.5%

5
OVP=Vout*113%
5
FSW=475KHz

AON7506_DFN8-5
D
CS1

LDO5

LDO3
VIN

CS2
21
UVP=Vout*52%
AON7408L_DFN8-5

D
GND
TDC=8A OCP=12A 62 ALW_PWRGD
ALW _PW RGD 7
PGOOD

PQ603
PQ601

OVP=Vout*113% +3V_UG 10 UGATE1

16 +5V_UG 4
G
4 PR606 PC614
UVP=Vout*52% G PC613 PR607 UGATE2
PU601 2.2_0603_5% 0.1U_0603_25V7K

S2
S3

S1
0.1U_0603_25V7K 2.2_0603_5% 17 +5V_BST1 2 1 2
S1

S3
S2

1 2 1 2 +3V_BST9 BOOT1
BOOT2
PL601
+5VALWP

3
2
1
PL602 2.2UH +-20% PCMB064T-2R2MS 9A
+3VALWP
1
2
3

2.2UH_PCMB063T-2R2MS_8A_20% 18 +5V_LX 1 2
1 2 +3V_LX 8 PHASE1
PHASE2
5

5
RT6585BGQW_WQFN20_3x3LGATE1 15 +5V_LG

2
+3V_LG 11

AON6380_DFN8-5
AON7506_DFN8-5

LGATE2
2

14 PR608
PR609 BYP1 4.7_0805_5%

PR612
VCLK
EN2

EN1

FB1
FB2
4.7_0805_5%
PQ602

PQ604
EMC_NS@
220U_6.3V_M

4 4
PC625 @

PC618 @

PC624 @
EMC_NS@
22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1U_0402_25V6
0.1U_0402_25V6

1 G 1 1

2
@

@
13K_0402_1%

220U_6.3V_M

220U_6.3V_M
20

1+3V5V_CLK 19
1

2
1

1
+ + +
PC615

PC617

PC620

PC616
S1

S3
S2
PR610

+5V_FB
EC_ON_5V_R
EC_ON_3V_R
2

1
2
3

3
2
1

2
2 2 2

1
1

PC619

30K_0402_1%
1

PC621 1000P_0402_50V9-J

2
1000P_0402_50V9-J EMC_NS@

200_0402_1%
2

EMC_NS@

PR611
+3V_FB

2
1 2 1 2
44,49 EC_ON EC_ON_5V 49
2

PR614 0_0402_5% PR615 0_0402_5%

B B
1

1
1M_0402_5%

1M_0402_5%
1

1
Vout=2V*(1+PR610/PR613) PR613 PC622 PC623 @

PR618
PR617

1
20K_0402_1% 0.1U_0402_10V7K @ @ 0.1U_0402_10V7K
1

2
PR616 Vout=2V*(1+PR612/PR616)
2

2
19.6K_0402_1%

2
PD601

2 EC_ON_3V_R

1
49 MAINPWON
3 EC_ON_5V_R

BAT54CW _SOT323-3
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-3/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size
DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 60 of 75
5 4 3 2 1
 A B C D

V20B+

PJ1401 @
+1.2V_VIN 1
1 2
2 2A
JUMP_43X79
@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
1 1

PC1401

PC1402

PC1403
2

2
+1.2V_P

1A

5
PR1401 PC1404
0.1U_0603_25V7-M PQ1401

D
2.2_0603_5%
AON7408L_DFN8-5
PC1418 1 2 +1.2V_BST_R 1 2
10U_0603_6.3V6M
1 2 1 2 +1.2V_UG_R 4
+0.6VSP G
PR1404

S2
S1
S3
0_0603_5%
PL1401
PJ1402@
+1.2V

3
2
1
0.68UH_PCMB063T-R68MS_16A_20%
1A 1 2 +1.2V_P 2 1

+1.2V_BST
2 1

+1.2V_UG

+1.2V_LX

330U_B2_2.5VM_R15M
PC1415 @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 JUMP_43X118

5
1

1
+
PC1413

AON7408L_DFN8-5
D
PR1402

PC1406

PC1407

PC1409

PC1420

PC1421
PC1408

PC1410

PC1417
4.7_0805_5%
17
20

19

18

16
2

2
2
EMC_NS@

PQ1402

470P_0402_50V7K

1
4
VTT

BOOT

UGATE

PHASE
VLDOIN

1
21

PC1405
PAD PR1407 @ @

S3

S1
S2
1 15 +1.2V_LG 60.4K_0402_1%
VTTGND LGATE

2
+1.2V_SN
3
2
1

2
2 14
@ 1A
VTTSNS PGND +1.2V_FB

3
PU1601
13 +1.2V_CS 1
PR1406
2 +5VALW +0.6VSP @
+0.6VS
GND CS

1
RT8231AGQW _W QFN20_3X3 560K_0402_1% PR1405 PJ1405

1
5.1_0603_5% PC1412 2 1
2

VTTREFP 4 12 +1.2V_VDD 1 2 1000P_0402_50V9-J PR1411 2 1 2

VTTREF VDD
+3VALW EMC_NS@ 100K_0402_1%

2
1

JUMP_43X79
PC1419 @

2
+1.2V_P 5 11 +1.2V_VID 1 PR1417 2
1U_0402_6.3V6K VDDQ VID

1
PC1411
PGOOD

100K_0402_1%
2

1U_0402_6.3V6K
TON
FB

S3

S5

2
1 PR1418 2
100K_0402_1%
6

10
+1.2V_FB

+1.2V_TON

+1.2V_PG

@
+1.2V_S5

PR1403 1 2 100K_0402_1% +3VALW

+1.2V_S3

PR1410 1 2 499K_0402_1%
Vout=1.2V± 5%
V20B+
Vset=1.212V± 2%
OCP=13A
Vref=0.6V
OVP=(1.25~1.35)*Vref
UVP=(0.7~0.8)*Vref
Fsw=700Khz(Rmode=0)
Fsw=500Khz(Rmode=150K)

3 3

Vout=0.6V± 5%
1
PR1408
2 +1.2V_S3 OCP=1.5A
6 SM_PG_CTRL
VTT=1/2VDDQ
1M_0402_5%
0.1U_0402_10V7K

0_0402_5%
1

PC1414

PR1413

49,53,64 SUSP# 1 2 @
STATE EN1 EN2 VDDQ VTT_REFP VTT
2

PR1409 @
2

0_0402_5%
S0 Hi Hi On On On
Off
S3 Lo Hi On On (Hi-Z)
PR1412
+1.2V_S5
49 SYSON_VDDQ 1 2 S4/S5 Lo Lo Off Off Off
1M_0402_5%
1

0_0402_5%
1

PC1416
PR1414

0.1U_0402_10V7K
@
Note: S3 - sleep ; S5 - power off
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VDDQ/VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size
DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 61 of 75
A B C D
 A B C D

1 1

+5VALW
1.5A 1.5A

1
PC2001
+3VALW 1U_0402_6.3V6K +2.5V

2
@ @
PJ2001 6 PJ2002
2 1 +2.5V_VIN 5 VCNTL 3 +2.5V_P 2 1
2 1 9 VIN VOUT1 4 2 1
TP VOUT2
@

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
JUMP_43X39 JUMP_43X39

1
8
EN

1
+2.5V_POK 7 2 PC2002 @

PC2004

PC2007

22U_0603_6.3V6-M

22U_0603_6.3V6-M
GND
POK FB PR2001 220P_0402_50V7K @

1
39K_0402_1%

2
Vout=2.5V± 5%

PC2003

PC2006
1

2
PU2001

2
1
+2.5V_FB
2
PR2002@
0_0402_5% PR2003 @
G971MF11U_SO8 Vset=2.514V± 3% 2

60 ALW_PWRGD
1 2 100K_0402_5% OCP=3A

1
PR2005
PR2004 Vref=0.8V

2
18.2K_0402_1%
1 2 +2.5V_EN
49,53 SYSON
+3VALW

2
0_0402_5%

1
PC2005 @
0.1U_0402_10V6-K

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 62 of 75
A B C D
 A B C D

+5VALW

2
PR3537
V20B+
2.2_0603_5%
@
PJ3502 1.5A

1
+3VALW +1.0VALW_VIN 2 1
2 1
PR3526 JUMP_43X79

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
5
1 1
2.2_0603_5%

1U_0603_10V6K

1
2+1.0VALW_BST_R

EMC_NS@
1

100K_0402_5%

PC3535

PC3542
AON7506_DFN8-5
D
1

1
PC3529

PC3532
PR3535

2
@

PQ3510
2

1
PU3502 PC3536 4
0.22U_0603_16V7K G
+1.0VALW

2
7 @

S3
S2
S1
VCC

2
10 +1.0VALW_BST PJ3503
BOOT 2 1
2 1

3
2
1
+1.0VALW_PG 1
PGOOD 9 +1.0VALW_HG JUMP_43X79
PR3538 UGATE PL3502 @
+1.0VALW_EN
49 EC_ON_1V
1 2 3
EN 8 +1.0VALW_LX
0.68UH_PCMB063T-R68MS_16A_20%
1 2 +1.0VALW _P 2
PJ3504
1
11A
PHASE 2 1

1
0_0402_5% +1.0VALW_RF 5
0.1U_0402_10V6-K

1 RF

1M_0402_5%
@ PR3536
1

PR3539 +1.0VALW _CS2 6 +1.0VALW_LG 4.7_0805_5% @ JUMP_43X79

330U_2.0V_M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CS LGATE 1

+1.0VALW_SN
5
EMC_NS@
PC3544

1
4 +1.0VALW_FB +

PC3534
PC3539

PC3540

PC3538
AON6380_DFN8-5
FB
2

2
1

1
11

470K_0402_1%

113K_0402_1%
GND
2

PR3524

PR3531

2
RT8237EZQW-2_WDFN10_3X3 2

PQ3509
4
2

1
PC3533
1000P_0402_50V9-J
EMC_NS@

3
2
1

2
2 2

PR3534
90.9K_0402_1%
1 2

1 2+1.0VALW_FB_R21 2

PR3533 PC3543

1
1K_0402_1% 330P_0402_50V8J
PR3540 @ @
210K_0402_1%

2
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-1VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 63 of 75
A B C D
 A B C D

1 1

+3VALW

1
PR901
Merge
@
V20B+ 10K_0402_5%

@ PR902
PU901 VCCIO

2
2A 2
PJ901
1 VCCIO_VIN 5 9
@ VCCIO_PG_R
0_0402_5%
2 1
2 1 IN1 PG VCCIO_PG 49,53
4 1 VCCIO_BS 1 2
JUMP_43X79 EMC@ 3 IN2 BS PL901 @
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6

IN3
1

2 PC903 1UH_PCMB053T-1R0MS_7A_20% PJ902 5.5A

PC902

PC904
IN4 VCCIO_LX VCCIO_P
Jump need open LX1
6 0.1U_0603_25V7-M 1 2 2
2 1
1
7 19 @
GND1 LX2
2

1
8 20 JUMP_43X79
PC901

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
18 GND2 LX3 PR903 PC908
GND3
2 2

1
21
GND4
4.7_0805_5% 330P_0402_50V8J Jump need open

2
PR904 @ 14 VCCIO_FB EMC_NS@

PC905

PC906

PC907

PC909
VCCIO_FB_R3
@ @ FB @

1
100K_0402_5%

2
+3VALW 1 2 VCCIO_ILMT 13 12 PR905

1VALW_SN
VCCIO_EN ILMT NC3
+3VALW
11
EN NC1
10
16
10_0402_1% Vout=0.95V± 50mV
NC2
1

@ 15
BYP @ @ @ @ Vset=0.953V± 1.78%

2
1

2
PR906 17 VCCIO_VCC PC910
VCC @
1M_0402_5%
Merge 1000P_0402_50V9-J
Vref=0.6V

4.7U_0603_6.3V6K
1

SY8288RAC_QFN20_3X3 EMC_NS@ PR907

2
1
PC911 @ 1K_0402_1% PR908 PR909 OCP=12A

PC912
2

4.7U_0603_6.3V6K 36.5K_0402_1% 0_0402_5%

2

1
VCCIO_FB_R1 2
@
@
1 2 1 OVP=(1.15~1.25)*Vout

2
VCC_IO_SEN 10
@ @ UVP=(0.6~0.7)*Vout

1
@
PR910
Fsw=500Khz
ILMT=0 OCP=8A 62K_0402_1%
PR911
ILMT=floating OCP=12A 0_0402_5%

2
VCCIO_FB_R2 2 1
@ VSS_IO_SEN 10
ILMT=1 OCP=16A

1
@
PR912
10_0402_1%

PR913

2
0_0402_5%
VCCIO_EN @
3
49,53,61 SUSP# 1 2 3

@ @
0.1U_0402_10V6-K
2

1M_0402_5%
1

PC913

PR916

@
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 64 of 75
A B C D
 5 4 3 2 1

81205_EN C139 1 2 .01U_0402_16V7-K @

81205_SCLK C136 1 2 .01U_0402_16V7-K @

81205_ALERT C137 1 2 .01U_0402_16V7-K @

PC2901
2200P_0402_25V7-K 81205_SDIO C138 1 2 .01U_0402_16V7-K @
1 2
PH2901 PR2903 PR2904
PR2901
100K_0402_1%_TSM0B104F4251RZ 14.3K_0402_1% 7.5K_0402_1%
10 VSSSA_SENSE
1 2 VSN_1PH_R 1 2 VSN_1PH 1 2 CSN_1PH_R 1 2 1 2
LX_1PH
VCCSA
68
PR2902
0_0402_5%

1
PC2902 1K_0402_1%
1000P_0402_50V7K PC2904 1 2 5600P_0402_25V7-K VCCST

1
PR2909 +3VS

100_0402_1%

45.3_0402_1%
PR2908
1.47K_0402_1% PC2903

PR2905

PR2906
D D
1 2 VSP_1PH_R 1 2 VSP_1PH PC2905 1 2 5600P_0402_25V7-K 0.1U_0402_25V6
10 VCCSA_SENSE

2
26.7K_0402_1%
330P_0402_50V7K
0_0402_5%

2
1
1 2 VCCSA PR2910

10K_0402_1%
VCCSA

1
49.9_0402_1%

PC2907

PR2913
PR2914 81205_SCLK 1 2
PC2906

PR2911
1000P_0402_50V7K PC2908 1 2 1000P_0402_50V7K 2 1 SVID_CLK 6

2
CPU_PW RGD 49
PR2912

2
0_0402_5%

2
PR2915 1 2 13K_0402_1% PW M1_1PH/ICCMAX1 68 81205_ALERT 1 2
SVID_ALERT# 6
PR2916
81205_VR_RDY PR2919 0_0402_5%
10_0402_1%
PR2918 81205_SDIO
PR2917 PC2909 34.8K_0402_1% 1 2
1 2 VSP_3PH_A 1.5K_0402_1% 8200P_0402_50V7-K 1 2 SVID_DATA 6
9 VCCCORE_SENSE
1 2 81205_COMP_1PH_C 1 2
81205_EN PR2920 1 2 0_0402_5%
0_0402_5%

1
PC2910 81205_SCLK CPUCORE_ON 6,49
1000P_0402_50V7K PC2911 1 2 15P_0402_50V 81205_ALERT
81205_SDIO PR2921

2
PR2923 1 2
PR2922 VCCGT_SENSE 9
910_0402_1%

81205_COMP_1PH

81205_IMON_1PH
VSN_3PH_A_R 2 VSN_3PH_A

81205_CSP_1PH
81205_ILIM_1PH
1 2 1
9 VSSCORE_SENSE 0_0402_5%

1
VSN_1PH PC2913
1000P_0402_50V7K
0_0402_5% 1 2 VSP_1PH PR2924
PR2925

2
1.21K_0402_1%
PC2912 1 2 VSN_3PH_B_R 1 2
2200P_0402_25V7-K VSSGT_SENSE 9

PC2914 0_0402_5%
PR2927 1 2

51

49
53

52

50

48
47
46
45
44
43
42
41
40
PC2915 PR2926 PC2916 100_0402_1%
15P_0402_50V8J 49.9_0402_1% 470P_0402_50V7K 1 2 H_PROCHOT# 6,49 2200P_0402_25V7-K

H_PROCHOT
SCLK
PW M_1PH/ICCMAX_1PH

SDIO
VR_RDY
ILIM_1PH

EN

ALERT#
PAD

COMP_1PH

CSN_1PH

IMON_1PH
CSP_1PH
VSP_1PH
VSN_1PH
1 2 1 2COMP121 2 PR2928
23.2K_0402_1% PR2930 PR2931 PC2918 PC2919
1 2 22.6K_0402_1% 49.9_0402_1% 470P_0402_50V7K 15P_0402_50V8J
1 2 1 2 COMP13 1 2 1 2
C 1 2 COMP11 1 2 1 2 PC2921 VSP_3PH_A 1 39 C
470P_0402_50V7K VSN_3PH_A 2 VSP_3PH_A VR_HOT# 38 VSP_3PH_B PC2920
PR2929 PC2917 PR2932 1 2 IMON_3PH_A 3 VSN_3PH_A VSP_3PH_B 37 VSN_3PH_B 470P_0402_50V7K 1 2 1 2 COMP141 2
4.02K_0402_1% 3300P_0402_50V7K 1K_0402_1% DIFFOUT_3PH_A 4 IMON_3PH_A VSN_3PH_B 36 IMON_3PH_B 1 2
FB_3PH_A 5 DIFFOUT_3PH_A IMON_3PH_B 35 DIFFOUT_3PH_B PR2933 PR2934 PC2922
COMP_3PH_A 6 FB_3PH_A DIFFOUT_3PH_B 34 FB_3PH_B 1K_0402_1% 3.74K_0402_1% 3300P_0402_50V7K
PR2935 1 2 14.7K_0402_1% ILIM_3PH_A 7 COMP_3PH_A PU2901 FB_3PH_B 33 COMP_3PH_B
CSCOMP_3PH_A 8 ILIM_3PH_A NCP81205MNTXG_QFN52_6X6 COMP_3PH_B 32 ILIM_3PH_B PR2936 1 2 17.4K_0402_1%
CSSUM_3PH_A 9 CSCOMP_3PH_A ILIM_3PH_B 31 CSCOMP_3PH_B
CSSUM_3PH_A CSCOMP_3PH_B
2

CSREF_3PH_A 10 30 CSSUM_3PH_B

PW M1_3PH_B/ICCMAX_3PH_B
PW M1_3PH_A/ICCMAX_3PH_A
CSREF_3PH_A CSSUM_3PH_B
1

1
PR2937 CSP1_3PH_A 11 29 CSREF_3PH_B
560P_0402_50V7-K

PH2902 75K_0402_1% CSP2_3PH_A 12 CSP1_3PH_A CSREF_3PH_B 28 CSP1_3PH_B PR2938

680P_0402_50V7K

PW M3_3PH_B/ROSC_3PH
PW M2_3PH_B/ROSC_1PH
CSP2_3PH_A CSP1_3PH_B

1
220K_0402_5%_TSM0B224J4702RE CSP3_3PH_A 13 27 CSP2_3PH_B 75K_0402_1% PH2903

680P_0402_50V7K

560P_0402_50V7-K
CSP3_3PH_A CSP2_3PH_B
1

PC2928 220K_0402_5%_TSM0B224J4702RE
PC2923

PC2924

PW M3_3PH_A/VBOOT
1

TTSENSE_1PH/PSYS
PW M2_3PH_A/ADDR

1
0.1U_0402_25V6

PC2927
PC2926
3PH_A_R
2

2
PC2925 3PH_B_R
V20B+

TTSENSE_3PH_A

TTSENSE_3PH_B
2

0.1U_0402_25V6

1
CSP3_3PH_B
PR2939 80.6K_0402_1% PR2941
SW _A3 1 2 PR2940 54.9K_0402_1%
2

160K_0402_1% 1 2 SW _B2

DRON
VRMP
PR2943 80.6K_0402_1%

VCC
SW _A2 1 2 PR2942 PR2944

2
165K_0402_1% 1K_0402_1% 1 2 SW _B1
PR2946 80.6K_0402_1%

16

18
1

14
15

17

19
20
21
22
23
24
25
26
SW _A1 1 2 PC2929 PR2947 PR2945

2
0.1U_0402_25V6 0_0402_5% 54.9K_0402_1%
1 2 TSENSE_3PH_A CSP3_3PH_B 1 2 +5VALW

PC2930 PC2931 PSYS 59

VCC Phase1 VCCCPUCORE PR2948 1 2 10_0402_1% 0.01U_0402_25V 0.1U_0402_25V6 PR2950
81205_VRMP TSENSE_3PH_B
GT Phase1

PW M3_3PH_B
1 2 1 2 11.8K_0402_1% PR2949 1 2 10_0402_1% VCCGFXCORE
1 2
VCC Phase2 VCCCPUCORE PR2951 1 2 10_0402_1%
+5VALW 1 2 81205_VCC 1 2

PR2952 PR2953
PR2954 1 2 10_0402_1%
VCCGFXCORE GT Phase2
VCC Phase3 VCCCPUCORE PR2955 1 2 10_0402_1% 2.2_0603_1% 43.2K_0402_1%

53.6K_0402_1%
1
PC2932
B
1U_0402_10V6-K 1 PW M1_3PH_B/ICCMAX3B 67 B

130K_0402_1%
PR2956

97.6K_0402_1%
4.32K_0402_1%
1

1
PW M2_3PH_B/DOSC1 67

PR2957

PR2958

PR2959
PR2960

2
2.37K_0402_1%
PR2975 1 2 0_0402_5% CSP1_3PH_B 1 2
66,67,68 DRON

2
SW _B1 67
66 PW M1_3PH_A/ICCMAX3A

1
PC2933
PR2973 0.1U_0402_25V6
66 PW M2_3PH_A/ADDR
2.37K_0402_1%

2
1 2 CSP1_3PH_A @
66 SW _A1 66 PW M3_3PH_A/VBOOT

1
2

PR2961 CSREF_3PH_B
1

2.37K_0402_1% PR2970

1
PC2934 2.37K_0402_1%
0.1U_0402_25V6 @ PR2962 PR2963
2

24.9K_0402_1% 2.37K_0402_1%
1

CSREF_3PH_A CSP2_3PH_B 1 2
TSENSE_3PH_A TSENSE_3PH_B SW _B2 67
2

1
PR2974 PC2935
1

2.37K_0402_1% 0.1U_0402_25V6
1 2 CSP2_3PH_A PR2965 PR2966 @
66 SW _A2

2
0_0402_5% 0_0402_5%

1
1

PR2964 CSREF_3PH_B
2.37K_0402_1% PC2936 PR2971
2

0.1U_0402_25V6 2.37K_0402_1%
2

TSENSE_3PH_A_R

TSENSE_3PH_B_R

@
1

CSREF_3PH_A

1 2 CSP3_3PH_A
66 SW _A3
1

PR2967
1

A 2.37K_0402_1% PC2937 PR2972 A

0.1U_0402_25V6 2.37K_0402_1% PH2904 PR2968 PH2905 PR2969
2

@ 220K_0402_5%_TSM0B224J4702RE 61.9K_0402_1% 220K_0402_5%_TSM0B224J4702RE 61.9K_0402_1%

1

CSREF_3PH_A
2

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-CPUCORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Custom
Document Number
DZ510/DY512 Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Frid ay, No ve m ber 25, 20 16 Sheet 65 of 75
5 4 3 2 1
 5 4 3 2 1

VCCCPUCORE_VIN V20B+
@
2
PJ3001
1
8A
2 1
@ @

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
JUMP_43X118 1@

EMC@
PC3053

PC3003

PC3004
PC3052

PC3005

33U_D2_25VM_R40M
+

PC3006
2

2
PR3001 2
2.2_0603_1%
D
1 2 BST11_R D

5
1
PC3009

AON6380_DFN8-5
0.22U_0603_25V7-K

BST11

PQ3001
PU3001 HG_A3 4
1
BST FLAG
9
VCCCPUCORE
2 8 PL3001
Vboot=0V Loadline=1.8mΩ
65 PWM3_3PH_A/VBOOT PWM DRVH 0.15UH_PCME064T-R15MS0R667_36A_20%
68A Ripple=+30mV/-10mV(0A-0.5A)

3
2
1
3 7 SW_A3 1 2
65,67,68 DRON EN SW
Ripple=± 10mV(0.5A-TDC)

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
5

1
1 2 4 6 1 1 1 @ 1@
+5VALW VCC GND PR3002
Ripple=± 15mV(TDC-Iccmax)

1U_0402_10V6K

AON6764_DFN8-5
PR3011 5 4.7_0805_5% + + + +

PC3011

PC3013

PC3014
PC3012
DRVL

1
2.2_0603_5%
TDC=50A Iccmax=68A OCP=81.5A

PQ3002
EMC@

PC3010
NCP81151MNTBG_DFN8_2X2

2
LG_A3 2 2 2 2
4
OVP=2V(during SS) OVP=VID+400mV

CPUCORE_SN1
2
SW_A3 65 UVP=VID-300mV
Fsw=600Khz

3
2
1

1
PC3015
1000P_0402_50V7K
EMC@

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
VCCCPUCORE_VIN @ @ @ @

1
PC3016

PC3017

PC3018

PC3019

PC3020

PC3021

PC3023

PC3025
PC3022

PC3024
2

2
@ @ @

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
1

EMC@
PC3027

PC3028

PC3029
PC3026

PC3030
C C

2
PR3005
2.2_0603_1%

5
1 2 BST12_R

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AON6380_DFN8-5
1
PC3031 @ @ @
BST12

0.22U_0603_25V7-K

1
PQ3003

PC3032

PC3033

PC3034

PC3035

PC3036

PC3037

PC3039

PC3041
PC3038

PC3040
2
HG_A2 4
PU3002

2
1 9
BST FLAG
2 8 PL3002
PWM DRVH

3
2
1
65 PWM2_3PH_A/ADDR 0.15UH_PCME064T-R15MS0R667_36A_20%
DRON 3 7 SW_A2 1 2
EN SW

1
1 2 4 6
+5VALW VCC GND PR3006
1U_0402_10V6K

AON6764_DFN8-5
PR3012 5 4.7_0805_5%
DRVL
1

2.2_0603_5%

PQ3004
EMC@
PC3042

NCP81151MNTBG_DFN8_2X2

2
LG_A2 4

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CPUCORE_SN2
2

@
SW_A2 65

1
PC3044

PC3045

PC3046

PC3047

PC3048

PC3050
PC3049

PC3051
3
2
1

2
1
PC3043
1000P_0402_50V7K
2 EMC@

B B

VCCCPUCORE_VIN

@
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
EMC@
1

1
PC3055

PC3056

PC3057
PC3054

PC3058
2

PR3009
2.2_0603_1%
1 2 BST13_R
5
1

PC3059
AON6380_DFN8-5

0.22U_0603_25V7-K
BST13

PQ3005

PU3003 HG_A1 4
1 9
BST FLAG
2 8 PL3003
65 PWM1_3PH_A/ICCMAX3A PWM DRVH 0.15UH_PCME064T-R15MS0R667_36A_20%
3
2
1

DRON 3 7 SW_A1 1 2
EN SW
5

1 2 4 6
+5VALW VCC GND PR3010
1U_0402_10V6K

AON6764_DFN8-5

PR3013 5 4.7_0805_5%
DRVL
1

2.2_0603_5%
PQ3006
PC3060

EMC@
NCP81151MNTBG_DFN8_2X2
2

LG_A1 4
CPUCORE_SN3
2

SW_A1 65
A A
3
2
1

PC3061
1000P_0402_50V7K
EMC@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCCPUCORE
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 66 of 75
5 4 3 2 1
 5 4 3 2 1

VCCGFXCORE_VIN V20B+ Vboot=0V Loadline=2.65mΩ

@ Ripple=+30mV/-10mV(0A-0.5A)
PJ3101 6A
2
2 1
1
Ripple=± 10mV(0.5A-TDC)
@ @

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

10U_0805_25V6K
JUMP_43X79 Ripple=± 15mV(TDC-Iccmax)

0.1U_0402_25V6
D D

EMC@
PC3101

PC3103

PC3104

PC3105
PC3102
TDC=25A Iccmax=55A OCP=65.5A

2
PR3101
2.2_0603_1%
OVP=2V(during SS) OVP=VID+400mV
1 2 BST21_R
UVP=VID-300mV

5
Fsw=600Khz

1
PC3106

BST21

AON6380_DFN8-5
0.22U_0603_25V7-K

PQ3101
PU3101 HG_B2 4
1
BST FLAG
9
VCCGFXCORE
2 8 PL3101
65 PWM2_3PH_B/DOSC1 PWM DRVH 0.15UH_PCME064T-R15MS0R667_36A_20%
55A

3
2
1
3 7 SW_B2 1 2
65,66,68 DRON EN SW

330U_D2_2VM_R9M
330U_D2_2VM_R9M

330U_D2_2VM_R9M
5

1
1 2 4 6 1@ 1 1
+5VALW VCC GND PR3102

1U_0402_10V6K

AON6764_DFN8-5
PR3103 5 4.7_0805_5% + + +

PC3107

PC3111

PC3109
DRVL

1
2.2_0603_5%

PC3110

PQ3102
EMC@
NCP81151MNTBG_DFN8_2X2

2
LG_B2 4 2 2 2

GFXCORE_SN1
2

SW_B2 65

3
2
1

1
PC3112
1000P_0402_50V7K
C C
EMC@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
@ @ @ @

1
PC3122

PC3121

PC3119

PC3117

PC3116

PC3115
PC3120

PC3118

PC3114

PC3113
2

2
VCCGFXCORE_VIN

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
1

EMC@
PC3123

PC3124

PC3125

PC3127
PC3126

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
@ @ @ @

2
PR3105

1
2.2_0603_1%

PC3137

PC3136

PC3134

PC3132

PC3131

PC3130
PC3135

PC3133

PC3129

PC3128
1 2 BST22_R

2
5
1

PC3138
BST22

AON6380_DFN8-5
0.22U_0603_25V7-K
2

PQ3103
PU3102 HG_B1 4
1 9
BST FLAG
2 8 PL3102
65 PWM1_3PH_B/ICCMAX3B PWM DRVH 0.15UH_PCME064T-R15MS0R667_36A_20%
3
2
1

DRON 3 7 SW_B1 1 2
EN SW
B B
5

1 2 4 6 1
+5VALW VCC GND PR3106
1U_0402_10V6K

AON6764_DFN8-5

PR3104 5 4.7_0805_5%
DRVL
1

2.2_0603_5% EMC@
PC3139

PQ3104

NCP81151MNTBG_DFN8_2X2
2

LG_B1 4
GFXCORE_SN2
2

SW_B1 65
3
2
1

PC3150
1000P_0402_50V7K
EMC@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCGFXCORE
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 67 of 75
5 4 3 2 1
 5 4 3 2 1

D D
VCCSA_VIN
@ V20B+ Vboot=1.05V Loadline=10mΩ
PJ3201 1.5A
2
2 1
1 Ripple=+30mV/-10mV(0A-0.5A)
Ripple=± 10mV(0.5A-TDC)

10U_0805_25V6-K

10U_0805_25V6-K
JUMP_43X79

0.1U_0402_25V6
1

1
Ripple=± 15mV(TDC-Iccmax)

EMC@
PC3201

PC3202

PC3203
+5VALW TDC=10A Iccmax=11.1A OCP=19A

2
PR3201 OVP=2V(during SS) OVP=VID+400mV

5
2.2_0603_1%
1 2 BST31_R
UVP=VID-300mV

AON7408L_DFN8-5
D
2

BST31

1
Fsw=600Khz

PQ3201
PR3203 PC3204
2.2_0603_5% 0.22U_0603_25V7K
HG_1PH 4
G

2
PU3201
1

S3
S2
S1
BST
4
VCC VCCSA
8 10A
1U_0402_10V6K

PL3201
DRVH

3
2
1
2 0.47UH +-20% PCMB053T-R47MS 13A
C PWM C
1

7 LX_1PH 1 2
PC3205

3 SW
EN 5

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
DRVL
2

1
9 @
FLAG 6 PR3202

AON7534_DFN8-5
D
GND

1
LG_1PH 4.7_0805_5%

PC3208

PC3206
PC3213

PC3212

PC3211

PC3210

PC3209

PC3207
NCP81253MNTBG_DFN8_2X2

PQ3202
EMC@

2
4
65 PWM1_1PH/ICCMAX1 G

VCCSA_SN
S3
S2
S1
65,66,67 DRON
LX_1PH 65

3
2
1

1
PC3214
1000P_0402_50V7K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
EMC@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
@ @

2
PC3220
PC3215

PC3216

PC3217

PC3218

PC3219

PC3221
2

1
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 68 of 75
5 4 3 2 1
 A B C D

1
+5VALW 1

V20B+

2
PR1821
2.2_0603_5% @
Change PR1802 from 100K to 10K due to Improve GPU power sequence Hai Y520 SVT
+3VS +1.55VGS_VIN 2
PJ1801
1
3A
2 1

4.7U_0603_25V6-M
4.7U_0603_25V6-M
PR1801 @ JUMP_43X79

1U_0603_10V6K

10U_0805_25V6K

10U_0805_25V6-K

10U_0805_25V6-K
5
2.2_0603_5%

PC1803

PC1804
1

1
1 2+1.55VGS_BST_R

PC1

PC2
PC1801

PC1802
AON7400A_DFN8-5
D
1
PR1802

2
10K_0402_1%

PQ1801
1
PU1802 PC1805 4
0.22U_0603_16V7K G
FBVDDQ
2
7 @ @ @

S3
S2
S1
VCC

2
10 +1.55VGS_BST PJ1802
BOOT 2 1
2 1

3
2
1
27 VDDQPWROK 1
PGOOD 9 +1.55VGS_HG JUMP_43X79
PR1804 UGATE PL1801 @
+1.55VGS_EN
27,29 FBVDDQ_PWR_EN
1 2 3
EN 8 +1.55VGS_LX
0.68UH_PCMB063T-R68MS_16A_20%
1 2 +1.55VGS_P 2
PJ1803
1
13A
PHASE 2 1

1
1K_0402_1% +1.55VGS_RF 5
RF PR1806
@
1

+1.55VGS_CS2 6 +1.55VGS_LG 4.7_0805_5% @ @ @ @ JUMP_43X79

1M_0402_5%

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
CS LGATE

+1.55VGS_SN
EMC_NS@
PR1805

PC3528

1
4 +1.55VGS_FB + + +

PC1815

PC1807

PC1808

PC1809

PC1810

PC1811

PC1812

PC1816

PC1817
2 2

AON6764_DFN8-5
FB

2
1

0.047U_0402_16V7K 11
470K_0402_1%

53.6K_0402_1%

2 GND

PQ1802
PR1807

PR1808
2

2
2 2 2

1
RT8237EZQW-2_W DFN10_3X3
4 PR1809
100_0402_1%
2

1
PC1813
1000P_0402_50V9-J

2
EMC_NS@

3
2
1

2
Change PR1804 from 0ohm to 1K & PC3528 from ns to 0.047u to fine tune FBVDDQ sequence Hai Y520 SVT
PR1811
1 2 +1.55VGS_FB_R1 1 2
FBVDD_VCC_SENSE 28
PR1810
0_0402_5%

1
18.2K_0402_1%

1.35/ 1.55V PR1812=66.5K

1
PR1812 1 2+1.55VGS_FB_R2 1 2
1.35/ 1.50V PR1812=82.5K 88.7K_0402_1% PR1813 Vout:
︵

︶
change to X76 VRA M 20K_0402_1% PR1814 PC1814
P5=1.35V± 3%

2
1K_0402_1% 330P_0402_50V8J

+1.55VGS_FB_R3
@ @ P0=1.5V± 3%

2
CAD Note ：VRAM_VDDQ_ADJ
L = 1.362V EDP-c=11A EDP-p=20A
H = 1.507V
OCP=25A
PR1815 D OVP=(1.2~1.3)*Vout

1
PQ1803
VRAM_VDDQ_ADJ_R
3 27 VRAM_VDDQ_ADJ 1 2 2
G
LBSS139WT1G_SC70-3 UVP=(0.65~0.75)*Vout 3

0_0402_5%
S Fsw=290Khz
3
1

PR1816
10K_0402_1%
@
2

4 4

RRF Fsw(kHz)
(kΩ )470 290
200 340
100 380 Security Classification LC Future Center Secret Data Title
39 430 Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-FBVDDQ
Note: DEM RRF to GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CCM RRF to PGOOD Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 69 of 75
A B C D
 A B C D

+5VALW
@
1
1A 2
PJ801
2 1
1 +1.0VGS
1

PC801 EMC@

22U_0603_6.3V6-M
22U_0603_6.3V6-M
0.1U_0402_25V6
JUMP_43X79 @ @

1
PU801 PL801 PJ802
Change PR801 from 100K to 10K due to Improve GPU power sequence Hai Y520 SVT 1UH_SDTR041B-1R0MSD_3.8A_20% JUMP_43X79
2A

PC802

PC803
+1.0VGS_VIN 4 3 +1.0VGS_LX 1 2 +1.0VGS_P 2 1
+3VS IN LX 2 1

2
5 2
PG GND

1
6 1 PR803

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
FB EN

1
4.7_0603_5% @

1
PR801
10K_0402_1%
SY8032ABC_SOT23-6 EMC_NS@ Vout=1.0V± 3%

PC806
PC804

PC805
+1.0VGS_SN 2
Vset=1.01V± 1.88%

2
2
1.0VGS_PG Vref=0.6V
27 1.0VGS_PG
OCP=6A
OVP=1.2*Vout

1
PC809
680P_0402_50V7K
PR804
0_0402_5% EMC_NS@
Fsw=1Mhz

2
1 2 +1.0VGS_EN
27,29 1V0_MAIN_EN

1 2

0.1U_0402_10V6-K
+1.0VGS_FB PR807 1 2 88.7K_0402_1%

1
PD1

1M_0402_5%
@

1
LRB751V-40T1G_SOD323-2

PR806

PC807
PC810

1
220P_0402_50V7K

2
2
2 @ @ PR808 1 2 2

133K_0402_1%

2
+5VALW
@
1A 2
PJ3506
2 1
1 +1.8VS_AON
PC3547 EMC@

22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1U_0402_25V6

JUMP_43X79 @ @
1

PU3503 PL3503 PJ3505

1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
2A
PC3546

PC3551

+1.8VGS_VIN 4 3 +1.8VGS_LX 1 2 +1.8VGS_P 2 1

IN LX 2 1
2

+3VS 5 2
PG GND

1
6 1 PR3543

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
FB EN
1

4.7_0603_5% @

1
3
PR3545 SY8032ABC_SOT23-6 EMC_NS@ Vout=1.8V± 3% 3

PC3549

PC3548

PC3550
100K_0402_1%

+1.8VGS_SN 2
@ Vset=1.8V± 1.88%

2
2

+1.8VGS_PG Vref=0.6V
OCP=6A
OVP=1.2*Vout

1
PC3553
680P_0402_50V7K
PR1902 EMC_NS@
Fsw=1Mhz

2
0_0402_5%
1 2 +1.8VGS_EN
20,27,28 PXS_PWREN PR3546
33K_0402_1%
1

+1.8VGS_FB 1 2
1M_0402_5%
1

PD2 0_0402_5%
PR3

@
3 PR1 1 2 PC1906 @
0.1U_0402_10V6-K PC3552
2

1 @ 220P_0402_50V7K
2

0_0402_5% @ 1 2
Hai 2 PR2 1 2
PR3542
16.2K_0402_1%

LBAT54SWT1G_SOT323-3
2

@
Hai

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-1.8/1.0VGS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 70 of 75
A B C D
 5 4 3 2 1

PWM-VID Specification Component Value

Config R1(KΩ ) PR9440 6.19 PSI Level Power Mode Phase Configuration
Vmin(V) 0.3 R2(KΩ ) PR9434 20.5 Connected to PVCC PSH 2Phase Auto CCM/DCM
Vmax(V) 1.3 R3(KΩ ) PR9436 4.32 High PS0 2Phase FCCM
Vboot(V) 0.8 R4(KΩ ) PR9437 16.5 Intermediate PS1 2Phase Auto CCM/DCM
Vstep(mV) 6.25 R5(KΩ ) PR9431 0.309 Low PS2 1Phase Auto CCM/DCM
N(level) 160 C(nF) PC1277 4.7
Fpwm(KHz) 675
Tdmin(nS) 9.26
D
T(uS) <100 Change MOS HLZ SDV 0617 D
+5VALW
NVVDD_VIN V20B+
@

1
PJ3401
PR3401 PU3401 2 1
2 1
2.2_0603_5%

EMC@
JUMP_43X79

2200P_0402_25V7-K

10U_0805_25V6-K

10U_0805_25V6-K
10U_0805_25V6-K

10U_0805_25V6-K
2
NVVDD_PVCC 18 @
PVCC

1
2 NVVDD_HG1
UGATE1

PC3402

PC3403

PC3404

PC3450
1
VGA_AON_3V_1.8V PC3407 PR3404 PC3409 PQ3401 PQ3402

2
1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K AON6982_DFN8-7 AON6982_DFN8-7

PC3401
2

2
1 NVVDD_BS1 1 2 1 2
BOOT1

2
1 1
1

21
PR3402 GND NVVDD
5.1K_0402_1% PL3401
20 NVVDD_PH1 7NVVDD_PH1 7NVVDD_PH1 1 2
PHASE1 0.22UH_PCMB104T-R22MS_35A_20%
PR3403
2

1
6 6 @

PC3412 50W@
330U_D2_2VM_R9M

330U_D2_2VM_R9M
330U_B2_2.5VM_R9M

330U_D2_2VM_R9M

330U_B2_2.5VM_R9M
1 1 1 1 1
1 2 0_0402_5% NVVDD_PSI_R 4 PR3405
27,72 NVVDD_PSI PSI + + + + +
PR3406 @ 4.7_0805_5%

PC3411

PC3414
PC3410

PC3413
5.1K_0402_1% EMC_NS@
VGA_AON_3V_1.8V 1 PR3428 2 1 2

3
4
5

3
4
5

2
10K_0402_1% 19 NVVDD_LG1 2 2 2 2 2

NVVDD_SN2
13 LGATE1 50W@ 50W@
27 NVVDD_PW RGD PGOOD
PR3407
1 2 10K_0402_1% NVVDD_EN_R 3
27,29 NVVDD_EN EN

1
PC3416
1

PD4 0_0402_5% @ 1000P_0402_50V9-J

1M_0402_5%

NVVDD_VIN
1

3 PR6 1 2 PC3417 EMC_NS@ @ @ @ @ @ @

PC3419 50W@
PR8

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2
.1U_0402_10V6-K @

1
1

PC3420

PC3422

PC3423

PC3440
PC3418

PC3421
C C
2

0_0402_5% @
Hai
2

2 PR7 1 2

2
5 14 NVVDD_HG2
Hai

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
LBAT54SW T1G_SOT323-3 VID UGATE2

EMC@
2200P_0402_25V7-K
@ PR3409 PC3425 @

1
2.2_0603_5% 0.22U_0603_25V7K PQ3403 PQ3404
PR3408 1 2 0_0402_5% NVVDD_VID_R 15 NVVDD_BS2 1 2 1 2 AON6982_DFN8-7 AON6982_DFN8-7

PC3427

PC3429

PC3451
PC3428
27 NVVDD_VID BOOT2

2
1

1 1
PC3424

PC3426
0.1U_0402_10V7K
2

@ PL3402
16 NVVDD_PH2 7 NVVDD_PH2 7 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2 0.22UH_PCMB104T-R22MS_35A_20%
VREF 6 6

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

PC344350W@
PC3434

10U_0603_6.3V6M
1
1

1
0.01U_0402_25V7K PR3410

PC3442

PC3445

PC3446
PC3441

PC3444
PR3411 4.7_0805_5%
19.6K_0402_1% EMC_NS@

3
4
5

3
4
5

2
2
50W@ 50W@

2
17 NVVDD_LG2

PC3447
NVVDD_SN1
LGATE2
2

NVVDD_REFIN 7
REFIN
PR3412
1

1
PC3433 100_0402_1% Change PC3447 from 22U ns to 10U stuff Hai Y520 SVT
PR3424 1000P_0402_50V9-J 1 2
13.7K_0402_1% EMC_NS@

2
PR3413
PR3415
5.9K_0402_1%
PR3414
2

1 2 1 2 NVVDD_VIDBUF 6
PC3448 @ REFADJ
1

10 NVVDD_FBRTN 1 2
0.01U_0402_25V7K RGND NVVDD_VSS_SENSE 29
3.16K_0402_1%
1

0_0402_5%
2

PR3425 PC3435 VR Remote Sense - Tie to GPU sense points

1
649_0402_1% 4700P_0402_25V7-K 11 NVVDD_FB PC3436 @
B VSNS 1000P_0402_25V7-K B
2

PR3421
2

2
1 2NVVDD_FS9 12 NVVDD_COMP 1 2
PR3416 TON OCSET/SS NVVDD_VCC_SENSE 29
PR3427 442K_0402_1%
2.2_0603_5% 0_0402_5%
PR3422
1 2 100_0402_1%
NVVDD_VIN
1

1 2 NVVDD
1

PR3418
1

PC3449 PC3438 80.6K_0402_1%

1U_0402_25V6-K RT8816AGQW _W QFN20_3X3 1000P_0402_25V7-K
2

@ 50W@
2

Vboot=0.8V
Ripple=± 20mV
TDC=58A Iccmax=101AOCP≈ 116A
Vref=2V
FUVP:Vfb=0.2V
SUVP:Vcomp=3V
OVP:Vfb=2V
Fsw=400KHz

A A

Security Classification LC Future Center Secret Data Title

PWR-NVVDD
Issued Date 2016/01/20 Deciphered Date 2016/01/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size
DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 71 of 75
5 4 3 2 1
 5 4 3 2 1

PWM-VID Specification Component Value

Config R1(KΩ ) PR9440 6.19 PSI Level Power Mode Phase Configuration
Vmin(V) 0.3 R2(KΩ ) PR9434 20.5 Connected to PVCC PSH 2Phase Auto CCM/DCM
Vmax(V) 1.3 R3(KΩ ) PR9436 4.32 High PS0 2Phase FCCM
Vboot(V) 0.8 R4(KΩ ) PR9437 16.5 Intermediate PS1 2Phase Auto CCM/DCM
Vstep(mV) 6.25 R5(KΩ ) PR9431 0.309 Low PS2 1Phase Auto CCM/DCM
N(level) 160 C(nF) PC1277 4.7
Fpwm(KHz) 675
Tdmin(nS) 9.26
D T(uS) <100 +5VALW D

NVVDDS_VIN V20B+
@

1
PJ3501
PR3501 2 1
PU3501 2 1
2_0603_5%

PC3501 EMC_NS@
JUMP_43X79

2200P_0402_25V7-K

10U_0805_25V6-K
10U_0805_25V6K
2

5
NVVDDS_PVCC 18
PVCC

1
2 NVVDDS_HG1

AON6372_DFN8-5
HG1

PC3506

PC3507
1
VGA_AON_3V_1.8V PC3503 PR3505 PC3509

2
4.7U_0402_6.3V6M 2.2_0603_5% 0.22U_0603_25V7K

PQ3501
1 NVVDDS_BS11 2 1 2 4
BST1

2
NVVDDS
1
21
PR3502 THERM/GND
5.1K_0402_1% PL3501

3
2
1
20 NVVDDS_PH1 1 2
PH1

1
PR3503 0.22UH_PCME064T-R22MS0R985_28A_20%
2

5
0_0402_5% PR3506 @

330U_D2_2VM_R9M

330U_D2_2VM_R9M
1 1
1 2 NVVDDS_PSI_R 4 4.7_0805_5%

AON6764_DFN8-5
27,71 NVVDD_PSI PSI + +
@ PR3529 EMC_NS@

PC3505
PC3504
PR3504 1 2

PQ3503

2
1 2 5.1K_0402_1%

NVVDDS_SN2
+3VS NVVDDS_LG1 2 2
10K_0402_1% 19 4
13 LG1
Hai PGOOD

1
PR3507 1 2 0_0402_5% NVVDDS_EN_R 3 PC3510
27 NVVDDS_EN EN

3
2
1
1000P_0402_50V9-J
1

1 2 PC3511 EMC_NS@

2
@ 0.1U_0402_10V7K @ @

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PD3501 @

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1
2

1
LRB751V-40T1G_SOD323-2

PC3512

PC3514

PC3515

PC3516

PC3519
PC3513
C C

2
NVVDDS_VID_R 5 2 2
PR3508 1 2 0_0402_5% 14 Delete 2Pcs MOS for NVVDDS 0617

PC3517

PC3518
27 NVVDDS_VID VID HG2
1

PC3520 @
0.1U_0402_10V7K 15
BST2
2

Change PC3517/PC358 from 22U ns to 4.7U stuff Hai Y520 SVT

16
2 1 NVVDDS_VREF 8 PH2
VREF
PC3521
Vboot=0.8V
1

0.01U_0402_25V7K Ripple=± 20mV

PR3509
20.5K_0402_1%
TDC=13A Iccmax=18A OCP≈ 26A
LG2
17
Vref=2V
2

NVVDDS_REFIN 7 FUVP:Vfb=0.2V
REFIN
PR3510
SUVP:Vcomp=3V
1

PR3521
100_0402_1%
1 2
OVP:Vfb=2V
16.5K_0402_1%
PR3512
Fsw=450KHz
6.19K_0402_1%
PR3511
2

2 1 1 2 NVVDDS_VIDBUF 6
VIDBUF
1

PC3527 10 NVVDDS_FBRTN 1 2
4700P_0402_25V7-K PR3513 FBRTN NVVDDS_VSS_SENSE 28
1

4.32K_0402_1%
0_0402_5%
2

PR3522 PC3522 VR Remote Sense - Tie to GPU sense points

309_0402_1% 4700P_0402_25V7-K 11 NVVDDS_FB
FB
2

B B

1
@ PR3515 PC3524 PC3525
2

49.9_0402_1% 47P_0402_50V8J 1000P_0402_25V7-K

1 2NVVDDS_FS 9 12 NVVDDS_COMP PC3523 1 2 22P_0402_50V8-J 1 2 COMP32 1 2 @
FS COMP/ILMT

2
PR3514
39K_0402_1%
PR3518
PR3519
1

10K_0402_1%
1 2 COMP31 1 2 1 2 COMP30 1 2
PR3516 NVVDDS_VCC_SENSE 28
56.2K_0402_1% PR3517 PC3526
NCP81278MNTXG_QFN20_3X3 51K_0402_1% 220P_0402_50V7K 0_0402_5%
PR3520
@
2

100_0402_1%
1 2 NVVDDS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-NVVDDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, November 25, 2016 Sheet 72 of 75

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 PWR-Power schematic history
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
Custom
DZ510/DY512 1 .0

Date: Friday, November 25, 2016 Sheet 73 of 75

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: F riday, Novem ber 25, 2016 Sheet 74 of 75
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D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: F riday, Novem ber 25, 2016 Sheet 75 of 75
5 4 3 2 1