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Analog and Digital VLSI Design

1. The document describes the steps to design and simulate an inverter circuit using analog and digital VLSI design tools. 2. Key steps include creating a schematic of the inverter, generating a symbol, creating a test bench, simulating the design, laying out the inverter in layout view, performing DRC, LVS and parasitic extraction, and post-layout simulation with extracted parasitics. 3. The layout is generated by placing the transistors and connecting the appropriate layers like poly, metal-1, wells and contacts. DRC, LVS and parasitic extraction help verify and refine the design before post-layout simulation.

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Skvk
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46 views

Analog and Digital VLSI Design

1. The document describes the steps to design and simulate an inverter circuit using analog and digital VLSI design tools. 2. Key steps include creating a schematic of the inverter, generating a symbol, creating a test bench, simulating the design, laying out the inverter in layout view, performing DRC, LVS and parasitic extraction, and post-layout simulation with extracted parasitics. 3. The layout is generated by placing the transistors and connecting the appropriate layers like poly, metal-1, wells and contacts. DRC, LVS and parasitic extraction help verify and refine the design before post-layout simulation.

Uploaded by

Skvk
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Analog and Digital VLSI Design

1. Open a terminal and browse to any of the location.


2. Open a C-shell and invoke DAIC following the below
commands cd /home/software/practice/my_inverter
csh
source
/home/software/cshrc/ams.cshrc da_ic
&
3. Open the palette moving to
MGC -7 Setup -7 Show Palette

4. On the Palette click on


Session -7 schematic
5. Now click on enter schematic name you required
/home/software/practice/my_inverter

6. Click on the worksheet and select the following options from the
palette Library -7 Device Library

7. Add a 4-pin PMOS and NMOS from the device lib.


8. Connect the PMOS and NMOS as shown in the figure below to connect from one node
to another node select “w” to select wire.
9. Click on “back” tab on device lib palette. Select generic lib and add a input port
and output port by selecting the portin and portout tabs.
10. Select the input NET, and right click the mouse button and select “Name
Nets:”.Change the net names.
11. Change the properties of transistors by selecting the transistor and pressing ‘Q’.
Change the ASIM_Model from NCH to N for NMOS & PCH to P for PMOS
12. Change the W & L values of the Transistors to
For PMOS : L -7 2u; W-79u
For NMOS : L -7 2u; W -7 9u
12. Go to Miscellanious-7 Generate Symbol
13. Select Replace existing & activate symbol options
14. Click Ok. Symbol gets generated for you.
Change the shape of symbol if required.
Save the symbol.
Test Bench Creation
1. Close all schematics & symbols.
2. Create a new schematic inv_test by selecting new schematic from session.
3. Add symbol of the schematic made.
Add-7 Instance-7 Choose Symbol.
4. Add a Pulse Source at the input to inverter and a DC Voltage source VDD port. And
do the necessary connections. Connect ground symbol from generic library
(LIBRARY-7Generic Library) to VSS.
** (from sources library we can pick various sources)
5. Right click on the Pulse Generator Source and
select Properties -7 Modify Multiple.
6. Change the values of the below mentioned parameters and apply the changes. Once
you change the values that have to be reflected once you click on OK tab.
Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS
Fall = 1nS Width = 25nS Period = 50ns.

7. Also change the magnitude of the Voltage Source from 1V to 5V by following the
below step.
8. Right Click on the Voltage source adjacent to VDD and
then Properties -7 Modify Multiple
8. Now from the menu bar click on check and save button. This will report if any
errors present.
9. Now click on “back” tab and then select ‘Simulation’ from the palette to run
the simulation and select ok.
10. Select a New configuration (Give a new name for simulation).
11. Now select the Session tab -7simulator/viewer from Setup on the palette and ensure that
the following options are set.
Simulator -7 Eldo and Viewer -7 EZwave and then Ok.
12. Select Lib/Temp/Inc-7Libraries and provide the following path by selecting the
browse button. $ADK/technology/ic/models/ami05.mod.
13. Select Analyses -7 Transient. Give the Start and Stop Time.
14. Select the input path A and then hold CTRL key and then output path Y and click on
“Wave Outputs -7 Save Selected” from the palette. Select Voltage from the Popup,
click Ok and then a Setup Difference Plot window opens where you select the plot type
as individual and click on Ok.

15. Now click on Run Eldo tab from the palette where it opens 2 windows showing various
steps running in command line. Once it finishes it will invoke the EZWave waveform viewer.
If it is not invoked Click on the View Waves Tab from the palette to invoke the EZWave
Waveform Viewer.
16. Now the EZWave displays the input and output signals.
17. Here if you go and explore the folders and search for spi file in the simulation folder
inside test bench folder. It will be something like the below path
/home/student/practice/inverter_test/simulation_name/inverter.spi
This .spi file will be used at post layout simulation
Inverter Layout Generation
Before Layout generation, change the ASIM_Model of PMOS from P to PMOS and
NMOS from N to NMOS in inverter schematic.
Invoke the IC station tool by typing the following command-7 ic & on command prompt
Now choose the “create” option from the palette.

Select DA_IC connectivity.


Component--7 to the path of inverter schematic Cell name-7 name of inverter schematic
Process-7 $ADK/technology/ic/process/ami05

Rules-7$ADK/technology/ic/process/ami05.rules
Set Grid to 0.5.
Other-7 Window-7 Set Grid
Snap Grid Coordinates -7 X: 0.5 Y 0.5 Setup-
7 SDL
In Componet Subtype change ‘model ‘to ‘asim _model’
Choose SDL parts, then OK.
Select PMOS in schematic.
Go to Place-7 Inst in Palate.
This will place transistor in Layout view.
Similarly do for NMOS and ports.
Select POLY for Layer Palate and connect the two gates of
Transistors. Easy Edit -7 Shape

Similarly connect the Drain of PMOS and Drain of NMOS with Metal-
1. Extend the Metal-1 layer that connects drains with IRoute option
Route-7 IRoute the after extending a layer of metal from M-1 layer that connects drains &
press ‘Shift +V’ which adds a via on which the port has to be

placed.
Draw a square of 5X5 at POLY layer connecting two gates. At 1.5 distance from sides of
square draw a square with CONTACT TO PLOY as an inner square to

POLY.
Now connect input pin to Via drawn with Metal 1 layer using IRoute method.
Connect VDD to Source of PMOS and VSS to Source of NMOS using M1 layer.
Easy Edit-7 shape (M1 from Layer palate).
Draw M1 layer above PMOS & below NMOS to keep NWELL and PSUB contacts.
Add-7 Cell
Go to $ADK/technology/ic/process/ami05_via
Add Pwell_contact at M1 layer below NMOS
Add Nwell_contact at M1 layer above PMOS
DRC Checking
DRC check using Calibre:
First we have to generate GDS2
file: Translate-7 Write GDSII
Give the path where it has to be
saved. Go to Write Options.

Check Replace Existing GDSII File & Add Text on Ports.


Calibre-7 Run DRC
Give details as

Rules: $ADK/technology/ic/process/ami05.rules
DRC Run Directory: your directory

Inputs: To the gds2 file


UnCheck ‘Export from layout Viewer’
Format : GDSII

Run DRC:
It will report with no results when the design is error free.
Layout versus Schematic:
Calibre-7 Run LVS
Give details as

Rules: $ADK/technology/ic/process/ami05.calibre.rules
DRC Run Directory: your directory

Inputs:-7 layout -7GDSII file Format: GDSII


Inputs -7 netlist -7 inverter.spi (in your simulation directory of testbench); Format:
SPICE
UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’
Format: SPICE
Run LVS
Parasitic
Extraction Calibre-
7 Run PEX Give
details as

Rules: $ADK/technology/ic/process/ami05.calibre.rules
DRC Run Directory: your directory

Inputs:-7 layout -7GDSII file ;Format : GDSII


Inputs -7 netlist -7 inverter.spi in your simulation directory; Format: SPICE
UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’
Outputs: Netlist -7Format= DSPF
Used Names for -7Schematic
Select only R+C instead of
R+C+C

Run LVS
It will generate a Pex Netlist file has to be used in post layout simulation
POST LAYOUT SIMULATION
Open your Test Bench:
Descend into your schematic and change the Asim_model of PMOS to P and NMOS to
N Check and Save.

Simulate your Test Bench.


In Simulation Window on top palette,
Parasitic-7 Add DSPF
Go to the directory to find inverter.pex (inverter.pex.netlsit)
Select RC. OK

Now Simulate with Eldo.


You can Add & Remove DSPF in Parasitic which show results with & without Parasitic.

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