EZ-PD™ CCG2 Datasheet

USB Type-C Port Controller

USB Type-C Port Controller

General Description
EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a
complete USB Type-C and U1SB Power Delivery port control solution for passive cables, active cables, and powered accessories. It
can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8
technology with a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver
including the Type-C termination resistors RP, RD and RA.
Applications Type-C Support
■ USB Type-C EMCA cables ■ Integrated transceiver (baseband PHY)
■ USB Type-C powered accessories
■ Integrated UFP (RD), EMCA (RA) termination resistors, and
current sources for DFP (RP)
■ USB Type-C upstream facing ports
■ Supports one USB Type-C port
■ USB Type-C downstream facing ports
Low-Power Operation
Features ■ 2.7-V to 5.5-V operation
32-bit MCU Subsystem ■ Two independent VCONN rails with integrated isolation
between the two
■ 48-MHz ARM Cortex-M0 CPU
■ Independent supply voltage pin for GPIO that allows 1.71-V to
■ 32-KB Flash
5.5-V signaling on the I/Os
■ 4-KB SRAM
■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA
■ In-system reprogrammable
System-Level ESD on CC and VCONN Pins
Integrated Digital Blocks
■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
■ Integrated timers and counters to meet response times on IEC61000-4-2 level 4C
required by the USB-PD protocol
■ Run-time reconfigurable serial communication block (SCB)
Packages
with reconfigurable I2C, SPI, or UART functionality ■ 1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with
0.4-mm ball pitch
Clocks and Oscillators
■ 2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN
■ Integrated oscillator eliminating the need for external clock
■ 4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN
■ Supports industrial (40 °C to +85 °C) and extended industrial
(40 °C to +105 °C) temperature ranges
Logic Block Diagram
CCG2: USB Type-C Cable Controller
MCU Subsystem Integrated Digital Blocks I/O Subsystem
CC5
TCPWM1

VCONN1
SCB2
CORTEX-M0 (I2C, SPI, UART)
VCONN2
Advanced High-Performance Bus (AHB)

48 MHz SCB2
(I2C, SPI, UART) VDDIO
Programmable IO Matrix

GPIO6
Profiles and Port
Configurations

Flash Baseband MAC

(32 KB)

Baseband PHY

SRAM
(4 KB) Integrated Rd3, Ra4,
and Rp7

Serial Wire Debug

1 Timer, counter, pulse-width modulation block

2 Serial communication block configurable as UART, SPI, or I2C
3 Termination resistor denoting a UFP
4 Termination resistor denoting an EMCA
5 Configuration Channel
6 General-purpose input/output
7 Current Sources to indicate a DFP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-93912 Rev. *M Revised July 11, 2018
 EZ-PD™ CCG2 Datasheet

Available Firmware and Software Tools

EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility

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 EZ-PD™ CCG2 Datasheet

Contents
Functional Overview .........................................................4 Ordering Code Definitions ......................................... 28
CPU and Memory Subsystem .....................................4 Packaging ........................................................................29
USB-PD Subsystem (SS) ............................................5 Acronyms ........................................................................32
System Resources .......................................................5 Document Conventions ................................................. 33
Peripherals ..................................................................6 Units of Measure ....................................................... 33
GPIO ............................................................................6 References and Links To Applications Collaterals .... 34
Pinouts............................................................................... 7 Document History Page .................................................35
Power .................................................................................9 Sales, Solutions, and Legal Information ...................... 36
Application Diagrams .....................................................10 Worldwide Sales and Design Support ....................... 36
Electrical Specifications .................................................19 Products ....................................................................36
Absolute Maximum Ratings ....................................... 19 PSoC®Solutions ........................................................36
Device Level Specifications .......................................20 Cypress Developer Community .................................36
Digital Peripherals...................................................... 22 Technical Support ......................................................36
Memory...................................................................... 24
System Resources..................................................... 25
Ordering Information ...................................................... 28

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 EZ-PD™ CCG2 Datasheet

Figure 1. EZ-PD CCG2 Block Diagram

CPU Subsystem
CCG2
SWD/TC SPCIF
Cortex
32-bit FLASH SRAM SROM
M0
32 KB 4 KB 8 KB
48 MHz
AHB-Lite FAST MUL
Read Accelerator SRAM Controller SROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (Single Layer AHB)
Power
Sleep Control Peripherals
WIC
POR REF
PWRSYS
PCLK Peripheral Interconnect (MMIO)

Clock
Clock Control
WDT USB-PD SS
IMO ILO

6 x TCPWM
IOSS GPIO (3 x ports)

2 x SCB
Reset
Reset Control
XRES

Test
DFT Logic

2 X VCONN
CC BB PHY
DFT Analog

Pads, ESD
Power Modes High Speed I/O Matrix
Active/Sleep
Deep Sleep
12 x GPIOs, 2 x OVTs

I/O Subsystem

Functional Overview The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
CPU and Memory Subsystem EZ-PD CCG2 has four break-point (address) comparators and
two watchpoint (data) comparators.
CPU
The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU Flash
subsystem, which is optimized for low-power operation with The EZ-PD CCG2 device has a flash module with a flash
extensive clock gating. It mostly uses 16-bit instructions and accelerator, tightly coupled to the CPU to improve average
executes a subset of the Thumb-2 instruction set. This enables access times from the flash block. The flash block is designed to
fully compatible binary upward migration of the code to higher deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS
performance processors such as the Cortex-M3 and M4, thus access time at 24 MHz. The flash accelerator delivers 85% of
enabling upward compatibility. The Cypress implementation single-cycle SRAM access performance on average. Part of the
includes a hardware multiplier that provides a 32-bit result in one flash module can be used to emulate EEPROM operation if
cycle. It includes a nested vectored interrupt controller (NVIC) required.
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up SROM
from the Deep Sleep mode, allowing power to be switched off to A supervisory ROM that contains boot and configuration routines
the main processor when the chip is in the Deep Sleep mode. is provided.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.

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 EZ-PD™ CCG2 Datasheet

USB-PD Subsystem (SS) EZ-PD CCG2 USB-PD sub-system can be configured to

respond to SOP, SOP', or SOP” messaging.
EZ-PD CCG2 has a USB-PD subsystem consisting of a USB
Type-C baseband transceiver and physical-layer logic. This The USB-PD sub-system contains a 8-bit SAR (Successive
transceiver performs the BMC and the 4b/5b encoding and Approximation Register) ADC for analog to digital conversions.
decoding functions as well as the 1.2-V front end. This The ADC includes a 8-bit DAC and a comparator. The DAC
subsystem integrates the required termination resistors to output forms the positive input of the comparator. The negative
identify the role of the EZ-PD CCG2 solution. RA is used to input of the comparator is from a 4-input multiplexer. The four
identify EZ-PD CCG2 as an accessory or an electronically inputs of the multiplexer are a pair of global analog multiplex
marked cable. RD is used to identify EZ-PD CCG2 as a UFP in busses an internal bandgap voltage and an internal voltage
a hybrid cable or a dongle. When configured as a DFP, integrated proportional to the absolute temperature. All GPIO inputs can be
current sources perform the role of RP or pull-up resistors. These connected to the global Analog Multiplex Busses through a
current sources can be programmed to indicate the complete switch at each GPIO that can enable that GPIO to be connected
range of current capacity on VBUS defined in the Type-C spec. to the mux bus for ADC use. The CC1, CC2 and RD1 pins are
EZ-PD CCG2 responds to all USB-PD communication. The not available to connect to the mux busses.
Figure 2. USB-PD Subsystem
To/From system Resources
vref iref VDDD

To/ from AHB VCONN power logic

8-bit ADC
VDDD

From AMUX Enable

Logic VCONN1
Ra
Ra Enable
VConn1 detect
VCONN
VConn2 detect Detect Ra
VCONN2

TxRx Enable 8kV IEC ESD

Digital Baseband PHY Analog Baseband PHY

Tx_data Enable Logic
from AHB Tx 4b5b SOP BMC
SRAM Encoder Insert Encoder

TX Rp
CRC CC1
Rx_data RX RD1
to AHB Rx 4b5b SOP BMC
SRAM Decoder Detect Decoder CC2
Ref
Comp
Active DB 8kV IEC ESD
CC control Rd Rd
CC detect

Deep Sleep Reference Enable Deep Sleep

Vref & Iref Gen vref, iref

Functional, Wakeup Interrupts

System Resources
Power System Clock System
The power system is described in detail in the section Power on The clock system for EZ-PD CCG2 consists of the Internal Main
page 9. It provides assurance that voltage levels are as required Oscillator (IMO) and the Internal Low-power Oscillator (ILO).
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD
CCG2 can operate from three different power sources over the
range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
EZ-PD CCG2 provides Sleep and Deep Sleep low-power
modes.

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 EZ-PD™ CCG2 Datasheet

Peripherals GPIO
Serial Communication Blocks (SCB) EZ-PD CCG2 has up to 10 GPIOs in addition to the I2C and SWD
pins, which can also be used as GPIOs. The I2C pins from SCB
EZ-PD CCG2 has two SCBs, which can be configured to 0 are overvoltage-tolerant. The number of available GPIOs vary
implement an I2C, SPI, or UART interface. The hardware I2C with the package. The GPIO block implements the following:
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can ■ Seven drive strength modes:
be configured to act as master or slave. ❐ Input only

In the I2C mode, the SCB blocks are capable of operating at ❐ Weak pull-up with strong pull-down
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible ❐ Strong pull-up with weak pull-down
buffering options to reduce interrupt overhead and latency for the ❐ Open drain with strong pull-down
CPU. These blocks also support I2C that creates a mailbox ❐ Open drain with strong pull-up
address range in the memory of EZ-PD CCG2 and effectively ❐ Strong pull-up with strong pull-down
reduce I2C communication to reading from and writing to an ❐ Weak pull-up with weak pull-down
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for ■ Input threshold select (CMOS or LVTTL)
the CPU to read data, greatly reduce the need for clock ■ Individual control of input and output buffer enabling/disabling
stretching caused by the CPU not having read data on time. in addition to the drive strength modes
The I2C peripherals are compatible with the I2C Standard-mode,
■ Hold mode for latching previous state (used for retaining I/O
Fast-mode, and Fast-mode Plus devices as defined in the NXP
state in Deep Sleep mode)
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes. ■ Selectable slew rates for dV/dt related noise control to improve
The I2C
port on SCB 1 block of EZ-PD CCG2 is not completely EMI
compliant with the I2C spec in the following respects: During power-on and reset, the I/O pins are forced to the disable
2 state so as not to crowbar any inputs and/or cause excess
■ The GPIO cells for SCB 1's I C port are not overvoltage-tolerant
turn-on current. A multiplexing network known as a high-speed
and, therefore, cannot be hot-swapped or powered up
I/O matrix is used to multiplex between various signals that may
independently of the rest of the I2C system.
connect to an I/O pin.
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit
timer, counter, pulse-width modulator (PWM), and quadrature
decoder functionality. The block can be used to measure the
period and pulse width of an input signal (timer), find the number
of times a particular event occurs (counter), generate PWM
signals, or decode quadrature signals.

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 EZ-PD™ CCG2 Datasheet

Pinouts

Pin Map Ball Location Pin Map

Group Name Description
24-QFN 20-CSP 14-DFN
USB Type-C CC1 2 B4 3 USB PD connector detect/Configuration Channel 1
Port
CC2 1 A4 N/A USB PD connector detect/Configuration Channel 2
RD1 3 B3 N/A Dedicated Rd resistor pin for CC1
Must be left open for cable applications and connected
together with CC1 ball for UFP or DFP with dead battery
applications
GPIOs and GPIO 22 C3 N/A GPIO / SPI_0_CLK / UART_0_ RX
serial interfaces
GPIO 18 D3 13 GPIO / SPI_0_MOSI / UART_0_TX
GPIO 13 C2 10 GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX
GPIO 10 D2 N/A GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX
GPIO 15 B2 11 GPIO / SPI_1_SEL / UART_1_RTS
GPIO 14 N/A N/A GPIO
GPIO 17 N/A N/A GPIO
GPIO 21 N/A N/A GPIO
GPIO 23 N/A N/A GPIO
GPIO 24 N/A N/A GPIO
I2C_0_SCL 20 A3 1 GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS
I2C_0_SDA 19 A2 14 GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS
SWD _IO 11 E2 8 SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI
SWD_CLK 12 D1 9 SWD clock / GPIO
RESET XRES 16 B1 12 Reset input
POWER VCONN1 5 E4 5 VCONN 1 input (4.0 V to 5.5 V)
VCONN2 4 C4 4 VCONN 2 input (4.0 V to 5.5 V)
VDDIO 8 E1 N/A 1.71-V to 5.5-V supply for I/Os
VCCD 7 A1 6 1.8-V regulator output for filter capacitor
VDDD 9 VDDD supply input/output (2.7 V to 5.5 V)
E3 7
VDDD 6 VDDD supply input/output (2.7 V to 5.5 V)
VSS N/A EPAD Ground supply
VSS EPAD D4 Ground supply
2
VSS C1 Ground supply

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 EZ-PD™ CCG2 Datasheet

Figure 3. 20-ball WLCSP EZ-PD CCG2 Ball Map (Bottom (Balls Up) View)
4 3 2 1

CC2 I2C_0_SCL I2C_0_SDA VCCD A

CC1 RD1 GPIO XRES B

VCONN2 GPIO GPIO VSS C

VSS GPIO GPIO SWD_CLK D

VCONN1 VDDD SWD_IO VDDIO E

Figure 4. 14-pin DFN Pin Map (Top View)

I2C_0_SCL 1 14 I2C_0_SDA
VSS 2 13 GPIO
CC1 3 12 XRES
VCONN2 4 11 GPIO
VCONN1 5 10 GPIO
VCCD 6 9 SWD_CLK
VDDD 7 8 SWD_IO

Figure 5. 24-Pin QFN Pin Map (Top View)

I2C_0_SDA
I2C_0_SCL
GPIO
GPIO
GPIO
GPIO
24
23
22
21
20
19

CC2 1 18 GPIO
CC1 2 17 GPIO
RD1 3 16 XRES
EPAD
VCONN2 4 15 GPIO
VCONN1 5 14 GPIO
VDDD 6 13 GPIO
10
11
12
7
8
9
VDDIO

GPIO
SWD_IO
SWD_CLK
VCCD

VDDD

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 EZ-PD™ CCG2 Datasheet

Power
The following power system diagram shows the set of power A separate I/O supply pin, VDDIO, allows the GPIOs to operate
supply pins as implemented in EZ-PD CCG2. at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or
EZ-PD CCG2 can operate from three different power sources. less than the voltages connected to the VCONN1, VCONN2, and
VCONN1 and VCONN2 pins can be used as connections to the VDDD pins. The independent VDDIO supply is not available on
VCONN pins on a Type-C plug of a cable or VCONN-powered the 14-DFN package. On this package, the VDDIO rail is
accessory. Each of these inputs support operation over 4.0 to internally connected to the VDDD rails.
5.5 V. An internal isolation between VCONN1 and VCONN2 pins The VCCD output of EZ-PD CCG2 must be bypassed to ground
is provided allowing them to be at different levels simultaneously. via an external capacitor (in the range of 1 to 1.6 µF; X5R
CCG2 can be used in EMCA applications with only one or both ceramic or better).
VCONN pins as power sources. This is illustrated later in the
section on Applications. Besides being power inputs, each Bypass capacitors must be used from VDDD and VCONN pins
VCONN pin is also internally connected to a RA termination to ground; typical practice for systems in this frequency range is
resistor required for EMCA and VCONN-powered accessories. to use a 0.1-µF capacitor. Note that these are simply rules of
thumb and that for critical applications, the PCB layout, lead
EZ-PD CCG2 can also be operate from 2.7 to 5.5 V when inductance, and the bypass capacitor parasitic should be
operated from the VDDD supply pin. VCONN-powered simulated to design and obtain optimal bypassing.
accessory applications require that CCG2 work down to 2.7 V. In
such applications, both the VDDD and VCONN pins should be An example of the power supply bypass capacitors is shown in
connected to the VCONN pin of the Type-C plug in the Figure 6.
accessory.
In UFP, DFP, and DRP applications, CCG2 can be operated from
VDDD as the only supply input. In such applications, the VCONN
pins are left open. In DFP applications, the lowest VDDD level
that CCG2 can operate is 3.0 V due to the need to support
disconnect detection thresholds of up to 2.7 V.
Figure 6. EZ-PD CCG2 Power and Bypass Scheme Example

VCONN1 VCONN2
0.1uF RA RA 0.1uF

VDDD
1uF
Core Regulator
(srsslt)
VCCD
VDDIO
1uF
CC
GPIO Core
Tx/Rx

VSS

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 EZ-PD™ CCG2 Datasheet

Application Diagrams device can be powered irrespective of which plug is connected

to the host (DFP). However, in the application diagrams shown
Figure 7 to Figure 10 show the application diagrams of a Passive in Figure 9 and Figure 10, the VCONN signal does not run
EMCA application using CCG2 devices. Figure 7 and Figure 8 through the entire cable, but only runs to the respective VCONN
show the application using a single CCG2 device per cable pin of the CCG2 device at each end of the plug. Also, only one
present at one of the two plugs, whereas Figure 9 and Figure 10 CCG2 device is powered at any given instance, depending on
show the same with two CCG2 devices per cable present at each which one is nearer to the DFP that supplies VCONN.
plug. The VBUS signal, the SuperSpeed lines, HighSpeed lines, Note: Application diagram in Figure 8 requires external diodes
and CC lines are connected directly from one end to another. to operate in the extended VCONN voltage range of 2.7V to 5.5V.
The application diagrams shown in Figure 7 and Figure 8 require
a single VCONN wire to run through the cable so that the CCG2
Figure 7. Passive EMCA Application – Single EZ-PD CCG2 Per Cable (VCONN range between 4.0V to 5.5V)
Type-C Type-C
Plug Plug

VBUS

VCONN 1 VCONN 2

1uF

E3 E1
VDDD VDDIO
E4 C4
VCONN1 VCONN2
0.1uF
0.1uF D3
GPIO
C3 C2
GPIO GPIO
D2
A1 GPIO
VCCD
VDDIO 1uF B2
CCG2 GPIO

4.7 k 20-CSP A4
B1 CC2
XRES
D4 VSS CC1 B4

C1 VSS B3
RD1
I2C_0 I2C_0 SWD_ SWD_
_SCL _SDA IO CLK
A3 A2 E2 D1

CC

SuperSpeed and HighSpeed Lines

GND

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 EZ-PD™ CCG2 Datasheet

Figure 8. Passive EMCA Application – Single EZ-PD CCG2 Per Cable (VCONN range between 2.7V to 5.5V)
Type-C Type-C
Plug Plug

VBUS

Select a diode with VF less than 0.3V at 10mA

NSR0620P2T5G NSR0620P2T5G VCONN 2
VCONN 1 2 1
1 2

1uF
E3 E1
VDDD VDDIO
E4 C4
VCONN1 VCONN2
0.1uF D3 0.1uF
GPIO
C3 C2
GPIO GPIO
D2
GPIO
A1 B2
VCCD GPIO
1uF CCG2
A4
B1 CC2
XRES
D4 CC1 B4
VSS
C1 VSS B3
RD1
I2C_0 I2C_0 SWD_ SWD_
_SCL _SDA IO CLK
A3 A2 E2 D1

CC

SuperSpeed and HighSpeed Lines

GND

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 EZ-PD™ CCG2 Datasheet

Figure 9. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 4.0V to 5.5V)
Type-C Type-C
Plug Plug

VBUS

VCONN VCONN

1uF
1uF E3 E1
E3 E1
VDDD VDDIO
VDDD VDDIO C4 E4
E4 C4 VCONN2 VCONN1
VCONN1 VCONN2
D3 0.1uF
0.1uF D3 GPIO
GPIO C3
GPIO C2
C3 C2 GPIO
GPIO GPIO A1 D2
A1 D2 VCCD GPIO
VCCD 1uF
1uF GPIO
VDDIO B2
VDDIO B2 CCG2 GPIO
CCG2 GPIO
4.7k A4
4.7k A4 B1 CC2
B1 CC2 XRES
XRES
D4 VSS CC1 B4
D4 VSS CC1 B4
C1 VSS B3
C1 VSS B3 RD1
RD1
I2C_0 I2C_0 SWD_ SWD_
I2C_0 I2C_0 SWD_ SWD_ _SCL _SDA IO CLK
_SCL _SDA IO CLK A3 A2 E2 D1
A3 A2 E2 D1

CC

SuperSpeed and HighSpeed Lines

GND

Figure 10. Passive EMCA Application – Single EZ-PD CCG2 Per Plug (VCONN range between 2.7V to 5.5V)
Type-C Plug Type-C Plug

VBUS

VCONN1 VCONN2

1uF
1uF
B1 A2
B1 A2
VDDD VDDIO
VDDD A1 D2
VDDIO VCONN1 VCONN2
A1 D2
VCONN1 VCONN2
C2 0.1uF
0.1uF C2 GPIO
GPIO
B2
B2 GPIO
GPIO

D1 CCG2
D1 VCCD
VCCD CCG2 1uF
1uF C3
C3 D3 CC2
D3 CC2 XRES
XRES D4
CC1
D4
CC1
C1 VSS B3
C1 VSS B3 RD1
RD1
I2C_SCL I2C_SDA SWD_IO SWD_CLK
I2C_SCL I2C_SDA SWD_IO SWD_CLK C4 A3 A4
B4
B4 C4 A3 A4

CC

SuperSpeed and HighSpeed Lines

GND

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 EZ-PD™ CCG2 Datasheet

Figure 11 shows a CCG2 device being used in a UFP application (tablet with a Type-C port) only as a power consumer.
The Type-C receptacle brings in HighSpeed and SuperSpeed lines, which are connected directly to the applications processor. The
VBUS line from the Type-C receptacle goes directly to the UFP (tablet) charger circuitry. The applications processor communicates
over the I2C signal with the CCG2 device, and the CC1 and CC2 lines from the Type-C receptacle are connected directly to the
respective CC1/2 pins of the CCG2 device.
Figure 11. Upstream Facing Port (UFP) Application – Tablet with a Type-C Port

Charger
VBUS

5.0 V 1.8 V

1 uF 1 uF

E3 E1
C4 VDDD VDDIO D3
VCONN2 GPIO

1.8 V E4 C2
VCONN1 GPIO

E2 D2
SWD_IO GPIO

D1 B2
SWD_CLK GPIO
4.7 kΩ 4.7 kΩ CCG2 Type-C
INT C3 GPIO A4
CC2 Receptacle
A3 I2C_0_SCL CC1 B4
Application
Processor B3 390 pF 390 pF
A2 I2C_0_SDA RD1

VSS VSS VCCD XRES 1.8 V

D4 C1 A1 B1
4.7 kΩ
1 uF

HighSpeed Lines

SuperSpeed Lines
Application
Processor/
Graphics
Controller

Figure 12 shows a Notebook DRP application diagram using a Optional FETs are provided for applications that need to provide
CCG2 device. The Type-C port can be used as a power provider power for accessories and cables using the VCONN pin of the
or a power consumer. The CCG2 device communicates with the Type-C receptacle. VBUS FETs are also used for providing
Embedded controller (EC) over I2C. It also controls the Data Mux power over VBUS and for consuming power over VBUS. A
to route the High Speed signals either to the USB chipset (during VBUS_DISCHARGE FET controlled by CCG2 device is used to
normal mode) or the DisplayPort Chipset (during Alternate quickly discharge VBUS after the Type-C connection is
Mode). The SBU lines, SuperSpeed and HighSpeed lines are detached.
routed directly from the Display Mux of the notebook to the
Type-C receptacle.

Document Number: 001-93912 Rev. *M Page 13 of 36

 EZ-PD™ CCG2 Datasheet

Figure 12. Dual Role Port (DRP) Application

VBUS FETs for

VBUS_SINK CONSUMER PATH
CHARGER

VBUS_C_CTRL
VBUS FETs for
VBUS
VBUS_SOURCE PROVIDER PATH (5-20V)
DC/DC VBUS

3.3V VDDIO

VBUS_P_CTRL

1uF 1uF
6

7
VDDD

VDDD

VDDIO

VCCD
5 15 VBUS_P_CTRL
VCONN1 GPIO
VBUS_DISCHARGE
5.0V
VDDIO 4 18 VBUS_C_CTRL
VCONN2 GPIO
5.0V
11 22 VBUS_DISCHARGE
SWD_IO GPIO
2.2kΩ OPTIONAL
12 21 CC2_VCONN_CTRL
SWD_CLK GPIO FETS for DFPs
2.2kΩ 2.2kΩ
SUPPORTING Type-C
I2C_INT 14 CCG2 24 CC1_VCONN_CTRL VCONN
GPIO
24-QFN
GPIO Receptacle
20 1 CC2
I2C_0_SCL CC2
Embedded
Controller 19
I2C_0_SDA CC1
2 CC1
VBUS
VDDIO 4.7kΩ 16 3
XRES RD1 390pF 390pF
100kΩ
23 GPIO

10 GPIO

13 GPIO

EPAD 17 VBUS_MON
VSS GPIO
10kΩ

D+/- HPD
USB
Chipset SS
SS

D+/- DP/DN

HS/SS/DP/
DisplayPort SCL SDA SBU Lines GND
Chipset HPD
SS
Data Mux
DP0/1/2/3

AUX+/-

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 EZ-PD™ CCG2 Datasheet

Figure 13 shows a CCG2 receptacle-based Power Adapter voltage on the Type-C port is monitored using internal ADC to
application in which the CCG2 device is used as a DFP. CCG2 detect undervoltage and overvoltage conditions on VBUS. To
integrates all termination resistors and uses GPIOs (VSEL_0 ensure quick discharge of VBUS when the power adapter cable
and VSEL_1) to indicate the negotiated power profile. The VBUS is detached, a discharge path is also provided.
Figure 13. Downstream Facing Port (DFP) Application

DC/DC VBUS
VSEL_1
OR
VBUS_IN (5-20V)
VSEL_0
AC-DC
SECONDARY
(5-20V) OPTIONAL VDDIO
SUPPLY. CAN SHORT
3.3V VDDIO TO VDDD IN SINGLE
SUPPLY SYSTEMS
VBUS_P_CTRL

1uF 1uF
6

7
VDDD

VDDD

VDDIO

VCCD
VSEL_1 and VSEL_0 5 15 VBUS_P_CTRL
VCONN1 GPIO
CONTROL THE SECONDARY VBUS_DISCHARGE
SIDE OF AN AC-DC OR A DC-DC 5.0V
4 18
TO SELECT THE VOLTAGE ON VCONN2 GPIO
VBUS_IN. AN EXAMPLE IS 5.0V Type-C
SHOWN BELOW: 11 22 VBUS_DISCHARGE
VSEL_1 VSEL_0 VBUS_IN
SWD_IO GPIO Receptacle
0 0 5V 12 21 CC2_VCONN_CTRL OPTIONAL
0 1 9V SWD_CLK GPIO FETS for DFPs
1 0 15V SUPPORTING
1 1 20V 14 CCG2 24 CC1_VCONN_CTRL VCONN
GPIO GPIO
24-QFN
VSEL_1 20 1
GPIO CC2

VSEL_0 19 2
GPIO CC1
VBUS
VDDIO 4.7kΩ 16 3 390pF 390pF
XRES RD1
100kΩ
23 GPIO

10 GPIO

13 GPIO

EPAD 17 VBUS_MON
VSS GPIO
10kΩ

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 EZ-PD™ CCG2 Datasheet

Figure 14 shows a USB Type-C to HDMI/DVI/VGA adapter appli- cation meets the requirements described in Section 4.3 of the
cation, which enables connectivity between a PC that supports VESA DisplayPort Alt Mode on USB Type-C Standard Version
a Type-C port with DisplayPort Alternate Mode support and a 1.0. This application supports display output at a resolution of up
legacy monitor that has HDMI/DVI/VGA interface. It enables to 4K Ultra HD (3840x2160) at 60 Hz. It also supports the USB
users of any Notebook that implements USB-Type C to connect Billboard Device Class, which is required by the USB PD speci-
to other display types. fication for enumeration of any accessories that support
This application has a Type-C plug on one end and the legacy Alternate Mode when connected to a host PC.
video (HDMI/DVI/VGA) receptacle on the other end. This appli-
Figure 14. USB Type-C to HDMI/DVI/VGA Dongle Application Diagram

VBUS_VCONN 5V
1.2V
VBUS 3.3V
Power OR BuckBoost Regulator
VCONN

VBUS

D+/- USB-Billboard
CY7C65210
XRES INT SDA SCL 3.3V

2.2k: 5%

2.2k: 5%
VBUS
VBUS_VCONN VCONN 2.2k: 5%
18 10 13 22
P1.7 P2.1 P1.3 P1.0
14
P1.4 4 100KΩ, ±1% HDMI/DVI/
Type-C 4.7KΩ 16 VCONN2
VGA
XRES 17
Plug 1µF 0.1µF P1.6 Receptacle
5 12
VCONN1 SWD_CLK
6 10KΩ, ±1%
VDDD1 11
3.3V SWD_IO
9 21
VDDD2 CYPD2119 P2.0
8 24QFN
VDDIO 23
P2.2
1µF 2
CC1 7
CC 3 VCCD
RD1
1 1µF
CC2
EPAD
P1.5 P2.3:P0.0 P0.1
15 [24:19] 20 HotPlug Detect

3.3V 1.2V

SBU_1/2 DP to HDMI/
SW for AUX DVI/VGA
Display Port
Convertor
Data Lanes

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 EZ-PD™ CCG2 Datasheet

Figure 15 shows a USB Type-C to DisplayPort adapter appli- Type-C to DisplayPort Cables). It also supports the USB
cation, which enables connectivity between a PC that supports Billboard Device Class, which is required by the USB PD speci-
a Type-C port with DisplayPort Alternate Mode support and a fication for enumeration of any accessories that support
legacy monitor that has a DisplayPort interface. Alternate Mode when connected to a host PC.
Figure 15 shows a Type-C plug on one end and a DP/mDP plug
on the other end. The application meets the requirements
described in Section 4.2 of the VESA DisplayPort Alt Mode on
USB Type-C Standard Version 1.0 (Scenarios 2a and 2b USB
Figure 15. USB Type-C to Display Port Application Diagram

Paddle Card

VBUS_VCONN
VBUS

Power OR
VCONN
VBUS

D+/-
USB-Billboard
CY7C65210 VBUS_VCONN
XRES INT SDA SCL

2.2k: 5%

2.2k: 5%
VBUS
18 10 13 22 2.2k: 5%
P1.7 P2.1 P1.3 P1.0
14 4 100KΩ, ±1%
P1.4
Type-C VCONN 4.7KΩ 16 VCONN2 mDP/
XRES 17
Plug P1.6 DP
5 12
VCONN1 SWD_CLK
0.1µF 6 10KΩ, ±1%
VDDD1 11
VBUS_VCONN SWD_IO
9 21
VDDD2 CYPD2120 P2.0
8 24QFN 23
VDDIO P2.2
1µF 2
CC1 7
CC 3 VCCD
RD1
1 1µF
CC2
EPAD
P1.5 P2.3:P0.0 P0.1
15 [24:19] 20

HotPlug Detect

SBU_1/2 AUX_P/N
SW for AUX
Display Port Display Port
Data Lanes Data Lanes

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 EZ-PD™ CCG2 Datasheet

Figure 16 shows a CCG2 Monitor/Dock application diagram. It enables connectivity ■ Provides simultaneous 4K display output with USB 3.1 Gen 1 on the USB Type-A
between a USB Type-C host system on the Upstream port and multiple Display/Data port
devices on the Downstream port. This application has a USB Type-C receptacle on
the Upstream port, which supports data, power, and display. On the Downstream ■ Four-lane display on the DisplayPort connector
port, this application supports: USB Type-A, Gigabit Ethernet, DisplayPort, and USB ■ Multi-Stream support on DisplayPort and Downstream Type-C port
Type-C receptacle.
■ USB 3.1 Gen 1 hub for USB port expansion
The main features of this solution are:
■ Gigabit Ethernet using RJ45 connector
■ Powered from an external 24-V DC power adapter
■ Supports firmware upgrade of CCG2 controllers, HX3 Hub controller, and Billboard
■ Provides up to 45 W (15 V at 3A) on the Upstream Type-C port and up to 15 W controller
(5 V at 3A) on the Downstream USB Type-C port
Figure 16. CCG2 in Dock/Monitor Application Diagram

5-20V
DS_I2C_INT 5.0V
VSEL_0
5-20V 5V 1.2V 3.3V VBUS_DS
Regulator VSEL_1
Power In 100KΩ
VBUS_US 5V Brick
Power
INT2
100KΩ
USB-Billboard Discharge DS_VBUS_DIS
CY7C65210 HS_DS2 1KΩ
NFET
100Ω 3.3V
INT1 SDA SCL
US_VBUS_P_CTRL
1KΩ
Discharge US_VBUS_DIS US_VBUS_P_CTRL
2.2k: 5%
NFET I2C Slave 100KΩ VCONN
2.2k: 5% 100KΩ
SYS_I2C_SDA

SYS_I2C_SDA
SYS_I2C_SCL

SYS_I2C_SCL

DS_VBUS_DIS
100KΩ 100KΩ
3.3V

2.2k: 5% 200KΩ

14 19 20 2.2k: 5% 20 19 22 24
15
P1.4 P0.0 P0.1 P1.3
13 2.2k: 5%
Cypress USB3.0 HUB 2.2k: 5% 2.2k: 5% 13
P1.3 P0.1 P0.0 P2.1 P2.3
15 Type-C
P1.5 I2C Master I2C Master P1.5
Type-C 3.3V P1.0 10 10 P1.0
3.3V VCONN to
5 18 VSEL_0 18 P1.7 5
SYS_I2C_SCL
SYS_I2C_SCL

VCONN1 P1.7 VCONN1

to 24 VSEL_1 VBUS VBUS Device
8 P2.3 8
Notebook VDDIO VDDIO 100KΩ
21 HUB_VBUS_US USB Type-A
6 P2.0 4 VCONN2 6
4.7KΩ

4.7KΩ
0.1µF 1µF VDDD1 Receptacle VDDD1 1µF 0.1µF
9 DRP VCONN2 4 100KΩ, ±1% 100KΩ, ±1%
DFP 9
VDDD2 CYPD2121 CYPD2125 VDDD2 200KΩ
16 P1.6 17 DS1 17 P1.6 16
XRES 24QFN HUB_VBUS_US 24QFN XRES
0.1µF HS_DS2 11 0.1µF
2
CC1 SWD_IO_P1.1 11 USB Ethernet GX3 SWD_IO RD1
3
10KΩ, ±1% 10KΩ, ±1% 7
CC1 3 VCCD 7 USB D+/- Hub DS3
CYUSB3610- VCCD 2 CC1
RD1 CYUSB3304 HS_DS4 CC1
CC2 1 1µF SS Data Lines -68LTXC
SS_DS4
68LTXC 1µF 1 CC2
CC2 CC2
22 EPAD EPAD 21
US_VBUS_DIS
P2.1 SWD_CLK_P1.2 P2.2 P2.2 P1.4 SWD_CLK P2.0
12 23 HotPlug Detect DS_HotPlug Detect DS_HotPlug Detect 23 14 12

DS_I2C_INT
USB D+/- HPD SCL SDA SDA SCL HPD HS_DS4
DP2
SBU_1/2 DP SS Data Lines_1
Type-C Mux Port Type-C Mux
SS Data Lanes SS_DS4 SS Data Lines_2
DP
Spliter DP2

CCG2 connected on the Downstream Port

CCG2 connected on the Upstream Port

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 EZ-PD™ CCG2 Datasheet

Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]

Parameter Description Min Typ Max Units Details/Conditions

VDDD_MAX Digital supply relative to VSS –0.5 – 6 V Absolute max

VCONN1_MAX Max supply voltage relative to VSS – – 6 V Absolute max
VCONN2_MAX Max supply voltage relative to VSS – – 6 V Absolute max
VDDIO_MAX Max supply voltage relative to VSS – – 6 V Absolute max
VGPIO_ABS GPIO voltage –0.5 – VDDIO + 0.5 V Absolute max
Absolute max voltage for CC1 and
VCC_ABS – – 6 V Absolute max
CC2 pins
IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max
GPIO injection current, Max for Absolute max, current
IGPIO_injection –0.5 – 0.5 mA
VIH > VDDD, and Min for VIL < VSS injected per pin
Electrostatic discharge human
ESD_HBM 2200 – – V –
body model
Electrostatic discharge charged
ESD_CDM 500 – – V –
device model
LU Pin current for latch-up –200 – 200 mA –
Contact discharge on
Electrostatic discharge
ESD_IEC_CON 8000 – – V CC1, CC2, VCONN1, and
IEC61000-4-2
VCONN2 pins
Air discharge for pins
Electrostatic discharge
ESD_IEC_AIR 15000 – – V CC1, CC2, VCONN1, and
IEC61000-4-2
VCONN2

Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

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 EZ-PD™ CCG2 Datasheet

Device Level Specifications

All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.

Table 2. DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.PWR#1 VDDD Power supply input voltage 2.7 – 5.5 V UFP Applications
SID.PWR#1_A VDDD Power supply input voltage 3.0 – 5.5 V DFP/DRP Applications
SID.PWR#23 VCONN1 Power supply input voltage 4.0 – 5.5 V –
SID.PWR#23_A VCONN2 Power supply input voltage 4.0 – 5.5 V –
SID.PWR#13 VDDIO GPIO power supply 1.71 – 5.5 V –
SID.PWR#24 VCCD Output voltage (for core logic) – 1.8 – V –
External regulator voltage bypass on
SID.PWR#15 CEFC 1 1.3 1.6 µF X5R ceramic or better
VCCD
Power supply decoupling capacitor
SID.PWR#16 CEXC – 1 – µF X5R ceramic or better
on VDDD
Power Supply Decoupling Capacitor
SID.PWR#25 – 0.1 – µF X5R ceramic or better
on VCONN1 and VCONN2
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
VCONN1 or VCONN2 = 5 V,
TA = 25 °C,
SID.PWR#12 IDD12 Supply current – 7.5 – mA CC I/O IN Transmit or
Receive, RA disconnected,
no I/O sourcing current, CPU
at 12 MHz
Sleep Mode, VDDD = 2.7 to 5.5 V
VDDD = 3.3 V, TA = 25 °C, all
I2C wakeup. WDT ON. IMO at blocks except CPU are ON,
SID25A IDD20A – 2.0 3.0 mA
48 MHz CC I/O ON, no I/O sourcing
current
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
VCONN1, VCONN2 = 5 V,
TA = 25 °C.
RA termination disabled on
VCONN1 = 5.0, RA termination
SID_DS_RA IDD_DS_RA – 100 – µA VCONN1 and VCONN2, see
disabled
SID.PD.7.
VCONN leaker circuits
turned off during deep sleep
RA switch disabled on
VDDD = 2.7 to 3.6 V. I2C wakeup and
SID34 IDD29 – 50 – µA VCONN1 and VCONN2.
WDT ON
VDDD = 3.3 V, TA = 25 °C
Power source = VDDD,
Type-C not attached, CC
SID_DS IDD_DS VDDD = 2.7 to 3.6 V. CC wakeup ON – 2.5 – µA
enabled for wakeup, RP
disabled
XRES Current
SID307 IDD_XR Supply current while XRES asserted – 1 10 µA –

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 EZ-PD™ CCG2 Datasheet

Table 3. AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.CLK#4 FCPU CPU frequency DC – 48 MHz 3.0 V VDDD 5.5 V
Guaranteed by
SID.PWR#20 TSLEEP Wakeup from sleep mode – 0 – µs
characterization
24-MHz IMO.
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode – – 35 µs Guaranteed by charac-
terization
Guaranteed by
SID.XRES#5 TXRES External reset pulse width 5 – – µs
characterization
Power-up to “Ready to accept I2C / Guaranteed by
SYS.FES#1 T_PWR_RDY – 5 25 ms
CC command” characterization

I/O
Table 4. I/O DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.GIO#37 VIH[2] Input voltage HIGH threshold 0.7 × VDDIO – – V CMOS input
SID.GIO#38 VIL Input voltage LOW threshold – – 0.3 × VDDIO V CMOS input
SID.GIO#39 VIH[2] LVTTL input, VDDIO < 2.7 V 0.7× VDDIO – – V –
SID.GIO#40 VIL LVTTL input, VDDIO < 2.7 V – – 0.3 × VDDIO V –
SID.GIO#41 VIH[2] LVTTL input, VDDIO  2.7 V 2.0 – – V –
SID.GIO#42 VIL LVTTL input, VDDIO  2.7 V – – 0.8 V –
IOH = 4 mA at 3-V
SID.GIO#33 VOH Output voltage HIGH level VDDIO – 0.6 – – V
VDDIO
IOH = 1 mA at 1.8-V
SID.GIO#34 VOH Output voltage HIGH level VDDIO – 0.5 – – V
VDDIO
IOL = 4 mA at 1.8-V
SID.GIO#35 VOL Output voltage LOW level – – 0.6 V
VDDIO
SID.GIO#36 VOL Output voltage LOW level – – 0.6 V IOL = 8 mA at 3 V VDDIO
SID.GIO#5 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ –
SID.GIO#6 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ –
25 °C, VDDIO = 3.0
Input leakage current (absolute
SID.GIO#16 IIL – – 2 nA V.Guaranteed by
value)
characterization
Guaranteed by
SID.GIO#17 CIN Input capacitance – – 7 pF
characterization
VDDIO  2.7 V.
SID.GIO#43 VHYSTTL Input hysteresis LVTTL 25 40 – mV Guaranteed by
characterization.
Guaranteed by
SID.GPIO#44 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO – – mV
characterization
Current through protection diode to Guaranteed by
SID69 IDIODE – – 100 µA
VDDIO/Vss characterization
Maximum total source or sink chip Guaranteed by
SID.GIO#45 ITOT_GPIO – – 200 mA
current characterization

Note
2. VIH must not exceed VDDIO + 0.2 V.

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 EZ-PD™ CCG2 Datasheet

Table 5. I/O AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID70 TRISEF Rise time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF
SID71 TFALLF Fall time 2 – 12 ns 3.3-V VDDIO, Cload = 25 pF

XRES
Table 6. XRES DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

0.7 ×
SID.XRES#1 VIH Input voltage HIGH threshold – – V CMOS input
VDDIO
0.3 ×
SID.XRES#2 VIL Input voltage LOW threshold – – V CMOS input
VDDIO
Guaranteed by
SID.XRES#3 CIN Input capacitance – – 7 pF
characterization
0.05 ×
SID.XRES#4 VHYSXRES Input voltage hysteresis – – mV Guaranteed by characterization
VDDIO

Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 7. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Fc max = CLK_SYS. Maximum
SID.TCPWM.3 TCPWMFREQ Operating frequency – Fc – MHz
= 48 MHz.
SID.TCPWM.4 TPWMENEXT Input trigger pulse width – 2/Fc – ns For all Trigger Events
Minimum possible width of
Overflow, Underflow, and CC
SID.TCPWM.5 TPWMEXT Output trigger pulse width – 2/Fc – ns
(Counter equals Compare
value) outputs
Minimum time between
SID.TCPWM.5A TCRES Resolution of counter – 1/Fc – ns
successive counts
Minimum pulse width of PWM
SID.TCPWM.5B PWMRES PWM resolution – 1/Fc – ns
output
Minimum pulse width between
SID.TCPWM.5C QRES Quadrature inputs resolution – 1/Fc – ns
quadrature-phase inputs

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 EZ-PD™ CCG2 Datasheet

I2C
Table 8. Fixed I2C DC Specifications
(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID149 II2C1 Block current consumption at 100 kbps – – 60 µA –
SID150 II2C2 Block current consumption at 400 kbps – – 185 µA –
SID151 II2C3 Block current consumption at 1 Mbps – – 390 µA –
2
SID152 II2C4 I C enabled in Deep Sleep mode – – 1.4 µA –

Table 9. Fixed I2C AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate – – 1 Mbps –

Table 10. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

Block current consumption at Guaranteed by
SID160 IUART1 – – 125 µA
100 Kbps characterization
Block current consumption at Guaranteed by
SID161 IUART2 – – 312 µA
1000 Kbps characterization

Table 11. Fixed UART AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Guaranteed by
SID162 FUART Bit rate – – 1 Mbps
characterization

Table 12. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

Guaranteed by
SID163 ISPI1 Block current consumption at 1 Mbps – – 360 µA
characterization
Guaranteed by
SID164 ISPI2 Block current consumption at 4 Mbps – – 560 µA
characterization
Guaranteed by
SID165 ISPI3 Block current consumption at 8 Mbps – – 600 µA
characterization

Table 13. Fixed SPI AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SPI Operating frequency (Master; 6X Guaranteed by
SID166 FSPI – – 8 MHz
oversampling) characterization

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 EZ-PD™ CCG2 Datasheet

Table 14. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
MOSI Valid after SClock driving Guaranteed by
SID167 TDMO – – 15 ns
edge characterization
Full clock, late MISO
MISO Valid before SClock
SID168 TDSI 20 – – ns sampling. Guaranteed
capturing edge
by characterization
Referred to Slave
capturing edge.
SID169 THMO Previous MOSI data hold time 0 – – ns
Guaranteed by
characterization

Table 15. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
MOSI Valid before Sclock Guaranteed by
SID170 TDMI 40 – – ns
Capturing edge characterization
TCPU = 1/FCPU.
MISO Valid after Sclock driving
SID171 TDSO – – 42 + 3 * TCPU ns Guaranteed by
edge
characterization.
MISO Valid after Sclock driving Guaranteed by
SID171A TDSO_EXT – – 48 ns
edge in Ext Clk mode characterization
Guaranteed by
SID172 THSO Previous MISO data hold time 0 – – ns
characterization
Guaranteed by
SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 – – ns
characterization

Memory
Table 16. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Row (block) write time (erase and Row (block) =
SID.MEM#4 TROWWRITE[3] – – 20 ms
program) 128 bytes
SID.MEM#3 TROWERASE[3] Row erase time – – 13 ms –
SID.MEM#8 TROWPROGRAM[3] Row program time after erase – – 7 ms –
SID178 TBULKERASE[3] Bulk erase time (32 KB) – – 35 ms –
Guaranteed by
SID180 TDEVPROG[3] Total device program time – – 7.5 seconds
characterization
Guaranteed by
SID181 FEND Flash endurance 100 K – – cycles
characterization
Flash retention. TA  55 °C, 100 K Guaranteed by
SID182 FRET1 20 – – years
P/E cycles characterization
Flash retention. TA  85 °C, 10 K Guaranteed by
SID182A FRET2 10 – – years
P/E cycles characterization

Note
3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.

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 EZ-PD™ CCG2 Datasheet

System Resources
Power-on-Reset (POR) with Brown Out
Table 17. Imprecise Power On Reset (PRES)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Guaranteed by
SID185 VRISEIPOR Rising trip voltage 0.80 – 1.50 V
characterization
Guaranteed by
SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V
characterization

Table 18. Precise Power On Reset (POR)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
BOD trip voltage in active and Guaranteed by
SID190 VFALLPPOR 1.48 – 1.62 V
sleep modes characterization
Guaranteed by
SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.1 – 1.5 V
characterization

SWD Interface
Table 19. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SWDCLK ≤ 1/3 CPU
SID.SWD#1 F_SWDCLK1 3.3 V  VDDIO  5.5 V – – 14 MHz
clock frequency
SWDCLK ≤ 1/3 CPU
SID.SWD#2 F_SWDCLK2 1.8 V  VDDIO  3.3 V – – 7 MHz
clock frequency
Guaranteed by
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns
characterization
Guaranteed by
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – ns
characterization
Guaranteed by
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 * T ns
characterization
Guaranteed by
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns
characterization

Internal Main Oscillator

Table 20. IMO DC Specifications
(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID218 IIMO IMO operating current at 48 MHz – – 1000 µA –

Table 21. IMO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Frequency variation at 24, 36,
SID.CLK#13 FIMOTOL – – ±2 % –
and 48 MHz (trimmed)
Guaranteed by
SID226 TSTARTIMO IMO startup time – – 7 µs
characterization
Guaranteed by
SID229 TJITRMSIMO RMS jitter at 48 MHz – 145 – ps
characterization
FIMO – IMO frequency 24 – 48 MHz –

Document Number: 001-93912 Rev. *M Page 25 of 36

 EZ-PD™ CCG2 Datasheet

Internal Low-Speed Oscillator

Table 22. ILO DC Specifications
(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

Guaranteed by
SID231 IILO ILO operating current at 32 kHz – 0.3 1.05 µA
Characterization
SID233 IILOLEAK ILO leakage current – 2 15 nA Guaranteed by Design

Table 23. ILO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Guaranteed by
SID234 TSTARTILO ILO startup time – – 2 ms
characterization
Guaranteed by
SID236 TILODUTY ILO duty cycle 40 50 60 %
characterization
SID.CLK#5 FILO ILO Frequency 20 40 80 kHz –

Power Down
Table 24. PD DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
DFP CC termination for default
SID.PD.1 Rp_std 64 80 96 µA –
USB Power
DFP CC termination for 1.5A
SID.PD.2 Rp_1.5A 166 180 194 µA –
power
DFP CC termination for 3.0A
SID.PD.3 Rp_3.0A 304 330 356 µA –
power
SID.PD.4 Rd UFP CC termination 4.59 5.1 5.61 kΩ –
All supplies forced to 0 V
UFP Dead Battery CC termi-
SID.PD.5 Rd_DB 4.08 5.1 6.12 kΩ and 0.6 V applied at RD1
nation on RD1 and CC2
or CC2
All supplies forced to 0 V
SID.PD.6 RA Power cable termination 0.8 1.0 1.2 kΩ and 0.2 V applied at
VCONN1 or VCONN2
2.7 V applied at VCONN1
Power cable termination -
SID.PD.7 Ra_OFF 0.4 0.75 – MΩ or VCONN2 with RA
Disabled
disabled
SID.PD.8 Rleak_1 VCONN leaker for 0.1-µF load – – 216 kΩ
SID.PD.9 Rleak_2 VCONN leaker for 0.5-µF load – – 41.2 kΩ
SID.PD.10 Rleak_3 VCONN leaker for 1.0-µF load – – 19.6 kΩ Managed Active Cable
SID.PD.11 Rleak_4 VCONN leaker for 2.0-µF load – – 9.8 kΩ (MAC) discharge
SID.PD.12 Rleak_5 VCONN leaker for 5.0-µF load – – 4.1 kΩ
SID.PD.13 Rleak_6 VCONN leaker for 10-µF load – – 2.0 kΩ
Leaker on VCONN1 and VCONN2
SID.PD.14 Ileak 150 – – µA –
for discharge upon cable detach

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 EZ-PD™ CCG2 Datasheet

Analog-to-Digital Converter
Table 25. ADC DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.ADC.1 Resolution ADC resolution – 8 – bits Guaranteed by characterization
SID.ADC.2 INL Integral non-linearity –1.5 – 1.5 LSB Guaranteed by characterization
SID.ADC.3 DNL Differential non-linearity –2.5 – 2.5 LSB Guaranteed by characterization
SID.ADC.4 Gain Error Gain error –1 – 1 LSB Guaranteed by characterization

Table 26. ADC AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Rate of change of sampled voltage
SID.ADC.5 SLEW_Max – – 3 V/ms Guaranteed by characterization
signal

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 EZ-PD™ CCG2 Datasheet

Ordering Information
The EZ-PD CCG2 part numbers and features are listed in Table 27.
Table 27. EZ-PD CCG2 Ordering Information
Part Number Application Type-C Ports Termination Resistor Role Package
CYPD2103-20FNXIT Cable 1 RA[4] Cable 20-ball CSP
CYPD2103-14LHXIT Cable 1 RA[4] Cable 14-pin DFN
CYPD2104-20FNXIT Accessory 1 RD[5] Accessory 20-ball CSP
CYPD2105-20FNXIT Active Cable 1 RA[4] Active Cable 20-ball CSP
CYPD2119-24LQXIT C-DP 1 RD[5] UFP 24-pin QFN
CYPD2120-24LQXIT C-HDMI 1 RD[5] UFP 24-pin QFN
CYPD2121-24LQXIT Dock/Monitor Upstream port 1 RP , RD[5]
[6] DRP 24-pin QFN
CYPD2122-20FNXIT Tablet 1 RP[6], RD[5] DRP 20-ball CSP
CYPD2122-24LQXI Notebook 1 RP[6], RD[5] DRP 24-pin QFN
CYPD2122-24LQXIT Notebook 1 RP[6], RD[5] DRP 24-pin QFN
CYPD2125-24LQXIT Dock/Monitor Downstream port 1 RP[6] DFP 24-pin QFN
CYPD2134-24LQXIT DFP 1 RP[6] DFP 24-pin QFN
CYPD2134-24LQXQT DFP 1 RP[6] DFP 24-pin QFN

Ordering Code Definitions

CY PD 2 1 X X - XX XX X I T

T = Tape and Reel

Temperature Grade:
I = Industrial (40 °C to 85 °C), Q = Extended Industrial (40 °C to105 °C)
Pb-free
Package Type: XX = FN, LH or LQ
FN = CSP; LH = DFN; LQ = QFN
Number of pins in the package: XX = 14, 20, or 24
Device Role: Unique combination of role and termination:
X = 0 or 1 or 2 or 3 or 4 or 5 or 9
Feature: Unique Applications:
X = 0 or 1 or 2 or 3
Number of Type-C Ports: 1 = 1 Port
Product Type: 2 = Second-generation product family, CCG2
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress

Notes
4. Termination resistor denoting an EMCA.
5. Termination resistor denoting an accessory or upstream facing port.
6. Termination resistor denoting a downstream facing port.

Document Number: 001-93912 Rev. *M Page 28 of 36

 EZ-PD™ CCG2 Datasheet

Packaging
Table 28. Package Characteristics
Parameter Description Conditions Min Typ Max Units
Industrial 85 °C
TA Operating ambient temperature –40 25
Extended Industrial 105 °C
Industrial 100 °C
TJ Operating junction temperature –40 –
Extended Industrial 125 °C
TJA Package JA (20-ball WLCSP) – – 66 – °C/W
TJC Package JC (20-ball WLCSP) – – 0.7 – °C/W
TJA Package JA (14-pin DFN) – – 31 – °C/W
TJC Package JC (14-pin DFN) – – 59 – °C/W
TJA Package JA (24-pin QFN) – – 22 – °C/W
TJC Package JC (24-pin QFN) – – 29 – °C/W

Table 29. Solder Reflow Peak Temperature

Package Maximum Peak Temperature Maximum Time within 5 °C of Peak Temperature
20-ball WLCSP 260 °C 30 seconds
14-pin DFN 260 °C 30 seconds
24-pin QFN 260 °C 30 seconds

Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package MSL
20-ball WLCSP MSL 1
14-pin DFN MSL 3
24-pin QFN MSL 3

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 EZ-PD™ CCG2 Datasheet

Figure 17. 20-ball WLCSP (1.63 × 2.03 × 0.55 mm) FN20B Package Outline, 001-95010

001-95010 *B

Document Number: 001-93912 Rev. *M Page 30 of 36

 EZ-PD™ CCG2 Datasheet

Figure 18. 14-pin DFN (2.5 × 3.5 × 0.6 mm), LH14A, 0.95 × 3.00 E-Pad (Sawn) Package Outline, 001-96312

001-96312 **

Figure 19. 24-Pin QFN (4 × 4 × 0.55 mm), LQ24A, 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937

001-13937 *G

Document Number: 001-93912 Rev. *M Page 31 of 36

 EZ-PD™ CCG2 Datasheet

Acronyms Table 31. Acronyms Used in this Document (continued)

Table 31. Acronyms Used in this Document Acronym Description

NVIC nested vectored interrupt controller
Acronym Description
opamp operational amplifier
ADC analog-to-digital converter
OCP overcurrent protection
API application programming interface
OVP overvoltage protection
ARM® advanced RISC machine, a CPU architecture
PCB printed circuit board
CC configuration channel
PD power delivery
CCG2 Cable Controller Generation 2
PGA programmable gain amplifier
CPU central processing unit
PHY physical layer
cyclic redundancy check, an error-checking
CRC
protocol POR power-on reset
CS current sense PRES precise power-on reset
®
DFP downstream facing port PSoC Programmable System-on-Chip™
digital input/output, GPIO with only digital capabil- PWM pulse-width modulator
DIO
ities, no analog. See GPIO.
RAM random-access memory
DRP dual role port
RISC reduced-instruction-set computing
electrically erasable programmable read-only
EEPROM RMS root-mean-square
memory
RTC real-time clock
a USB cable that includes an IC that reports cable
EMCA characteristics (e.g., current rating) to the Type-C RX receive
ports
SAR successive approximation register
EMI electromagnetic interference
SCL I2C serial clock
ESD electrostatic discharge
SDA I2C serial data
FPB flash patch and breakpoint
S/H sample and hold
FS full-speed
Serial Peripheral Interface, a communications
SPI
GPIO general-purpose input/output protocol
IC integrated circuit SRAM static random access memory
IDE integrated development environment SWD serial wire debug, a test protocol
Inter-Integrated Circuit, a communications TX transmit
I2C, or IIC
protocol
a new standard with a slimmer USB connector and
ILO internal low-speed oscillator, see also IMO Type-C a reversible cable, capable of sourcing up to
100 W of power
IMO internal main oscillator, see also ILO
Universal Asynchronous Transmitter Receiver, a
I/O input/output, see also GPIO UART
communications protocol
LVD low-voltage detect
USB Universal Serial Bus
LVTTL low-voltage transistor-transistor logic
USB input/output, CCG2 pins used to connect to a
USBIO
MCU microcontroller unit USB port
NC no connect XRES external reset I/O pin
NMI nonmaskable interrupt

Document Number: 001-93912 Rev. *M Page 32 of 36

 EZ-PD™ CCG2 Datasheet

Document Conventions Table 32. Units of Measure (continued)

Symbol Unit of Measure
Units of Measure
µV microvolt
Table 32. Units of Measure
µW microwatt
Symbol Unit of Measure
mA milliampere
°C degrees Celsius
ms millisecond
Hz hertz
mV millivolt
KB 1024 bytes
nA nanoampere
kHz kilohertz
ns nanosecond
k kilo ohm
 ohm
Mbps megabits per second
pF picofarad
MHz megahertz
ppm parts per million
M mega-ohm
ps picosecond
Msps megasamples per second
s second
µA microampere
sps samples per second
µF microfarad
V volt
µs microsecond

Document Number: 001-93912 Rev. *M Page 33 of 36

 EZ-PD™ CCG2 Datasheet

References and Links To Applications Collaterals ■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
Knowledge Base Articles
■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
CCG4 - KBA210740 ■ AN210403 - Hardware Design Guidelines for Dual Role Port
Applications Using EZ-PD™ USB Type-C Controllers
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477 ■ AN210771 - Getting Started with EZ-PD™ CCG4
■ CCGX Frequently Asked Questions (FAQs) - KBA97244 Reference Designs
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560 ■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
■ Cypress EZ-PD™ CCGx Hardware - KBA204102 (EMCA) Paddle Card Reference Design
■ Difference between USB Type-C and USB-PD - KBA204033 ■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ CCGx Programming Methods - KBA97271 ■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Getting started with Cypress USB Type-C Products - ■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
KBA04071
■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ Type-C to DisplayPort Cable Electrical Requirements
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
■ Dead Battery Charging Implementation in USB Type-C Card Reference Design
Solutions - KBA97273
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
■ Termination Resistors Required for the USB Type-C Connector Reference Schematics
– KBA97180
■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■ VBUS Bypass Capacitor Recommendation for Type-C Cable
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270 ■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ Need for Regulator and Auxiliary Switch in Type-C to ■ CCG2 20W Power Adapter Reference Design
DisplayPort (DP) Cable Solution - KBA97274
■ CCG2 18W Power Adapter Reference Design
■ Need for a USB Billboard Device in Type-C Solutions –
KBA97146 ■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
Design Kit
■ CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies
– KBA97145 Kits
■ Cypress USB Type-C Controller Supported Solutions – ■ CY4501 CCG1 Development Kit
KBA97179
■ CY4502 EZ-PD™ CCG2 Development Kit
■ Termination Resistors for Type-C to Legacy Ports – KBA97272
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ Handling Instructions for CY4502 CCG2 Development Kit –
KBA97916 ■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Thunderbolt™ Cable Application Using CCG3 Devices - Datasheets
KBA210976
■ CCG1 Datasheet: USB Type-C Port Controller with Power
■ Power Adapter Application Using CCG3 Devices - KBA210975
Delivery
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
■ Device Flash Memory Size and Advantages - KBA210973 Controller on Type-C
■ Applications of EZ-PD™ CCG4 - KBA210739 ■ CCG3: USB Type-C Controller Datasheet
Application Notes ■ CCG4: Two-Port USB Type-C Controller Datasheet
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers

Document Number: 001-93912 Rev. *M Page 34 of 36

 EZ-PD™ CCG2 Datasheet

Document History Page

Description Title: EZ-PD™ CCG2 Datasheet USB Type-C Port Controller
Document Number: 001-93912
Orig. of Submission
Revision ECN Description of Change
Change Date
*E 4680071 GAYA 03/07/2015 Release to web
Added 24-pin QFN pin and package information.
*F 4718374 AKN 04/09/2015
Added DRP and DFP Application diagrams
Changed datasheet status from Preliminary to Final.
Updated Logic Block Diagram.
Changed number of GPIOs to 10 and added a note about the number of GPIOs
varying depending on the package.
*G 4774142 AKN 06/15/2015 Updated Power and Digital Peripherals section.
Updated Application diagrams.
Added SID.PWR#1_A parameter.
Added CYPD2122-20FNXIT part in Ordering Information.
Removed Errata.
Updated Figure 1 and Figure 5.
Added VCC_ABS spec and updated the SID.ADC.4 parameter.
*H 4979175 VGT 10/23/2015 Added “Guaranteed by characterization” note for the following specs:
SID.GIO#16, SID.GIO#17, SID.XRES#3, SID 160 to SID 172A, SID 2226, SID
229, SID.ADC.1 to SID.ADC.5.
Updated Application Diagrams:
Added Figure 14.
Added Figure 15.
*I 5028128 VGT 12/04/2015 Added Figure 16.
Updated Ordering Information.
Added part numbers CYPD2119-24LQXIT, CYPD2120-24LQXIT,
CYPD2121-24LQXIT, CYPD2125-24LQXIT.
Updated temperature ranges in Features.
*J 5186972 VGT 03/28/2016 Updated Table 28.
Updated Ordering Information.
Added Available Firmware and Software Tools.
Updated Figure 8: Per the USB PD3.0 spec, SOP” implementation is no longer
valid for passive cables.
Updated Figure 11, Figure 12, and Figure 13.
*K 5303957 VGT 06/13/2016
Added descriptive notes for the application diagrams.
Added References and Links To Applications Collaterals.
Updated Ordering Information.
Updated Cypress logo and copyright information.
*L 5387677 VGT 08/02/2016 Added CYPD2122-24LQXI part number in Ordering Information.
Added Figure 8 and Figure 10.
Updated the title of Figure 7 and Figure 9.
Added “Note: Application diagram in Figure 8 requires external diodes to
operate in the extended VCONN voltage range of 2.7V to 5.5V” in Application
*M 6097993 VGT 07/11/2018 Diagrams.
Updated Figure 17 (Spec 001-95010 from *A to *B).
Updated Figure 19 (Spec 001-13937 from *F to *G).
Added compliance to USB Specification.
Updated Cypress Logo and Copyright year.

Document Number: 001-93912 Rev. *M Page 35 of 36

 EZ-PD™ CCG2 Datasheet

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Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
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including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-93912 Rev. *M Revised July 11, 2018 Page 36 of 36