L5: Simple Sequential Circuits and Verilog

Acknowledgements: Nathan Ickes and Rex Min

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1

 Key Points from L4 (Sequential Blocks)
Classification:
„ Latch: level sensitive (positive latch passes input to output on high phase, hold
value on low phase)
„ Register: edge-triggered (positive register samples input on rising edge)
„ Flip-Flop: any element that has two stable states. Quite often Flip-flop also used
denote an (edge-triggered) register

D Q D Q Positive
Positive D Q D Q
Latch Register

Clk Clk

„ Latches are used to build Registers (using the Master-Slave Configuration), but
are almost NEVER used by itself in a standard digital design flow.
„ Quite often, latches are inserted in the design by mistake (e.g., an error in your
Verilog code). Make sure you understand the difference between the two.
„ Several types of memory elements (SR, JK, T, D). We will most commonly use
the D-Register, though you should understand how the different types are built
and their functionality.

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 The Sequential always Block

„ Edge-triggered circuits are described using a sequential

always block
Combinational Sequential
module combinational(a, b, sel, module sequential(a, b, sel,
out); clk, out);
input a, b; input a, b;
input sel; input sel, clk;
output out; output out;
reg out; reg out;
always @ (a or b or sel) always @ (posedge clk)
begin begin
if (sel) out = a; if (sel) out <= a;
else out = b; else out <= b;
end end
endmodule endmodule

a 1 a 1
out D Q out
b 0 b 0

sel sel clk

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 Importance of the Sensitivity List
„ The use of posedge and negedge makes an always block sequential
(edge-triggered)
„ Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!
D Flip-flop with synchronous clear D Flip-flop with asynchronous clear
module dff_sync_clear(d, clearb,
module dff_async_clear(d, clearb, clock, q);
clock, q);
input d, clearb, clock;
input d, clearb, clock; output q;
output q; reg q;
reg q;
always @ (posedge clock) always @ (negedge clearb or posedge clock)
begin begin
if (!clearb) q <= 1'b0; if (!clearb) q <= 1’b0;
else q <= d; else q <= d;
end end
endmodule
endmodule
always block entered only at always block entered immediately
each positive clock edge when (active-low) clearb is asserted
Note: The following is incorrect syntax: always @ (clear or negedge clock)
If one signal in the sensitivity list uses posedge/negedge, then all signals must.

ƒ Assign any signal or variable from only one always block, Be

wary of race conditions: always blocks execute in parallel
L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5
 Simulation

ƒ DFF with Synchronous Clear

tc-q
Clear on Clock Edge
ƒ DFF with Asynchronous Clear

Clear happens on falling edge of clearb

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6

 Blocking vs. Nonblocking Assignments
„ Verilog supports two types of assignments within always blocks, with
subtly different behaviors.
„ Blocking assignment: evaluation and assignment are immediate
always @ (a or b or c)
begin
x = a | b; 1. Evaluate a | b, assign result to x
y = a ^ b ^ c; 2. Evaluate a^b^c, assign result to y
z = b & ~c; 3. Evaluate b&(~c), assign result to z
end

„ Nonblocking assignment: all assignments deferred until all right-hand

sides have been evaluated (end of simulation timestep)
always @ (a or b or c)
begin
x <= a | b; 1. Evaluate a | b but defer assignment of x
y <= a ^ b ^ c; 2. Evaluate a^b^c but defer assignment of y
z <= b & ~c; 3. Evaluate b&(~c) but defer assignment of z
end 4. Assign x, y, and z with their new values

„ Sometimes, as above, both produce the same result. Sometimes, not!

L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7

 Assignment Styles for Sequential Logic

Flip-Flop Based q1 q2
in D Q D Q D Q out
Digital Delay
Line
clk

„ Will nonblocking and blocking assignments both produce

the desired result?
module nonblocking(in, clk, out); module blocking(in, clk, out);
input in, clk; input in, clk;
output out; output out;
reg q1, q2, out; reg q1, q2, out;
always @ (posedge clk) always @ (posedge clk)
begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end
endmodule endmodule

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 Use Nonblocking for Sequential Logic

always @ (posedge clk) always @ (posedge clk)

begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end

“At each rising clock edge, q1, q2, and out “At each rising clock edge, q1 = in.
simultaneously receive the old values of in, After that, q2 = q1 = in.
q1, and q2.” After that, out = q2 = q1 = in.
Therefore out = in.”

q1 q2 q1 q2
in D Q D Q D Q out in D Q out

clk clk

„ Blocking assignments do not reflect the intrinsic behavior of multi-stage

sequential logic
„ Guideline: use nonblocking assignments for sequential
always blocks
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 Simulation

ƒNon-blocking Simulation

ƒBlocking Simulation

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 Use Blocking for Combinational Logic
module blocking(a,b,c,x,y);
Blocking Behavior abc xy input a,b,c;
output x,y;
(Given) Initial Condition 110 11 a x reg x,y;
a changes;
b
always @ (a or b or c)
always block triggered 010 11 y begin
c x = a & b;
x = a & b; 010 01 y = x | c;
y = x | c; end
010 00
endmodule

Nonblocking Behavior abc xy Deferred module nonblocking(a,b,c,x,y);

input a,b,c;
(Given) Initial Condition 110 11 output x,y;
reg x,y;
a changes;
always block triggered 010 11 always @ (a or b or c)
begin
x <= a & b; 010 11 x<=0 x <= a & b;
y <= x | c;
y <= x | c; 010 11 x<=0, y<=1 end
Assignment completion 010 01 endmodule

„ Nonblocking and blocking assignments will synthesize correctly. Will both

styles simulate correctly?
„ Nonblocking assignments do not reflect the intrinsic behavior of multi-stage
combinational logic
„ While nonblocking assignments can be hacked to simulate correctly (expand
the sensitivity list), it’s not elegant
„ Guideline: use blocking assignments for combinational always blocks
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 The Asynchronous Ripple Counter
Count [3:0]
A simple counter architecture Count[0] Count[1] Count[2] Count[3]
† uses only registers
(e.g., 74HC393 uses T-register and D Q D Q D Q D Q
negative edge-clocking) Q Q Q Q
† Toggle rate fastest for the LSB
…but ripple architecture leads to
large skew between outputs Clock
D register set up to
always toggle: i.e., T
Register with T=1
Skew

Count [3]
Count [2]
Count [1]
Count [0]
Clock

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