A B C D E

1 1

Compal Confidential

/
/x
su
2 2

JALB0 Schematics Document

p.
om
AMD Griffin Processor with RS780M+SB700

yc
(With ATI MXM/B)

m
//
3 2008-4-16 3
p:

REV:1.0
tt
h

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 1 of 50
A B C D E
 A B C D E

Compal Confidential
Model Name : JALB0 Clock Generator Thermal Sensor
AMD S1G2 Processor Memory BUS(DDRII)
File Name: LA-4171P ICS9LPRS488B ADM1032
page 15 page 5 Dual Channel
1
200pin DDRII-SO-DIMM X2 1
uPGA-638 Package BANK 0, 1, 2, 3 page 8,9
1.8V DDRII 667/800
Fan Control
page 36
page 4,5,6,7

HDMI Conn. LCD Conn. CRT Conn. Hyper Transport Link

page 17 page 16 page 18 16 x 16

ATI RS780M

/
PCI-Express 16x

/x
MXM II VGA/B
page 14 BGA-528
PCI-Express 1x

su
2
page 10,11,12,13 USB Conn CMOS Bluetooth Finger 2

x4 Camera Conn Printer

port 0 port 1,2 port 3 port 4

p.
page 29 page 16 page 29 page 28
New Card MINI Card x2 LAN(GbE) A link
Card Reader
Socket B5764M Express2 USB port 0,7 USB port 5 USB port 9 USB port1
TV-Tuner WLAN JMB385

om
page 29 page 28 page 26 page 25
3.3V 48MHz USB
ATI SB700
5 in 1

yc
3.3V 24MHz HD Audio
RJ45
Socket
page 27 page 25 S-ATA
BGA-528

m
SPI
page 19,20,21,22,23

RTC CKT. BIOS ROM // MDC 1.5 HDA Codec Int. MIC
page 19
page 21 Conn
page 33
ALC888S
page 34 page 35
3
BTN/B Conn. LPC BUS SATA HDD SATA ODD 3

Digital/Analog MIC.
page 32
Conn. page 24 Conn.page 24
p:

Power On/Off CKT. port 0 port 1

page 32 ENE KB926 Audio AMP Mono AMP
LED/B Conn.
tt

(for Woofer)
page 32 page 30 page 34 page 35
DC/DC Interface CKT.
h

page 37
Media/B Conn. Touch Pad Int.KBD Phone Jack x3
page 32
page 31 page 31 page 34
Cable Dock Conn.
VGA, DVI, LAN, Audio, FUN/B Conn. CIR EC ROM
USB page 38 page 32 page 30 page 31

4 4
Power Circuit DC/DC USB/B Conn.
page 39,40,41
USB port 2, 4
42,43,44,45 page 28

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4181P
Date: Friday, April 18, 2008 Sheet 2 of 50
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A

1
+CPU_CORE_0 Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+CPU_CORE_1 Core voltage for CPU ON OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.05V switched power rail ON OFF OFF
Board ID / SKU ID Table for AD channel
+1.2V_HT 1.25V switched power rail ON OFF OFF
+NB_CORE 1.0V~1.1V switched power rail for NB VDDC ON OFF OFF
Vcc 3.3V +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
0 0 0 V 0 V 0 V
+2.5VS 2.5V for CPU_VDDA and MXM/B ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V

/
+3VALW 3.3V always on power rail ON ON ON*
+3V_LAN 3.3V power rail for LAN ON ON ON
3 33K +/- 5% 0.712 V 0.819 V 0.875 V

/x
+3VS 3.3V switched power rail ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON*
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V

su
2
+VSB VSB always on power rail ON ON ON* 2

+RTCVCC RTC power ON ON ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table BTO Option Table

p.
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
0 0.1 Discrete VGA@

om
Device IDSEL# REQ#/GNT# Interrupts
1 0.2 UMA UMA@
No PCI device * 2 0.3 0.4 1.0
3
4

yc
5
6
7

m
EC SM Bus1 address EC SM Bus2 address PROJECT ID Table
//
3 3
Device Address Device Address Board ID PROJECT
Smart Battery 0001 011X b ADI ADM1032 1001 100X b 0 JALB0
p:

EEPROM(24C16/02) 1010 000X b CPU SB 1001 101X b 1 JALC0

MXM GMT G781-1 1001 101X b 2
3
tt

4
SB700 SB700 5
h

SM Bus 0 address SM Bus 1 address 6

7
Device Address Device Address
New card
Clock Generator 1101 001Xb
(ICS9LPRS365) Lan

DDR DIMM0 1001 000Xb

DDR DIMM2 1001 010Xb

Minicard

4 Minicard 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4181P
Date: Friday, April 18, 2008 Sheet 3 of 50
A B C D E
 A B C D E

1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1
C535 C534 C520 C518 C516 C517

/
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10

/x
Near CPU Socket
+1.2V_HT +1.2V_HT
JCPU1A

su
2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
D2 AE3 C533 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

p.
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
L0_CADIN_H2 L0_CADOUT_H2

om
H_CADIN2 G2 AA1 H_CADON2
H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3
H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2

yc
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5

m
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
L0_CADIN_L11 L0_CADOUT_L11
H_CADIP12
H_CADIN12
K3
K4
L0_CADIN_H12
L0_CADIN_L12
L0_CADOUT_H12
L0_CADOUT_L12
Y5
W5
H_CADOP12
H_CADON12
//
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
p:

H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15

P5 L0_CADIN_L15 L0_CADOUT_L15 T3

10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10

10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
10 H_CLKIP1 J5 Y4 H_CLKOP1 10
tt

L0_CLKIN_H1 L0_CLKOUT_H1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10

10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10

10 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 10
h

10 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 10

10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10

6090022100G_B
Athlon 64 S1
Processor Socket

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 4 of 50
A B C D E
 A B C D E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH JCPU1C
9 DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] 8
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C244 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2

1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4

R79 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRB_SDQ6 D12 C13 DDRA_SDQ6
DDRA_CLK1 DDRB_SDQ7 MB_DATA6 MA_DATA6 DDRA_SDQ7
A13 MB_DATA7 MA_DATA7 E13
1 DDRB_SDQ8 A15 H15 DDRA_SDQ8
1

+MCH_REF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_50V7K
0.1U_0402_16V4Z

C178 DDRB_SDQ10 A19 E17 DDRA_SDQ10

MB_DATA10 MA_DATA10
2

1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11

2 MB_DATA11 MA_DATA11
C181

C189

R78 DDRA_CLK1# DDRB_SDQ12 C14 E14 DDRA_SDQ12

1K_0402_1% DDRB_SDQ13 MB_DATA12 MA_DATA12 DDRA_SDQ13
D14 MB_DATA13 MA_DATA13 F14
DDRB_SDQ14 C18 C17 DDRA_SDQ14
2 2 DDRB_CLK0 DDRB_SDQ15 MB_DATA14 MA_DATA14 DDRA_SDQ15
D18 G17
1

DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16

1 D20 MB_DATA16 MA_DATA16 G18
DDRB_SDQ17 A21 C19 DDRA_SDQ17
C509 DDRB_SDQ18 MB_DATA17 MA_DATA17 DDRA_SDQ18
D24 MB_DATA18 MA_DATA18 D22
1.5P_0402_50V9C DDRB_SDQ19 C25 E20 DDRA_SDQ19
DDRB_CLK0# 2 DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
MB_DATA21 MA_DATA21

/
DDRB_CLK1 DDRB_SDQ22 B24 B22 DDRA_SDQ22
DDRB_SDQ23 MB_DATA22 MA_DATA22 DDRA_SDQ23
1 C24 MB_DATA23 MA_DATA23 C23
DDRB_SDQ24 E23 F20 DDRA_SDQ24
C447 DDRB_SDQ25 MB_DATA24 MA_DATA24 DDRA_SDQ25

/x
E24 MB_DATA25 MA_DATA25 F22
1.5P_0402_50V9C DDRB_SDQ26 G25 H24 DDRA_SDQ26
DDRB_CLK1# 2 DDRB_SDQ27 MB_DATA26 MA_DATA26 DDRA_SDQ27
G26 MB_DATA27 MA_DATA27 J19
DDRB_SDQ28 C26 E21 DDRA_SDQ28
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 H22

su
JCPU1B DDRB_SDQ32 MB_DATA31 MA_DATA31 DDRA_SDQ32
AA24 MB_DATA32 MA_DATA32 Y24
2 DDRB_SDQ33 DDRA_SDQ33 2
AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDRB_SDQ34 AD24 AB22 DDRA_SDQ34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDRB_SDQ36 AA26 W22 DDRA_SDQ36
VTT3 VTT7 DDRB_SDQ37 MB_DATA36 MA_DATA36 DDRA_SDQ37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21

p.
R343 39.2_0402_1% A10 DDRB_SDQ38 AD26 Y22 DDRA_SDQ38
VTT9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
+1.8V 1 2 AE10 Y10 VTT_SENSE DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
MEMZN VTT_SENSE PAD T2 MB_DATA40 MA_DATA40
R352 39.2_0402_1% DDRB_SDQ41 AD22 AA20 DDRA_SDQ41
+MCH_REF DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
T5 PAD H16 RSVD_M1 MEMVREF W17 @ AE20 MB_DATA42 MA_DATA42 AA18

om
DDRB_SDQ43 AF20 AB18 DDRA_SDQ43
DDRA_ODT0 DDRB_SDQ44 MB_DATA43 MA_DATA43 DDRA_SDQ44
8 DDRA_ODT0 @ T19 MA0_ODT0 RSVD_M2 B18 PAD T17 AF24 MB_DATA44 MA_DATA44 AB21
DDRA_ODT1 V22 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
8 DDRA_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDRB_ODT0 @ DDRB_SDQ46 AC20 AD19 DDRA_SDQ46
MA1_ODT0 MB0_ODT0 DDRB_ODT0 9 MB_DATA46 MA_DATA46
V19 W23 DDRB_ODT1 DDRB_SDQ47 AD20 Y18 DDRA_SDQ47
MA1_ODT1 MB0_ODT1 DDRB_ODT1 9 MB_DATA47 MA_DATA47
Y26 DDRB_SDQ48 AD18 AD17 DDRA_SDQ48
DDRA_SCS0# MB1_ODT0 DDRB_SDQ49 MB_DATA48 MA_DATA48 DDRA_SDQ49
8 DDRA_SCS0# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDRA_SCS1# U19 V26 DDRB_SCS0# DDRB_SDQ50 AC14 W14 DDRA_SDQ50
8 DDRA_SCS1# MA0_CS_L1 MB0_CS_L0 DDRB_SCS0# 9 MB_DATA50 MA_DATA50

yc
U20 W25 DDRB_SCS1# DDRB_SDQ51 AD14 Y14 DDRA_SDQ51
MA1_CS_L0 MB0_CS_L1 DDRB_SCS1# 9 MB_DATA51 MA_DATA51
V20 U22 DDRB_SDQ52 AF19 Y17 DDRA_SDQ52
MA1_CS_L1 MB1_CS_L0 DDRB_SDQ53 MB_DATA52 MA_DATA52 DDRA_SDQ53
AC18 MB_DATA53 MA_DATA53 AB17
DDRA_CKE0 J22 J25 DDRB_CKE0 DDRB_SDQ54 AF16 AB15 DDRA_SDQ54
8 DDRA_CKE0 MA_CKE0 MB_CKE0 DDRB_CKE0 9 MB_DATA54 MA_DATA54
DDRA_CKE1 J20 H26 DDRB_CKE1 DDRB_SDQ55 AF15 AD15 DDRA_SDQ55
8 DDRA_CKE1 MA_CKE1 MB_CKE1 DDRB_CKE1 9 MB_DATA55 MA_DATA55
DDRB_SDQ56 AF13 AB13 DDRA_SDQ56
MB_DATA56 MA_DATA56

m
N19 P22 DDRB_SDQ57 AC12 AD13 DDRA_SDQ57
MA_CLK_H0 MB_CLK_H0 DDRB_SDQ58 MB_DATA57 MA_DATA57 DDRA_SDQ58
N20 MA_CLK_L0 MB_CLK_L0 R22 AB11 MB_DATA58 MA_DATA58 Y12
DDRA_CLK0 E16 A17 DDRB_CLK0 DDRB_SDQ59 Y11 W11 DDRA_SDQ59
8 DDRA_CLK0 MA_CLK_H1 MB_CLK_H1 DDRB_CLK0 9 MB_DATA59 MA_DATA59
DDRA_CLK0# F16 A18 DDRB_CLK0# DDRB_SDQ60 AE14 AB14 DDRA_SDQ60
8 DDRA_CLK0# MA_CLK_L1 MB_CLK_L1 DDRB_CLK0# 9 MB_DATA60 MA_DATA60
DDRA_CLK1 Y16 AF18 DDRB_CLK1 DDRB_SDQ61 AF14 AA14 DDRA_SDQ61
8 DDRA_CLK1 MA_CLK_H2 MB_CLK_H2 DDRB_CLK1 9 MB_DATA61 MA_DATA61
8 DDRA_CLK1#
DDRA_CLK1# AA16
P19
MA_CLK_L2
MA_CLK_H3
MB_CLK_L2
MB_CLK_H3
AF17
R26
DDRB_CLK1#
// DDRB_CLK1# 9
DDRB_SDQ62
DDRB_SDQ63
AF11
AD11
MB_DATA62
MB_DATA63
MA_DATA62
MA_DATA63
AB12
AA12
DDRA_SDQ62
DDRA_SDQ63
P20 MA_CLK_L3 MB_CLK_L3 R25 9 DDRB_SDM[7..0] DDRA_SDM[7..0] 8
3 DDRB_SDM0 DDRA_SDM0 3
8 DDRA_SMA[15..0] DDRB_SMA[15..0] 9 A12 MB_DM0 MA_DM0 E12
DDRA_SMA0 N21 P24 DDRB_SMA0 DDRB_SDM1 B16 C15 DDRA_SDM1
DDRA_SMA1 MA_ADD0 MB_ADD0 DDRB_SMA1 DDRB_SDM2 MB_DM1 MA_DM1 DDRA_SDM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDRA_SMA2 N22 P26 DDRB_SMA2 DDRB_SDM3 E25 F24 DDRA_SDM3
p:

DDRA_SMA3 MA_ADD2 MB_ADD2 DDRB_SMA3 DDRB_SDM4 MB_DM3 MA_DM3 DDRA_SDM4

M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDRA_SMA4 M22 N26 DDRB_SMA4 DDRB_SDM5 AE22 Y19 DDRA_SDM5
DDRA_SMA5 MA_ADD4 MB_ADD4 DDRB_SMA5 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDRA_SMA6 M24 N25 DDRB_SMA6 DDRB_SDM7 AD12 Y13 DDRA_SDM7
DDRA_SMA7 MA_ADD6 MB_ADD6 DDRB_SMA7 MB_DM7 MA_DM7
L21 L24
tt

DDRA_SMA8 MA_ADD7 MB_ADD7 DDRB_SMA8 DDRB_SDQS0 DDRA_SDQS0

L19 MA_ADD8 MB_ADD8 M26 9 DDRB_SDQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDRA_SDQS0 8
DDRA_SMA9 K22 K26 DDRB_SMA9 DDRB_SDQS0# B12 H13 DDRA_SDQS0#
MA_ADD9 MB_ADD9 9 DDRB_SDQS0# MB_DQS_L0 MA_DQS_L0 DDRA_SDQS0# 8
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQS1 D16 G16 DDRA_SDQS1
MA_ADD10 MB_ADD10 9 DDRB_SDQS1 MB_DQS_H1 MA_DQS_H1 DDRA_SDQS1 8
DDRA_SMA11 L22 L26 DDRB_SMA11 DDRB_SDQS1# C16 G15 DDRA_SDQS1#
MA_ADD11 MB_ADD11 9 DDRB_SDQS1# MB_DQS_L1 MA_DQS_L1 DDRA_SDQS1# 8
h

DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQS2 A24 C22 DDRA_SDQS2

MA_ADD12 MB_ADD12 9 DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 8
DDRA_SMA13 V24 W24 DDRB_SMA13 DDRB_SDQS2# A23 C21 DDRA_SDQS2#
MA_ADD13 MB_ADD13 9 DDRB_SDQS2# MB_DQS_L2 MA_DQS_L2 DDRA_SDQS2# 8
DDRA_SMA14 K24 J23 DDRB_SMA14 DDRB_SDQS3 F26 G22 DDRA_SDQS3
MA_ADD14 MB_ADD14 9 DDRB_SDQS3 MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3 8
DDRA_SMA15 K19 J24 DDRB_SMA15 DDRB_SDQS3# E26 G21 DDRA_SDQS3#
MA_ADD15 MB_ADD15 9 DDRB_SDQS3# MB_DQS_L3 MA_DQS_L3 DDRA_SDQS3# 8
DDRB_SDQS4 AC25 AD23 DDRA_SDQS4
9 DDRB_SDQS4 MB_DQS_H4 MA_DQS_H4 DDRA_SDQS4 8
DDRA_SBS0# R20 R24 DDRB_SBS0# DDRB_SDQS4# AC26 AC23 DDRA_SDQS4#
8 DDRA_SBS0# MA_BANK0 MB_BANK0 DDRB_SBS0# 9 9 DDRB_SDQS4# MB_DQS_L4 MA_DQS_L4 DDRA_SDQS4# 8
DDRA_SBS1# R23 U26 DDRB_SBS1# DDRB_SDQS5 AF21 AB19 DDRA_SDQS5
8 DDRA_SBS1# MA_BANK1 MB_BANK1 DDRB_SBS1# 9 9 DDRB_SDQS5 MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5 8
DDRA_SBS2# J21 J26 DDRB_SBS2# DDRB_SDQS5# AF22 AB20 DDRA_SDQS5#
8 DDRA_SBS2# MA_BANK2 MB_BANK2 DDRB_SBS2# 9 9 DDRB_SDQS5# MB_DQS_L5 MA_DQS_L5 DDRA_SDQS5# 8
DDRB_SDQS6 AE16 Y15 DDRA_SDQS6
9 DDRB_SDQS6 MB_DQS_H6 MA_DQS_H6 DDRA_SDQS6 8
DDRA_SRAS# R19 U25 DDRB_SRAS# DDRB_SDQS6# AD16 W15 DDRA_SDQS6#
8 DDRA_SRAS# MA_RAS_L MB_RAS_L DDRB_SRAS# 9 9 DDRB_SDQS6# MB_DQS_L6 MA_DQS_L6 DDRA_SDQS6# 8
DDRA_SCAS# T22 U24 DDRB_SCAS# DDRB_SDQS7 AF12 W12 DDRA_SDQS7
8 DDRA_SCAS# MA_CAS_L MB_CAS_L DDRB_SCAS# 9 9 DDRB_SDQS7 MB_DQS_H7 MA_DQS_H7 DDRA_SDQS7 8
DDRA_SWE# T24 U23 DDRB_SWE# DDRB_SDQS7# AE12 W13 DDRA_SDQS7#
8 DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# 9 9 DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# 8

Athlon 64 S1 6090022100G_B Athlon 64 S1

Processor Processor Socket
Socket

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 5 of 50
A B C D E
 A B C D E

+2.5VDDA
VDDA=300mA
L33
+2.5VS 1 2 3300P_0402_50V7K
A:Need to re-Link "SGN00000200" 1 FBM_L11_201209_300L_0805
1 1 1 +1.8V 1 2
+ C282 R364 10K_0402_5%
4.7U_0805_10V4Z C264 C255 C261 1 2
150U_D2_6.3VM 0.22U_0603_16V4Z R358 300_0402_5%
2 2 2 2

2
B
1 R335 2
MAINPWON 40,41
<BOM Structure> Q32 @ 0_0402_5%
JCPU1D

E
1 CPU_THERMTRIP#_R R334 2 1
3 1 1 H_THERMTRIP# 20

C
0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 VDDA2 KEY2 W18

1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC

15 CLK_CPU_BCLK CLKIN_H SVC CPU_SVC 46
C531 CPU_CLKIN_SC_N A8 A4 CPU_SVD
CLKIN_L SVD CPU_SVD 46

1
+1.8V 1 2
LDT_RST# B7 R357 300_0402_5%
R409 H_PWRGD RESET_L
A7 PWROK
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R
LDTSTOP_L THERMTRIP_L R353
CPU_LDT_REQ# C6 AC7 H_PROCHOT#
11 CPU_LDT_REQ#

2
LDTREQ_L PROCHOT_L CPU_MEMHOT#_1.8V H_PROCHOT# R370 2
15 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 +1.8V 1 H_PROCHOT# 19
C532 3900P_0402_50V7K CPU_SIC AF4 0_0402_5%
CPU_SID SIC
Address:100_1100 AF5 SID 300_0402_5%
+1.8VS 1 @ 2 AE6 W7 THERMDC_CPU
+1.8V ALERT_L THERMDC
Place close to CPU wihtin 1.5" R356 1K_0402_5% W8 THERMDA_CPU
R82 THERMDA
1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
2

R86 1 2 44.2_0402_1% CPU_HTREF1 P6

R420
+1.2V_HT HT_REF1 +1.8V sense no support
T30
T29
300_0402_5% 46 CPU_VDD0_FB_H CPU_VDD0_FB_H F6 W9 @ PAD +CPU_CORE_NB
VDD0_FB_H VDDIO_FB_H

/
46 CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9 @ PAD
+CPU_CORE_0 VDD0_FB_L VDDIO_FB_L R101 10_0402_5%
1

LDT_RST# R92 10_0402_5% 46 CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H CPU_VDDNB_FB_H 1 2

19 LDT_RST# VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_H 46
2CPU_VDD0_FB_H CPU_VDD1_FB_L AB6 CPU_VDDNB_FB_L CPU_VDDNB_FB_L

/x
1 46 CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_FB_L 46 1 2
1 1 2CPU_VDD0_FB_L R106 10_0402_5%
C554 R95 10_0402_5% CPU_DBRDY G10
0.01U_0402_16V7K CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10 Close to CPU
@ CPU_TCK AC9
2 CPU_TRST# TCK CPU_TDO
AD9 TRST_L TDO AE9
Close to CPU CPU_TDI AF9

su
TDI
2 T10 PAD CPU_TEST23_TSTUPD CPU_TEST28_H_PLLCHRZ_P 2
AD7 TEST23 TEST28_H J7 PAD T3 route as differential
+CPU_CORE_1 @ H8 CPU_TEST28_L_PLLCHRZ_N as short as possible
+1.8VS TEST28_L PAD T4
R80 10_0402_5% @ @ CPU_TEST18_PLLTEST1 H10 @ testpoint under package
T27 PAD TEST18
1 2CPU_VDD1_FB_H T28 PAD
CPU_TEST19_PLLTEST0 G9
TEST19 TEST17 D7 CPU_TEST17_BP3
PAD @T16
1 2CPU_VDD1_FB_L TEST16 E7 CPU_TEST16_BP2
PAD T7
2

p.
1@ R108 2 510_0402_5% E9 F7 CPU_TEST15_BP1 @ +1.8V
+1.8V TEST25_H TEST15 PAD T6
R419 R81 10_0402_5% 1@ R107 2 510_0402_5% E8 C7 CPU_TEST14_BP0 @ 0718 AMD --> 1K ohm
TEST25_L TEST14 PAD T9
300_0402_5% @ @
@ CPU_TEST21_SCANEN AB8 C3 @ CPU_SVC 1 2
T21 PAD TEST21 TEST7
@ CPU_TEST20_SCANCLK2 AF7 K8 CPU_SVD R415 1 1K_0402_5%
2
T22 PAD
1

TEST20 TEST10

om
H_PWRGD @ CPU_TEST24_SCANCLK1 AE7 R416 1K_0402_5%
19 H_PWRGD T23 PAD TEST24
@ CPU_TEST22_SCANSHIFTEN AE8 C4
T24 PAD TEST22 TEST8
1 @ CPU_TEST12_SCANSHIFTENB AC8
T25 PAD TEST12
C553 CPU_TEST27_SINGLECHAIN AF8
T26 PAD TEST27
0.01U_0402_16V7K C9 CPU_TEST29_H_FBCLKOUT_P
TEST29_H PAD T8
@ 1 R418 2 0_0402_5% C2 C8 CPU_TEST29_L_FBCLKOUT_N CPU_TEST21_SCANEN 1 2
2 TEST9 TEST29_L PAD T15
AA6 @ CPU_TEST24_SCANCLK1 R5381 2300_0402_5%
TEST6 R539 300_0402_5%
@

yc
A3 RSVD1 RSVD10 H18
A5 RSVD2 RSVD9 H19
B3 RSVD3 RSVD8 AA7
+1.8VS B5 D5
RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
2

m
JP29
R113 6090022100G_B 1
CPU_DBREQ# 1
300_0402_5% 2 2
CPU internal thermal sensor CPU_DBRDY 3 3
CPU_TCK 4
1

4
11,19 LDT_STOP#
LDT_STOP#
@
// CPU_TMS
CPU_TDI
5
6
5
6
1 1 2 CPU_TRST# 7
3 C245 CPU_TDO
7 3
8 8
0.01U_0402_16V7K C436 0.1U_0402_16V4Z HDT_RST# 9
@ 9
R351 10 10
2 R360 11
p:

@ @ GND
+3VS 2 1 2 1 12 GND
2.09V for Gate
20K_0402_5% 34.8K_0402_1%~N ACES_85201-1005N
@
1 2 ICH_SMBDATA1 20,26,29
tt

+1.8V 2 1 R566 @ 0_0402_5%

2
G

R361 2.2K_0402_5%
+1.8V
20 CPU_SID_SB 1 2CPU_SID 3 1 1 2 EC_SMB_DA1 14,30,40
h

R564 @ 0_0402_5% R567 @ 0_0402_5%

S

220_0402_5%R112

220_0402_5%R115

220_0402_5%R118

220_0402_5%R119

300_0402_5%R129
Q31 @ FDV301N_NL_SOT23-3
HDT Connector

1
+1.8V 2 1 1 2 JP1
ICH_SMBCLK1 20,26,29
2
G

R365 2.2K_0402_5% R568 @ 0_0402_5%

1 2

2
3 4
20 CPU_SIC_SB 1 2CPU_SIC 3 1 1 2 EC_SMB_CK1 14,30,40 5 6
R565 @ 0_0402_5% R569 @ 0_0402_5% @ @ @ @ R93
S

CPU_DBREQ# 1 2
+3VS Q30 CPU_DBRDY 7 8 0_0402_5%
@ FDV301N_NL_SOT23-3 CPU_TCK
9 10
11 12 +3VS
FDV301N, the Vgs is: CPU_TMS
13 14
EC is PU to 5VALW CPU_TDI
min = 0.65V 15 16
0.1U_0402_16V4Z

1 CPU_TRST#
17 18

5
Typ = 0.85V CPU_TDO U8
C446 19 20 LDT_RST#
Max = 1.5V 2

P
21 22 HDT_RST# B
23 24 4 Y
2
26 A 1 SB_PWRGD 20,32

G
4 U27 4
NOTE: HDT TERMINATION IS REQUIRED
1 8 EC_SMB_CK2 @ NC7SZ08P5X_NL_SC70-5
EC_SMB_CK2 30,31 FOR REV. Ax SILICON ONLY.

3
VDD SCLK @ SAMTEC_ASP-68200-07
THERMDA_CPU 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 30,31
C449
1 2 THERMDC_CPU 3 6
2200P_0402_50V7K D- ALERT#
2200p change to 4 5
1000p for ADT7421
THERM# GND Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title
ADM1032ARMZ_MSOP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 CTRL
Address:100_1101 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 6 of 50
A B C D E
 A B C D E

JCPU1F

VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JCPU1E +CPU_CORE_1

AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C80 + C79 + C77 + C78 K12 T8 AC11 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 U9 AC21 L10
Near CPU Socket L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15 U11 AD6
VSS17
VSS18
VSS82
VSS83 L12
L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE_0 M10 V10 AE15 M9
+CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
C214 C225 C221 C224 1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C196 C200 C186 C201 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9

/
+CPU_CORE_0 H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8

/x
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C220 C217 C219 C195 C184 C179 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket

su
VDDIO10 VDDIO15 VSS43 VSS108
M25 VDDIO11 VDDIO14 P21 D13 VSS44 VSS109 T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
6090022100G_B D21 U8
Athlon 64 S1 VSS48 VSS113
D23 U10
VDDIO decoupling. VSS49 VSS114

p.
Processor Socket D25 U12
VSS50 VSS115
E4 VSS51 VSS116 U14
F2 U16
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2

om
+1.8V F15 V7
VSS55 VSS120
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C206 C226 C216 C230 C191 C182 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C198 C207 C223 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127

yc
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
6090022100G_B
Under CPU Socket Athlon 64 S1

m
Processor Socket

Between CPU Socket and DIMM

//
+1.8V +0.9V
3 3
Near Power Supply
1
C235
1
C234
1
C165
1
C166
VTT decoupling. 1
C: Change to NBO CAP
+ C281
1
C273
p:

0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_D2_4VM_R15 22U_0805_6.3V6M

2 2 2 2 2 2
tt

180PF Qt'y follow the distance between

+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V
h

1 1 1 1 1 1
C162 C163 C164 C237 C238 C239 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C141 C146 C144 C148 C174 C173 C172 C175
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 2 2 2 2 2 2 2 2
to follow AMD Layout
+1.8V
review recommand for
EMI Near CPU Socket Right side.
+0.9V
1 1
1 1 1 1
+ C233 + C218
C167 C168 C169 C170 220U_D2_4VM_R15
220U_D2_4VM_R15 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C541 C530 C514 C515 C528 C537 C540 C543
2 2 2 2 2 2 @ 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 C: Change to NBO CAP 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 7 of 50
A B C D E
 A B C D E

+1.8V +1.8V
RESERVE
JDIMM1
+V_DDR_MCH_REF 1 VREF VSS 2
DDRA_SDQ4
+V_DDR_MCH_REF BUFFER CIRCUIT
3 VSS DQ4 4
DDRA_SDQ0 5 6 DDRA_SDQ5
DDRA_SDQ1 DQ0 DQ5 DDRA_SDQ[0..63]
7 DQ1 VSS 8 DDRA_SDQ[0..63] 5
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 DDRA_SDM[0..7]
5 DDRA_SDQS0# 11 DQS0# VSS 12 DDRA_SDM[0..7] 5
DDRA_SDQS0 13 14 DDRA_SDQ6
1 5 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7 1
15 VSS DQ7 16
DDRA_SDQ2 17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ12 DDRA_SMA[0..15]
19 DQ3 DQ12 20 DDRA_SMA[0..15] 5
21 22 DDRA_SDQ13
DDRA_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRA_SDQ9 25 26 DDRA_SDM1 +0.9V +1.8V
DQ9 DM1 RP20
27 VSS VSS 28
DDRA_SDQS1# 29 30 DDRA_SMA6 1 8 1 2
5 DDRA_SDQS1# DQS1# CK0 DDRA_CLK0 5
DDRA_SDQS1 31 32 DDRA_SMA7 2 7 C187 0.1U_0402_16V4Z
5 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 5
33 34 DDRA_SMA11 3 6 1 2
DDRA_SDQ10 VSS VSS DDRA_SDQ14 DDRA_SMA15 C213 0.1U_0402_16V4Z
35 DQ10 DQ14 36 4 5
DDRA_SDQ11 37 38 DDRA_SDQ15
DQ11 DQ15 47_0804_8P4R_5%
39 VSS VSS 40
+1.8V RP23
DDRA_CKE0 8 1 1 2
41 42 DDRA_SBS2# 7 2 C194 0.1U_0402_16V4Z
VSS VSS

2
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SMA14 6 3 1 2
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 R148 DDRA_CKE1 C222 0.1U_0402_16V4Z
45 DQ17 DQ21 46 5 4
47 48 1K_0402_1%
DDRA_SDQS2# VSS VSS 47_0804_8P4R_5%
5 DDRA_SDQS2# 49 DQS2# NC 50
DDRA_SDQS2 51 52 DDRA_SDM2 RP17

1
5 DDRA_SDQS2 DQS2 DM2

/
53 54 +V_DDR_MCH_REF +V_DDR_MCH_REF DDRA_SBS1# 1 8 1 2
VSS VSS

1U_0402_6.3V4Z
DDRA_SDQ18 55 56 DDRA_SDQ22 DDRA_SMA0 2 7 C157 0.1U_0402_16V4Z
DQ18 DQ22

1000P_0402_50V7K
DDRA_SDQ19 57 58 DDRA_SDQ23 1 1 DDRA_SMA2 3 6 1 2
DQ19 DQ23

2
C257
DDRA_SMA4 C152 0.1U_0402_16V4Z

/x
59 VSS VSS 60 4 5

C256
DDRA_SDQ24 61 62 DDRA_SDQ28 R141
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29 1K_0402_1% 47_0804_8P4R_5%
63 DQ25 DQ29 64
2 2 RP18
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3# DDRA_SMA5 8 1 1 2

1
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 5 DDRA_SMA8 C190 0.1U_0402_16V4Z
69 NC DQS3 70 DDRA_SDQS3 5 7 2
71 72 DDRA_SMA9 6 3 1 2

su
DDRA_SDQ26 VSS VSS DDRA_SDQ30 DDRA_SMA12 C211 0.1U_0402_16V4Z
73 DQ26 DQ30 74 5 4
2 DDRA_SDQ27 DDRA_SDQ31 2
75 DQ27 DQ31 76
77 78 47_0804_8P4R_5%
DDRA_CKE0 VSS VSS DDRA_CKE1 RP15
5 DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 5
81 82 DDRA_SBS0# 8 1 1 2
VDD VDD DDRA_SMA15 DDRA_SMA10 C180 0.1U_0402_16V4Z
83 NC NC/A15 84 7 2

p.
DDRA_SBS2# 85 86 DDRA_SMA14 DDRA_SMA1 6 3 1 2
5 DDRA_SBS2# BA2 NC/A14
87 88 DDRA_SMA3 5 4 C199 0.1U_0402_16V4Z
DDRA_SMA12 VDD VDD DDRA_SMA11
89 A12 A11 90
DDRA_SMA9 91 92 DDRA_SMA7 47_0804_8P4R_5%
DDRA_SMA8 A9 A7 DDRA_SMA6 RP9
93 A8 A6 94

om
95 96 DDRA_SCS1# 8 1 1 2
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_ODT1 C161 0.1U_0402_16V4Z
97 A5 A4 98 7 2
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SWE# 6 3 1 2
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SCAS# C156 0.1U_0402_16V4Z
101 A1 A0 102 5 4
103 VDD VDD 104
DDRA_SMA10 105 106 DDRA_SBS1# 47_0804_8P4R_5%
A10/AP BA1 DDRA_SBS1# 5
DDRA_SBS0# 107 108 DDRA_SRAS# RP12
5 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 5
DDRA_SWE# 109 110 DDRA_SCS0# DDRA_SMA13 1 8 1 2
5 DDRA_SWE# WE# S0# DDRA_SCS0# 5

yc
111 112 DDRA_ODT0 2 7 C159 0.1U_0402_16V4Z
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SCS0#
5 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 5 3 6 1 2
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SRAS# 4 5 C154 0.1U_0402_16V4Z
5 DDRA_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 47_0804_8P4R_5%
5 DDRA_ODT1 NC/ODT1 NC
121 VSS VSS 122

m
DDRA_SDQ32 123 124 DDRA_SDQ36
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 DQ33 DQ37 126
127 VSS VSS 128
DDRA_SDQS4# 129 130 DDRA_SDM4
5 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4
5 DDRA_SDQS4 131 DQS4 VSS 132

DDRA_SDQ34
133
135
VSS
DQ34
DQ38
DQ39
134
136
DDRA_SDQ38
DDRA_SDQ39
//
DDRA_SDQ35 137 138
3 DQ35 VSS DDRA_SDQ44 3
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDRA_SDQS5#
p:

DDRA_SDM5 VSS DQS5# DDRA_SDQS5 DDRA_SDQS5# 5

147 DM5 DQS5 148 DDRA_SDQS5 5
149 VSS VSS 150
DDRA_SDQ42 151 152 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 DQ43 DQ47 154
155 156
tt

DDRA_SDQ48 VSS VSS DDRA_SDQ52

157 DQ48 DQ52 158
DDRA_SDQ49 159 160 DDRA_SDQ53
DQ49 DQ53
161 VSS VSS 162
163 NC,TEST CK1 164 DDRA_CLK1 5
h

165 VSS CK1# 166 DDRA_CLK1# 5

DDRA_SDQS6# 167 168
5 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
5 DDRA_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRA_SDQ50 173 174 DDRA_SDQ54
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRA_SDM7 185 186 DDRA_SDQS7#
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# 5
187 VSS DQS7 188 DDRA_SDQS7 5
DDRA_SDQ58 189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
ICH_SMBDATA0 VSS DQ63
9,15,17,20,28 ICH_SMBDATA0 195 SDA VSS 196
ICH_SMBCLK0 197 198 R314 1 2 10K_0402_5%
9,15,17,20,28 ICH_SMBCLK0 SCL SAO
+3VS 199 200 R315 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204
4 4
FOX_AS0A426-M2RN-7F
+3VS CONN@

1 1
C413 C414 DIMM1 REV H:5.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2008/04/16 2009/04/16 Title
2
4.7U_0805_10V4Z 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 8 of 50
A B C D E
 A B C D E

+1.8V +1.8V

JDIMM2 DDRB_SDQ[0..63]
DDRB_SDQ[0..63] 5
+V_DDR_MCH_REF 1 VREF VSS 2
3 4 DDRB_SDQ4 DDRB_SDM[0..7]
VSS DQ4 DDRB_SDM[0..7] 5 +1.8V
DDRB_SDQ0 5 6 DDRB_SDQ5 +0.9V
DDRB_SDQ1 DQ0 DQ5 RP14
7 DQ1 VSS 8
9 10 DDRB_SDM0 DDRB_SRAS# 1 8 2 1
DDRB_SDQS0# VSS DM0 DDRB_SMA[0..15] DDRB_SMA0 C185 0.1U_0402_16V4Z
5 DDRB_SDQS0# 11 DQS0# VSS 12 DDRB_SMA[0..15] 5 2 7
1 DDRB_SDQS0 DDRB_SDQ6 DDRB_SMA2 1
5 DDRB_SDQS0 13 DQS0 DQ6 14 3 6 1 2
15 16 DDRB_SDQ7 DDRB_SMA4 4 5 C176 0.1U_0402_16V4Z
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12 47_0804_8P4R_5%
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24 RP19
DDRB_SDQ9 DQ8 VSS DDRB_SDM1 DDRB_SMA6
25 DQ9 DM1 26 1 8 2 1
27 28 DDRB_SMA7 2 7 C188 0.1U_0402_16V4Z
DDRB_SDQS1# VSS VSS DDRB_SMA11
5 DDRB_SDQS1# 29 DQS1# CK0 30 DDRB_CLK0 5 3 6 1 2
DDRB_SDQS1 31 32 DDRB_SMA14 4 5 C193 0.1U_0402_16V4Z
5 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 5
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 47_0804_8P4R_5%
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 40 RP22
VSS VSS DDRB_CKE0 8 1 2 1
DDRB_SBS2# 7 2 C203 0.1U_0402_16V4Z
41 42 DDRB_SMA15 6 3 1 2
DDRB_SDQ16 VSS VSS DDRB_SDQ20 DDRB_CKE1 C215 0.1U_0402_16V4Z
43 DQ16 DQ20 44 5 4
DDRB_SDQ17 45 46 DDRB_SDQ21
DQ17 DQ21 47_0804_8P4R_5%
47 VSS VSS 48
DDRB_SDQS2# 49 50
5 DDRB_SDQS2# DQS2# NC

/
DDRB_SDQS2 51 52 DDRB_SDM2 RP21
5 DDRB_SDQS2 DQS2 DM2 DDRB_SMA8
53 VSS VSS 54 8 1 2 1
DDRB_SDQ18 55 56 DDRB_SDQ22 DDRB_SMA5 7 2 C205 0.1U_0402_16V4Z
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23 DDRB_SMA12

/x
57 DQ19 DQ23 58 6 3 1 2
59 60 DDRB_SMA9 5 4 C210 0.1U_0402_16V4Z
DDRB_SDQ24 VSS VSS DDRB_SDQ28
61 DQ24 DQ28 62
DDRB_SDQ25 63 64 DDRB_SDQ29 47_0804_8P4R_5%
DQ25 DQ29
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# RP16
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 5 DDRB_SBS0#
69 70 8 1 2 1

su
NC DQS3 DDRB_SDQS3 5 DDRB_SMA10 C204 0.1U_0402_16V4Z
71 VSS VSS 72 7 2
2 DDRB_SDQ26 DDRB_SDQ30 DDRB_SMA3 2
73 DQ26 DQ30 74 6 3 1 2
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_SMA1 5 4 C209 0.1U_0402_16V4Z
DQ27 DQ31
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1 47_0804_8P4R_5%
5 DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 5
81 VDD VDD 82

p.
83 84 DDRB_SMA15 RP10
DDRB_SBS2# NC NC/A15 DDRB_SMA14 DDRB_ODT1
5 DDRB_SBS2# 85 BA2 NC/A14 86 8 1 2 1
87 88 DDRB_SCS1# 7 2 C171 0.1U_0402_16V4Z
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_SWE#
89 A12 A11 90 6 3 1 2
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SCAS# 5 4 C153 0.1U_0402_16V4Z
A9 A7

om
DDRB_SMA8 93 94 DDRB_SMA6
A8 A6 47_0804_8P4R_5%
95 VDD VDD 96
DDRB_SMA5 97 98 DDRB_SMA4
DDRB_SMA3 A5 A4 DDRB_SMA2 RP11
99 A3 A2 100
DDRB_SMA1 101 102 DDRB_SMA0 DDRB_SMA13 1 8 2 1
A1 A0 DDRB_ODT0 C158 0.1U_0402_16V4Z
103 VDD VDD 104 2 7
DDRB_SMA10 105 106 DDRB_SBS1# DDRB_SCS0# 3 6 1 2
A10/AP BA1 DDRB_SBS1# 5
DDRB_SBS0# 107 108 DDRB_SRAS# DDRB_SBS1# 4 5 C160 0.1U_0402_16V4Z
5 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 5

yc
DDRB_SWE# 109 110 DDRB_SCS0#
5 DDRB_SWE# WE# S0# DDRB_SCS0# 5
111 112 47_0804_8P4R_5%
DDRB_SCAS# VDD VDD DDRB_ODT0
5 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 5
DDRB_SCS1# 115 116 DDRB_SMA13
5 DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120
5 DDRB_ODT1 NC/ODT1 NC

m
121 VSS VSS 122
DDRB_SDQ32 123 124 DDRB_SDQ36
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
125 DQ33 DQ37 126
127 VSS VSS 128
DDRB_SDQS4# 129 130 DDRB_SDM4
5 DDRB_SDQS4# DQS4# DM4
5 DDRB_SDQS4
DDRB_SDQS4 131
133
DQS4
VSS
VSS
DQ38
132
134 DDRB_SDQ38
//
DDRB_SDQ34 135 136 DDRB_SDQ39
3 DDRB_SDQ35 DQ34 DQ39 3
137 DQ35 VSS 138
139 140 DDRB_SDQ44
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
p:

DQ41 VSS DDRB_SDQS5#

145 VSS DQS5# 146 DDRB_SDQS5# 5
DDRB_SDM5 147 148 DDRB_SDQS5
DM5 DQS5 DDRB_SDQS5 5
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
153 154
tt

DQ43 DQ47
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 VSS VSS 162
h

163 NC,TEST CK1 164 DDRB_CLK1 5

165 VSS CK1# 166 DDRB_CLK1# 5
DDRB_SDQS6# 167 168
5 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6
5 DDRB_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRB_SDQ50 173 174 DDRB_SDQ54
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRB_SDQ56 179 180 DDRB_SDQ60
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 5
187 VSS DQS7 188 DDRB_SDQS7 5
DDRB_SDQ58 189 190
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
ICH_SMBDATA0 VSS DQ63
8,15,17,20,28 ICH_SMBDATA0 195 SDA VSS 196
ICH_SMBCLK0 197 198 R331 1 2 10K_0402_5% +3VS
8,15,17,20,28 ICH_SMBCLK0 SCL SAO
+3VS 199 200 R327 1 2 10K_0402_5%
4 VDDSPD SA1 4
201 GND GND 202

FOX_AS0A426-MARG-7F
CONN@

DIMM1 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 9 of 50
A B C D E
 A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
14 PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] 14
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
14 PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] 14

U25B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C451 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C450 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_GTX_C_MRX_P1
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
PCIE_MTX_GRX_P1
2
C467 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
A3 GFX_RX1P GFX_TX1P A4 2
PCIE_GTX_C_MRX_N1 B3 B4 PCIE_MTX_GRX_N1 C466 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
1 PCIE_GTX_C_MRX_P2 GFX_RX1N GFX_TX1N PCIE_MTX_GRX_P2 C453 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 2
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C452 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C469 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 2
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C468 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C455 1
G5 GFX_RX4P GFX_TX4P E2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 G6 E1 PCIE_MTX_GRX_N4 C454 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C471 1
H5 GFX_RX5P GFX_TX5P F4 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C470 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_P6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C457 1
J6 GFX_RX6P GFX_TX6P F1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 J5 F2 PCIE_MTX_GRX_N6 C456 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_GTX_C_MRX_P7 GFX_RX6N GFX_TX6N PCIE_MTX_GRX_P7 C473 1 PCIE_MTX_C_GRX_P7
J7 GFX_RX7P GFX_TX7P H4 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N7 J8 H3 PCIE_MTX_GRX_N7 C472 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8 C459 1 PCIE_MTX_C_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C458 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9 C475 1
M8 GFX_RX9P GFX_TX9P J2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 L8 J1 PCIE_MTX_GRX_N9 C474 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
GFX_RX9N GFX_TX9N

PCIE I/F GFX

PCIE_GTX_C_MRX_P10 P7 K4 PCIE_MTX_GRX_P10 C461 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C460 1 PCIE_MTX_C_GRX_N10
M7 GFX_RX10N GFX_TX10N K3 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P11 P5 K1 PCIE_MTX_GRX_P11 C477 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C476 1
M5 GFX_RX11N GFX_TX11N K2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 R8 M4 PCIE_MTX_GRX_P12 C463 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
GFX_RX12P GFX_TX12P

/
PCIE_GTX_C_MRX_N12 P8 M3 PCIE_MTX_GRX_N12 C462 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13 C479 1 PCIE_MTX_C_GRX_P13
R6 GFX_RX13P GFX_TX13P M1 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C478 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C465 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14

/x
P4 GFX_RX14P GFX_TX14P N2
PCIE_GTX_C_MRX_N14 P3 N1 PCIE_MTX_GRX_N14 C464 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_GTX_C_MRX_P15 GFX_RX14N GFX_TX14N PCIE_MTX_GRX_P15 C481 1
T4 GFX_RX15P GFX_TX15P P1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 T3 P2 PCIE_MTX_GRX_N15 C480 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GFX_RX15N GFX_TX15N
AE3 AC1 PCIE_ITX_PRX_P0 C18 1 2 0.1U_0402_16V7K
29 PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 29
AD4 AC2 PCIE_ITX_PRX_N0 C19 1 2 0.1U_0402_16V7K New Card

su
29 PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 29
AE2 AB4 PCIE_ITX_PRX_P1 C31 1 2 0.1U_0402_16V7K
2 28 PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 28 2
AD3 AB3 PCIE_ITX_PRX_N1 C30 1 2 0.1U_0402_16V7K TV Tuner
28 PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 28
AD1 AA2 PCIE_ITX_PRX_P2 C21 1 2 0.1U_0402_16V7K
28 PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 28
AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 C20 1 2 0.1U_0402_16V7K WLAN
28 PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 28
V5 Y1 PCIE_ITX_PRX_P3 C23 1 2 0.1U_0402_16V7K
26 PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 26
W6 Y2 PCIE_ITX_PRX_N3 C22 1 2 0.1U_0402_16V7K GLAN
26 PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 26

p.
U5 Y4 PCIE_ITX_PRX_P4 C33 1 2 0.1U_0402_16V7K
25 PCIE_PTX_C_IRX_P4 GPP_RX4P GPP_TX4P PCIE_ITX_C_PRX_P4 25 H_CADOP[0..15] H_CADIP[0..15]
U6 Y3 PCIE_ITX_PRX_N4 C32 1 2 0.1U_0402_16V7K Card Reader4
25 PCIE_PTX_C_IRX_N4 GPP_RX4N GPP_TX4N PCIE_ITX_C_PRX_N4 25 H_CADOP[0..15] H_CADIP[0..15] 4
U8 GPP_RX5P GPP_TX5P V1
U7 V2 H_CADON[0..15] H_CADIN[0..15]
GPP_RX5N GPP_TX5N 4 H_CADON[0..15] H_CADIN[0..15] 4

om
19 SB_RX0P AA8 AD7 SB_TX0P_C C271 1 2 0.1U_0402_16V7K
SB_RX0P SB_TX0P SB_TX0P 19
19 SB_RX0N Y8 AE7 SB_TX0N_C C268 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 19
19 SB_RX1P AA7 AE6 SB_TX1P_C C290 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 19
19 SB_RX1N Y7 AD6 SB_TX1N_C C295 1 2 0.1U_0402_16V7K U25A
SB_RX1N SB_TX1N SB_TX1N 19
19 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C263 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P 19 HT_RXCAD0P HT_TXCAD0P
19 SB_RX2N AA6 AC6 SB_TX2N_C C265 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N 19 HT_RXCAD0N HT_TXCAD0N
19 SB_RX3P W5 AD5 SB_TX3P_C C262 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P 19 HT_RXCAD1P HT_TXCAD1P
19 SB_RX3N Y5 AE5 SB_TX3N_C C260 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N 19 HT_RXCAD1N HT_TXCAD1N

yc
H_CADOP2 V25 F24 H_CADIP2
R33 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 1 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R31 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22

HYPER TRANSPORT CPU I/F

m
RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
P24 HT_RXCAD6N HT_TXCAD6N K25
DP0 H_CADOP7 N24 K23 H_CADIP7
HT_RXCAD7P HT_TXCAD7P
AUX0 and HPD0
// H_CADON7 N25 HT_RXCAD7N HT_TXCAD7N K22 H_CADIN7

H_CADOP8 AC24 F21 H_CADIP8

3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
p:

H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10

AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 J19
tt

H_CADOP13 HT_RXCAD12N HT_TXCAD12N H_CADIP13

V21 HT_RXCAD13P HT_TXCAD13P M19
H_CADON13 V20 L18 H_CADIN13
H_CADOP14 HT_RXCAD13N HT_TXCAD13N H_CADIP14
U20 HT_RXCAD14P HT_TXCAD14P M21
H_CADON14 U21 P21 H_CADIN14
HT_RXCAD14N HT_TXCAD14N
h

H_CADOP15 U19 P18 H_CADIP15

H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

4 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 4

4 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 4
4 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 4
4 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 4
H_CTLOP0 M22 M24 H_CTLIP0
4 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 4
H_CTLON0 M23 M25 H_CTLIN0
4 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 4
H_CTLOP1 R21 P19 H_CTLIP1
4 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 4
H_CTLON1 R20 R18 H_CTLIN1
4 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 4
1 R75 2 C23 B24 1 R76 2
HT_RXCALP HT_TXCALP
A24 HT_RXCALN HT_TXCALN B25
301_0402_1% 301_0402_1%
0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"
layout 1:2 layout 1:2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780-HT/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 10 of 50
A B C D E
 A B C D E

For RS780M A13 +3VS

L7 AVDD=100mA
1 2 GMCH_CRT_R 1 2 +AVDD1
R64 133_0402_1% FBM-L11-201209-300LMA30T_0805 1
1 2 GMCH_CRT_G
R63 150_0402_1% +1.8VS C75
1 GMCH_CRT_B L14 22U_0805_6.3V6M 1
1 2
R71 150_0402_1% +AVDD2 2
1 2
FBM-L11-201209-300LMA30T_0805 1
U25C
C106 F12 A22 GMCH_TXOUT0+ 16
+1.8VS 2.2U_0603_6.3V4Z AVDD1(NC) TXOUT_L0P(NC)
2
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 GMCH_TXOUT0- 16
F14 AVDDDI(NC) TXOUT_L1P(NC) A21 GMCH_TXOUT1+ 16
L12 G15 B21 GMCH_TXOUT1- 16
+AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 1 H15 AVDDQ(NC) TXOUT_L2P(NC) B20 GMCH_TXOUT2+ 16
+1.8VS +NB_HTPVDD FBM-L11-201209-300LMA30T_0805 H14 A20
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) GMCH_TXOUT2- 16
L10 C99 A19
2.2U_0603_6.3V4Z TXOUT_L3P(NC)
1 2 E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
MBK2012221YZF 0805 1 2

CRT/TVOUT
F17 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 GMCH_TZOUT0+ 16
C84 A18 GMCH_TZOUT0- 16
2.2U_0603_6.3V4Z GMCH_CRT_R TXOUT_U0N(NC)
18 GMCH_CRT_R G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17 GMCH_TZOUT1+ 16
2 +1.1VS G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 GMCH_TZOUT1- 16
L41 +NB_PLLVDD GMCH_CRT_G E18 D20
18 GMCH_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC) GMCH_TZOUT2+ 16
1 2 F18 GREENb(NC) TXOUT_U2N(NC) D21 GMCH_TZOUT2- 16
MBK2012221YZF 0805 1 GMCH_CRT_B E19 D18 L42
18 GMCH_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
F19 D19 +VDDLTP18 1 2 +1.8VS
BLUEb(NC) TXOUT_U3N(NC)

/
+1.8VS +VDDA18HTPLL C433 1 MBC1608121YZF_0603
L17 2.2U_0603_6.3V4Z GMCH_CRT_HSYNCA11 B16 GMCH_TXCLK+ 16
2 13,18 GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
1 2 GMCH_CRT_VSYNCB11 A16 GMCH_TXCLK- 16 C439
13,18 GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
MBK2012221YZF 0805 1 GMCH_CRT_CLK F8 2.2U_0603_6.3V4Z

/x
18 GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16 GMCH_TZCLK+ 16
GMCH_CRT_DATAE8 2
18 GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17 GMCH_TZCLK- 16
C118
2.2U_0603_6.3V4Z R59 1 2 715_0402_1% DAC_RSET G14 DAC_RSET(PWM_GPIO1)
2 +VDDLTP18 L46
VDDLTP18(NC) A13
+NB_PLLVDD +NB_PLLVDD A12 B13 +VDDLT18 1 2 +1.8VS
+NB_HTPVDD PLLVDD(NC) VSSLTP18(NC) MBC1608121YZF_0603
+NB_HTPVDD D14 1 1

su
PLLVDD18(NC)
B12 A15

LVTM
2 PLLVSS(NC) VDDLT18_1(NC) +VDDLT18 C442 C443 2
B15

PLL PWR
+1.8VS +VDDA18PCIEPLL VDDLT18_2(NC) 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
L6 2 2
VDDLT33_2(NC) B14
1 2 +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
MBK2012221YZF 0805 1 E7 C14
VDDA18PCIEPLL2 VSSLT1(VSS)

p.
VSSLT2(VSS) D15
C69 1 2 NB_RESET#
D8 C16
13,19,25,26,28,29,30 PLT_RST# SYSRESETb VSSLT3(VSS)
2.2U_0603_6.3V4Z NB_PWRGD_R
R319 0_0402_5% A10 C18
2 NB_LDTSTOP# POWERGOOD VSSLT4(VSS)
C10 LDTSTOPb VSSLT5(VSS) C20
NB_ALLOW_LDTSTOPC12 E20

PM
ALLOW_LDTSTOP VSSLT6(VSS)

om
VSSLT7(VSS) C22
15 CLK_NBHT C25 HT_REFCLKP
15 CLK_NBHT# C24 HT_REFCLKN

15 NB_OSC_14.318M E11 REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 1 UMA@ 2 GMCH_ENVDD 16
F7 R3301 20_0402_5% ENBKL 14,30
LVDS_BLON(PCE_RCALRP) R317 UMA@ 0_0402_5%
+1.1VS 1 2 1 2 15 CLK_NBGFX T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12

2
yc
R40 R34 T1
15 CLK_NBGFX# GFX_REFCLKN
4.7K_0402_5% 4.7K_0402_5% R328 R313
U1 1.27K_0402_1% 1.27K_0402_1%
GPP_REFCLKP
U2 GPP_REFCLKN UMA@ UMA@

1
15 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)

m
V3 R26 @ 10K_0402_5%
+3VS 15 CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN)
1 2
GMCH_LCD_CLK B9
16 GMCH_LCD_CLK I2C_CLK
GMCH_LCD_CLK GMCH_LCD_DATA
1
R325
2
4.7K_0402_5%
16 GMCH_LCD_DATA
GMCH_DDC_DATA
A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HDMI_DET 14,17
17 GMCH_DDC_DATA DDC_DATA0/AUX0N(NC) HPD(NC)
1
R329
2 GMCH_LCD_DATA
4.7K_0402_5%
17 GMCH_DDC_CLK
//
GMCH_DDC_CLK A8
B7
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 1 2 SUS_STAT# 20
A7 R316 0_0402_5% SUS_STAT_R# 13 Strap pin
3 GMCH_DDC_CLK DDC_DATA1/AUX1N(NC) 3
1 2 THERMALDIODE_P AE8 NB_THERMAL_DA 21
R3181 4.7K_0402_5%
2 GMCH_DDC_DATA Strap pin +3VS 2 1 B10 AD8 NB_THERMAL_DC 21 NB temp to SB
R323 4.7K_0402_5% R41 10K_0402_5% STRP_DATA THERMALDIODE_N
POWER_SEL G11 D13 1 2
p:

43 POWER_SEL RSVD TESTMODE

1 2 GMCH_CRT_CLK R359
R5111 4.7K_0402_5%
2 GMCH_CRT_DATA C8 1.8K_0402_5%
13 AUX_CAL AUX_CAL(NC)
R512 4.7K_0402_5%
Strap pin RS780M_FCBGA528
tt

+1.8VS +1.8VS +3VS

h

2
R540

2
300_0402_5%
+1.8VS +3VS R338 R534
+1.8VS +1.8VS 0_0402_5% 300_0402_5% @ 4.7K_0402_5%

1
6 CPU_LDT_REQ# 1 2
2

R414 @

21

1
G
R333 R324
300_0402_5% @ 4.7K_0402_5%
3 1 NB_ALLOW_LDTSTOP
19 ALLOW_LDTSTOP
2

2
G

FDV301N_NL_SOT23-3

D
1

Q56
3 1 NB_PWRGD_R 3 1 NB_LDTSTOP# @
20 NB_PWRGD 6,19 LDT_STOP#
FDV301N_NL_SOT23-3 FDV301N_NL_SOT23-3
S

Q29 Q28
@ @
R571
R570
R332 1 2
4 4
1 2
1 2 0_0402_5%
0_0402_5%
0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 11 of 50

A B C D E
 A B C D E

U25F
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L16 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
2A H19 VSSAHT7 VSSAPCIE7 G2
+1.1VS 2 1 +VDDHT J22 G4
VSSAHT8 VSSAPCIE8
FBMA-L11-201209-221LMA30T_0805
0.68A L17
L22
VSSAHT9 VSSAPCIE9 H7
J4
1 1 1 1 1 VSSAHT10 VSSAPCIE10
L5 L24 R7
C109 C116 C117 C121 C114 VSSAHT11 VSSAPCIE11
1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 2 U25E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z J17 A6 +VDDA11PCIE P20 L7
VDDHT_1 VDDPCIE_1 C35 22U_0805_6.3V6M VSSAHT15 VSSAPCIE15
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1.1A C34 22U_0805_6.3V6M
R19 VSSAHT16 VSSAPCIE16 M6
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L25 M16 D6 R24 P6
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C74 1U_0402_6.3V4Z VSSAHT18 VSSAPCIE18
2 1 2A P16 VDDHT_5 VDDPCIE_5 E6 1 2 R25 VSSAHT19 VSSAPCIE19 R1
C85 1U_0402_6.3V4Z
FBMA-L11-201209-221LMA30T_0805
0.68A R16
T16
VDDHT_6 VDDPCIE_6 F6
G7 C81
1
1
2
2 1U_0402_6.3V4Z
H20
U22
VSSAHT20 VSSAPCIE20 R2
R4
1 1 1 1 1 VDDHT_7 VDDPCIE_7 VSSAHT21 VSSAPCIE21
H8 C86 1 2 1U_0402_6.3V4Z V19 V7
C150 C131 C127 C147 C139 VDDPCIE_8 VSSAHT22 VSSAPCIE22

GROUND
H18 VDDHTRX_1 VDDPCIE_9 J9 W22 VSSAHT23 VSSAPCIE23 U4
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 W24 VSSAHT24 VSSAPCIE24 V8
2 2 2 2 2 C73
F20 VDDHTRX_3 VDDPCIE_11 M9 1 20.1U_0402_16V4Z W25 VSSAHT25 VSSAPCIE25 V6
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 C82 0.1U_0402_16V4Z Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2

/
B23 VDDHTRX_6 VDDPCIE_14 R9 VSSAPCIE28 W4
A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L21 V9 M14 W8
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30

/x
+1.2V_HT 2 1 2A AE25 VDDHTTX_1 VDDPCIE_17 U9 N13 VSS13 VSSAPCIE31 Y6
AD24 VDDHTTX_2 P12 VSS14 VSSAPCIE32 AA4
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 AC23 K12 +1.1VS L4 1 2 +NB_CORE P15 AB5
VDDHTTX_3 VDDC_1 FBMA-L11-201209-221LMA30T_0805 VSS15 VSSAPCIE33
AB22 VDDHTTX_4 VDDC_2 J14 R11 VSS16 VSSAPCIE34 AB1
C130 C123 C134 C136 C135 AA21 U16 L3 1 2 R14 AB7
VDDHTTX_5 VDDC_3 FBMA-L11-201209-221LMA30T_0805 VSS17 VSSAPCIE35
Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
2 2 2 2 2
W19 K15 U14 AC4

su
VDDHTTX_7 VDDC_5 VSS19 VSSAPCIE37

POWER
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z V18 M12 VDD_CORE=5A U11 AE1
2 VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38 2
U17
T17
VDDHTTX_9 VDDC_7 L14
L11
7.6A U15
V12
VSS21 VSSAPCIE39 AE4
AB2
VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

p.

330U_D2E_2.5VM
C101

C107

C94

C104

C112

C110

C97

C102

C103

C36

C38
L9 2A N14 1 AA14 D11
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8

C29
FBMA-L11-201209-221LMA30T_0805 +
0.6A P10
K10
VDDA18PCIE_2 VDDC_14 P13
P14
AB11
AB15
VSS28 VSS4 E14
E15
1 1 1 1 1 1 1 VDDA18PCIE_3 VDDC_15 VSS29 VSS5

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C72 M10 R12 AB17 J15
VDDA18PCIE_4 VDDC_16 VSS30 VSS6

om
22U_0805_6.3V6M C88 C92 C87 C91 C93 C89 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
22U_0805_6.3V6M W9 T11 AE20 K14
2 2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 K11 L15
VDDA18PCIE_8 VDDC_20 VSS34 VSS10
R10 VDDA18PCIE_9 VDDC_21 T14
22U_0805_6.3V6M Y9 J16 RS780M_FCBGA528
VDDA18PCIE_10 VDDC_22
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10

yc
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
0.64A F9
VDD_MEM5(NC) AB10
AC10
+1.8VS VDD18_1 VDD_MEM6(NC)
G9 VDD18_2

m
+1.8VS AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 +3VS
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12
1 1
1 1 RS780M_FCBGA528
C432 C95 C96
U25D
1U_0402_6.3V4Z C431
1U_0402_6.3V4Z
// 0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z
PAR 4 OF 6
2 2
@ AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
3 3
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 V17
p:

MEM_A4(NC) MEM_DQ4(NC)
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 AD19
tt

MEM_A9(NC) MEM_DQ9/DVO_D5(NC)

SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
h

MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18

RS780M_FCBGA528
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 12 of 50
A B C D E
 A B C D E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

11,18 GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC)
R46 3K_0402_5%
1 : Disable (RS780)
2 1
1 R45 @ 3K_0402_5% 0 : Enable (Rs780) 1

DFT_GPIO1: LOAD_EEPROM_STRAPS

11 AUX_CAL 1 2 Selects Loading of STRAPS from EPROM

@R320
@ R320 150_0402_1%
D17
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
@ CH751H-40_SC76 0 : I2C Master can load strap values from EEPROM if connected, or use

/
RS780 DFT_GPIO1 11 SUS_STAT_R# 2 1 PLT_RST# 11,19,25,26,28,29,30 default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

/x
su
2 2

p.
RS780 use HSYNC to enable SIDE PORT

RS780 use HSYNC to enable SIDE PORT RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)

om
2 1 1 : Disable(RS780)
11,18 GMCH_CRT_HSYNC +3VS
R340 3K_0402_5%
2 @ 1
R339 3K_0402_5%

yc
m
//
3 3
p:
tt
h

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 13 of 50
A B C D E
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
10 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
10 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
10 PCIE_GTX_C_MRX_N[0..15]
D PCIE_GTX_C_MRX_P[0..15] D
10 PCIE_GTX_C_MRX_P[0..15]

JMXM1A JMXM1B

+MXM_B+ 1 2 +1.8VS PCIE_GTX_C_MRX_N14 109 110

PWR_SRC 1V8RUN PCIE_GTX_C_MRX_P14 PEX_RX1# GND PCIE_MTX_C_GRX_N14
3 PWR_SRC 1V8RUN 4 111 PEX_RX1 PEX_TX1# 112
5 6 140mil(3.5A) 113 114 PCIE_MTX_C_GRX_P14
PWR_SRC 1V8RUN PCIE_GTX_C_MRX_N15 GND PEX_TX1
7 PWR_SRC 1V8RUN 8 115 PEX_RX0# GND 116
9 10 PCIE_GTX_C_MRX_P15 117 118 PCIE_MTX_C_GRX_N15
PWR_SRC 1V8RUN PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P15
11 PWR_SRC 1V8RUN 12 119 GND PEX_TX0 120
13 14 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN 15 CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
15 16 CLK_PCIE_VGA 123 124
PWR_SRC RUNPWROK VGA_ON 32 15 CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr
17 GND 5VRUN 18 +5VS 125 CLK_REQ# GND 126
19 GND GND 20 19 VGA_RST# 127 PEX_RST# TV_Y/HDTV_Y 128
21 22 20 HDA_SYNC_MXM HDA_SYNC_MXM 129 130
GND GND HDA_BCLK_MXM RSVD GND

/
23 GND GND 24 20 HDA_BCLK_MXM 131 RSVD TV_CVBS/HDTV_Pb 132
D_EC_SMB_DA1 133 134 R502 1 @ 2 1K_0402_5% HDA_RST#_MXM 20
D_EC_SMB_CK1 SMB_DAT GND VGA_CRT_R
135 SMB_CLK VGA_RED 136 VGA_CRT_R 18

/x
137 THERM# GND 138
18 VGA_CRT_HSYNC VGA_CRT_HSYNC 139 140 VGA_CRT_G VGA_CRT_G 18
VGA_CRT_VSYNC VGA_HSYNC VGA_GRN
18 VGA_CRT_VSYNC 141 VGA_VSYNC GND 142
18 VGA_DDC_CLK VGA_DDC_CLK 143 144 VGA_CRT_B VGA_CRT_B 18
PCIE_GTX_C_MRX_N0 VGA_DDC_DATA DDCA_CLK VGA_BLU
25 PEX_RX15# PRSNT2# 26 18 VGA_DDC_DATA 145 DDCA_DAT GND 146
PCIE_GTX_C_MRX_P0 27 28 PCIE_MTX_C_GRX_N0 20 HDA_SDI_MXM HDA_SDI_MXM 147 148 VGA_TZCLK- VGA_TZCLK- 16
PEX_RX15 PEX_TX15# IGP_UCLK# LVDS_UCLK#

su
29 30 PCIE_MTX_C_GRX_P0 20 HDA_SDO_MXM HDA_SDO_MXM 149 150 VGA_TZCLK+ VGA_TZCLK+ 16
C PCIE_GTX_C_MRX_N1 GND PEX_TX15 IGP_UCLK LVDS_UCLK C
31 PEX_RX14# GND 32 151 GND GND 152
PCIE_GTX_C_MRX_P1 33 34 PCIE_MTX_C_GRX_N1 153 154
PEX_RX14 PEX_TX14# PCIE_MTX_C_GRX_P1 +3VS RSVD LVDS_UTX3# R377 0_0402_5%
35 GND PEX_TX14 36 C668 155 RSVD LVDS_UTX3 156
PCIE_GTX_C_MRX_N2 37 38 @ 157 158 1 @ 2 SPDIF_HDMI 33
PCIE_GTX_C_MRX_P2 PEX_RX13# GND PCIE_MTX_C_GRX_N2 RSVD GND VGA_TZOUT2-
39 40 2 1 159 160

p.
PEX_RX13 PEX_TX13# IGP_UTX2# LVDS_UTX2# VGA_TZOUT2- 16
41 42 PCIE_MTX_C_GRX_P2 161 162 VGA_TZOUT2+ VGA_TZOUT2+ 16
GND PEX_TX13 IGP_UTX2 LVDS_UTX2

5
PCIE_GTX_C_MRX_N3 43 44 0.1U_0402_16V4Z U43 163 164
PCIE_GTX_C_MRX_P3 PEX_RX12# GND PCIE_MTX_C_GRX_N3 GND GND VGA_TZOUT1-
45 46 2 165 166

P
PEX_RX12 PEX_TX12# B IGP_UTX1# LVDS_UTX1# VGA_TZOUT1- 16
47 48 PCIE_MTX_C_GRX_P3 4 167 168 VGA_TZOUT1+ VGA_TZOUT1+ 16
GND PEX_TX12 Y IGP_UTX1 LVDS_UTX1

om
PCIE_GTX_C_MRX_N4 49 50 1 169 170
PEX_RX11# GND 21,30,31,37,39,42 ACIN A GND GND

G
PCIE_GTX_C_MRX_P4 51 52 PCIE_MTX_C_GRX_N4 @ 171 172 VGA_TZOUT0- VGA_TZOUT0- 16
PEX_RX11 PEX_TX11# PCIE_MTX_C_GRX_P4 IGP_UTX0# LVDS_UTX0# VGA_TZOUT0+
53 54 173 174 VGA_TZOUT0+ 16

3
PCIE_GTX_C_MRX_N5 GND PEX_TX11 NC7SZ08P5X_NL_SC70-5 IGP_UTX0 LVDS_UTX0
55 PEX_RX10# GND 56 175 GND GND 176
PCIE_GTX_C_MRX_P5 57 58 PCIE_MTX_C_GRX_N5 177 178 VGA_TXCLK- VGA_TXCLK- 16
PEX_RX10 PEX_TX10# PCIE_MTX_C_GRX_P5 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# VGA_TXCLK+
59 GND PEX_TX10 60 179 IGP_LCLK/DVI_B_CLK LVDS_LCLK 180 VGA_TXCLK+ 16
PCIE_GTX_C_MRX_N6 61 62 181 182
PCIE_GTX_C_MRX_P6 PEX_RX9# GND PCIE_MTX_C_GRX_N6 DVI_B_HPD/GND GND
63 64 183 184

yc
PEX_RX9 PEX_TX9# PCIE_MTX_C_GRX_P6 RSVD LVDS_LTX3#
65 GND PEX_TX9 66 185 RSVD LVDS_LTX3 186
PCIE_GTX_C_MRX_N7 67 68 187 188
PCIE_GTX_C_MRX_P7 PEX_RX8# GND PCIE_MTX_C_GRX_N7 GND GND VGA_TXOUT2-
69 PEX_RX8 PEX_TX8# 70 189 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# 190 VGA_TXOUT2- 16
71 72 PCIE_MTX_C_GRX_P7 191 192 VGA_TXOUT2+ VGA_TXOUT2+ 16
PCIE_GTX_C_MRX_N8 GND PEX_TX8 IGP_LTX2/DVI_B_TX2 LVDS_LTX2
73 74 193 194

m
PCIE_GTX_C_MRX_P8 PEX_RX7# GND PCIE_MTX_C_GRX_N8 GND GND VGA_TXOUT1-
75 PEX_RX7 PEX_TX7# 76 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 VGA_TXOUT1- 16
77 78 PCIE_MTX_C_GRX_P8 197 198 VGA_TXOUT1+ VGA_TXOUT1+ 16
PCIE_GTX_C_MRX_N9 GND PEX_TX7 IGP_LTX1/DVI_B_TX1 LVDS_LTX1
79 PEX_RX6# GND 80 199 GND GND 200
PCIE_GTX_C_MRX_P9 81 82 PCIE_MTX_C_GRX_N9 201 202 VGA_TXOUT0- VGA_TXOUT0- 16
PEX_RX6 PEX_TX6# PCIE_MTX_C_GRX_P9 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# VGA_TXOUT0+
PCIE_GTX_C_MRX_N10
83
85
GND
PEX_RX5#
PEX_TX6
GND
84
86
// 11,17 HDMI_DET
203
205
IGP_LTX0/DVI_B_TX0
DVI_A_HPD
LVDS_LTX0
GND
204
206
VGA_TXOUT0+ 16
PCIE_GTX_C_MRX_P10 87 88 PCIE_MTX_C_GRX_N10 17 VGA_DVI_TXC- VGA_DVI_TXC- 207 208 I2CC_SDA I2CC_SDA 16
B PEX_RX5 PEX_TX5# PCIE_MTX_C_GRX_P10 VGA_DVI_TXC+ DVI_A_CLK# DDCC_DAT I2CC_SCL B
89 GND PEX_TX5 90 17 VGA_DVI_TXC+ 209 DVI_A_CLK DDCC_CLK 210 I2CC_SCL 16
PCIE_GTX_C_MRX_N11 91 92 211 212 ENVDD
PEX_RX4# GND GND LVDS_PPEN ENVDD 16
PCIE_GTX_C_MRX_P11 93 94 PCIE_MTX_C_GRX_N11 17 VGA_DVI_TXD2- VGA_DVI_TXD2- 213 214
PEX_RX4 PEX_TX4# DVI_A_TX2# LVDS_BL_BRGHT
p:

95 96 PCIE_MTX_C_GRX_P11 17 VGA_DVI_TXD2+ VGA_DVI_TXD2+ 215 216 ENBKL

GND PEX_TX4 DVI_A_TX2 LVDS_BLEN ENBKL 11,30
PCIE_GTX_C_MRX_N12 97 98 217 218 VGA_DVI_SDATA VGA_DVI_SDATA 17
PCIE_GTX_C_MRX_P12 PEX_RX3# GND PCIE_MTX_C_GRX_N12 VGA_DVI_TXD1- GND DDCB_DAT VGA_DVI_SCLK
99 PEX_RX3 PEX_TX3# 100 17 VGA_DVI_TXD1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_DVI_SCLK 17
101 102 PCIE_MTX_C_GRX_P12 17 VGA_DVI_TXD1+ VGA_DVI_TXD1+ 221 222 +2.5VS
PCIE_GTX_C_MRX_N13 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
tt

PCIE_GTX_C_MRX_P13 105 106 PCIE_MTX_C_GRX_N13 17 VGA_DVI_TXD0- VGA_DVI_TXD0- 225 226 +3VS

PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P13 VGA_DVI_TXD0+ DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 17 VGA_DVI_TXD0+ 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230
231 232
h

ACES_88990-2D08 GND GND

CONN@ Lane Reversal on PCIEX16 ACES_88990-2D08
CONN@ +3VS

2
+MXM_B+ +1.2V_HT +2.5VS +5VS

160mil(4A) L26 2 1 6 1 D_EC_SMB_DA1

B+ 6,30,40 EC_SMB_DA1
KC FBM-L11-201209-221LMAT_0805
VGA@ 2 160mil(4A) 1 1 1 VGA@
L27 2 C202 C567 C483 C482 Q34A
1
KC FBM-L11-201209-221LMAT_0805 2N7002DW-T/R7_SOT363-6

5
1 1 VGA@ 0.1U_0402_16V4Z
C183 C197 1
0.1U_0603_25V7K 2 VGA@ 2 2
VGA@ 0.1U_0402_16V4Z 3 4 D_EC_SMB_CK1
6,30,40 EC_SMB_CK1
680P_0402_50V7K 68P_0402_50V8J 0.1U_0402_16V4Z VGA@
A 2 2 A

VGA@ Q34B
VGA@ 2N7002DW-T/R7_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 14 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS_CLK
R230
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
FBMA-L11-201209-601LMT10805 1 1 1 1 1 1 1 1 1 1
C348 C324 C344 C364 C363 C339 C319 C326 C325 C362 C350

+1.2V_HT +VDDCLK_IO 22U_0805_10V4Z 1U_0402_6.3V4Z

2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R192
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1U CLOSE PIN 69
FBMA-L11-201209-601LMT 0805 C313 C316 C361 C365 C346 C323 C322

D D
2 2 2 2 2 2 2
22U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R190
+3VS_CLK 1 2 +CLK_VDDA
+3VS_CLK
FBMA-L11-201209-601LMT 0805 1 1
C311 U20

1
C321
CLK_XTAL_OUT 22U_0805_10V4Z R197
2 2
0.1U_0402_16V4Z
ICS 9LPRS488 8.2K_0402_5%
CLK_XTAL_IN 49 1
VDDA SMBCLK ICH_SMBCLK0 8,9,17,20,28
48 2

2
GNDA SMBDAT ICH_SMBDATA0 8,9,17,20,28
SRC_SLOW

/
+3VS_CLK 62 41 SRC_SLOW
VDDREF SB_SRC_SLOW# CLK_CPU_BCLK 6

1
Y4 66 GNDREF

1
2 1 R214
C343 0.1U_0402_16V4Z 261_0402_1% R210

/x
2 1
CLK_CPU
CPU @
+VDDCLK_IO 12 VDDSRC_IO CPUKG0T_LPRS 56 1 2 @ 8.2K_0402_5%
14.31818MHZ_20P_6X1430004201 18 55 CLK_CPU# R215 1 2 0_0402_5% CLK_CPU_BCLK# 6

2
VDDSRC_IO CPUKG0C_LPRS R206 0_0402_5%
1 1 28

2
C368 C360 VDDATIG_IO
37 VDDSB_SRC_IO
53 60 CLK_HTT 1 2
VDDCPU_IO HTT0T_LPRS / 66 M CLK_NBHT 11
22P_0402_50V8J 22P_0402_50V8J 59 CLK_HTT# R225
1 2 0_0402_5%

su
2 2 HTT0C_LPRS / 66 M CLK_NBHT# 11
R222 0_0402_5%
C +3VS_CLK 3 C
+3VS_CLK VDDDOT
17 VDDSRC SB_SRC0T_LPRS 40
29 VDDATIG SB_SRC0C_LPRS 39
38 VDDSB_SRC
44 VDDSATA

p.
R195 8.2K_0402_5%

R205 8.2K_0402_5%

R201 8.2K_0402_5%

R503 54 VDDCPU SB_SRC1T_LPRS 35

61 VDDHTT SB_SRC1C_LPRS 34
2

1 2 69 VDD48
FBMA-L11-160808-601LMT 0603 33 CLK_ATIG0 1 2
ATIG0T_LPRS CLK_NBGFX 11

om
32 CLK_ATIG0# R223
1 2 0_0402_5% NB GFX
ATIG0C_LPRS CLK_NBGFX# 11
R226 0_0402_5%
1

24 CLKREQ0 #
31 CLK_ATIG1 1 2
ATIG1T_LPRS CLK_PCIE_VGA 14
REQ0# FOR SRC1 51 30 CLK_ATIG1# R227
1 2 0_0402_5% VGA chip(Dis)
29 EXP_CLKREQ# CLKREQ1# ATIG1C_LPRS CLK_PCIE_VGA# 14
R229VGA@ 0_0402_5%
REQ2# FOR SRC2 28 MINI1_CLKREQ#
50 CLKREQ2# VGA@
ATIG2T_LPRS 26

yc
REQ3# FOR SRC3 28 MINI2_CLKREQ# 43 CLKREQ3# ATIG2C_LPRS 25

42 CLKREQ4#
23 CLK_SRC0 1 2 SRC 0 LAN
SRC0T_LPRS CLK_PCIE_LAN 26
1 2 22 CLK_SRC0# R239
1 2 0_0402_5% GLAN
SRC0C_LPRS CLK_PCIE_LAN# 26
R231 100_0402_5% R240 0_0402_5% SRC 1 NEW CARD

m
1 2 63 21 CLK_SRC1 1 2 SRC 2 MINI2
11 NB_OSC_14.318M REF2/SEL_27 SRC1T_LPRS CLK_PCIE_CARD 29
R232 200_0402_1% 20 CLK_SRC1# R244
1 2 0_0402_5% New Card
SRC1C_LPRS CLK_PCIE_CARD# 29
CLK_14M_SIO 2 R522 1 SEL_SATA 64 R251 0_0402_5% SRC 3 MINI1
30 CLK_14M_SIO REF1/SEL_SATA
33_0402_5%
SEL_HT66 65 REF0/SEL_HTT66
// SRC2T_LPRS
SRC2C_LPRS
16
15
CLK_SRC2
CLK_SRC2#
1
R256
1
2
2 0_0402_5%
CLK_PCIE_MINI1 28
CLK_PCIE_MINI1# 28 MiniCard_1
R255 0_0402_5% NB CLOCK INPUT TABLE
B B
71 14 CLK_SRC3 1 2 NB CLOCKS RS740 RX780 RS780
48MHz_0 SRC3T_LPRS CLK_PCIE_MINI2 28
13 CLK_SRC3# R263
1 2 0_0402_5% MiniCard_2
SRC3C_LPRS CLK_PCIE_MINI2# 28
2 R243 1 70 R262 0_0402_5% HT_REFCLKP
p:

20 CLK_48M_USB 33_0402_5% 48MHz_1 66M SE(SINGLE END) 100M DIFF 100M DIFF
10 CLK_SB_SRC0 1 2 HT_REFCLKN NC 100M DIFF 100M DIFF
SRC4T_LPRS CLK_SBLINK_BCLK 11
9 CLK_SB_SRC0# R199
1 2 0_0402_5% NB A LINK
SRC4C_LPRS CLK_SBLINK_BCLK# 11
CLK_XTAL_IN 67 R200 0_0402_5% REFCLK_P
X1 14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
tt

CLK_XTAL_OUT 68 8 CLK_SRC5 1 2 CLK_PCIE_READER 25 REFCLK_N NC NC vref

X2 SRC5T_LPRS CLK_SRC5# R261
SRC5C_LPRS 7 1 2 0_0402_5% CLK_PCIE_READER# 25 Card Reader
R260 0_0402_5% GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)*
+3VS_CLK
h

6 46 CLK_SB_SRC1 1 2 GPP_REFCLK NC 100M DIFF NC

GNDDOT SRC6T/SATAT_LPRS CLK_SBSRC_BCLK 19
11 45 CLK_SB_SRC1# R213
1 2 0_0402_5% SB RCLK
GNDSRC SRC6C/SATAC_LPRS CLK_SBSRC_BCLK# 19
19 R218 0_0402_5% GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF
GNDSRC
27 GNDATIG
36 GNDSB_SRC SRC7T_LPRS/27MHz_SS 5
47 GNDSATA SRC7C_LPRS/27MHz_NS 4
2

52 GNDCPU
R234 R237 58
8.2K_0402_5% @ @ GNDHTT
72 GND48
8.2K_0402_5% 73 57 2 1 +3VS_CLK
GNDPAD PD# R220 8.2K_0402_5%
1

SEL_SATA 1
SEL_HT66 ICS9LPRS488AKLFT_MLF72_10x10 C669
@
2

R235 R238 2
8.2K_0402_5% 8.2K_0402_5% 1U_0603_10V6K

A A
1

1 configure as single-ended 66MHz output 1 configure as 27M and 27M_SS output

SEL_HTT66
0* configure as differential 100MHz output
NB_OSC_14.318M
0* configure as SRC_7 output
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

1* 100M SATA SRC6 output

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
SEL_SATA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0 SPREAD 100M SATA SRC6 output DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
* default MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 15 of 50
5 4 3 2 1
 5 4 3 2 1

TXOUT0+ 1 4 VGA_TXOUT0+
VGA_TXOUT0+ 14
TXOUT0- 2 3 VGA_TXOUT0-
LCD POWER CIRCUIT TXOUT1+
RP31
1 4
VGA@ 0_0404_4P2R_5%
VGA_TXOUT1+
VGA_TXOUT0- 14

+LCDVDD VGA_TXOUT1+ 14
TXOUT1- 2 3 VGA_TXOUT1-
VGA_TXOUT1- 14
RP30 VGA@ 0_0404_4P2R_5%
+3VALW +3VS TXOUT2+ VGA_TXOUT2+
1 4 VGA_TXOUT2+ 14

1
W=60mils TXOUT2- 2 3 VGA_TXOUT2-
VGA_TXOUT2- 14
R5 RP29 VGA@ 0_0404_4P2R_5%
300_0603_5% TXCLK+ 1 4 VGA_TXCLK+
VGA_TXCLK+ 14

1
1 TXCLK- 2 3 VGA_TXCLK-
VGA_TXCLK- 14
R9 C2 RP28 VGA@ 0_0404_4P2R_5%

2
100K_0402_5% TZOUT0+ 1 4 VGA_TZOUT0+
D VGA_TZOUT0+ 14 D
4.7U_0805_10V4Z TZOUT0- 2 3 VGA_TZOUT0-
VGA_TZOUT0- 14

6
2 RP27 VGA@ 0_0404_4P2R_5%

2
TZOUT1+ 1 4 VGA_TZOUT1+
VGA_TZOUT1+ 14

3
S
TZOUT1- 2 3 VGA_TZOUT1-
2N7002DW-T/R7_SOT363-6 G
AO3413_SOT23-3 VGA_TZOUT1- 14
2 2 1 2 RP26 VGA@ 0_0404_4P2R_5%
Q2A R3 1K_0402_5% Q1 TZOUT2+ 1 4 VGA_TZOUT2+
VGA_TZOUT2+ 14
1
D TZOUT2- 2 3 VGA_TZOUT2-
VGA_TZOUT2- 14

1
3
C3 +LCDVDD RP25 VGA@ 0_0404_4P2R_5%
W=60mils TZCLK+ 1 4 VGA_TZCLK+
VGA_TZCLK+ 14
UMA@ 0.047U_0402_16V7K TZCLK- 2 3 VGA_TZCLK-
2N7002DW-T/R7_SOT363-6 2 VGA_TZCLK- 14
R6 1 2 0_0402_5% 5 RP24 VGA@ 0_0404_4P2R_5%
11 GMCH_ENVDD Q2B
VGA@ 1 1
R4 1 2 0_0402_5% C5 C6
14 ENVDD

4
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z I2CC_SCL 1 4 GMCH_LCD_CLK GMCH_LCD_CLK 11
R7 VGA@ 2 2 I2CC_SDA GMCH_LCD_DATA
2 3 GMCH_LCD_DATA 11
100K_0402_5% RP13 UMA@ 0_0404_4P2R_5%
2

TXOUT0- 2 3 GMCH_TXOUT0-
GMCH_TXOUT0- 11

/
TXOUT0+ 1 4 GMCH_TXOUT0+
GMCH_TXOUT0+ 11
RP1 UMA@ 0_0404_4P2R_5%
TXOUT1- 2 3 GMCH_TXOUT1-
+3VS GMCH_TXOUT1- 11
TXOUT1+ GMCH_TXOUT1+

/x
1 4 GMCH_TXOUT1+ 11
RP2 UMA@ 0_0404_4P2R_5%
TXOUT2- 2 3 GMCH_TXOUT2-
GMCH_TXOUT2- 11
1

DAC_BRIG 1 2 TXOUT2+ 1 4 GMCH_TXOUT2+

GMCH_TXOUT2+ 11
R8 C11 220P_0402_50V7K RP3 UMA@ 0_0404_4P2R_5%
INVTPWM 1 2 TXCLK- 2 3 GMCH_TXCLK-
GMCH_TXCLK- 11
4.7K_0402_5% C9 220P_0402_50V7K TXCLK+ 1 4 GMCH_TXCLK+

su
GMCH_TXCLK+ 11
D2 DISPOFF# 1 2 RP4 UMA@ 0_0404_4P2R_5%
2

C BKOFF# DISPOFF# TZOUT0- GMCH_TZOUT0- C

30 BKOFF# 1 2 RB751V_SOD323 C8 220P_0402_50V7K 2 3 GMCH_TZOUT0- 11
TZOUT0+ 1 4 GMCH_TZOUT0+
GMCH_TZOUT0+ 11
RP5 UMA@ 0_0404_4P2R_5%
TZOUT1- 2 3 GMCH_TZOUT1-
LCD/PANEL BD. Conn. TZOUT1+ 1 4 GMCH_TZOUT1+
GMCH_TZOUT1- 11
GMCH_TZOUT1+ 11

p.
RP6 UMA@ 0_0404_4P2R_5%
TZOUT2- 2 3 GMCH_TZOUT2-
GMCH_TZOUT2- 11
JLVDS1 TZOUT2+ 1 4 GMCH_TZOUT2+
GMCH_TZOUT2+ 11
42 41 RP7 UMA@ 0_0404_4P2R_5%
GND GND DAC_BRIG TZCLK- GMCH_TZCLK-
+INVPWR_B+ 40 40 39 39 DAC_BRIG 30 2 3 GMCH_TZCLK- 11

om
38 37 INVTPWM TZCLK+ 1 4 GMCH_TZCLK+
38 37 INVT_PWM 30 GMCH_TZCLK+ 11
+3VS 36 35 DISPOFF# RP8 UMA@ 0_0404_4P2R_5%
I2CC_SCL 36 35
14 I2CC_SCL 34 34 33 33 +LCDVDD
I2CC_SDA 32 31 W=60mils
14 I2CC_SDA 32 31
30 30 29 29
TZOUT0- 28 27
TZOUT0+ 28 27 TXOUT0-
26 26 25 25
24 23 TXOUT0+
24 23

yc
TZOUT1+ 22 21
TZOUT1- 22 21 TXOUT1-
20 20 19 19
18 17 TXOUT1+
TZOUT2+ 18 17
16 16 15 15
TZOUT2- 14 13 TXOUT2+
14 13 TXOUT2-
12 12 11 11

m
TZCLK- 10 9
TZCLK+ 10 9 TXCLK-
8 8 7 7
0_0603_5% 6 5 TXCLK+
R1 USB20_CMOS_N5 6 5
20 USB20_N5 1 2 4 4 3 3
R2 1 2 USB20_CMOS_P5 2 1 R574 1 2 0_0603_5% +3VS
20 USB20_P5 2 1
0_0603_5%
ACES_88242-4001
R575 1 @ 2 0_0603_5% +3VALW
//
CONN@ 1
B B

C10 0.1U_0402_16V4Z
2
p:
tt
h

+INVPWR_B+
+LCDVDD
L1 2 1 B+
W=40mils KC FBM-L11-201209-221LMAT_0805

L2 2 1 1 1
KC FBM-L11-201209-221LMAT_0805 C4 C7
1 1
C12 C13 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
680P_0402_50V7K 68P_0402_50V8J
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 16 of 50
5 4 3 2 1
 5 4 3 2 1

reserve HDMI I2C ESD diode

DDC to Docking

EC_DOCKIN +HDMI_5V_OUT +HDMI_5V_OUT

38 EC_DOCKIN DDC to HDMI CONN
JHDMI1
HDMI_HPD 19 HP_DET

1
D EC_DOCKIN#_S0 D
18,33,38 EC_DOCKIN#_S0 +HDMI_5V_OUT 18 +5V
11 GMCH_DDC_CLK 1 UMA@ 2 R90 R91 R84 R87 17 DDC/CEC_GND
R89 0_0402_5% 2K_0402_5% 2K_0402_5% 6.8K_0402_5% 6.8K_0402_5% HDMI_SDATA 16 SDA

2
G

G
HDMI_SCLK 15 SCL
14

2
VGA_DVI_SCLK_R VGA_DVI_SCLK_R HDMI_SCLK Reserved
14 VGA_DVI_SCLK 1 VGA@ 2 3 1 D_DVI_SCLK 38 3 1 13 CEC
R88 0_0402_5% HDMI_R_CK-

D
12 CK- GND 20
11 CK_shield GND 21

2
G

G
BSH111 1N_SOT23-3 BSH111 1N_SOT23-3 HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
Q48 Q50 9 D0- GND 23
14 VGA_DVI_SDATA 1 VGA@ 2 VGA_DVI_SDATA_R 3 1 D_DVI_SDATA 38 VGA_DVI_SDATA_R 3 1 HDMI_SDATA 8
R98 0_0402_5% HDMI_R_D0+ D0_shield

D
7 D0+
HDMI_R_D1- 6 D1-
11 GMCH_DDC_DATA 1 UMA@ 2 BSH111 1N_SOT23-3 BSH111 1N_SOT23-3 Place closed to JHDMI1 5 D1_shield
R94 0_0402_5% Q47 Q49 HDMI_R_D1+ 4
HDMI_R_D2- D1+
3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
TYCO_1939864-1
+HDMI_5V_OUT CONN@
U41

/
VGA_DVI_SCLK_R 2 8
VGA_DVI_SDATA_R 1A VCC D_DVI_SCLK
5 2A 1B 3
EC_DOCKIN#_S0 D_DVI_SDATA +HDMI_5V_OUT

/x
1 1OE# 2B 6
7 2OE# GND 4
D6 F1
W=40mils
SN74CBTD3306CPWR_TSSOP8 +5VS 2 1 1 2
@ 1
+HDMI_5V_OUT RB491D_SC59-3 1.1A_6VDC_FUSE
U42 C177

su
VGA_DVI_SCLK_R 2 8 0.1U_0402_16V4Z
C VGA_DVI_SDATA_R 1A VCC HDMI_SCLK 2 C
5 2A 1B 3
EC_DOCKIN 1 6 HDMI_SDATA HDMI_CLK- 1 2 HDMI_R_CK-
1OE# 2B R382 0_0402_5%
7 2OE# GND 4

SN74CBTD3306CPWR_TSSOP8 L50

p.
@ 1 2
1 2
1 2 D_DVI_DET 38
R524 0_0402_5% 4 3
4 3

om
+HDMI_5V_OUT @ WCM-2012-900T_0805

HDMI_HPD HDMI_CLK+ 1 2 HDMI_R_CK+

1 R383 0_0402_5%
1 R123 2 +3VS 1
1

C243
5
1

0.1U_0402_16V7K R105 C242 HDMI_TX0- 1 2 HDMI_R_D0-

2 2.2K_0402_5% R384 0_0402_5%
P
OE#

yc
2 A Y 4 HDMI_DET 11,14
0.1U_0402_16V7K L51
2
G

U9 1 2
SN74AHCT1G125GW_SOT353-5 100K_0402_5% 1 2
3

4 4 3 3

m
@ WCM-2012-900T_0805

+3VS HDMI_TX0+ 1 2 HDMI_R_D0+

R385 0_0402_5%
//
2

+3VS 1 2 HDMI_TX1- 1 2 HDMI_R_D1-

B R393 4.7K_0402_5% D21 R386 0_0402_5% B
1 2 MS SS1040_SOD123
R392 @ 0_0402_5% L52
1

1 2
p:

OE +3VS_D80 1 2
+3VS 2 1
D22 RB751V_SOD323
1 2 4 4 3 3
R400 4.7K_0402_5%
11
15
24
36
48

22

1 1
2
6

U28 C486 C485 @ WCM-2012-900T_0805

tt

0.1U_0402_16V4Z
AVDD
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

0.1U_0402_16V4Z HDMI_TX1+ 1 2 HDMI_R_D1+

2 2 R387 0_0402_5%
14 VGA_DVI_TXC+ 4 D0+
14 VGA_DVI_TXC- 5 D0-
h

14 VGA_DVI_TXD0+ 7 D1+
NOTE: L : D-->A 8 25 HDMI_TX2- HDMI_TX2- 1 2 HDMI_R_D2-
14 VGA_DVI_TXD0- D1- D3-_B
9 26 HDMI_TX2+ R388 0_0402_5%
H: D-->B 14 VGA_DVI_TXD1+ D2+ D3+_B
10 28 HDMI_TX1-
14 VGA_DVI_TXD1- D2- D2-_B
12 29 HDMI_TX1+ L53
14 VGA_DVI_TXD2+ D3+ D2+_B
13 31 HDMI_TX0- 1 2
14 VGA_DVI_TXD2- D3- D1-_B 1 2
32 HDMI_TX0+
D1+_B HDMI_CLK-
T12 PAD 16 SEL_OUT D0-_B 34
PAD 55 35 HDMI_CLK+ 4 3
T13 SEL_IN D0+_B 4 3
@
@ 19 @ WCM-2012-900T_0805
8,9,15,20,28 ICH_SMBCLK0 SCL/S3
8,9,15,20,28 ICH_SMBDATA0 20 SDA/S2 D3-_A 37 D_DVI_TXD2- 38
38 D_DVI_TXD2+ 38 HDMI_TX2+ 1 2 HDMI_R_D2+
MS D3+_A R390 0_0402_5%
+3VS 1 2 1 MS D2-_A 40 D_DVI_TXD1- 38
R395 @ 4.7K_0402_5% PAD 17 41 D_DVI_TXD1+ 38
T11 TEST_OUT D2+_A
1 2 A0 54 43 D_DVI_TXD0- 38
R401 0_0402_5% OE TEST_IN D1-_A
@ 56 OE D1+_A 44 D_DVI_TXD0+ 38
+3VS 1 2 D0-_A 46 D_DVI_TXC- 38
R396 @ 4.7K_0402_5% A0 49 47 D_DVI_TXC+ 38
A A1 A1 A0/S4 D0+_A A
1 2 50 A1/S5
R402 0_0402_5% A2 51 18
A3 A2/S6 NC
+3VS 1 2 52 A3/S7 T-pad 57
R397 @ 4.7K_0402_5%
VSS10

AVSS

A2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

1 2
R403 0_0402_5%
+3VS 1 2
R398 @ 4.7K_0402_5% PI3HDMI412ADZBE_TQFN56_8X8
Security Classification Compal Secret Data Compal Electronics, Inc.
3
14
21
27
30
33
39
42
45
53

23

1 2 A3
R404 0_0402_5% 2008/04/16 2009/04/16 Title
Issued Date Deciphered Date
SMBus Address: 1100 000X (b) DVI/HDMI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 17 of 50
5 4 3 2 1
 A B C D E

CRT Connector D5 D4 D3
W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D18 F2 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
C430

3
0.1U_0402_16V4Z
2
1
+5VS 1

CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1

L23 FCM2012C-800_0805 L24 FCM2012C-800_0805 6
11
CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
L18 FCM2012C-800_0805 L20 FCM2012C-800_0805 7
12
CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
L13 FCM2012C-800_0805 L15 FCM2012C-800_0805 8

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C
13

6P_0402_50V8D

6P_0402_50V8D

6P_0402_50V8D
R74 R70 1 1 1 1 1 1 1 1 1 3
R54 C140 C120 C100 C145 C129 C108 C133 C115 C105 9
14
150_0402_1% @ @ @ 4

2
2 2 2 2 2 2 2 2 2
10 16

2
150_0402_1% 15 17
150_0402_1% 1 5
C83

/
SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L11 FCM1608C-121T_0603 2
change to 47pf for ATI M66/M7x 100P_0402_50V8J
CRT_DET# 20,38

/x
1 2 CRT_VSYNC_2
L8 FCM1608C-121T_0603 DSUB_12

2
+CRT_VCC
1 1 R30
1 2 2 1 C98 C90 100K_0402_5%
C67 0.1U_0402_16V4Z R13 10K_0402_5% @

su
@ DSUB_15

1
5

1
2 R381 0_0402_5% U3 100P_0402_50V8J 2 2
1 1
2
2 UMA@1 CRT_VSYNC 100P_0402_50V8J
C125 C76

OE#
11,13 GMCH_CRT_VSYNC
2 UMA@1 CRT_HSYNC CRT_HSYNC 2 4 D_CRT_HSYNC
11,13 GMCH_CRT_HSYNC A Y

100P_0402_50V8J

100P_0402_50V8J
R378 0_0402_5% +CRT_VCC

G
2 2

p.
R371 0_0402_5% SN74AHCT1G125DCKR_SC70-5

3
2 UMA@1 CRT_R_SW
11 GMCH_CRT_R +CRT_VCC
R372 0_0402_5%
2 UMA@1 CRT_G_SW
11 GMCH_CRT_G
R373 0_0402_5% 1 2

om
2 UMA@1 CRT_B_SW C66 0.1U_0402_16V4Z
11 GMCH_CRT_B

1
U4

OE#
CRT_VSYNC 2 4D_CRT_VSYNC
A Y

G
+CRT_VCC +3VS
SN74AHCT1G125DCKR_SC70-5 check with MXM board

3
D_CRT_HSYNC 38 Place closed to chipset

yc
D_CRT_VSYNC 38

1
R380 0_0402_5% +3VS

1
2 VGA@1 CRT_VSYNC
14 VGA_CRT_VSYNC
2 VGA@1 CRT_HSYNC R367 R366 R36 R326
14 VGA_CRT_HSYNC
R379 0_0402_5% 6.8K_0402_5% 4.7K_0402_5% 4.7K_0402_5%

m
6.8K_0402_5%

2
R375 0_0402_5%

2
VGA@1 CRT_R_SW

G
14 VGA_CRT_R 2
R374 0_0402_5%
2 VGA@1 CRT_G_SW DSUB_12 2 R369 1 1 3 1 2
14 VGA_CRT_G VGA_DDC_DATA 14
R376 0_0402_5%
// R35 VGA@ 0_0402_5%

S
2 VGA@1 CRT_B_SW 33_0402_5% VGA@
14 VGA_CRT_B

2
BSH111 1N_SOT23-3

G
3 3
Q52
Place closed to chipset DSUB_15 2 R368 1 1 3 1 2
R27 VGA@ 0_0402_5% VGA_DDC_CLK 14

S
33_0402_5% VGA@
p:

BSH111 1N_SOT23-3
Q53

public board write w/o PH

tt

+5VS
1 UMA@2 GMCH_CRT_DATA
38 D_CRT_DATA GMCH_CRT_DATA 11
R17 0_0402_5%
1 2 0.1U_0402_16V4Z 1 UMA@2 GMCH_CRT_CLK
38 D_CRT_CLK GMCH_CRT_CLK 11
h

C155 R18 0_0402_5%

U7

VCC 16
17,33,38 EC_DOCKIN#_S0 1 SEL
15 2 D_CRT_R
OE# 1B1 D_CRT_R 38
5 D_CRT_G
2B1 D_CRT_G 38
11 D_CRT_B
3B1 D_CRT_B 38
CRT_R_SW 4 14
CRT_G_SW 1A 4B1
7 2A
CRT_B_SW 9 3A CRT_R
12 4A 1B2 3
6 CRT_G
2B2 CRT_B
3B2 10
4B2 13
8 GND
FSAV330MTC_TSSOP16

4 4

NOTE: L : A-->B1
H: A-->B2

R525 VALUE@ 0_0402_5%

CRT_R_SW 2 1 CRT_R
R526 VALUE@ 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
CRT_G_SW 2 1 CRT_G 2008/04/16 2009/04/16 Title
R527 VALUE@ 0_0402_5%
Issued Date Deciphered Date
CRT_B_SW 2 1 CRT_B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 18 of 50
A B C D E
 A B C D E

1 2 A_RST#
R154 @ 8.2K_0402_5%

U10A

A_RST# N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3

PCI CLKS
C275 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
1 10 SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 23 1
C278 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
10 SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 23
C287 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
10 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 23
C279 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
10 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 23
C272 1 2 0.1U_0402_16V7K SB_RX2P_C U25
10 SB_RX2P PCIE_TX2P
C274 1 2 0.1U_0402_16V7K SB_RX2N_C U24
10 SB_RX2N PCIE_TX2N
C266 1 2 0.1U_0402_16V7K SB_RX3P_C T23
10 SB_RX3P PCIE_TX3P
C267 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
10 SB_RX3N PCIE_TX3N PCIRST#

PCI EXPRESS INTERFACE

10 SB_TX0P U22 PCIE_RX0P
10 SB_TX0N U21 PCIE_RX0N AD0 U2
10 SB_TX1P U19 PCIE_RX1P AD1 P7
10 SB_TX1N V19 PCIE_RX1N AD2 V4
10 SB_TX2P R20 PCIE_RX2P AD3 T1
R21 V3 +1.8VS +3VS
10 SB_TX2N PCIE_RX2N AD4
10 SB_TX3P R18 PCIE_RX3P AD5 U1
10 SB_TX3N R17 PCIE_RX3N AD6 V1

2
AD7 V2
R149 2 1 562_0402_1% T25 T2 R394
R143 2.05K_0402_1% T24 PCIE_CALRP AD8
+PCIE_VDDR 2 1 PCIE_CALRN AD9 W1 4.7K_0402_5%
L59 T9
AD10

2
G
+1.2V_HT 1 2 +SB_PCIEVDD P24 R6

1
PCIE_PVDD AD11

/
MBC1608121YZF_0603 1 1 R7
AD12 H_PWRGD
P25 PCIE_PVSS AD13 R5 3 1 H_PWRGD_L 46
+3VALW C523 C524 FDV301N_NL_SOT23-3

D
C294 AD14 U8
10U_0805_10V4Z 1U_0402_6.3V4Z Q35

/x
AD15 U5
2 2
2 1 AD16 Y7
AD17 W8
5

0.1U_0402_16V4Z U12 V9
AD18
2 Close to SB Y8
P

B PLT_RST# AD19
Y 4 PLT_RST# 11,13,25,26,28,29,30 AD20 AA8
A_RST# 1 Y4

su
A AD21
G

NC7SZ08P5X_NL_SC70-5 Y3
2 AD22 PCI_AD23 2
Y2 PCI_AD23 23
3

AD23 PCI_AD24
AD24 AA2 PCI_AD24 23
AB4 PCI_AD25
AD25 PCI_AD25 23
N25 AA1 PCI_AD26
15 CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 23
2 1 N24 AB3 PCI_AD27
15 CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 23

p.
R179 33_0402_5% AB2 PCI_AD28
AD28 PCI_AD28 23
@ K23 AC1
NB_DISP_CLKP AD29
K22 NB_DISP_CLKN AD30 AC2
AD31 AD1
+3VALW M24 W2

PCI INTERFACE
C298 NB_HT_CLKP CBE0#

om
M25 NB_HT_CLKN CBE1# U7
2 1 CBE2# AA7
P17 CPU_HT_CLKP CBE3# Y1
5

0.1U_0402_16V4Z U13 M18 AA6

CPU_HT_CLKN FRAME#
2 W5
P

B VGA_RST# DEVSEL#
Y 4 VGA_RST# 14 M23 SLT_GFX_CLKP IRDY# AA5
A_RST# 1 M22 Y5
A SLT_GFX_CLKN TRDY#
G

NC7SZ08P5X_NL_SC70-5 U6
PAR

yc
J19 W6
3

GPP_CLK0P STOP#
J18 GPP_CLK0N PERR# W4
SERR# V7
L20 GPP_CLK1P REQ0# AC3
2 1 L19 GPP_CLK1N REQ1# AD4
R185 @ 33_0402_5% AB7
REQ2#

m
M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 GPP_CLK2N REQ4#/GPIO71 AB6
GNT0# AD2

CLOCK GENERATOR
N22 GPP_CLK3P GNT1# AE4
P22 GPP_CLK3N GNT2# AD5
//
L18 25M_48M_66M_OSC
GNT3#/GPIO72
GNT4#/GPIO73
AC6
AE5 PAD
@
T18
@ R83
@R83 20M_0402_5% AD6 1 2 PM_CLKRUN# 30
3 CLKRUN# R180 0_0402_5% 3
1 2 LOCK# V5
J21 25M_X1
C192 INTE#/GPIO33 AD3
AC4
p:

SB_32KHI INTF#/GPIO34
1 2 INTG#/GPIO35 AE2
X2 J20 25M_X2 INTH#/GPIO36 AE3
12P_0402_50V8J
1

4 OUT NC 3
R85 G22 R120 1 2 22_0402_5% CLK_PCI_EC
CLK_PCI_EC 23,30
tt

20M_0603_5% LPCCLK0
1 IN NC 2
SB_32KHI A3
LPCCLK1 E22
H24
LPCCLK1 23,30 STRAP PIN
X1 LAD0 LPC_AD0 30
C212 H23 LPC_AD1 30 EC & Debug
2

32.768KHZ_12.5P_MC-306 LAD1
LAD2 J25 LPC_AD2 30
h

1 2 SB_32KHO J24
RTC XTAL

LAD3 LPC_AD3 30
LPC

SB_32KHO B3 H25
X2 LFRAME# LPC_FRAME# 30
12P_0402_50V8J H22
LDRQ0#
Close to SB LDRQ1#/GNT5#/GPIO68 AB8 LPC_DRQ1# 30
BMREQ#/REQ5#/GPIO65 AD7
SERIRQ V15 SERIRQ 30

Change Capacitors to correct RTC timeing 11 ALLOW_LDTSTOP F23 ALLOW_LDTSTP

6 H_PROCHOT#
H_PWRGD
F24
F22
PROCHOT# RTCCLK C3
C2 1 @ 2
RTC_CLK 23 STRAP PIN +RTCBATT
6 H_PWRGD LDT_PG INTRUDER_ALERT# +RTCVCC
R127 1M_0402_5%
CPU

6,11 LDT_STOP# G25 LDT_STP# VBAT B2

G24 +RTCVCC
6 LDT_RST# LDT_RST#
RTC

D10
+RTCVCC_R 1 2 2 1 3
218S7EALA11FG_BGA528_SB700 R184 510_0402_5% R178 1K_0402_5%

0.1U_0402_16V4Z
C289 1 1 C293 W=20mils 1

2
0.1U_0402_16V4Z

1U_0402_6.3V4Z 1
4 J1 C297 4
2
@
2 2 0_0603_5%
for Clear CMOS 2 BAS40-04_SOT23-3

1
+CHGRTC

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700-PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 19 of 50
A B C D E
 A B C D E

SKU-ID R509 R510

POP
UMA
POP C232
DIS U10D 22P_0402_50V8J @
33_0402_5% @ 1 2 R109 1 2
SB700 Part 4 of 5
1 1
30 EC_SWI# E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 15
demo circuit LID use RI# CRT_DET H7
R417 SLP_S2/GPM9#
@ F5 G8 USB_RCOMP 1 2
30 PM_SLP_S3# SLP_S3# USB_RCOMP
1 2 NB_PWRGD G1 11.8K_0402_1% R405
30 PM_SLP_S5# SLP_S5#

USB MISC
ACPI / WAKE UP EVENTS
30 PBTN_OUT# H2 PWR_BTN#
10K_0402_5% H1
6,32 SB_PWRGD PWR_GOOD
+3VS 1 2 SUS_STAT# SUS_STAT# K3
11 SUS_STAT# SUS_STAT#
R137 10K_0402_5% SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
SB700 has internal PD SB_TEST0 H3 TEST0

USB 1.1
30 EC_GA20 Y15 GA20IN/GEVENT0# USB_FSD12P F7
+3VALW 1 2 SB_TEST2 W15 E8
30 EC_KBRST# KBRST#/GEVENT1# USB_FSD12N
R133 @ 2.2K_0402_5% K4
30 EC_SCI# LPC_PME#/GEVENT3#
1 2 SB_TEST1 K24 H11 USB20_P11
30 EC_SMI# LPC_SMI#/EXTEVNT1# USB_HSD11P USB20_P11 29
R132 @ 2.2K_0402_5% F1 J10 USB20_N11 USB-11 New Card
S3_STATE/GEVENT5# USB_HSD11N USB20_N11 29
1 2 SB_TEST0 J2
R131 @ 2.2K_0402_5% SYS_RESET#/GPM7# USB20_P10
26,28,29 SB_PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11 USB20_P10 28
CR_PE# F2 F11 USB20_N10 USB-10 MiniCard(TV tuner)
25 CR_PE# BLINK/GPM6# USB_HSD10N USB20_N10 28
H_THERMTRIP# J6
6 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD W14 A11 USB20_P9
11 NB_PWRGD NB_PWRGD USB_HSD9P USB20_P9 29

/
B11 USB20_N9 USB-9 Bluetooth
USB_HSD9N USB20_N9 29
EC_RSMRST# D3
30 EC_RSMRST# RSMRST#
C10 USB20_P8
USB_HSD8P USB20_P8 28
USB20_N8

/x
USB_HSD8N D10 USB20_N8 28 USB-8 WLAN
1 2 EC_RSMRST#
R124 2.2K_0402_5% AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 29
CR_WAKE# AD18 H12 USB20_N7 USB-7 M/B
25 CR_WAKE# CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 29
R509 VGA@ 2.2K_0402_5% AA19
SKU_ID SMARTVOLT1/SATA_IS2#/GPIO4
+3VS 1 2 W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12
R510 2.2K_0402_5% V17 E14

su
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N
1 UMA@ 2 W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
2 USB20_P5 2
33 SB_SPKR W21 C12

USB 2.0
+3VS SPKR/GPIO2 USB_HSD5P USB20_P5 16
8,9,15,17,28 ICH_SMBCLK0 ICH_SMBCLK0 AA18 D12 USB20_N5 USB-5 USB Camera
SCL0/GPOC0# USB_HSD5N USB20_N5 16
8,9,15,17,28 ICH_SMBDATA0 ICH_SMBDATA0 W18
ICH_SMBCLK1 SDA0/GPOC1# USB20_P4
6,26,29 ICH_SMBCLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 28
R537 1 2 10K_0402_5% CR_WAKE# ICH_SMBDATA1 K2 A12 USB20_N4 USB-4 TV/B
6,26,29 ICH_SMBDATA1 SDA1/GPOC3# USB_HSD4N USB20_N4 28

p.
AA20 DDC1_SCL/GPIO9

GPIO
R413 1 2 2.2K_0402_5% ICH_SMBCLK0 Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 38
C1 G14 USB20_N3 USB-3 DOCK
LLB#/GPIO66 USB_HSD3N USB20_N3 38
R410 1 2 2.2K_0402_5% ICH_SMBDATA0 Y19 SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB20_P2 28

om
+3VALW USB20_N2
USB_HSD2N H15 USB20_N2 28 USB-2 USB/B
R535 1 @ 2 100K_0402_5% CR_PE# A13 USB20_P1
USB_HSD1P USB20_P1 28
B13 USB20_N1 USB-1 Fingerprint
USB_HSD1N USB20_N1 28
R136 1 2 2.2K_0402_5% ICH_SMBCLK1
B14 USB20_P0
USB_HSD0P USB20_P0 29
R135 1 2 2.2K_0402_5% ICH_SMBDATA1 B9 A14 USB20_N0 USB-0 M/B
27,30,38 EC_DOCKIN# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 29
29 CP_PE# B8 USB_OC5#/IR_TX0/GPM5#

yc
R134 1 2 10K_0402_5% SB_PCIE_WAKE# EC_LID_OUT# A8 A18

USB OC
30 EC_LID_OUT# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
R536 1 @ 2 100K_0402_5% EC_LID_OUT# USB_OC#2 E5 F21
28 USB_OC#2 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
USB_OC#1 F8 D21
29 USB_OC#1 USB_OC1#/GPM1# SCL2/IMC_GPIO11
R146 33_0402_5% 1 2 USB_OC#0 E4 F19
33 HDA_BITCLK_AUDIO 29 USB_OC#0 USB_OC0#/GPM0# SDA2/IMC_GPIO12
R152 33_0402_5% 1 2 HDA_BITCLK E20
32 HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13 CPU_SIC_SB 6

m
R153 33_0402_5% 1 2 M1 E21
32 HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14 CPU_SID_SB 6
R147 33_0402_5% 1 2 HDA_SDOUT M2 E19
33 HDA_SDOUT_AUDIO AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
33 HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 23
HDA_SDIN1
32 HDA_SDIN1
HDA_SDIN2
J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 23 STRAP PIN

HD AUDIO
AZ_SDIN2/GPIO44

32 HDA_SYNC_MDC
R144 33_0402_5% 1 2 HDA_SYNC
M3
L6
//AZ_SDIN3/GPIO46
AZ_SYNC
IMC_GPIO18
IMC_GPIO19
G20
G21
R150 33_0402_5% 1 2 M4 D25
3 33 HDA_SYNC_AUDIO AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
R145 33_0402_5% HDARST#

INTEGRATED uC
33 HDA_RST_AUDIO# 1 2 IMC_GPIO22 C25
R151 33_0402_5% 1 2 C24
32 HDA_RST_MDC# IMC_GPIO23
PAD T14 B25
p:

@ IMC_GPIO24
IMC_GPIO25 C23
STRAP PIN 23 HDARST#
B24
IMC_GPIO26
IMC_GPIO27 B23
A23
tt

IMC_GPIO28
IMC_GPIO29 C22
IMC_GPIO30 A22
IMC_GPIO31 B22
R504 1 2 33_0402_5% HDA_SYNC B21
14 HDA_SYNC_MXM +3VS IMC_GPIO32
h

R505 1 2 33_0402_5% HDA_BITCLK A21

14 HDA_BCLK_MXM IMC_GPIO33
R506 1 2 33_0402_5% HDARST# H19 D20
14 HDA_RST#_MXM IMC_GPIO0 IMC_GPIO34
R507 1 2 33_0402_5% HDA_SDIN2 H20 C20
14 HDA_SDI_MXM IMC_GPIO1 IMC_GPIO35
R508 33_0402_5% HDA_SDOUT
INTEGRATED uC

14 HDA_SDO_MXM 1 2 H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20

1 @ 2 F25 B20
R130 2.2K_0402_5% IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37
IMC_GPIO38 B19
D22 IMC_GPIO4 IMC_GPIO39 A19
E24 IMC_GPIO5 IMC_GPIO40 D18
FOR Nvidia VGA/B E25 IMC_GPIO6 IMC_GPIO41 C18
D23 IMC_GPIO7

218S7EALA11FG_BGA528_SB700
+3VALW
SB Power Domain :S5
2

R406
100K_0402_5%
4 HDA_SDIN0 4
1 2 High: CRT Plugged
R513 10K_0402_5%
1

1 @ 2 HDA_SDIN1 CRT_DET
R514 10K_0402_5%
1

HDA_SDIN2 D
1 @ 2
R515 10K_0402_5% 2
18,38 CRT_DET#
@ Q36G
2N7002_SOT23 S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 USB/HD audio
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 20 of 50
A B C D E
 A B C D E

Port Number Pri/SEC,Mas/Slave assignment SATA drive controlled by

Port 0 Primary master SATA controler

U10B
1 1
Port 1 Secondary master SATA controler
1 2 SATA_STX_DRX_P0 AD9
SB700 AA24
24 SATA_STX_R_DRX_P0 SATA_TX0P IDE_IORDY
R175 1 2 4.99_0402_1% SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25 Port 2 Primary slave SATA controler
24 SATA_STX_R_DRX_N0 SATA_TX0N IDE_IRQ
R174 4.99_0402_1% Y22
IDE_A0
24 SATA_DTX_C_SRX_N0 AB10 SATA_RX0N IDE_A1 AB23
24 SATA_DTX_C_SRX_P0 AC10 SATA_RX0P IDE_A2 Y23 Port 3 Secondary slave SATA controler
IDE_DACK# AB24
1 2 SATA_STX_DRX_P2 AE10 AD25
24 SATA_STX_R_DRX_P2 SATA_TX1P IDE_DRQ
R182 1 2 4.99_0402_1% SATA_STX_DRX_N2 AD10 AC25 Port 4 Primary (Secondary) master PATA controler
24 SATA_STX_R_DRX_N2 SATA_TX1N IDE_IOR#
R181 4.99_0402_1% AC24
IDE_IOW#
24 SATA_DTX_C_SRX_N2 AD11 SATA_RX1N IDE_CS1# Y25
24 SATA_DTX_C_SRX_P2 AE11 SATA_RX1P IDE_CS3# Y24 Port 5 Primary (Secondary) slave PATA controler
AB12 SATA_TX2P IDE_D0/GPIO15 AD24
AC12 SATA_TX2N IDE_D1/GPIO16 AD23

ATA 66/100/133
IDE_D2/GPIO17 AE22
AE12 AC22 @
SATA_RX2N IDE_D3/GPIO18
AD12 SATA_RX2P IDE_D4/GPIO19 AD21 +3VALW 2 1
AE20 D30 RB751V_SOD323
IDE_D5/GPIO20
AD13 SATA_TX3P IDE_D6/GPIO21 AB20

/
AE13 SATA_TX3N IDE_D7/GPIO22 AD19 R549
AE19 C667 0.1U_0402_16V4Z

SERIAL ATA
IDE_D8/GPIO23
AB14 SATA_RX3N IDE_D9/GPIO24 AC20 +3VALW 2 1 1 2

/x
AC14 SATA_RX3P IDE_D10/GPIO25 AD20
AE21 0_0603_5%
IDE_D11/GPIO26
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 AD22 +SB_SPI_VCC
SATA_TX4N IDE_D13/GPIO28
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23

2
AE15

su
SATA_RX4P R546 R547 R548
2 10P_0402_50V8J 2 SATA_X1 2
1 C284 AB16 SATA_TX5P
1K_0402_5%
AC16 SATA_TX5N
1

G6 SB_SI_SPI_SO 10K_0402_5%

1
R176 SPI_DI/GPIO12 SB_SO_SPI_SI
AE16 SATA_RX5N SPI_DO/GPIO11 D2
25MHZ_20P Y3 AD16 D1 SB_SPICLK 10K_0402_5% U23
SATA_RX5P SPI_CLK/GPIO47

p.
10M_0402_5% F4 SB_HOLD# SB_SPICS# 1 CE# 8

SPI ROM
2

SATA_CAL SPI_HOLD#/GPIO31 SB_SPICS# VDD SB_SPICLK

2 1 V12 F3 3 WP# 6
2

10P_0402_50V8J 2 SATA_CAL SPI_CS1#/GPIO32 SCK

1 C283 SATA_X2 R412 1K_0402_1% SB_HOLD# 1 @ 2 7 HOLD# SI 5 SB_SO_SPI_SI
SATA_X1 Y12 U15 R545 0_0402_5% 4 VSS 2 SB_SI_SPI_SO
SATA_X1 LAN_RST#/GPIO13 SO
ROM_RST#/GPIO14 J1

om
SATA_X2 AA12 If use, Un-pop R545 MX25L8005M2C-15G_SOP8
SATA_X2
+3VS R411 1 2 10K_0402_5% FANOUT0/GPIO3 M8
31 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5
+1.2V_HT M7
L61 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5 NB_THERMAL_DC
PLLVDD_SATA FANIN0/GPIO50 NB_THERMAL_DC 11
BLM18PG121SN1D_0603 P8 1
FANIN1/GPIO51

SATA PWR
0.1U_0402_16V4Z

2 2 1 W12 XTLVDD_SATA FANIN2/GPIO52 R8

yc
pop after bring up @ C229
C562 C560 C546 C6 NB_THERMAL_DC_R 1 @ 2 10P_0402_50V8J
2.2U_0603_6.3V4Z TEMP_COMM NB_THERMAL_DA_R R110 @ 0_0402_5% NB_THERMAL_DA 2
1U_0402_6.3V4Z TEMPIN0/GPIO61 B6 1 2 NB_THERMAL_DA 11
1 1 2 R111 0_0402_5%
TEMPIN1/GPIO62 A6
TEMPIN2/GPIO63 A5
B5

HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# 30

m
+3VS A4 2 1
VIN0/GPIO53 ACIN 14,30,31,37,39,42
L34 B4 D7 RB751V_SOD323
+XTLVDD_SATA VIN1/GPIO54 R104 1
2 1 VIN2/GPIO55 C4 2 100K_0402_5% +3VS
0.1U_0402_16V4Z

BLM18PG121SN1D_0603 2 1 D4
VIN3/GPIO56
C296 C545
// VIN4/GPIO57
VIN5/GPIO58
D5
D6 +3VALWS
C670
1U_0402_6.3V4Z A7 @
3 1 2 VIN6/GPIO59 3
VIN7/GPIO60 B7 1 2

5
U44 0.1U_0402_16V4Z
L55 2

P
p:

+SB_AVDD B
AVDD F6 2 1 +3VALW 4 Y
1 1 BLM18PG121SN1D_0603 1 ACIN
A

G
G7 @
AVSS C488

3
2.2U_0603_6.3V4Z NC7SZ08P5X_NL_SC70-5
tt

2 2
218S7EALA11FG_BGA528_SB700
C492
0.1U_0402_16V4Z
h

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 SATA/IDE/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 21 of 50
A B C D E
 A B C D E

FOR SB700 ALL issue

A12 Will change to +1.2V_HT
@
U10C U10E
1 2 +1.2VALW
R399 FBMA-L11-201209-221LMA30T_0805
SB700
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1
R391
2 +1.2V_HT
FBMA-L11-201209-221LMA30T_0805 SB700 A2
VDDQ_2 VDD_2 VSS_1
1 2 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
C561 22U_0805_6.3V6M U9 N13 C490 22U_0805_6.3V6M B1

CORE S0
1 C529 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C512 VSS_3 1
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C536 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C504 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO I/O
C556 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C521 U10 G19
C513 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C526 AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
C542 1 2 1U_0402_6.3V4Z Y6 T16 0.1U_0402_16V4Z 2 1 C519 U12 K9
C550 1U_0402_6.3V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C511 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C538 1 2 0.1U_0402_16V4Z AB5 V14 K16
C508 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 AVSS_SATA_9 VSS_13 L10
Y14 AVSS_SATA_10 VSS_14 L11
L31 Y17 L12
+1.2V_CKVDD AVSS_SATA_11 VSS_15
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 2 1 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 FBMA-L11-160808-221LMT 0603 AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
1 @ 2 AA22 L24 AB11 M6

IDE/FLSH I/O

CLKGEN I/O
C557 22U_0805_6.3V6M VDD33_18_3 CKVDD_1.2V_3 C505 1U_0402_6.3V4Z AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 1 2 AB13 AVSS_SATA_15 VSS_19 M10
C544 1 @ 2 0.1U_0402_16V4Z C249 1 2 1U_0402_6.3V4Z AB15 M11
C548 AVSS_SATA_16 VSS_20
1 @ 2 0.1U_0402_16V4Z C502 2 1 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C551 1 2 0.1U_0402_16V4Z C507 2 1 0.1U_0402_16V4Z AC8 M15
@ C248 10U_0805_10V4Z AVSS_SATA_18 VSS_22
1 2 AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12

/
VSS_25 N14
+PCIE_VDDR P6
L32 POWER VSS_26
VSS_27 P9

/x
+1.2V_HT 2 1 VSS_28 P10
FBMA-L11-201209-221LMA30T_0805 A15 P11
AVSS_USB_1 VSS_29
P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
1 2 P19 +3VALW C14 P15
C254 22U_0805_6.3V6M PCIE_VDDR_2 AVSS_USB_3 VSS_31
P20 PCIE_VDDR_3 D8 AVSS_USB_4 VSS_32 R1
C525 1 2 1U_0402_6.3V4Z P21 A17 +S5_3V 1 2 D9 R2

A-LINK I/O
C522 1 PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
2 1U_0402_6.3V4Z R22 A24 R138 FBMA-L11-201209-221LMA30T_0805 D11 R4

su
C527 1 PCIE_VDDR_5 S5_3.3V_2 AVSS_USB_6 VSS_34
2 1U_0402_6.3V4Z R24 PCIE_VDDR_6 S5_3.3V_3 B17 1 2 D13 AVSS_USB_7 VSS_35 R9

GROUND
2 C252 22U_0805_6.3V6M 2
R25 PCIE_VDDR_7 S5_3.3V_4 J4 D14 AVSS_USB_8 VSS_36 R10

3.3V_S5 I/O
C251 1 2 0.1U_0402_16V4Z J5 1U_0402_6.3V4Z 2 1 C241 D15 R12
C250 1 S5_3.3V_5 AVSS_USB_9 VSS_37
2 0.1U_0402_16V4Z S5_3.3V_6 L1 E15 AVSS_USB_10 VSS_38 R14
L2 1U_0402_6.3V4Z 2 1 C503 F12 T11
+1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z C253 AVSS_USB_11 VSS_39
2 1 F14 AVSS_USB_12 VSS_40 T12

p.
L60 0.1U_0402_16V4Z 2 1 C506 G9 T14
0.1U_0402_16V4Z C247 AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 2 1 H9 AVSS_USB_14 VSS_42 U4
FBMA-L11-201209-221LMA30T_0805 AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 J9 AVSS_USB_16 VSS_44 V6
1 2 AA17 G2 +S5_1.2V L56 FBMA-L11-160808-221LMT 0603 J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O

om
C565 22U_0805_6.3V6M AC18 G4 J12 AB1
C547 1 AVDD_SATA_5 S5_1.2V_2 +1.2VALW AVSS_USB_18 VSS_46
2 1U_0402_6.3V4Z AD17 AVDD_SATA_6
1U_0402_6.3V4Z 2 1 C495 J14 AVSS_USB_19 VSS_47 AB19
C549 1 2 1U_0402_6.3V4Z AE17 1U_0402_6.3V4Z 2 1 C494 J15 AB25
C552 1 AVDD_SATA_7 +1.2_USB AVSS_USB_20 VSS_48
2 0.1U_0402_16V4Z L28 FBMA-L11-160808-221LMT 0603 K10 AVSS_USB_21 VSS_49 AE1
C559 1 2 0.1U_0402_16V4Z A10 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
C227 22U_0805_6.3V6M K15 AVSS_USB_24
2 1 PCIE_CK_VSS_9 P23

yc
C231 2 1 1U_0402_6.3V4Z R16
C240 1U_0402_6.3V4Z PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
+AVDD_USB T17
L29 PCIE_CK_VSS_12
PCIE_CK_VSS_13 U18
+3VALW 2 1 A16 AE7 +V5_VREF 1K_0402_5% 2 1 R172 +5VS H18 U20
FBMA-L11-201209-221LMA30T_0805 AVDDTX_0 V5_VREF PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18

m
C16 J16 +AVDDCK_3.3V 1 2 +3VS J22 V20
C228 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C277 C291 PCIE_CK_VSS_3 PCIE_CK_VSS_16
1 2 D16 AVDDTX_3 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
C236 1 2 10U_0805_10V4Z D17 K17 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z D9 RB751V_SOD323 M16 W19
PLL

C491 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C497 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
C493
C489
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
F17
F18
AVDDRX_1
AVDDRX_2
// L54
P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25

C499 1 2 0.1U_0402_16V4Z G15 2 1 +3VALW F9 L17

3 AVDDRX_3 FBMA-L11-160808-221LMT 0603 AVSSC AVSSCK 3
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C487 218S7EALA11FG_BGA528_SB700
p:

0.1U_0402_16V4Z 2 1 C496
218S7EALA11FG_BGA528_SB700
tt

L57
+AVDDCK_1.2V 2 1 +1.2V_HT
h

FBMA-L11-160808-221LMT 0603

2.2U_0603_6.3V4Z 2 1 C501

0.1U_0402_16V4Z 2 1 C510

L30
+AVDDCK_3.3V 2 1 +3VS
FBMA-L11-160808-221LMT 0603

2.2U_0603_6.3V4Z 2 1 C246

0.1U_0402_16V4Z 2 1 C500

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 power/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 22 of 50
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2 PCI_CLK3 LPC_CLK0

CLK_PCI_PCM CLK_PCI_DBG PCI_CLK4 PCI_CLK5 CLK_PCI_EC LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
ENABLED STRAPS H,H = Reserved
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default L,NC)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R155

R158

R161

R159

R121

R116

R125

R139

R102

R103
@

2
/
@ @ @ @ @ @ @ @
19 PCI_CLK2

/x
19 PCI_CLK3
19 PCI_CLK4
19 PCI_CLK5
19,30 CLK_PCI_EC
19,30 LPCCLK1
19 RTC_CLK

su
20 HDARST#
2 20 GPIO17 2
20 GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
p. R126

R99

R100
R156

R157

R162

R160

R122

R117

R140
2 @

2
om
@ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

yc
m
PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG
// PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

p:

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS

RESET BCLK
tt
h

19 PCI_AD28
19 PCI_AD27
19 PCI_AD26
19 PCI_AD25
19 PCI_AD24
19 PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R167

R168

R165

R169

R166

R164
2

2
@ @ @ @ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 23 of 50
A B C D E
 A B C D E F G H

1 1

SATA ODD Conn.

JSATA1

1 GND
C302 1 2 0.01U_0402_16V7K SATA_STX_RC_DRX_P2 2
21 SATA_STX_R_DRX_P2 A+
C301 1 2 0.01U_0402_16V7K SATA_STX_RC_DRX_N2 3
21 SATA_STX_R_DRX_N2 A-
4 GND
21 SATA_DTX_C_SRX_N2 C300 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N2 5
C299 B-
21 SATA_DTX_C_SRX_P2 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P2 6 B+
7 GND

1 2 8 DP

/
R183 @ 1K_0402_1% 9 +5V
+5VS 10 +5V
+5VS Placea caps. near ODD CONN. 11 MD

/x
12 GND GND 15
13 GND GND 14
0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 SANTA_206401-1_13P
C288 C292 C276 CONN@

su
C280
2 2 2 2 2 2

1000P_0402_50V7K 1U_0402_6.3V4Z

p.
om
yc
SATA HDD Conn.

m
JSATA2

1 GND
C332 1 2 0.01U_0402_16V7K SATA_STX_RC_DRX_P0 2
21 SATA_STX_R_DRX_P0 C336 SATA_STX_RC_DRX_N0 HTX+
21 SATA_STX_R_DRX_N0 1 2 0.01U_0402_16V7K 3 HTX-
// 21 SATA_DTX_C_SRX_N0 SATA_DTX_C_SRX_N0C345
0.01U_0402_16V7K
1 2 SATA_DTX_SRX_N0
4
5
GND
HRX-
21 SATA_DTX_C_SRX_P0 SATA_DTX_C_SRX_P0 C347 1 2 SATA_DTX_SRX_P0 6
3 HRX+ 3
7 GND
0.01U_0402_16V7K
p:

+3VS 8 VCC3.3
9 VCC3.3
10 VCC3.3
11 GND
12
tt

+5VS GND
13 GND
10U_0805_10V4Z 14
+5VS VCC5
0.1U_0402_16V4Z 15
+3VS VCC5
16 VCC5
h

1 1 1 1 17 GND
1 C378 C384 C379 18
C369 RESERVED
19 GND
C386 20
0.1U_0402_16V4Z 2 2 2 2 VCC12
21 VCC12 GND 23
2
22 VCC12 GND 24
1000P_0402_50V7K 1U_0402_6.3V4Z

OCTEK_SAT-22SG1G_NR
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 24 of 50
A B C D E F G H
 5 4 3 2 1

+3VS +1.8VS_APVDD
40mil L64 @
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil 0.1U_0402_16V4Z
+1.8VS 1 2
+3V_MCVCC
1 1 1 1 BLM18AG601SN1D_0603 1 1 1 1 1 1
C597 C608 C605 C617 C585 C602 C587 C588 C612 C586
XDWP_SDWP 1 2
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z R458 10K_0402_5% D
2 2 2 2 2 2 2 2 2 2
10U_0805_10V4Z XD_RB 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R466 10K_0402_5%

+3VS

XD_CLE 1 2
U33 R460 10K_0402_5%

3 5 +1.8VS_APVDD XDCD0#_SDCD# 1 2
15 CLK_PCIE_READER# APCLKN APVDD
4 10 R450 4.7K_0402_5%
15 CLK_PCIE_READER APCLKP APV18
TAV33 30 +3VS
PCIE_ITX_C_PRX_N4 9 XDCD1#_MSCD# 1 2
10 PCIE_ITX_C_PRX_N4 APRXN
PCIE_ITX_C_PRX_P4 8 19 R451 4.7K_0402_5%
10 PCIE_ITX_C_PRX_P4 APRXP DV33
DV33 20
10 PCIE_PTX_C_IRX_N4 C584 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N4 11 44
C583 1 0.1U_0402_16V7K PCIE_PTX_IRX_P4 APTXN DV33
10 PCIE_PTX_C_IRX_P4 2 12 APTXP DV18 18 +1.8VS_APVDD

/
15mil DV18 37
1 2 APREXT 7
R444 8.2K_0402_5% APREXT XD_SD_MS_D0
MDIO0 48

/x
47 XD_SD_MS_D1
MDIO1 XD_SD_MS_D2
+3VS 38 PCIES_EN MDIO2 46
39 45 XD_SD_MS_D3 XD_RE 1 2
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# R471 200K_0402_5%
42 XDCE_SDCLK_MSCLK_R 1 2 XDCE_SDCLK_MSCLK
MDIO5 XDWP_SDWP R533 22_0402_5% XD_ALE
MDIO6 41 1 2

su
40 XD_CLE R462 200K_0402_5%
C
MDIO7 XD_D4 C
MDIO8 29
11,13,19,26,28,29,30 PLT_RST# 1 28 XD_D5 Vendor recommend
XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7
MDIO11 XD_RE
25

p.
CR_PE MDIO12 XD_RB
13 SEEDAT MDIO13 23
14 22 XD_ALE
T20 PAD SEECLK MDIO14
@ NC 34

om
D29 XDCD1#_MSCD# 15 35
XDCD0#_SDCD# CR1_CD1N NC
20 CR_WAKE# 1 2 16 CR1_CD0N NC 36

CH751H-40PT_SOD323-2 6
MC_PWREN# APGND D25
17 CR1_PCTLN
40 mil 24 XDCD0#_SDCD# 2
GND XD_CD#
GND 31 1
21 32 XDCD1#_MSCD# 3

yc
31 5IN1_LED# CR1_LEDN GND
GND 33
DAN202UT106_SC70-3 C594

270P_0402_50V7K
JMB385-LGEZ0B_LQFP48_7X7

m
+3VALW
4 IN 1 Socket Push Type(New)
//
2

R531
B B
10K_0402_5%
JREAD1
20 CR_PE# +3V_MCVCC 3 21 +3V_MCVCC
1 1

XD-VCC SD-VCC
p:

D MS-VCC 28
XD_SD_MS_D0 32
CR_PE XD_SD_MS_D1 XD-D0 XDCE_SDCLK_MSCLK
2 10 XD-D1 7 IN 1 CONN SD_CLK 20
G XD_SD_MS_D2 9 14 XD_SD_MS_D0
Q55 XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
S 8 12
3

XD-D3 SD-DAT1
tt

2N7002_SOT23 XD_D4 7 30 XD_SD_MS_D2 C676

XD_D5 6
XD-D4 SD-DAT2
29 XD_SD_MS_D3 For EMI
XD_D6 XD-D5 SD-DAT3 XD_D4 33P_0402_50V8K
5 XD-D6 SD-DAT4 27
XD_D7 4 23 XD_D5
h

XD-D7 SD-DAT5 XD_D6

SD-DAT6 18
SDCMD_MSBS_XDWE# 34 16 XD_D7
XDWP_SDWP XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
33 XD-WP SD-CMD 25
XD_ALE 35 1 XDCD0#_SDCD#
XD_CD# XD-ALE SD-CD-SW
40 XD-CD
XD_RB 39 2 XDWP_SDWP
XD_RE XD-R/B SD-WP-SW
38 XD-RE
XDCE_SDCLK_MSCLK 37
XD_CLE XD-CE XDCE_SDCLK_MSCLK
36 XD-CLE MS-SCLK 26
+3V_MCVCC 17 XD_SD_MS_D0
MS-DATA0 XD_SD_MS_D1
11 7IN1 GND MS-DATA1 15
40mil 31 19 XD_SD_MS_D2
MC_PWREN# 7IN1 GND MS-DATA2 XD_SD_MS_D3
1 2 MS-DATA3 24
R477 0_0805_5% 22 XDCD1#_MSCD#
C620 1 C619 1 C625 1 C626 1 MS-INS SDCMD_MSBS_XDWE#
MS-BS 13
41 7IN1 GND
A 42 7IN1 GND A
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 TAITW_R015-B10-LM
0.1U_0402_16V4Z CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader JMB385
C620 must close Chipset AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 25 of 50
5 4 3 2 1
 A B C D

+3VALW 1 2 +3V_LAN
R77 0_1206_5% +3V_LAN R309 1 2 1_1206_1%

R12 1 2 1_1206_1% +3V_LAN_R

1 1
+3V_LAN 1 2 LAN_PME# C27 C28

3
R60 4.7K_0402_5%
0.1U_0402_16V4Z
LAN_REGCTL12 1 2 2
4.7U_0805_10V4Z
Q3 +1.2V_LAN
+3V_LAN MMJT9435T1G_SOT223

2
4
+3V_LAN
60mil
1 1

1 1 1 1 1 1 1 1 1
1 1 1 1 C68 C412 C71 C132 C37 C448 C409 C438 C111
C149 C417 C422 C428 1
C678 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2
2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
0.1U_0402_16V4Z

+1.2V_VDDCIO

1 1
C415 C39
U5 +3V_LAN
0.1U_0402_16V4Z
LAN_MIDI0- 2 2
TRD0_N 41 LAN_MIDI0- 27

2
LAN_MIDI0+ 0.1U_0402_16V4Z

/
15 CLK_PCIE_LAN# 28 PCIE_REFCLK_N TRD0_P 40 LAN_MIDI0+ 27
42 +LAN_AVDD R299
TRD1_N/AVDD LAN_MIDI1-
15 CLK_PCIE_LAN 29 PCIE_REFCLK_P TRD1_P/T1_N 43 LAN_MIDI1- 27
48 +LAN_AVDD 4.7K_0402_5%

/x
TRD2_N/AVDD LAN_MIDI2-
11 47 LAN_MIDI2- 27

1
CLKREQ TRD2_P/T2_N LAN_MIDI3- SPROM_DIN
TRD3_N 49 LAN_MIDI3- 27
50 LAN_MIDI3+
TRD3_P LAN_MIDI3+ 27
R37 1 2 10K_0402_5% 3 LOW PWR

su
R21 1 2 1K_0402_5% 53 2 2 1 +3V_LAN +3V_LAN +3V_LAN
+3VS VMAIN_PRSNT LINKLED LAN_LINK# 27
2
1 R24 +3V_LAN
2

R20 SPD100LED
+3V_LAN 1 2 1K_0402_5% 54 VAUX_PRSNT SPD1000LED 67 0_0402_5% 1
66 2 1 C410
TRAFFICLED LAN_ACTIVITY# 27

2
R25
0_0402_5% 0.1U_0402_16V4Z R311 R312 R321

p.
SPROM_CLK 2
30 ENERGY_DET 59 ENERGY_DET SCLK(EECLK) 65 4.7K_0402_5% 4.7K_0402_5%4.7K_0402_5%
63 SPROM_DIN U24
+LAN_GPHYPLLVDD SI SPROM_DOUT
35 64 1 8

1
GPHY_PLLVDD SO(EEDATA) SPROM_CS R29 A0 VCC SPROM_WP
CS 62 1 2 4.7K_0402_5% 2 A1 WP 7
PCIE_ITX_C_PRX_N3 32 2 1 3 6 SPROM_CLK

om
10 PCIE_ITX_C_PRX_N3 PCIE_RXD_N A2 SCL
R308 @ 0_0402_5% 4 5 SPROM_DOUT
PCIE_ITX_C_PRX_P3 GND SDA
10 PCIE_ITX_C_PRX_P3 31 PCIE_RXD_P +1.2V_VDDCIO
14 LAN_REGCTL12 AT24C64AN-10SU-2.7_SO8
C142 1 PCIE_PTX_IRX_N3 REGCTL12
10 PCIE_PTX_C_IRX_N3 2 25 PCIE_TXD_N REGCTL25/12_IO 18
0.1U_0402_16V7K 37 LAN_RDAC 1 2
C143 1 PCIE_PTX_IRX_P3 RDAC R66 1.18K_0402_1%
10 PCIE_PTX_C_IRX_P3 2
0.1U_0402_16V7K
26 PCIE_TXD_P 20mil L47
L48 +LAN_PCIEPLLVDD 1 2

yc
+1.2V_LAN
23 +LAN_XTALVDD 1 2 +3V_LAN 1 1 BLM18AG601SN1D_0603
R47 0_0402_5% LAN_RESET# XTALVDD BLM18AG601SN1D_0603 C440 C445
11,13,19,25,28,29,30 PLT_RST# 1 2 10 PERST VDDIO 6 +3V_LAN
VDDIO 15 1
R56 1 @ 2 0_0402_5% LAN_PME# 12 19 C444 0.1U_0402_16V4Z
20,28,29 SB_PCIE_WAKE# WAKE VDDIO 2 2
R61 1 2 0_0402_5% 56
30 EC_PME# VDDIO 4.7U_0805_10V4Z

m
VDDIO 61
2
0.1U_0402_16V4Z
+3V_LAN LAN_SMBCLK +1.2V_VDDCIO
R14
58 SMB_CLK VDDP 17 20mil L45
VDDP/DC 68
4.7K_0402_5% LAN_SMBDATA 57 +LAN_PCIEVDD 1 2 +1.2V_LAN
SMB_DATA
5

1 2 +3V_LAN VDDC
VDDC
// 5
13 +1.2V_LAN C434
1
C441
1 BLM18AG601SN1D_0603

3 4 LAN_SMBDATA 20
6,20,29 ICH_SMBDATA1 VDDC
4 34 0.1U_0402_16V4Z
3

Q4B @ GPIO_0(SERIAL_DO) VDDC 2 2

3

VDDC 55
2N7002DW-T/R7_SOT363-6 SPROM_WP 7 60 4.7U_0805_10V4Z
R15 1 GPIO_1(SERIAL_DI) VDDC L43
2
p:

0_0402_5% @ 8 36 +LAN_BIASVDD 1 2 +3V_LAN 20mil

GPIO_2 BIASVDD +LAN_PCIEPLLVDD BLM18AG601SN1D_0603 L39
PCIE_PLLVDD 30
+3V_LAN 9 27 +LAN_AVDD 1 2
UART_MODE PCIE_VDD/PLL 1 +3V_LAN
R16 33 +LAN_PCIEVDD C437 1 1 BLM18AG601SN1D_0603
4.7K_0402_5% PCIE_VDD C427 C70
tt
2

1 2 +3V_LAN 38 0.1U_0402_16V4Z
LAN_XTALI AVDD/DC 2
21 XTALI AVDD/AVDDL 45 +LAN_AVDDL 0.1U_0402_16V4Z
LAN_SMBCLK 2 2
6,20,29 ICH_SMBCLK1 6 1 AVDD/DC 52
XTALO 22 0.1U_0402_16V4Z
h

Q4A @ XTALO +LAN_AVDDL

AVDDL 39
2N7002DW-T/R7_SOT363-6 44 LAN_MIDI1+ 20mil
AVDDL/T1_P LAN_MIDI1+ 27
R19 1 2 @ 1 2 16 46 LAN_MIDI2+ L38
REG_GND/S_IDDQ AVDDL/T2_P LAN_MIDI2+ 27
0_0402_5% R67 39K_0402_5% 51 +LAN_AVDDL +LAN_AVDDL 1 2 +1.2V_LAN
+LAN_PCIEVDD AVDDL BLM18AG601SN1D_0603
24 PCIE_GND/VDD E- PAD 69 1 1
C426 C416

BCM5764MKML_QFN68 0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z

20mil L19
LAN_XTALI +LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_0603
XTALO C126 C122
1

0.1U_0402_16V4Z
R73 2 2
4
200_0402_1% 4.7U_0805_10V4Z 4
2

Y1
1 2 LAN_XTALO

1 25MHZ_20P 1
C138 C137 Security Classification Compal Secret Data Compal Electronics, Inc.
27P_0402_50V8J 27P_0402_50V8J 2008/04/16 2009/04/16 Title
2 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BCM5764M_5787M
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 26 of 50
A B C D
 5 4 3 2 1

D T1 D
1 TCT1 MCT1 24
L_LAN_MIDI0+ 2 23 RJ45_MIDI0+
L_LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0-
3 TD1- MX1- 22
4 TCT2 MCT2 21
L_LAN_MIDI1+ 5 20 RJ45_MIDI1+
L_LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1-
6 TD2- MX2- 19
7 TCT3 MCT3 18 1 2
L_LAN_MIDI2+ 8 17 RJ45_MIDI2+
L_LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- C397
9 TD3- MX3- 16
10 15 220P_0402_50V7K
L_LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ JRJ45
11 TD4+ MX4+ 14
L_LAN_MIDI3- 12 13 RJ45_MIDI3- 2 1 12 Amber LED+
TD4- MX4- +3V_LAN
R298 1K_0402_5%
350uH_GSL5009LF-1 L_LAN_ACTIVITY# 11 Amber LED-
SHLD2 16
RJ45_MIDI3- 8 Guide Pin
PR4-
SHLD1 15
RJ45_MIDI3+ 7 PR4+

/
RJ45_MIDI1- 6
R300 R302 PR2-

/x
75_0402_1% 75_0402_1% RJ45_MIDI2- 5 PR3-

1
RJ45_MIDI2+ 4 PR3+
1 1 1 1 R303 R304 RJ45_MIDI1+ 3
C400 C402 C403 C406 75_0402_1% 75_0402_1% PR2+

su
RJ45_MIDI0- 2

2
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z PR1- C
SHLD2 14
2 2 2 2 RJ45_GND RJ45_MIDI0+ 1 PR1+
SHLD1 13
0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil L_LAN_LINK# 10 Green LED-

p.
+3V_LAN 2 1 9 Green LED+
1K_0402_5%
Place close to TCT pin R307 FOX_JM36113-L2R8-7F
CONN@

om
1 2

C408
+3V_LAN 220P_0402_50V7K

RJ45_GND 1 2 LANGND 40mil

yc
1 1
C25
56
50
38
27
18
10
4

U2 1000P_1206_2KV7K C24 C26

4.7U_0805_10V4Z
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0

D_LAN_MIDI0+ 2 2
48 D_LAN_MIDI0+ 38

m
0B1 D_LAN_MIDI0- VALUE@
1B1 47 D_LAN_MIDI0- 38
26 LAN_MIDI0+ 2 LAN_MIDI0+ 2 3 L_LAN_MIDI0+ 0.1U_0402_16V4Z
A0 D_LAN_MIDI1+ LAN_MIDI0- L_LAN_MIDI0-
2B1 43 D_LAN_MIDI1+ 38 1 4
26 LAN_MIDI0- 3 42 D_LAN_MIDI1- D_LAN_MIDI1- 38 RP32 0_0404_4P2R_5%
A1 3B1 VALUE@
4B1 37
//
D_LAN_MIDI2+ D_LAN_MIDI2+ 38 LAN_MIDI1+ 2 3 L_LAN_MIDI1+
26 LAN_MIDI1+ 7 36 D_LAN_MIDI2- D_LAN_MIDI2- 38 LAN_MIDI1- 1 4 L_LAN_MIDI1-
B A2 5B1 RP33 0_0404_4P2R_5% B

26 LAN_MIDI1- 8 32 D_LAN_MIDI3+ D_LAN_MIDI3+ 38 VALUE@

A3 6B1 D_LAN_MIDI3- LAN_MIDI2+ L_LAN_MIDI2+
7B1 31 D_LAN_MIDI3- 38 2 3
p:

LAN_MIDI2- 1 4 L_LAN_MIDI2-
26 LAN_MIDI2+ 11 22 D_LAN_ACTIVITY# RP34 0_0404_4P2R_5%
A4 0LED1 D_LAN_ACTIVITY# 38
23 D_LAN_LINK# VALUE@
1LED1 D_LAN_LINK# 38
26 LAN_MIDI2- 12 52 LAN_MIDI3+ 2 3 L_LAN_MIDI3+
A5 2LED1 LAN_MIDI3- L_LAN_MIDI3-
1 4
tt

46 L_LAN_MIDI0+ RP35 0_0404_4P2R_5%

0B2 L_LAN_MIDI0-
26 LAN_MIDI3+ 14 A6 1B2 45
VALUE@ L_LAN_ACTIVITY# 1 2
26 LAN_MIDI3- 15 41 L_LAN_MIDI1+ LAN_ACTIVITY# 2 3 L_LAN_ACTIVITY# C398
h

A7 2B2 L_LAN_MIDI1- LAN_LINK# L_LAN_LINK# 68P_0402_50V8J

3B2 40 1 4
RP36 0_0404_4P2R_5% @
17 35 L_LAN_MIDI2+
20,30,38 EC_DOCKIN# SEL 4B2 L_LAN_MIDI2- L_LAN_LINK#
5B2 34 1 2
C405
19 30 L_LAN_MIDI3+ 68P_0402_50V8J
26 LAN_ACTIVITY# LED0 6B2 L_LAN_MIDI3- @
26 LAN_LINK# 20 LED1 7B2 29
54 LED2
25 L_LAN_ACTIVITY#
0LED2 L_LAN_LINK#
NOTE: L : A-->B1 5 NC 1LED2 26
For EMI
51
H: A-->B2 57
2LED2
PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

PI3L500-AZFEX_TQFN56_11X5
1
6
9
13
16
21
24
28
33
39
44
49
53
55

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 27 of 50
5 4 3 2 1
 A B C D E

For Wireless LAN For TV-Tuner/HW MPEG

+3VS +1.5VS +3VS
+3VS +1.5VS +5VS

1 1 1 1 1 1
C609 C613 C390 C381 C382 C615 1 1 1 1 1 1
C387 C380 C383 C385 C389 C392
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 +5VS 1

JMINI1 JMINI2
SB_PCIE_WAKE# R282 1 @ 2 0_0402_5% 1 2 +3VS SB_PCIE_WAKE# 1 @ 2 1 2 +3VS
20,26,29 SB_PCIE_WAKE# 1 2 1 2
WLAN_BT_DATA 3 4 R498 0_0402_5% 3 4
29 WLAN_BT_DATA 3 4 3 4
WLAN_BT_CLK 5 6 +1.5VS 5 6 +1.5VS
29 WLAN_BT_CLK 5 6 5 6
15 MINI1_CLKREQ# 7 7 8 8 15 MINI2_CLKREQ# 7 7 8 8
9 9 10 10 9 9 10 10
15 CLK_PCIE_MINI1# 11 11 12 12 15 CLK_PCIE_MINI2# 11 11 12 12
15 CLK_PCIE_MINI1 13 13 14 14 15 CLK_PCIE_MINI2 13 13 14 14
15 15 16 16 15 15 16 16

17 17 18 18 17 17 18 18
19 20 WL_OFF# 19 20
19 20 WL_OFF# 30 19 20
21 22 PLT_RST# 21 22 PLT_RST#
21 22 PLT_RST# 11,13,19,25,26,29,30 21 22
23 24 R279 1 2 0_0603_5% +3VS 23 24
10 PCIE_PTX_C_IRX_N2 23 24 10 PCIE_PTX_C_IRX_N1 23 24
25 26 R278 1 2 0_0603_5% +3VALW 25 26
10 PCIE_PTX_C_IRX_P2 25 26 10 PCIE_PTX_C_IRX_P1 25 26
27 28 @ 27 28
27 28 ICH_SMBCLK0 27 28 ICH_SMBCLK0
29 29 30 30 ICH_SMBCLK0 8,9,15,17,20 29 29 30 30
10 PCIE_ITX_C_PRX_N2 31 32 ICH_SMBDATA0 ICH_SMBDATA0 8,9,15,17,20 10 PCIE_ITX_C_PRX_N1 31 32 ICH_SMBDATA0
31 32 31 32

/
10 PCIE_ITX_C_PRX_P2 33 33 34 34 10 PCIE_ITX_C_PRX_P1 33 33 34 34
35 35 36 36 USB20_N8 20 35 35 36 36 USB20_N10 20
37 37 38 38 USB20_P8 20 37 37 38 38 USB20_P10 20

/x
+3VS 39 39 40 40 +3VS 39 39 40 40
41 42 (MINI1_LED#) 41 42 (MINI1_LED#)
41 42 41 42
43 43 44 44 MINI1_LED# 31 43 43 44 44
45 45 46 46 45 45 46 46
0_0402_5% 47 47 48 48 (9~16mA) 47 47 48 48

1
R469 1 2 E51TXD_P80DATA_R 49 50 E51TXD_P80DATA_R 49 50
30 E51TXD_P80DATA 49 50 49 50
E51RXD_P80CLK 51 52 R550 E51RXD_P80CLK 51 52

su
30 E51RXD_P80CLK 51 52 51 52
100K_0402_5%
2 G1 2
G2
G3
G3

G1
G2
G3
G3
@

2
FOX_AS0B226-S99N-7F FOX_AS0B226-S99N-7F
53
54
55
56

53
54
55
56
CONN@ CONN@
+3VALW

p.
H=5.2 mm H=9.2 mm
Mini Card Power Rating

om
Power Primary Power (mA) Auxiliary Power (mA)
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)

yc
+1.5VS 500 375 5 (Not wake enable)

Fingerprint Conn

m
//
R572 1 @ 2 0_0603_5%
3
To USB/B Connector To USB/B Connector
+3VS
+3VALW R573 1 2 0_0603_5%
JP7
3

C484 6 G2
2 1 5
p:

0.1U_0402_16V4Z G1
4 4
20 USB20_N1 3 3
20 USB20_P1 2 2
1 1
tt

80mil For EMI ACES_85201-0405N

80mil JP9 1 2 CONN@
JP8 1 2 9 1 +5VALW C680 33P_0402_50V8K
C679 33P_0402_50V8K GND 1
9 GND 1 1 +5VALW 2 2
h

2 2 3 3 1 2 SYSON# SYSON# 29,37,38,45

3 1 2 SYSON# 4 R576 MBK1005121YZF_0402
3 R563 MBK1005121YZF_0402 4 USB20_N2
4 4 5 5 USB20_N2 20
5 USB20_N4 6 USB20_P2 change to 120Ohm bead
5 USB20_N4 20 6 USB20_P2 20
6 USB20_P4 change to 120Ohm bead 7
6 USB20_P4 20 7
7 7 10 GND 8 8 USB_OC#2 20
10 GND 8 8
ACES_87213-0800G
ACES_87213-0800G CONN@
CONN@

+5VALW +5VALW
+3VALW

1 1
1

C404 C333
R520
4.7U_0805_10V4Z 4.7U_0805_10V4Z 100K_0402_5%
4 2 2 4
2

USB_OC#2
1
C654
0.1U_0402_16V4Z
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & TV-Tuner)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 28 of 50
A B C D E
 A B C D E

New Card Power Switch

New Card Socket (Left/TOP)
U17 +3VALW_CARD +3VS_CARD +1.5VS_CARD
40mil JEXP1
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A
14 1.5Vin 1.5Vout 13
1 GND
60mils C372
1 1
C367 C341
1 1
C342 C370
1 1
C366
20 USB20_N11 2 USB_D-
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD 20 USB20_P11 3 USB_D+
1 CP_USB# 1
4 3.3Vin 3.3Vout 5 4 CPUSB#
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 5
2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z RSV
+3VALW 17 AUX_IN AUX_OUT 15 +3VALW_CARD 6 RSV
PLT_RST#
40mil 6,20,26 ICH_SMBCLK1 7 SMB_CLK
11,13,19,25,26,28,30 PLT_RST# 6 SYSRST# OC# 19 6,20,26 ICH_SMBDATA1 8 SMB_DATA
+1.5VS_CARD 9 +1.5V
SYSON 20 8 PERST1# 10
30,37,44 SYSON SHDN# PERST# +1.5V
20,26,28 SB_PCIE_WAKE# 11 WAKE#
SUSP# 1 16 +3VALW_CARD 12
30,32,37,45 SUSP# STBY# NC +3.3VAUX
PERST1# 13 PERST#
+3VALW R248 1 2 100K_0402_5%CP_PE# 10 CPPE# GND 7 +3VS_CARD 14 +3.3V
+3VS 15 +3.3V
R242 1 2 100K_0402_5%CP_USB# 9 CPUSB# TGND 21 CLKREQ1# 16 CLKREQ#
20 CP_PE# CP_PE# 17
RCLKEN1 +3VS CPPE#
18 RCLKEN 1 15 CLK_PCIE_CARD# 18 REFCLK-
C338 19
15 CLK_PCIE_CARD REFCLK+
G577NSR91U_TQFN_20P 20 GND

1
0.1U_0402_16V4Z 21
2 10 PCIE_PTX_C_IRX_N0 PERn0
R228 22
10 PCIE_PTX_C_IRX_P0 PERp0

5
10K_0402_5% U15 23
CLKREQ1# GND
2 24

G Vcc
B 10 PCIE_ITX_C_PRX_N0 PETn0

/
4 EXP_CLKREQ# 15 10 PCIE_ITX_C_PRX_P0 25

2
+3VS +3VALW +1.5VS Y PETp0
1 A 26 GND

1
D NC7SZ32P5X_NL_SC70-5

/x
27 29

3
RCLKEN1 2 Q17 GND GND
1 1 1 28 GND GND 30
C340 C353 C371 G 2N7002_SOT23
S FOX_1CH4110C_LT

3
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CONN@
2 2 2

su
2 2

+USB_VCCA +USB_VCCA

+USB_VCCA

p.
1 W=80mils W=80mils
1 1
+ C539 C498 C558

150U_D2_6.3VM 470P_0402_50V7K 470P_0402_50V7K

om
2 2 2

1 2 1 2
R407 @ 0_0402_5% R426 @ 0_0402_5%

Bluetooth Conn. L62 JUSB2

yc
L58 JUSB1 USB20_N7
1 1 2 1
20 USB20_N7 2 VCC
USB20_N0 1 2 1 USB20_N7_1 2
20 USB20_N0 1 2 VCC D-
USB20_N0_1 2 3
D- USB20_P7 USB20_P7_1 D+
3 D+ 20 USB20_P7 4 4 3 3 4 GND
+3VALW +3VS USB20_P0 4 3 USB20_P0_1 4
20 USB20_P0 4 3 GND WCM2012F2S-900T04_0805 5 GND1

m
WCM2012F2S-900T04_0805 5 6
GND1 GND2
6 GND2 7 GND3
1 7 GND3 1 2 8 GND4
C320 C334 1 2 8 R427 @ 0_0402_5%
// R408 @ 0_0402_5% GND4 SUYIN_020173MR004G565ZR
0.1U_0402_16V4Z 1U_0603_10V4Z SUYIN_020173MR004G565ZR CONN@
3

2
S
CONN@
AO3413_SOT23-3
G
30 BT_ON# 1 2 2
3 R202 10K_0402_5% Q16 3
D D23
1

USB20_P0_1 6 3 USB20_N7_1
C330 CH3 CH2
W=40mils
p:

+BT_VCC
0.1U_0402_16V4Z
1 +USB_VCCA 5 Vp Vn 2
1

C327 C335
R452
tt

4.7U_0805_10V4Z 300_0603_5%
2 0.1U_0402_16V4Z USB20_P7_1 USB20_N0_1
4 CH4 CH1 1
2

CM1293-04SO_SOT23-6
+3VALW
h
1

D
2 Q42
G 2N7002_SOT23
+5VALW

1
+USB_VCCA
S 80mil
3

U29
1 8 R421
GND OUT 100K_0402_5%
2 IN OUT 7
3 6

2
IN OUT R422 1
1 4 EN# FLG 5 2 10K_0402_5% USB_OC#0 20
C555
TPS2061DRG4_SO8 R425 1 2 10K_0402_5%
+BT_VCC USB_OC#1 20
4.7U_0805_10V4Z
2
JP10
1 1 GND 9 1 1
2 C566 C563
2 28,37,38,45 SYSON#
3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
20 USB20_P9 3
20 USB20_N9 4 4
4 2 2 4
5 5
28 WLAN_BT_DATA 6 6
28 WLAN_BT_CLK 7 7
8 8 GND 10

ACES_87213-0800G
CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 29 of 50
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

L35
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VALW
1 1 C315 1 1 2
1
2 FBM-L11-160808-800LMT_0603 JP11 Place on RAM door
C307 1 KSI[0..7] 1
KSI[0..7] 31 1
C337 C351 C356 C357 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK 28
1000P_0402_50V7K 1000P_0402_50V7K C312 3 E51TXD_P80DATA
2 2 2 2 1 1 KSO[0..17] 31 3 E51TXD_P80DATA 28
4 4
2

ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
ACES_85205-0400
@
D D

111
125
+3VALW

22
33
96

67
9
U16

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 @ 2 EC_PME#
R204 10K_0402_5%

1 2 LID_SW# 1 21 INVT_PWM
20 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 16
R211 10K_0402_5% 2 23 BEEP#
20 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 33
SERIRQ 3 26
19 SERIRQ SERIRQ# FANPWM1/GPIO12 ENCODER_DIR 34
LPC_FRAME# 4 27
19 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 42
C331 LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
19 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C305 0.01U_0402_16V7K R241 4.7K_0402_5%
19 LPC_AD2 LAD2
2 1 R219 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
19 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 40
LPC_AD0 BATT_OVP VR_ON
19 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 42
R551
2 1
100K_0402_5%
ADP_I/AD2/GPIO3A 65 ADP_I 42
12 AD Input 66 AD_BID0
19,23 CLK_PCI_EC PCICLK AD3/GPIO3B
PLT_RST# 13 75
11,13,19,25,26,28,29 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 AD_PID0

/
37 ECRST# SELIO2#/AD5/GPIO43 76
EC_SCI# 20
20 EC_SCI# SCI#/GPIO0E
+3VALW 2 1 19 PM_CLKRUN# 38 CLKRUN#/GPIO1D

/x
R188 47K_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 16
2 1 70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 36
C306 0.1U_0402_16V4Z DA Output 71 IREF
IREF/DA2/GPIO3E IREF 42 +3VALW
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 42
+3VALW KSI1 56
KSI2 KSI1/GPIO31 65W/90W#
57 KSI2/GPIO32 2 1

su
KSI3 58 83 EC_MUTE R246 100K_0402_5%
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE 34,35
2

C KSI4 59 84 C
KSI4/GPIO34 PSDAT1/GPIO4B EC_I2C_INT1 31
R198 KSI5 60 85 DOCKIN# 38 BT_ON# 2 1
10K_0402_5% KSI6 KSI5/GPIO35 PSCLK2/GPIO4C R552 100K_0402_5%
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 BT_LED# 31
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 31
KSO0 39 88 TP_DATA

p.
TP_DATA 31
1

D11 KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F

40 KSO1/GPIO21
KSO2 41
EC_RCIRRX KSO3 KSO2/GPIO22 3S/4S#
32 RCIRRX 1 2 42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# 42
KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# 42

om
KSO5
RB751V_SOD323 KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 EC_VLDT_EN 32 Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
+5VS KSO7 46 SPI Device Interface VGATE(A32) Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SPIDI/FWR#
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 31
1 2 TP_CLK KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 EC_SPIDO/FRD#
EC_SO_SPI_SI 31
+3VALW +3VALW
R221 4.7K_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 31
1 2 TP_DATA KSO12 51 128 EC_SPICS#/FSEL#

yc
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 31

2
R224 4.7K_0402_5% KSO13 52 @
+3VALW KSO14 KSO13/GPIO2D R189 R203
53 KSO14/GPIO2E
KSO15 54 73 EC_RCIRRX Ra 100K_0402_5% Ra 100K_0402_5%
EC_SMB_CK1 KSO16 KSO15/GPIO2F CIR_RX/GPIO40
1 2 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 ENCODER_PULSE 34
R207 4.7K_0402_5% KSO17 82 89 FSTCHG
FSTCHG 42

1
EC_SMB_DA1 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0 AD_PID0
1 2 BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 31
R208 4.7K_0402_5% 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 31

2
+3VS EC_SMB_CK1 BATT_AMB_LED#
6,14,40 EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# 31 1 1
EC_SMB_DA1 78 93 PWR_LED PWR_LED 31 R187 C308 R209 C317
6,14,40 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
EC_SMB_CK2 SYSON
1 2 EC_SMB_CK2
6,31
6,31
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_DA2
79
80
//
SCL2/GPIO46
SDA2/GPIO47
SM Bus SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
95
121 VR_ON
SYSON
VR_ON
29,37,44
46
Rb
18K_0402_5%
Rb
100K_0402_5%
R217 4.7K_0402_5% ACIN 2
0.1U_0402_16V4Z 2
0.1U_0402_16V4Z
127

1
B EC_SMB_DA2 AC_IN/GPIO59 ACIN 14,21,31,37,39,42 B
1 2
R216 4.7K_0402_5%
1 2 ESB_CLK PM_SLP_S3# 6 100
20 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20
p:

R561 4.7K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT# No EC change, so Keep the board ID = 0.3
20 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 20
1 2 ESB_DATA EC_SMI# 15 102 EC_ON
20 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 32
R562 4.7K_0402_5% LID_SW# 16 103
31 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 20
ESB_CLK 17 104 EC_PWROK EC_CRY1 EC_CRY2
31 ESB_CLK SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PWROK 32
ESB_DATA 18 GPO 105 BKOFF#
31 ESB_DATA PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16
tt

EC_PME# 19 GPIO 106 WL_OFF# 2 2

26 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 28
26 ENERGY_DET 25 EC_THERM#/GPIO11 GPXO10 107

4
FAN_SPEED1 28 108 C358 C359
36 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 EC_DOCKIN# 20,27,38
BT_ON# 29 15P_0402_50V8J

OUT
IN
h

29 BT_ON# FANFB2/GPIO15 1 1
E51TXD_P80DATA 30 15P_0402_50V8J
+5VS +3VS E51RXD_P80CLK EC_TX/GPIO16
LPC debug port ON/OFF
31
32
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110
112 ENBKL
VGATE
ENBKL
46
11,14
32 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2
PWR_SUSP_LED EAPD

NC

NC
31 PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD 33
JP28 NUM_LED# 36 GPI 115
31 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 21
116 SUSP#
SUSP# 29,32,37,45

3
1 GPXID5 PBTN_OUT#
2 GPXID6 117 PBTN_OUT# 20
3 GPXID7 118 ARCADE# 31
EC_CRY1 122 X1
4 EC_CRY2 XCLK1 32.768KHZ_12.5P_MC-306
5 123 XCLK0 V18R 124
CLK_14M_SIO 1
6 CLK_14M_SIO 15
AGND

LPC_AD0 C354
GND
GND
GND
GND
GND

7 LPC_AD1 4.7U_0805_10V4Z
8 LPC_AD2 C304 100P_0402_50V8J
9 LPC_AD3 KB926QFB1_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

10 LPC_FRAME# C303 100P_0402_50V8J

11 20mil L36 BATT_OVP
A 12 LPC_DRQ1# 19 2 1 A
PLT_RST# ECAGND 2 1 C355 100P_0402_50V8J
13 R521 1
14 2 0_0402_5% FBM-L11-160808-800LMT_0603 ACIN 2 1
R523 1 2 0_0402_5%
15 LPCCLK1 19,23
SERIRQ
16
17
18
19
Security Classification Compal Secret Data Compal Electronics, Inc.
20 Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
ACES_85201-20051 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
@ B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 30 of 50
5 4 3 2 1
 +3VALW 1 2 C374 1 2 0.1U_0402_16V4Z
R273 0_0603_5%
U19
+SPI_VCC EC_SPICS#/FSEL#
SPI_WP#
1
3
CE# VDD 8
6
+SPI_VCC
EC_SPICLK
To TP/B Conn.
U18 SPI_HOLD# WP# SCK EC_SO_SPI_SI
30 EC_SPICS#/FSEL# 7 HOLD# SI 5
EC_SPICS#/FSEL# 1 8 4 2 EC_SI_SPI_SO
R233 1 CE# VDD VSS SO
2 4.7K_0402_5% SPI_WP# 3 WP# SCK 6 R269 1 2 0_0402_5% EC_SPICLK 30
JP13
+3VALW R271 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R268 1 2 0_0402_5% MX25L1005AMC-12G_SOP8
HOLD# SI EC_SO_SPI_SI 30 +5VS 6
4 2 R236 1 2 0_0402_5% TP_CLK
VSS SO EC_SI_SPI_SO 30 30 TP_CLK 5
Reserved for BIOS simulator. TP_DATA
30 TP_DATA 4
MX25L8005M2C-15G_SOP8 LEFT_BTN#
@
Footprint SO8 RIGHT_BTN# 3
1 2
KSI[0..7] C259 1
1
INT_KBD Conn. KSO[0..17]
KSI[0..7] 30
C258
2
100P_0402_50V8J ACES_85201-0605
CONN@
KSO[0..17] 30
100P_0402_50V8J

JP15
To Media/B Conn. 2

(Left) KSO0 For ENE Cap sense IC +5VS +3VS TP_DATA

26 KSO0 G2 28
KSO1 25 27
KSO2 KSO1 G1 JP14 +5VS TP_CLK
24 KSO2
KSO3 23 R557 1 @ 2 0_0402_5%
KSO3 30 ESB_CLK 6

3
KSO4 22 R558 1 @ 2 0_0402_5%
KSO4 30 ESB_DATA 5
KSO5 21 R559 1 2 0_0402_5% C208
KSO5 6,30 EC_SMB_CK2 4
KSO6 20 R560 1 2 0_0402_5% D8
KSO6 6,30 EC_SMB_DA2 3
KSO7 19 0.1U_0402_16V4Z @
KSO7 30 EC_I2C_INT1 2
KSO8 18 2 2 2 2 PSOT24C_SOT23
KSO9 KSO8 1
17

1
KSO10 KSO9 C673 C674 C675 C677 ACES_85201-0605
16 KSO10
KSO11 15 CONN@
KSO12 KSO11 1 1 1 1
14
KSO13 13
KSO12 For EMI
KSO14 KSO13 SW1 SW2
12 KSO14

/
KSO15 11 100P_0402_50V8J 100P_0402_50V8J SMT1-05-A_4P SMT1-05-A_4P
KSO16 KSO15 100P_0402_50V8J 100P_0402_50V8J LEFT_BTN# 3 RIGHT_BTN#3
10 KSO16 1 1
KSO17 9
KSI0 KSO17

/x
8 KSI0 4 2 4 2
KSI1 7
KSI2 KSI1
6
To LED/B Conn. (POWER/B)

5
6

5
6
KSI3 KSI2
5 KSI3
KSI4 4
KSI5 KSI4 +3VS +5VS +5VALW
3 KSI5
KSI6 2 JP16

su
KSI7 KSI6
1 KSI7 1 1
(Right) 2 2
3 3
ACES_88747-2601 4
CONN@ 4 MEDIA_LED#
5 5
6 NUM_LED# ACIN# 1 2 +3VALW
6 NUM_LED# 30

p.
7 CAPS_LED# R258 100K_0402_5%
7 CAPS_LED# 30
8 PWR_LED# D15
8

1
KSO15 C55 100P_0402_50V8J KSO7 C47 100P_0402_50V8J D
1 2 1 2 9 9 ON/OFFBTN# 32 2 ARCADE# 30
10 PWR_SUSP_LED# Q18 2 ARCADE_BTN# 1
10 ACIN 14,21,30,37,39,42
KSO14 C54 1 2 100P_0402_50V8J KSO6 C46 1 2 100P_0402_50V8J 11 ACIN# G 3 51ON#
11 51ON# 32,39

om
12 LID_SW# 2N7002_SOT23 S
LID_SW# 30

3
KSO13 C53 100P_0402_50V8J KSO5 C45 100P_0402_50V8J 12 DAN202UT106_SC70-3
1 2 1 2 13 13 +3VALW
14 14
KSO12 C52 1 2 100P_0402_50V8J KSO4 C44 1 2 100P_0402_50V8J 17 15
G17 15
18 G18 16 16

KSI0 C58 1 2 100P_0402_50V8J KSO3 C43 1 2 100P_0402_50V8J ACES_85201-16051

CONN@ PWR_LED# PWR_SUSP_LED#

yc
KSO11 C51 1 2 100P_0402_50V8J KSI4 C62 1 2 100P_0402_50V8J

KSO10 C50 1 2 100P_0402_50V8J KSO2 C42 1 2 100P_0402_50V8J +5VALW +5VS +3VALW +3VS

3
KSI1 C59 1 2 100P_0402_50V8J KSO1 C41 1 2 100P_0402_50V8J
C664 C17 C401 C663
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

m
30 PWR_LED 2 30 PWR_SUSP_LED 5
KSI2 C60 1 2 100P_0402_50V8J KSO0 C40 1 2 100P_0402_50V8J Q20A Q20B

2
1

4
KSO9 C49 1 2 100P_0402_50V8J KSI5 C63 1 2 100P_0402_50V8J R264 R247
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 100K_0402_5% 100K_0402_5%
KSI3 C61 1 2 100P_0402_50V8J KSI6 C64 1 2 100P_0402_50V8J
//

1
KSO8 C48 1 2 100P_0402_50V8J KSI7 C65 1 2 100P_0402_50V8J LID_SW# C662 1 2 100P_0402_50V8J

MEDIA_LED# C655 1 2 100P_0402_50V8J

KSO16 C56 1 2 100P_0402_50V8J NUM_LED# C656 1 2 100P_0402_50V8J To FUN/B Conn.

p:

KSO17 C57 1 2 100P_0402_50V8J CAPS_LED# C657 1 2 100P_0402_50V8J +3VS +5VS

JP21

2
PWR_LED# C658 1 2 100P_0402_50V8J Q23A
6

2
ARCADE_BTN# 2N7002DW-T/R7_SOT363-6 R274 @
tt

ON/OFFBTN# C659 1 100P_0402_50V8J KSO0 5 100K_0402_5%

2 4
KSI5 1 6
3 25 5IN1_LED#
ACIN# C660 1 2 100P_0402_50V8J

1
2 SATA_LED# MEDIA_LED#
1 21 SATA_LED# 4 3
h

PWR_SUSP_LED# 1 2 100P_0402_50V8J
C661 ACES_85201-0605
CONN@ Q23B

5
2N7002DW-T/R7_SOT363-6
Compal Footprint R285 LED1 FOR EMI To BTN/B Conn. +3VS
1.5K_0402_5%
+5VS 1 2 3 YG 1 PWR_LED# JP17
1 +3VS
4 2 R284 KSO0 +5VS
4 2 PWR_SUSP_LED# 2 MINI1_LED#
+5VALW 1 2 A
3 MINI1_LED# 28
3 1 1.5K_0402_5% KSI1 WL_BTN# BT_LED#
4 BT_LED# 30
KSO0
HT-297UD/CB BLUE/AMB 0603 5 KSI1
KSI2 BT_BTN# 6 KSI2
7 KSI3
R286 LED2
KSI3 EMAIL_BTN# 8 KSI4
15" ONLY 1K_0402_5% KSI4 IE_BTN#
9
10
+5VALW 1 2 3 1 BATT_GRN_LED# BATT_GRN_LED# 30 11
YG

R287
KSI5 E-KEY_BTN# 12

+5VALW 1 2 4 A 2 BATT_AMB_LED# BATT_AMB_LED# 30 KSI6 PROGRAM_BTN# ACES_85201-1205

1K_0402_5% CONN@

HT-297DQ/GQ_AMB/YG_0603

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 31 of 50
 A B C D E

Power Button
ON/OFF switch HDA MDC Conn.
+3VALW
TOP Side +3VALW
1 2
1 R11 @ 10K_0603_5% 1
1

2
20mil C394
1 2 R194 JMDC1
R301 @ 10K_0603_5% 1U_0603_10V4Z
100K_0402_5% 2
1 GND1 RES0 2 1 2
Bottom Side 20 HDA_SDOUT_MDC 3 4 R283 0_0402_5%

1
D12 IAC_SDATA_OUT RES1
5 GND2 3.3V 6 +3VALW
2 ON/OFF 30 20 HDA_SYNC_MDC 7 IAC_SYNC GND3 8
ON/OFFBTN# 1 20 HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10
31 ON/OFFBTN# IAC_SDATA_IN GND4
3 51ON# R281 33_0402_5% 11 12
51ON# 31,39 20 HDA_RST_MDC# IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC 20

1
@ DAN202UT106_SC70-3
SW3 R280

GND
GND
GND
GND
GND
GND
SMT1-05-A_4P <BOM Structure> 0_0402_5%
ON/OFFBTN# 3 1
EMI Notice ACES_88018-124G

13
14
15
16
17
18

2
1
4 2 2 CONN@ 1
C329 D13 HDA_SNC_MDC ,HDA_SDOUT_MDC DONT Cross Mode C393
Connector for MDC Rev1.5
5
6

1000P_0402_50V7K RLZ20A_LL34 22P_0402_50V8J

1 2

/
For EMI

/x
1
D
EC_ON 2 Q15
30 EC_ON
G
2

S 2N7002_SOT23
R196 3

su
10K_0402_5%
2 2
1

p.
om
Power ON Circuit
+3VS

+3VALW +3VALW

yc
1

U21A U21B
R249 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
+3VALW CIR
P

P
2

m
1 I O 2 3 I O 4 1 2 SB_PWRGD 6,20
R254 @ 0_0402_5%
1

1
D
2
R501
37 SUSP 2 For South Bridge
7

G C349 100_0805_5%
Q19 S 1U_0805_25V4Z
//
3

2N7002_SOT23 1
30 EC_PWROK 1 2

2
R253 0_0402_5% IR1
3 RCIRRX 3
3 Vs OUT 4 RCIRRX 30
1 GND GND 2
+3VS
1
C645 TSOP36236TR_4P 1
p:

+3VALW +3VALW C644

4.7U_0805_10V4Z
1

2 1000P_0402_50V7K
R272 2
U21C U21D
14

14

tt

10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

D14 R267
@
P

P
2

SUSP# 1 2 5 6 9 8 1 2
29,30,37,45 SUSP# I O I O VLDT_EN 37,43,44
2
G

RB751V_SOD323 C377
For +VCCP/+1.05VS 0_0402_5%
7

0.1U_0402_16V4Z
1 R266

30 EC_VLDT_EN EC_VLDT_EN 1 2

0_0402_5%
+3VALW
C352
+3VALW
1 2 0.1U_0402_16V4Z

U21E U21F
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
R257 VGA@ 200K_0402_5%
P

SUSP# 1 2 11 10 13 12 1 2
I O I O VGA_ON 14
R250 0_0402_5%
G

1 2
7

4 4

D16 RB751V_SOD323 SUSP#

2 1 2
VGA@ C373 R252 @ 0_0402_5%

0.22U_0603_16V7K
VGA@ 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 32 of 50
A B C D E
 A B C D E F G H

+VDDA

1
R464
10K_0402_5%
+5VAMP
60mil U34 (output = 300 mA)

2
L70 1 2 1
1 2
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT 5 40mil +VDDA
C606 1U_0402_6.3V4Z 1 1 2 GND

1
L69 1 2 C607 C604 1 4.75V
R463 KC FBM-L11-201209-221LMAT_0805 3 4 C596
10K_0402_5% 10U_0805_10V4Z SHDN BYP
1 2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z 1
1 2
C595
BOM Option

2
C592
1 2 MONO_IN
1U_0402_6.3V4Z 2
ALC268 268@

1
C 1 2 0.01U_0402_16V7K
C575 1 R442 Q41 R461 2.4K_0402_1%
30 BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23

3
ALC888S-VC 888VC@
C574 1 R441
20 SB_SPKR 2 1 2
1U_0402_6.3V4Z

1
560_0402_5% L63
D24 MBK1608121YZF_0603
R445 RB751V_SOD323 10mil +3VS_DVDD 1 2 +3VS
10K_0402_5%
1 1
HD Audio Codec

2
C571 C572

/
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2

/x
+AVDD_HDA
L65
Intel: +1.5VS
40mil 10mil MBK1608121YZF_0603 AMD: +3VS
L66 1 2 0.1U_0402_16V4Z +1.5VS_DVDD 1 2 +3VS
+VDDA AMD SB700 only support +3VS I/O
FBM-L11-160808-800LMT_0603 1 1 1
C568 C589 1 1

su
C590 C581 C582
2 10U_0805_10V4Z 2

25

38

9
2 2 2 U31 0.1U_0402_16V4Z 10U_0805_10V4Z
0.1U_0402_16V4Z 2 2 MIC2_VREFO

DVDD
AVDD1

AVDD2

DVDD_IO

p.

1
14 35 AMP_LEFT
LINE2-L FRONT_L AMP_LEFT 34
R295
15 36 AMP_RIGHT 2.2K_0402_5%
LINE2-R FRONT_R AMP_RIGHT 34
15mil

om
1 2 MIC2_C_L 16 39 HP_LEFT-FRONT_LEFT
HP_LEFT-FRONT_LEFT 34

2
INT_MIC_R C598 4.7U_0805_6.3V6K MIC2_L SURR_L DMIC_CLK_R INT_MIC_R
1 2 MIC2_C_R 17 41 HP_RIGHT-FRONT_RIGHT R294 KC FBMA-L11-160808-121LMT_0603
MIC2_R SURR_R HP_RIGHT-FRONT_RIGHT 34
C599 4.7U_0805_6.3V6K DMIC_DATA_R 1
LINE_L-SURR_L 1 2 LINE_C_L 23 45 1 2 WOOFER_MONO R288 KC FBMA-L11-160808-121LMT_0603
C395
34 LINE_L-SURR_L LINE1_L SIDE_L WOOFER_MONO 35
C600 4.7U_0805_6.3V6K R432 0_0402_5%
LINE_R-SURR_R 1 2 LINE_C_R 24 46 1 2 DMIC_CLK 220P_0402_50V7K
34 LINE_R-SURR_R LINE1_R SIDE_R 2
C601 4.7U_0805_6.3V6K R431 268@ 0_0402_5%

yc
18 CD_L CENTER 43

20 CD_R LFE 44 1 2 1 2 C577

R440 10_0402_5% 22P_0402_50V8J
19 CD_GND
R456 1 2 0_0402_5% HP_PLUG# 6
38 D_HP_PLUG# BITCLK HDA_BITCLK_AUDIO 20

m
MIC1_L 1 2 MIC1_C_L 21

R454 1 2 0_0402_5% LINEIN_PLUG#

34 MIC1_L
MIC1_R
C610
1 2
4.7U_0805_6.3V6K
MIC1_C_R 22
MIC1_L
8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0 20
Digital/Analog MIC
38 D_LINEIN_PLUG# 34 MIC1_R MIC1_R SDATA_IN
C611 4.7U_0805_6.3V6K R437 33_0402_5%
MONO_IN 12 37 +3VS
PCBEEP PIN37_VREFO
38 D_MIC_PLUG#
R448 2 1 0_0402_5% MIC_PLUG#
// LINE1_VREFO 29 1
JP23
1
11 DMIC_CLK DMIC_CLK_R 2
3 20 HDA_RST_AUDIO# RESET# 2 3
31 R293 @ 0_0603_5% 3 5
LINE2_VREFO DMIC_DATA DMIC_DATA_R 3 GND
20 HDA_SYNC_AUDIO 10 SYNC 10mil R290 @ 0_0603_5%
4 4 GND 6
MIC1_VREFO_L 28 MIC1_VREFO_L
5 ACES_87213-0400G
p:
20 HDA_SDOUT_AUDIO SDATA_OUT
32 CONN@
MIC1_VREFO_R MIC1_VREFO_R

2
HDA_GPIO0 2
17,18,38 EC_DOCKIN#_S0 SPDIFO2
1 2HDA_GPIO3 3 GPIO0/DMIC_CLK MIC2_VREFO 30 MIC2_VREFO
D1
HP_PLUG# R457 2 1 39.2K_0402_1% R530 0_0402_5% SENSE_A 13 10mil SM05T1G_SOT23-3
34 HP_PLUG# SENSE A
LINEIN_PLUG# R455 1 2 10K_0402_1% CODEC_VREF @
34 LINEIN_PLUG# For EMI 34 27
tt

MIC_PLUG# R449 2 SENSE B VREF

34 MIC_PLUG# 1 20K_0402_1% 1 1
R577 2 1 47 40 C578 For ESD 10/11

1
30 EAPD MBK1005121YZF_0402 SPDIFI/EAPD JDREF C579

1
34,38 SPDIF 1 2SPDIF_R 48 SPDIFO SENSE C 33 0.1U_0402_16V4Z
2 2
h

R430
DMIC_DATA 1 2 MBK1005121YZF_0402 4 26 R433 10U_0805_10V4Z
R439 888VC@ 0_0402_5% GPIO1/DMIC_DATA AVSS1 20K_0402_1%
7 DVSS AVSS2 42

2
ALC888S-VC_LQFP48_7x7
Sense Pin Impedance Codec Signals 1 2
1
R468
2
0_0805_5%
1
R489
2
0_0805_5%
R438 268@ 0_0402_5%
39.2K PORT-A (PIN 39, 41) DGND AGND
1 2 1 2
R494 0_0805_5% R486 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) DMIC_DATA 1 2 HDA_GPIO0 R443 0_0805_5% R474 0_0805_5%
R435 268@ 0_0402_5%
14 SPDIF_HDMI 1 2
5.1K PORT-D (PIN 35, 36) R434 888VC@ 0_0402_5%

4
GND GNDA GND GNDA 4
39.2K PORT-E (PIN 14, 15) DMIC_CLK HDA_GPIO3
1 2
R436 888VC@ 0_0402_5%
20K PORT-F (PIN 16, 17)
SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC268
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 33 of 50
A B C D E F G H
 A B C D E

+5VAMP Int. Speaker Conn.

+3VS W=40mil
JP19
2 1 SPKL+ R50 1 2 0_0603_5% SPK_L+ 1
2 0.1U_0402_16V4Z SPKL- R49 SPK_L- 1
C638 1 2 0_0603_5% 2 2
C627 C630
Left

2
0.1U_0402_16V4Z
C622 1 2 D26
<BOM Structure> 1 3 G1
0.22U_0603_16V4Z 4.7U_0805_10V4Z SM05T1G_SOT23-3 4
AMP_RIGHT_C-1 AMP_RIGHT_C @ G2
33 AMP_RIGHT 1 2 1 2
C629 1U_0402_6.3V4Z 20mil ACES_88266-02001

11

19

20
10

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U36 CONN@

1
33 AMP_LEFT C621 C628 1U_0402_6.3V4Z

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.22U_0603_16V4Z JP20
1 R478 R479 SPKR+ R51 SPK_R+ 1
1 2 0_0603_5% 1 1
SPKR- R52 1 2 0_0603_5% SPK_R- 2
1K_0402_5% 1K_0402_5% SPKR+ 2
3 22
INR_A ROUT+ Right

2
5 21 SPKR-

2
INL_A ROUT- D27 3 G1
HPF Fc = 900Hz R492 1 2 100K_0402_5% 27 8 SPKL+ SM05T1G_SOT23-3 4
/AMP EN LOUT+ SPKL- @ G2
LOUT- 9
R491 1 2 100K_0402_5% 24 +5VAMP ACES_88266-02001
+5VAMP HP EN
17 HPOUT_R CONN@

1
HP_RIGHT-FRONT_RIGHT 1 HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L +5VAMP HP_PLUG#
33 HP_RIGHT-FRONT_RIGHT 2 2 4 INR_H HP_L 18 HP_PLUG# 33
C624 2.2U_0603_6.3V6K R482 39K_0402_5% HP_LEFT_R 6 INL_H

2
HP_LEFT-FRONT_LEFT 1 2 HP_LEFT_C 1 2
33 HP_LEFT-FRONT_LEFT

3
C623 2.2U_0603_6.3V6K R481 39K_0402_5% VOL_AMP 26 R484
/SD
CVSS 15 100K_0402_5%

2
28 Q45B
BEEP R485 2N7002DW-T/R7_SOT363-6
16 5

6 1
VSS
1 12 CP+ 1 100K_0402_5%
C632 14 2 C636

4
CP- GND
23 1U_0603_10V4Z

1
PGND

3
S
1U_0603_10V4Z 25 7 Q45A
2 BIAS PGND 2 G
SPDIF_PLUG# 2N7002DW-T/R7_SOT363-6
CGND 13 2 2

/
+5VAMP 1 29
C635 GND D Q44

1
APA2057A_TSSOP28 20mil AO3413_SOT23-3
2.2U_0603_6.3V6K S/PDIF Out JACK

/x
2 +5VSPDIF
LINE Out/Headphone Out
1

R490
42.2K_0402_1%

su
2

2 VOL_AMP 2
Gain= 6dB 2 2
1

D C634 C631
1

1 2 EC_MUTE
EC_MUTE 30,35
R493 C637 G 330P_0402_50V7K 330P_0402_50V7K

p.
61.9K_0402_1% S Q46 1 1 JHP1
3

For Docking 1
2
0.01U_0402_16V7K 2N7002_SOT23 2
2

HPOUT_L 1 R488 2HPOUT_L_1

1 2 HPOUT_L_2 6
D_HPOUT_L R487 1 2 56.2_0603_1% HPOUT_L 56.2_0603_1% L74 FBMA-L11-160808-800LMT_0603 3
38 D_HPOUT_L

om
D_HPOUT_R R480 1 2 56.2_0603_1% HPOUT_R HPOUT_R 1 R483 2HPOUT_R_1
1 2 HPOUT_R_2
38 D_HPOUT_R
56.2_0603_1% L73 FBMA-L11-160808-800LMT_0603 SPDIF_PLUG# 5

4
SPDIF 7
33,38 SPDIF
8
For Docking +5VSPDIF
1 10
@
D31

yc
D_LINE_L R459 1 2 75_0603_1% LINE_R-SURR_R C633 9
38 D_LINE_L
D_LINE_R R446 1 2 75_0603_1% LINE_L-SURR_L 3
38 D_LINE_R 2
1 SINGA_2SJ-E373-T01
SPDIF_PLUG# 2 100P_0402_50V8J CONN@

m
PSOT24C_SOT23
For Docking LINE-IN JACK
For EMI FOR EMI
D_MIC_L R475 1 2 75_0603_1% MIC1_R JLINE1
38 D_MIC_L
D_MIC_R R470 1 2 75_0603_1% MIC1_L 8
38 D_MIC_R
// 7

3 LINEIN_PLUG# 3
33 LINEIN_PLUG# 5
R465 1 2 0_0603_5%
38 AUDIO_GNDA
R553 75_0603_1% 4
p:

LINE_R-SURR_R 1 2 1 2 LINE_R_R 3
33 LINE_R-SURR_R
L68 FBMA-L11-160808-800LMT_0603 6
LINE_L-SURR_L 1 2 1 2 LINE_L_R 2
33 LINE_L-SURR_L
L67 FBMA-L11-160808-800LMT_0603 1
R554 75_0603_1% 1 1
tt

SINGA_2SJ-E351-S03
Volume Control Circuit +3VS
C593
220P_0402_50V7K
C603
220P_0402_50V7K
CONN@
+3VS 2 2 (HDA Jack)
h 1

C642
2 1 R495
+3VS
MIC JACK
1

100K_0402_5%
R500 R496 0.1U_0402_16V4Z FOR EMI
4

U37 10K_0402_5% 10K_0402_5% JMIC1

2

+3VS MIC1_VREFO_L MIC1_VREFO_R 8

GND

U39 1 7
2

C639
P

NC

1
2 1 2 2 4 0.1U_0402_16V4Z
A R497 10K_0402_5% A Y MIC_PLUG#
33 MIC_PLUG# 5
G

2 R472 R476
1 NC7SZ14P5X_NL_SC70-5 U38 2.2K_0402_5% 2.2K_0402_5% 4
3

COM R555 75_0603_1%

1 14

2
CD1# VCC MIC1_R MIC2_R_1
2 D1 CD2# 13 33 MIC1_R 1 2 1 2 3
3 1 2 3 12 L72 FBMA-L11-160808-800LMT_0603 6
B R499 10K_0402_5% CP1 D2 MIC1_L MIC2_L_1
4 SD1# CP2 11 33 MIC1_L 1 2 1 2 2
1 1 5 10 L71 FBMA-L11-160808-800LMT_0603 1
GND

Q1 SD2#
0.01U_0402_16V7K

0.01U_0402_16V7K

C640 C641 6 09 1 R556 75_0603_1% 1 1

4 Q1# Q2 SINGA_2SJ-E351-S01 4
7 GND Q2# 08
XRE094PHDINB1-2-12-E-7016_3P C643 C616 C618 CONN@
5

2 2 TC74LCX74FT_TSSOP14 220P_0402_50V7K 220P_0402_50V7K

0.1U_0402_16V4Z
2 2 2
(HDA Jack)
ENCODER_DIR 30
ENCODER_PULSE 30 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 34 of 50
A B C D E
 5 4 3 2 1

D D

/
/x
su
C C

p.
om
+5VAMP

Gain = 5.1dB(BTL Mode)

yc
Fc(low)= 2KHz C652
1 2
R518 1.8K_0402_5% C650
1 2 10U_0805_10V4Z 0.1U_0603_25V7K

m
2 1

C651 0.01U_0603_50V7K
1 2
Fc(high)= 482Hz
+5VAMP U40
//
6 1 MUTE_WOOFER# 1 2 +5VAMP
B C646 R516 R517 VDD SHUTDOWN# 100K_0402_5% R467 JP27 B

33 WOOFER_MONO
WOOFER_MONO 1 2 1 2 1 2 WOOFER_IN- 4 IN- Vo+ 5 WOOFER+ 30mil 1 1
4.7K_0402_1% 2 2
p:

0.33U_0603_16V4Z 1K_0402_1% 1 WOOFER_IN+ 3 8 WOOFER- 3

IN+ Vo- G1
4 G2
C647 2 7
BYPASS GND

1
D
2
0.068U_0603_16V7K ACES_87213-0200
2 EC_MUTE 30,34
tt

G
2 APA3011XA-TRL_MSOP8 Q40 S CONN@

3
2N7002_SOT23
C648
h

2.2U_0603_6.3V4Z
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUB WOOFER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
JALB0 LA-4171P 1.0

Date: Friday, April 18, 2008 Sheet 35 of 50

5 4 3 2 1
 H24 H22 H7 H20 H5 H13
H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4

FAN1 Conn @ @ @ @ @ @

1
+5VS
C435 10U_0805_10V4Z +5VS H2 H25 H14 H17 H10 H1
1 2 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H23
H_3P25

1
U26 D19 @ @ @ @ @ @

1
1 8 1SS355_SOD323-2 @

1
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6

2
EN_DFAN1 VO GND D20 H4 H19 H18 H8 H12
30 EN_DFAN1 4 VSET GND 5
1 2 Change to SC1BAS16000 H_3P25 H_3P25 H_3P25 H_3P25 H_3P25
G993P1UF_SOP8
BAS16_SOT23-3
C429 @ @ @ @ @

1
10U_0805_10V4Z
1 2
+3VS C425 H3 H11 H15 H16 H9
1000P_0402_50V7K H_3P25 H_3P25 H_4P2 H_4P2 H_4P2
1 2

/
R310 @ @ @ @ @

1
10K_0402_5%
40mil JP26

/x
2

+VCC_FAN1
1
30 FAN_SPEED1 2
3
1
C411 ACES_85205-03001
1000P_0402_50V7K CONN@

su
2

H6 H21
H_4P0N H_4P6X4P0N

p.
@ @

1
om
FD1 FD2 FD3 FD4

@ @ @ @

1
yc
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

m
//
p:
tt
h

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 36 of 50
 A B C D E

+5VALW TO +5VS +5VALW

+5VALW +5VS

2
U14 R177
8 1 100K_0402_5%
D S
7 D S 2

2
6 3 1 1

1
D S C318 C314 R193
1 1 5 D G 4
C309 C310 470_0603_5% SYSON#
28,29,38,45 SYSON#
AO4468_SO8 10U_0805_10V4Z

1
10U_0805_10V4Z 2 2
1U_0603_10V4Z D

1
1 2 2
10U_0805_10V4Z SYSON Q11 1
29,30,44 SYSON 2
G 2N7002_SOT23

1
D
S

3
1
2 SUSP
G R171
+VSB 2 1 5VS_GATE S Q13 100K_0402_5%

3
R212 2N7002_SOT23
200K_0402_5% 1

2
1

2
D C328
SUSP 2 R541
Q14G 0.1U_0603_25V7K
2N7002_SOT23 S @ 2 +5VALW
3

1M_0402_5%

2
1

D R276
ACIN 2 100K_0402_5%
14,21,30,31,39,42 ACIN G
Q43 S
3

1
2N7002_SOT23 SUSP
32 SUSP
@

1
D
2 Q24
29,30,32,45 SUSP#
2N7002_SOT23

/x
G
S

3
1
+3VALW TO +3VS R275
10K_0402_5%
+3VALW +3VS +1.2VALW +1.2V_HT

su

2
U22 U1
2 2
8 D S 1 8 D S 1
7 D S 2 7 D S 2
2

2
6 D S 3 1 1 6 D S 3 1 1
1 1 5 4 C391 C388 R277 1 5 4 C16 C15 R10
C375 C376 D G 470_0603_5% C14 D G 470_0603_5%

p.
AO4468_SO8 10U_0805_10V4Z SI4856ADY_SO810U_0805_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z +5VALW
1 1

1
2 2
10U_0805_10V4Z 2
10U_0805_10V4Z
D

2
5VS_GATE D
2 SUSP

om
G 2 VLDT_EN# R191
S Q25 G 100K_0402_5%
3

2N7002_SOT23 +VSB 2 1 1.2V_GATE S Q26

3
R306 2N7002_SOT23

1
150K_0402_5% VLDT_EN#
VLDT_EN#

2
+1.8V to +1.8VS 1

1
D R543 C407

1
VLDT_EN# 2 D
+1.8V +1.8VS

yc
Q27G 0.1U_0603_25V7K 2 Q12
2 32,43,44 VLDT_EN
2N7002_SOT23 S @ G 2N7002_SOT23

1
U11 S

3
1
8 1 1M_0402_5%
D S R186
7 D S 2 1 1
2

6 3 C269 C270 10K_0402_5%

D S

1
D

m
1 1 5 4 R163
C286 C285 D G 10U_0805_10V4Z 470_0603_5% ACIN 2

2
SI4856ADY_SO8 2 2
1U_0603_10V4Z G
10U_0805_10V4Z Q58 S
1

3
2 2
10U_0805_10V4Z
// 2N7002_SOT23
SI4856/AO4430 @
1

D
2 SUSP
3 G 3

+VSB 2 1 1.8VS_GATE S Q37

3

R424 2N7002_SOT23
510K_0402_5% 1
p:
2

C564
1

D R542
SUSP 2 0.1U_0603_25V7K
G 2
Q39 S @
3

tt

2N7002_SOT23
1M_0402_5%
1

D
h

ACIN 2
G
Q51 S
3

2N7002_SOT23
@

+1.5VS +2.5VS +1.1VS +0.9V +1.8V

2

R270 R423 R544 R170 R173

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
1

4 4
1

D D D D D
2 SUSP 2 SUSP 2VLDT_EN# 2 SYSON# 2 SYSON#
G G G G G
S Q22 S Q38 S Q57 S Q10 S Q9
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4181P
Date: Friday, April 18, 2008 Sheet 37 of 50
A B C D E
 +3VS

1
+3VS R532
10K_0402_5%
+3VALW

3 2
R265
EC_DOCKIN#_S0 17,18,33

1
10K_0402_5%
R259
Q54B

2
10K_0402_5% 5 2N7002DW-T/R7_SOT363-6

4
Q54A
20,27,30 EC_DOCKIN# 2

1
2N7002DW-T/R7_SOT363-6

EC_DOCKIN 17

+5VALW

1
C672

22U_0805_10V4Z @
2

/
10/15 Acer DVR 1028 Rev0.3

/x
JDOCK1
DOCK_B+ 67 ACER DOCK 65
19V_5A GND
+5VALW 68 66

su
5V_USB_3A GND
+3VALW
Normal
33 D_LINEIN_PLUG# 33 LIN_IN_DT# GND 1
34 D_LINE_L 34 LIN_IN_L DVI_CLK 2 D_DVI_TXC+ 17
1

46 P3 P1 1
34 D_LINE_R 35 LIN_IN_R DVI_CLK# 3 D_DVI_TXC- 17
R297 47 (67) (65) 2
33 D_MIC_PLUG# 36 MIC_DT# GND 4

p.
48 3
10K_0402_5% 34 D_MIC_L 37 MIC_L DVI_TX0 5 D_DVI_TXD0+ 17
49 33 20 4
34 D_MIC_R 38 MIC_R DVI_TX0# 6 D_DVI_TXD0- 17
AUDIO_GNDA 50 34 21 5
34 AUDIO_GNDA 39 7
2

DOCKIN# GNDA 51 35 22 6 GND

30 DOCKIN# 40 DOCK_DT1# DVI_TX1 8 D_DVI_TXD1+ 17
52 36 23 7
1 33,34 SPDIF 41 SPDIF 24 DVI_TX1# 9 D_DVI_TXD1- 17

om
C396 53 37 8
42 GND GND 10
D_LAN_MIDI2+ 54 38 25 9
27 D_LAN_MIDI2+ 43 LAN_2 DVI_TX2 11 D_DVI_TXD2+ 17
0.1U_0402_16V4Z D_LAN_MIDI2- 55 39 26 10
27 D_LAN_MIDI2- 44 LAN_2# DVI_TX2# 12 D_DVI_TXD2- 17
2 56 40 27 11
45 GND 28 12 GND 13
57 41
VGA_R 14 D_CRT_R 18
58 42 29 13
59 43 30 14 GND 15
46 GND VGA_G 16 D_CRT_G 18
USB20_P3 60 44 31 15
20 USB20_P3 47 USB GND 17
61 45 32 16

yc
USB20_N3 48 18
20 USB20_N3 USB# 62 17 VGA_B D_CRT_B 18
28,29,37,45 SYSON# 49 USB_EN# GND 19
63 P4 P2 18
50 RESERVED 64 (68) (66) 19
18,20 CRT_DET# 51 VGA_DT#
+3V_LAN R296 1 @ 2 0_0603_5% +LAN_VCC 52 20 DOCK_DT2# R289 1 2 1K_0402_5%
LAN_PWR DOCK_DT2#
27 D_LAN_ACTIVITY# 53 LAN_ACT HP_L 21 D_HPOUT_L 34

m
27 D_LAN_LINK# 54 LAN_LINK HP_R 22 D_HPOUT_R 34
55 GND HP_DT# 23 D_HP_PLUG# 33
27 D_LAN_MIDI0+ D_LAN_MIDI0+ 56 24 AUDIO_GNDA
D_LAN_MIDI0- LAN_0 GNDA
27 D_LAN_MIDI0- 57 LAN_0# DVI_DT 25 D_DVI_DET 17
58 GND DVI_DCDT 26 D_DVI_SDATA 17
27 D_LAN_MIDI1+
27 D_LAN_MIDI1-
D_LAN_MIDI1+
D_LAN_MIDI1-
// 59
60
LAN_1
LAN_1#
DVI_DDCCK
VGA_VS
27
28
D_DVI_SCLK 17
D_CRT_VSYNC 18
61 GND VGA_HS 29 D_CRT_HSYNC 18
27 D_LAN_MIDI3+ D_LAN_MIDI3+ 62 30
LAN_3 VGA_DDCCK D_CRT_CLK 18
27 D_LAN_MIDI3- D_LAN_MIDI3- 63 31
LAN_3# VGA_DDCDT D_CRT_DATA 18
64 GND 5V_S0 32 +5VS
p:

72 GND GND 69
73 GND ACER DVR1027 Rev: 0.5 GND 70
74 GND GND 71
tt

JAE_SP07-10207-22
CONN@
h

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CABLE DOCK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0 LA-4171P
Date: Friday, April 18, 2008 Sheet 38 of 50
 A B C D

PD11
2
DOCK_B+ 1
3

1
@ PC158
@PC158 PDS1040-13_POWERDI5-3
470P_0402_50V7K
SP02000EF00

2
1
PJP1 1

PR1
6 1M_0402_1%
G2
1 2
5 PL1
G1 VIN
SMB3025500YA_2P PJ1 VIN VS VIN
DC_IN_S1 1 2 DC_IN_S2 2 1
2 1

1
4 4
JUMP_43X79 PR2 PR3
10K_0402_5% 84.5K_0402_1%
3 PR5
3

8
PU1A 22K_0402_5%
ACIN 14,21,30,31,37,42

2
470P_0402_50V7K

470P_0402_50V7K
PC159

PC161
PC1 PC2 PC3 PC4 PD2 3 1 2

P
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J +
2 1 2 2 1 1

2
2 0

20K_0402_1%
- 2

1
G

PR6
PR4 1SS355TE-17_SOD323-2

1
PR7

PC5
0.1U_0603_25V7K
1 0_0402_5% LM358DT_SO8 PC6

4
1 PD3 1000P_0402_50V7K

2
RLZ4.3B_LL34

2
@
E&T_4510-E04C-01R

10K_0402_5%
2

2
/
/x
1 2 RTCVREF
PR8
10K_0402_5%

su
2
RTC Battery Vin Dectector 2

Min. Typ Max.

- +

p.
PBJ1 H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT +RTCBATT L-->H 17.430V 17.901V 18.384V

om
@ MAXEL_ML1220T10

SP093MX0000

yc
PJ2 PJ3
VIN 2 1 2 1
+3VALWP 2 1 +3VALW +1.8VP 2 1 +1.8V

m
@ JUMP_43X118 @ JUMP_43X118
2

(8.61A,400mils ,Via NO.= 20) (12.06A,480mils ,Via NO.=24)

PD4 PC165 470P_0402_50V7K
RLS4148_LL34-2
// PJ4
1 2
PJ5
1

+5VALWP 2 2 1 1 +5VALW +0.9VP 2 2 1 1 +0.9V

BATT+ 2 1
1

3 3

@ JUMP_43X118 @ JUMP_43X79
PD5 PR9 PR10 (8.61A,400mils ,Via NO.= 20) (2A,80mils ,Via NO.= 4)
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
p:

TP0610K-T1-E3_SOT23-3
PR11
PJ6
2

200_0603_5% PJ7
CHGRTCP 1 2 N1 3 1 VS +VSBP 2 1 +VSB +1.1VSP 2 1 +1.1VS
2 1 2 1
tt

@ JUMP_43X39 @ JUMP_43X118
1

PC8 (120mA,40mils ,Via NO.= 2) (1.9A,80mils ,Via NO.=4)

PR12 0.1U_0603_25V7K
h

100K_0402_1% PC7
2

0.22U_0603_25V7K PJ8 PJ9

2

+1.2VALWP 2 1 +1.2VALW +2.5VSP 2 1 +2.5VS

2 1 2 1
31,32 51ON# 1 2
PR13 @ JUMP_43X118 @ JUMP_43X118
22K_0402_1% (3.94A,160mils ,Via NO.=8)
(1.0A,40mils ,Via NO.=2)
RTCVREF PJ10 PJ11
1

+NB_COREP 2 1 +NB_CORE +1.5VSP 2 1 +1.5VS

PR14 2 1 2 1
200_0603_5% @ JUMP_43X118 @ JUMP_43X118
PR15 PR16 PU2 G920AT24U_SOT89-3 (8.8A,360mils ,Via NO.=18)
560_0603_5% 560_0603_5% 3.3V (1.0A,40mils ,Via NO.=2)
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN
1

GND
4
PC9 PC10 4

10U_0805_10V4Z 1
2

1U_0805_25V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0
Date: Friday, April 18, 2008 Sheet 39 of 50
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
VL
VL

VMB

2
SUYIN_200275MR007G161ZL
@ PL2 PR17
PJP2

1
1 1

SMB3025500YA_2P 100K_0402_1%
1 2 PH1 PC11
1 BATT+ MAINPWON 6,41
100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
2 100K_0402_1%
3

1
EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR19 PQ2
5

8
1000P_0402_50V7K 0.01U_0402_25V7K 18K_0402_1% PU3A DTC115EUA_SC70-3

2
6 PD6
1 2 3

P
7 +
O 1 2 1 2
TM_REF1 2 -

G
RLS4148_LL34-2
LM393DG_SO8

3
2

0.22U_0603_16V7K
PR20 PR21

11.3K_0402_1%
100_0402_1% 100_0402_1%

1
PC14

1000P_0402_50V7K
PR22
1

2 1 VL

1
PR24

PC15
6.49K_0402_1% PR23

/
2
2 1 100K_0402_1%
+3VALWP

1
/x
1

PR25
PR26 100K_0402_1%
1K_0402_1%

2
su
2

2 2

BATT_TEMP 30

p.
EC_SMB_CK1 6,14,30 PH2 near main Battery CONN :
BAT. thermal protection at 92 degree C
EC_SMB_DA1 6,14,30
Recovery at 56 degree C

om
VL

2
PR27
VL @ 100K_0402_1%

yc
PR28
@ 100K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
PH2

m
@ 100K_0603_1%_TH11-4H104FT VL
B+ 3 1 +VSBP

2
100K_0402_1%

0.22U_0603_25V7K

0.1U_0603_25V7K

@PR30
@ PR30
1

8
// 18K_0402_1% PU3B
1

1
PR29

PC16

PC17

1 2 5 PD7

P
+
O 7 2 1
TM_REF1 6
2

G
3 3

PR31 @ RLS4148_LL34-2
2

1
22K_0402_1% @ LM393DG_SO8

4
VL 1 2 PC18 PR32
p:

@ @ @ 0.22U_0603_16V7K 11.3K_0402_1%

2
2

PR33
100K_0402_1%
tt

PR34
1

0_0402_5% D
1 2 2 PQ4
h

41,43 POK
G SSM3K7002F_SC59-3
0.1U_0402_16V7K

S
3
1

PC19
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0
Date: Friday, April 18, 2008 Sheet 40 of 50
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PR35
PJ12
0_0805_5%
2 2 1 1 1 2
D D

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
@ JUMP_43X118

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22

8
7
6
5

1
PC25
PC166 VL

2
470P_0402_50V7K

PC23

PC24
2

1U_0603_10V6K
PQ6

2
2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0805_6.3V6K
4

1
PC27
4

PC28
1
+5VALWP

3
2
1
1
2
3
PL3

7
PL4 PU4 PC29 2 1
1 2 1U_0603_10V6K 8.2UH_PCMB063T-8R2MS_4.5A_20%

LDO
VIN

VCC
+3VALWP 8.2UH_PCMB063T-8R2MS_4.5A_20% 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
/
1

8
7
6
5
4.7_1206_5%

@ PR37
DH3 26 15 DH5
UGATE2 UGATE1

@ PR36
PR38 PR39 PQ8
0_0402_5%

/x
PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
2

1 AO4712_SO8 0_0603_5%

2
2

2
PR40

61.9K_0402_1%
0_0603_5% PC32 4

2
PC30 + 4 PC31

2
680P_0603_50V7K
330U_D3L_6.3VM_R25M 0.1U_0603_25V7K 0.1U_0603_25V7K

1
1
680P_0603_50V7K

PR41
LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

su
PC33

PC34
3
2
1

2
C + PC35 C

1
2
3
DL3 23 18 DL5 @ 150U_D2E_6.3VM_R18

1
@ LGATE2 LGATE1
2
10K_0402_1%
2

22

p.
PGND

2
PR42

FB3 30 OUT2

10K_0402_1%
PR43
OUT1 10
VL 32
1

REFIN2

om
@

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
9

yc
BYP
8 LDOREFIN @ PR44 0_0402_5%
SKIP 29 2 1 VL
PR45 0_0402_5%

m
1 2
20 NC POK2 28
PD8 PR46
VS RLZ5.1B_LL34 100K_0402_1%
POK 40,43
1 2 1 2
// 4 EN_LDO POK1 13 PR48
0.22U_0603_25V7K
2
200K_0402_5%

330K_0402_1%
2

B B
PR47

PC37

14 12 ILM1 2 1
EN1 ILIM1
PR49
1

p:

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2
1

NC
2

PD12 2 330K_0402_1%

0_0402_5%
1SS355_SOD323-2 @ PR50 ISL6237IRZ-T_QFN32_5X5

21
VL 0_0402_5%
tt
806K_0603_1%

PR51
2

1
PR52

2VREF_ISL6237 1

1
PC163
1U_0603_6.3V6M
h

PR54 @ PR55 PR53

0_0402_5% 47K_0402_5% 0_0402_5%
+5VALWP Ipeak=8.444A ; Imax=5.91A
1

2
6,40 MAINPWON
2 1 1 2
2VREF_ISL6237 2
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
0.047U_0402_16V7K

0.047U_0402_16V7K

Ilimit=165mV/18m ~ 165mV/15m
1

1
PC38

=9.167A ~ 11A
3

PC39
2

Iocp=Ilimit+Delta I/2
=9.7285A ~ 11.5615A
2
@ Delta I=1.123A (Freq=400KHz)
PQ38
TP0610K-T1-E3_SOT23-3
+3.3VALWP Ipeak=8.444A ; Imax=5.91A
A A
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
1

Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A Security Classification Compal Secret Data Compal Electronics, Inc.
Iocp=Ilimit+Delta I/2 Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title
+5V/+3V
=9.721A ~ 11.554A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Delta I=1.108A (Freq=300KHz) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
JALB0 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 41 of 50
5 4 3 2 1
 A B C D

B+
PQ9 PQ10
AO4407_SO8 AO4407_SO8 PR56
VIN 8 1 1 8 0.015_2512_1%
7 2 2 7 PJ13
6 3 3 6 1 4 2 1 CHG_B+
2 1

1
5 5

2
2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 @ JUMP_43X118 PR57
PC40 100K_0402_1%

CHGEN#
4

2
0.01U_0402_25V7K
PR58 0.01U_0402_25V7K

1
2

100K_0402_1%

PC42

PC43

PC45
3.3_1210_5% PC41

2
1
0.01U_0603_50V7K PC46 PC48

1 2

1
2

5
6
7
8

3
2
1
1 1

PC44
0.1U_0402_16V7K PU5 0.1U_0603_25V7K

1
/BATDRV

PR59
1 2 1 28 PVCC 1 2 PQ12
PR182 CHGEN PVCC
AO4407_SO8

1
3.3_1210_5% PR61 4

2
PC47 PC49 2.2_0603_5% PQ11
0.1U_0603_25V7K @0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8
1 2

2
BTST

2
PR60

1
@PD9
@ PD9 PC50 340K_0402_1% ACN 2 26 DH_CHG
RLZ24B_LL34 2.2U_0805_25V6K ACP ACN HIDRV
3

3
2
1

5
6
7
8
2 ACP PR62

1
ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH PD10 10UH_PCMB104T-100MS_6A_20% BATT+

5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M
1

10U_1206_25V6M
RLS4148_LL34-2 PC51

REGN
2 3

2
Icharge=(Vsrset/Vvdac)*(0.1/PR36) 0.1U_0603_25V7K PR65

5
6
7
8

PC53
PR64 4.7_1206_5%

PC52
90W adapter 54.9K_0402_1% ACSET 6 ACSET
24

2
REGN
Iadapter=(Vacset/Vvdac)*(0.1/PR48)=4.04A

/
1

1
PC55 PQ13

680P_0603_50V8J
65W adapter 1U_0603_10V6K 4 AO4466_SO8

PC56
/x
2
2

Iadapter=(Vacset/Vvdac)*(0.1/PR48)=2.90A
1 2 7 ACOP

2
Input OVP : 22.3V PR67 PC57 23 DL_CHG

3
2
1
340K_0402_1% 0.47U_0603_16V7K LODRV
Input UVP : 17.26V
1

22

su
OVPSET PGND PC58
Fsw : 300KHz 8 OVPSET
2
0.1U_0402_16V7K 2

1 2
9 AGND LEARN 21 ACOFF 30
2

24751_VREF

1
CELLS GND 3 Cell PR68

p.
54.9K_0402_1% PC59 PC60
2

VREF 4 Cell 24751_VREF 20 CELLS 0.1U_0603_25V7K @0.1U_0603_25V7K

2
PR69 CELLS
1

100K_0402_1% 24751_VREF 10
VREF

om
2

1
1 2 PC61
1

1U_0603_10V6K
@PR70
@ PR70 0_0402_5% PR71 19 SE_CHG+

2
CELLS 100K_0402_1% SRP
11 18 SE_CHG-
1

PQ14_GATE VDAC SRN

2
1

D
BAT 17
2

yc
3S/4S# 30
1

1
G PQ15 PQ14 VADJ 12
SSM3K7002F_SC59-3 PC62 SI2301BDS-T1-E3_SOT23-3 VADJ PC63
S
3

0.1U_0603_25V7K 0.1U_0603_25V7K
2

2
ACSET 29 CC=0.2~4.26A
ACGOOD# TP
Cells selector 13 ACGOOD ICHG setting Iref=0.77448*Icharge

m
Iref=0.155~3.3V 24751_VREF
RTCVREF 1 2 PR73
16 SRSET 2 1 IREF 30
PR72 /BATDRV SRSET
14 BATDRV 17.4K_0402_1%

2
100K_0402_1% PR76

1
24751_VREF 24751_VREF
// IADAPT 15
10_0603_5%
1 2
PR74
100K_0402_1% PC64
@
PR75
@0.01U_0402_25V7K 100K_0402_1%

2
200K_0402_1%

BQ24751ARHDR_QFN28_5X5

1
1

3 3
100K_0402_1%
1

1
PR196

PQ14_GATE
ACIN 14,21,30,31,37,39
PR194

PC65
p:

1
100P_0402_50V8J D

2
1

D PQ39 ACGOOD# PQ16

2
2

2 SSM3K7002F_SC59-3 VMB G SSM3K7002F_SC59-3

2

G S @

3
1

D
499K_0402_1% 340K_0402_1%

PC168 S 30 ADP_I
tt 3

ACOFF 1 2 2 VS
PR77

G
0.1U_0402_16V7K @PR188
@ PR188
LI-3S :13.5V----BATT-OVP=1.5V S
3
1
340K_0402_1%

0.01U_0402_25V7K

PQ40 0_0402_5% 24751_VREF

h
PR195

SSM3K7002F_SC59-3 1 2
2

1
LI-4S :18V----BATT-OVP=1.998V
1

PC66

PR80
1

887K_0402_1%
2

PR78

BATT-OVP=0.111*BATT+
2

24751_VREF

2
PR82

S
REGN VADJ

D
3 1 1 2
2
8

2
PR63 PR79 PU1B 0_0402_5%
64.9K_0402_1% 10K_0402_1% 5 PR83
P

4.3K_0402_5%
ACSET PQ17

G
24751_VREF 1 2 30 BATT_OVP 1 2 7 100K_0402_1%

2
0

1
6 PR84 SI2301BDS-T1-E3_SOT23-3
-

1
G

105K_0402_1%

PR189
100K_0402_1%

1
1

0.01U_0402_25V7K

LM358DT_SO8 PR85 CHGEN#

4

1
PR81

PR183 221K_0402_1%
2
PC67

100K_0402_1%

2
1

1
@ D
2

2
1
PR66 D PQ18
30 FSTCHG 2
1 2

PQ37 100K_0402_1% 2 PQ19 G SSM3K7002F_SC59-3

4
SSM3K7002F_SC59-3 D 30 Calibrate# G RHU002N06_SOT323-3 S 4

3
2 S
2

30 65W/90W# G
S
3

Charger ADJ Calibrate# PR80 PR85

4.0V L @ 0 Security Classification Compal Secret Data Compal Electronics, Inc.

CP setting Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title
4.1V L 887K 221K CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
4.2V H 887K 221K 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0
Date: Friday, April 18, 2008 Sheet 42 of 50
A B C D
 A B C D

POWER_SEL
FB1_NB_COREP PL6
PC68 PC69

1
HIGH 1.0V 1U_0402_6.3V6K 1U_0402_6.3V6K B+ 1 2 ISL6228_B+
+5VALW

470P_0402_50V7K

470P_0402_50V7K
FBMA-L11-322513-151LMA50T_1210

1
PC164

PC162
LOW 1.1V PR86
@ 12K_0402_1% PR88 PR89

1
+5VALW 2 1 1 2 +5VALW

2
PR87 @

1
1 1

@ 10K_0402_1% 2.2_0603_1% 2.2_0603_1%

PR90

1
@ 0_0402_5% D

2
1 2 2
PQ21 G

1
@ SSM3K7002F_SC59-3 D PC70 PC71
S

3
1 2 2 PQ20 0.1U_0603_25V7K 0.1U_0603_25V7K
11 POWER_SEL

1
PR91 G @ SSM3K7002F_SC59-3

2
@ 0_0402_5% S

3
1
PC72 ISL6228_B+ 2 PR92 1 2 PR93 1 ISL6228_B+

2
PC73 @ 0.1U_0402_16V7K
@ 0.01U_0402_25V7K 2 10_0603_1% 10_0603_1%

2
PR95

1
PC74 PR94 PC75 18.2K_0402_1%
1000P_0402_50V7K 22K_0402_1% 1000P_0402_50V7K

2
PC76 PR96

/
2

1
1000P_0402_25V8J 3.3K_0402_5% PR97
2 1 1 2 102K_0402_1%

/x
1

1
2 1 FB1_NB_COREP
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
PR98 GND_T

2
86.6K_0402_1%
PR99

su
1 2 8 28 PR100 PR101 PC77
2 FB1 PGOOD2 66.5K_0402_1% 3.3K_0402_5% 1000P_0402_25V8J 2

7.87K_0402_1% 2 1 1 2

1
ISL6228_B+ PR102
9 27 FB2_1.2V 1 2

p.
VO1 FB2
4.7U_1206_25V6K

4.7U_1206_25V6K

68.1K_0402_1%
1

1
PC78

PC79
8
7
6
5

PC80 PQ22 PR103

0.022U_0402_16V7K AO4466_SO8 10 26 1 2

om
2

OCSET1 VO2
1 2
8.06K_0402_1%
2

PR104 4 1 2
7.87K_0402_1% NB_COREP_EN 11 25
PR105 EN1 PU6 OCSET2
0_0603_5% ISL6228_B+
ISL6228HRTZ-T_QFN28_4X4
+1.1V

yc
1

1
2
3

PL7
+NB_COREP 1 2 LX_NB_COREP 12 24 1.2V_EN PC82
PHASE1 EN2 0.022U_0402_16V7K
1

5
6
7
8

4.7U_1206_25V6K

4.7U_1206_25V6K
1UH_MSCDRI-104R-1R0N-F_11A_30%
8
7
6
5

1
PC81

PC84
1 1 2
PQ24

m
D
D
D
D

PC83 + PR106 FDS6670AS_NL_SO8 UG_NB_COREP 13 23

2
UGATE1 PHASE2

2
330U_D2E_2.5VM 4.7_1206_5%
2

4 PQ23 PR107
2 PR109 AO4466_SO8 8.06K_0402_1%
G 4
1

PC85
680P_0603_50V8J 2 1 2 1BST_NB_COREP14
// 22 UG_1.2V
0_0603_5%
1 2

1
BOOT1 UGATE2
S
S
S
2

3
2
1
LGATE1

LGATE2
PC86 PR108 LX_1.2V 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.2VALWP
1
2
3

1
3 3

0.1U_0402_16V7K 0_0603_5% PL8

5
6
7
8
PR110 1.8U_D104C-919AS-1R8N_9.5A_30%
4.7_1206_5%
p:
1
15

16

17

18

19

20

21
PC87 +

2
330U_D2E_2.5VM
PR111 PR112 PC89 4 PQ25

1
47K_0402_1% BST_1.2V AO4712_SO8 PC88 2
1 2 1 2
tt

+5VALW +5VALW
2 1 NB_COREP_EN 680P_0603_50V8J
32,37,44 VLDT_EN
2

2
0_0603_5% 0.1U_0402_16V7K

2
0.1U_0402_10V7K

PC91 PC92

3
2
1
1

PC90

1U_0402_6.3V6K 1U_0402_6.3V6K
h
1

1
2

LG_NB_COREP LG_1.2V

1.2VP Ipeak=3.94A ; Imax=2.758A

DCR=10m ohm (max)
PR113
@ 0_0402_5% Rocset=(Iocp*DCR)/10E-06=6.65K ohm
1.1VP Ipeak=8.9A ; Imax=6.23A STB_SB 1 2 Iocp=5.542A(1.2*DCR)
DCR=6m ohm (max) 1.2V_EN
Csen=L/(Rocset*DCR)=0.027uF
40,41 POK 2 1
Rocset=(Iocp*DCR)/10E-06=7.68K ohm
PR114
Iocp=9.846A(1.3*DCR) Freq=366KHz
1

0_0402_5% @
Csen=L/(Rocset*DCR)=0.022uF PC93
Rfset=1/(1.5E-10 * Freq)=18.2K
0.01U_0402_25V7K
2

4 4

Freq=303KHz
Rfset=1/(1.5E-10 * Freq)=22K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB_COREP / 1.2VSB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0
Date: Friday, April 18, 2008 Sheet 43 of 50
A B C D
 5 4 3 2 1

PJ14
51117_B+ 2 1 B+
2 1

4.7U_1206_25V6K

4.7U_1206_25V6K
@ JUMP_43X118

D D

1
PC94

PC95
5
6
7
8

2
PQ26
AO4466_SO8

PR115 4
200K_0402_5%
1 2

3
2
1
BST_1.8V

PR116 PR117 PL9

15

14
PC96

1
0_0402_5% PU7 0_0603_1% 1UH_MSCDRI-104R-1R0N-F_11A_30%
1 2 1 2 BST_1.8V-1 1 2 1 2

EN_PSV

TP

VBST
29,30,37 SYSON +1.8VP
1

PR187 2 13 DH_1.8V 0.1U_0603_25V7K

TON DRVH

1
47K_0402_5% PC97 @

5
6
7
8

/
@0.1U_0402_16V7K 3 12 LX_1.8V PR190
2

VOUT LL 4.7_1206_5% 1

D
D
D
D
2

4 11 +5VALW
V5FILT TRIP

/x
PQ27 + PC98

2
5 10 FDS6670AS_NL_SO8 330U_D2E_2.5VM
VFB V5DRV
4 G

1
DL_1.8V @ 2
6 PGOOD DRVL 9

PGND
PC160

GND

S
S
S
PR118 680P_0603_50V8J

2
1
24K_0402_1%
0_0603_1%

su 3
2
1
1
+5VALW 1 2 @PC99
@ PC99 TPS51117RGYR_QFN14_3.5x3.5 PC100

8
C C

PR119
47P_0402_50V8J 4.7U_0805_10V6K

2
1 2
1

PC101

2
1U_0603_10V6K

p.
2

PR120
14K_0402_1%
1 2

om
1

PR121
10K_0402_1%
2

yc
m
VFB=0.75V
Vo=VFB*(1+PR120/PR121)=1.8V
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.1E-07
+1.2VALW
Freq=305KHz
//
Cesr=15m ohm +5VALW
B B
Ipeak=12.6A Imax=8.82A

1
Delta I=((19-1.8)*(1.8/19))/(L*Freq)=5.332A PJ15

1
p:

Vtrip=Rtrip*10uA=0.24V JUMP_43X79
@
1

Iocp-min=Vtrip/Rdsonmax*1.4+2.666=17.573A

2
Iocp-max=Vtrip/Rdsontyp*1.2+2.666=26.908A PC102

2
1U_0402_6.3V6K
Iocp=17.573~26.908A
2
tt

1
PC103
4.7U_0805_6.3V6K
6
h

PU8

2
5
VCNTL

VIN
7 POK
VOUT 4 +1.1VSP
PR122
VOUT 3

22U_0805_6.3V6M
0_0402_5%

PC105
VLDT_EN 1 2 8 2
EN FB
1

32,37,43 VLDT_EN PR123

GND

2
1

@ 9 1.15K_0402_1%
@ PC106
@PC106 PR186 VIN

2
1U_0603_10V6K 47K_0402_5% APL5912-KAC-TRL_SO8
2

1
2

PC104
1

0.01U_0402_25V7K

PR124
3K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VSP/+1.1VSP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 44 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS

+5VALW

1
PJ16

1
@ JUMP_43X79

2
D
PC107 D
1U_0402_6.3V6K

2
2
6
PU9

1
5 PC108

VCNTL
VIN 4.7U_0805_6.3V6K
7 POK
4

2
PR125 VOUT

VOUT 3 +2.5VSP
10K_0402_1%

22U_0805_6.3V6M
+3VS 1 2 8 EN FB 2

PC110
GND
1
@ 9 PR126 PC109

2
VIN

1
PR185 2.15K_0402_1% 0.01U_0402_25V7K

2
PC111 47K_0402_5% APL5915KAI-TRL_SO8

2
0.1U_0402_16V7K

1
/
PR127
1K_0402_1%

2
/x
su
C C

p.
om
+1.8V

yc

1
+1.8V
PJ17

1
@ JUMP_43X79

+5VALW

2
m
1

PU10

2
PJ18 1 6
1

VIN VCNTL +3VALW

@ JUMP_43X79
2 GND NC 5
1

1
2

PC112
//

1
1U_0402_6.3V6K PC113 3 7 PC114
2

4.7U_0805_6.3V6K PR128 VREF NC 1U_0402_6.3V6K

2

2
1K_0402_1% 4 8
B VOUT NC B
6

PU11 9

2
TP
1

5 PC115
VCNTL

VIN
p:

7 4.7U_0805_6.3V6K APL5331KAC-TRL_SO8
POK @
4
2

VOUT

0.1U_0402_16V7K
PR130 PR131 +0.9VP

1
0_0402_5% D PR129
VOUT 3 +1.5VSP

PC116
10K_0402_1% 1 2 2 1K_0402_1%
1

1
28,29,37,38 SYSON#
tt
22U_0805_6.3V6M

1 2 8 2 G

2
EN FB
1

1
29,30,32,37 SUSP#
PC119

S PQ28 PC120
GND

2
1

@ 9 PR132 PC117 PC118 SSM3K7002F_SC59-3 10U_0805_6.3V6M

2

2
VIN
1

PR184 1.54K_0402_1% 0.01U_0402_25V7K @ 0.1U_0402_16V7K @

2

2
47K_0402_5%
h

PC121 APL5915KAI-TRL_SO8
1

0.1U_0402_16V7K
2

PR133
1.74K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VP//1.5VSP/2.5VSP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JALB0
Date: Friday, April 18, 2008 Sheet 45 of 50

5 4 3 2 1
 5 4 3 2 1

CPU_B+ PL10
HCB4532KF-800T90_1812
PC122 1 2 B+

2200P_0402_50V7K
10U_1206_25V6M

0.01U_0402_25V7K
33P_0402_50V8K

220U_25V_M
2 1 1

5
6
7
8

1
PC124

PC152

PC155

PC125
+
2 1 2 1

2
PR134 PC123 2
44.2K_0402_1% 1200P_0402_50V7K UGATE_NB 4 PQ29
PR135 AO4466_SO8
2_0603_5%
D +5VS 1 2 PC127 PL11 D
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB

3
2
1
2 1 PHASE_NB 1 2
PR136
+VDDNB

5
6
7
8

1
PC128 PR137 0_0603_5%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 PR138
2 1
2 1 2
4.7_1206_5% 1
Design Current: 2.1A

2
PR140 PC129 Max current: 3A
10_0402_5% 0.22U_0603_10V7K PQ30 + PC130

1 2
220U_D2_4VM
1 2 PR141
1 2 +CPU_CORE_NB LGATE_NB 4 AO4712_SO8
PC131
OCP_min:5A
CPU_B+ 2
0_0402_5% 680P_0603_50V7K
PR139 2 1 CPU_VDDNB_FB_H 6

2
2_0603_5% PR142

3
2
1
+5VS +3VS 11.3K_0402_1%
2 1 PHASE_NB

LGATE_NB

1
PC132 CPU_B+
0.1U_0603_16V7K PHASE_NB
1

2200P_0402_50V7K
0.01U_0402_25V7K
PR143 PR144 UGATE_NB

10U_1206_25V6M

10U_1206_25V6M
0_0402_5% @ 105K_0402_1%

5
2 1 CPU_VDDNB_FB_L 6

/x
PR145
2

2
1

1
PC133

PC134

PC153

PC156
0_0402_5%
PR146 PQ31
1

PR147 @ 10K_0402_1% PR148 SI7686DP-T1-E3_SO8

2
105K_0402_1% PR149 10_0402_5% UGATE0 4
@ 105K_0402_1%

48

47

46

45

44

43

42

41

40

39

38

37
2

1
PU12

su
PHASE0

VIN

RTN_NB

LGATE_NB

PHASE_NB

UGATE_NB
VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

OCSET_NB

PGND_NB
2

C PR150 PL12 C

3
2
1
0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
30 VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE_0
PR153 0_0402_5% OFS/VFIXEN BOOT_NB

2
BOOT0 PC135

p.
1 2 2 PGOOD BOOT0 35

5
6
7
8

5
6
7
8
19 H_PWRGD_L 1 2 0.22U_0603_10V7K PR151

1
PR192 0_0402_5% @ 3 34 UGATE0 16.2K_0402_1%
PWROK UGATE0 PR154
2 1 4 33 PHASE0 PQ32 PQ33 4.7_1206_5%

1
6 CPU_SVD SVD PHASE0

om
PR152 0_0402_5% AO4456_SO8 AO4456_SO8 1 PR155 2
5 32 4 4 4.02K_0402_1%

1 2
SVC PGND0 +5VS
2 1
6 CPU_SVC PR156 0_0402_5% 6 31 LGATE0 PC136 PC137
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30

3
2
1

3
2
1

2
RBIAS PVCC 0.1U_0402_16V7K
30 VR_ON 8 29 LGATE1 @PH3
@ PH3
OCSET LGATE1

1
yc
PR157 PR158 ISL6265IRZ-T_QFN48_6X6~D PC138 2 1 2 PR159 1
2 1 2 1 9 28 1U_0603_16V6K LGATE0 10_0402_5%
34.8K_0402_1% 82.5K_0402_1% VDIFF0 PGND1 10K_0603_5%_TSM1A103J4302RE @

ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1

m
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 12.6A
COMP1
VDIFF1
VSEN0

VSEN1

2200P_0402_50V7K
0.01U_0402_25V7K
RTN0

RTN1
ISN0

ISN1
ISP0

ISP1
VW1
FB1

10U_1206_25V6M

10U_1206_25V6M
Max current: 18A
TP
//

5
OCP_min:24A
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC139

PC140

PC154

PC157
B ISP0 PQ34 B
PR160 ISN0 SI7686DP-T1-E3_SO8

2
ISN1
ISP1

0_0402_5% UGATE1 4
p:
6 CPU_VDD0_FB_H 2 1 VSEN0
PR161
+CPU_CORE_0 2 1 PHASE1
10_0402_5% PR163 PL13

3
2
1
6 CPU_VDD0_FB_L 2 PR164 1 RTN0 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
tt

0_0402_5% BOOT1 1 2 1 2 1 2 +CPU_CORE_1

6 CPU_VDD1_FB_L 2 PR165 1 RTN1

2
0_0402_5% PC141
2

5
6
7
8

5
6
7
8
10_0402_5%

10_0402_5%

0.22U_0603_10V7K PR168

1
PR166

h PR167

16.2K_0402_1%
PR169
PQ35 PQ36 4.7_1206_5%

1
AO4456_SO8 AO4456_SO8 1 PR170 2
1

PR171 4 4 4.02K_0402_1%

1 2
0_0402_5%
6 CPU_VDD1_FB_H 2 1 VSEN1 PC142 PC143
680P_0603_50V7K 2 1
+CPU_CORE_1 2 PR172 1

3
2
1

3
2
1

2
10_0402_5% 0.1U_0402_16V7K
@PH4
@ PH4
DIFF_0 VW0 DIFF_1 VW1 2 1 2 PR173 1
LGATE1 10_0402_5%
PR174 PC144 PR175 PC147 10K_0603_5%_TSM1A103J4302RE @

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

PC145 PC146 PC148 PC149 +CPU_CORE_1

180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K
A
Design Current: 12.6A A
PR176 PR178 PR179 PR181
1K_0402_5% PR177 PC150 6.81K_0402_1% 1K_0402_5% PR180 PC151 6.81K_0402_1%
Max current: 18A
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 OCP_min:24A
54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JALB0 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 46 of 50
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
7/9 DCIN Change PL1 to bead coil link to SM010008E10
7/9 DCIN Link RTC battery symbol link to SP093MX0000
7/9 Battery conn Change PL2 to bead coil link to SM010008E10
7/9 Battery conn Change PD3,PD4 to RLS4148 For low cost
7/9 Battery conn Change PU2 pin8 to VL Design change
7/9 Charger Delete PU3 PVCC resistor and change PC26 to 1U avoid PQ6 false turn-on when AC plug-in
7/9 Charger Change PQ7,PQ9 to AO4466 For low cost
7/9 Charger Change PU4 pin8 to +5VALW Design change
7/9 Charger Unpop PC28, PC37 avoid interfere by other signal
7/9 3V/5V Change PR54 and PC51 Add design margine
7/9 3V/5V Change MOSFET to AO4466+AO4712 For low cost
7/9 1.8V/1.5V Change MOSFET to AO4466+AO4712 For low cost
7/9 1.8V/1.5V Change PR75 to 2.2ohm Design change
7/9 1.05V/1.25V/0.9V Change MOSFET to AO4466+AO4712 For low cost
7/9 1.05V/1.25V/0.9V Change PC94 to 330U Decrease overshoot
7/9 1.05V/1.25V/0.9V Change PU7 PVCC source to +5VS Design change
7/9 1.05V/1.25V/0.9V Change PC105,PC108 size to 0805 For low cost
7/9 CPU CORE Change input MLCC to 4pcs Design change
7/9 CPU CORE Unpop PC111 Reserve for high frequency noise
7/10 Charger Change PR38, PR39 and unpop PC32 increase resistor to reduce power loss on resistor divider

/
7/10 Charger Change PR45, PR47 and unpop PC41 increase resistor to reduce power loss on resistor divider
7/10 Charger Change PR43 to 100K increase resistor to reduce power loss

/x
7/10 3V/5V Change PR65 to 100K_1% Let BOM clear
7/10 Charger/0.9V Change PQ4,PQ11,PQ12,PQ13,PQ24 to SB000009080 For low cost
8/1 Charger Change PR30 to 0.015ohm and PR38 to 80.6K Change over power protection point

su
p.
om
yc
m
//
p:
tt
h

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JALC0 LA-4181P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 47 of 50
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
12/11 p.11 DEL R26
12/11 P.15 UN-POP R234,POP R235
12/11 P.17 Change R123 to 2.2K
D
12/11 P.18 ADD R525,R526,R527 For non-Dockin sku D

12/11 P.20 Del R128

12/11 P.23 Change R103 to 2.2k
12/11 P.25 DEL U35,Q43,R473
12/11 P.27 ADD RP32,RP33,RP34,RP35,RP36 For non-Dockin sku
12/11 P.29 Change U17 P/N to SA000029E00
12/11 P.31 Change JP14.4 Net to EC_SMB_CK2,JP14.5 Net to EC_SMB_DA2
12/11 P.31 Change LED1,LED2 P/N to SC597UDB000
12/11 P.35 Change U40.3 to WOOFER_IN+,U40,4 to WOOFER_IN-
12/11 P.38 Del R291,R292

/
12/14 P.30 Raise KB926 pin.75

/x
12/12 P.14 ADD D28 and pull high R529 to +3VS to AC_IN form JMXM1.157
C 12/12 P.17 Change Q47,Q48,Q49,Q50 P/N to SB501110010 C

12/12 P.18 DEL Q5,ADD Q52,Q53

su
12/12 P.33 Change U31 P/N to SA000026V00
12/12 P.30 Change Board ID
12/12 P.26 Un-pop R56, POP R61

p.
12/13 P.25 DEL U35,R473,Q43
12/13 P.7 DEL C762,C763

om
12/14 P.38 update dock footprint and add CRT_Det#
12/19 P.18 change CRT_DET to CRT_DET# from CRT to Q36 and output CRT_DET TO U10.J2

yc
12/14 P.26 DEL U23,R305,C399,R28
12/14 P.6 Change R420, R419, R113 pull-up change to +1.8VS
12/14 P.12 Delete U6, R68, R65, Q6, R55, C119, C113, C128, C151,C124 Remove 1.35V LDO circuit

m
B B

12/14 P.12 Del L22, POP L21 Change VDDHTTX from 1.35V to 1.2V
12/14 P.14 Change C183 to 0402 package
//
12/14 P.16 Change C12 to 0402 package
12/14 P.17 Change R90,R91 from 1.5K to 2K
p:

12/14 P.22 Delete R399, add R391 VDD should connect to S0 power on A12
12/14 P.34 Change R480, R487 from 0Ohm to 75Ohm
12/14 P.37 Change R306 to 10K
tt

1.2V_HT should faster than NB_CORE

12/14 P.32 Change D16.1 from +3VS to SUSP#
VGA_ON should drop before +3VS
h

12/19 P.25 Connect U33.16 to U10.AD18 (CR_WAKE#) through D29; U33.13 to U10.F2 (CR_PE#) through a MOS(Q55)

12/17 P.28 DEL TV_THERM#,ADD Port80 Signal to JMINI2.49,JMINI2.51

A 12/17 P.19 Delete R179,R185, add U12, U13 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
12/17 P.26 Del BCM5787 Co-lay part
12/17 P.38 ADD EC_DOCKIN#_S0
12/18 P.25 ADD R533
D
12/19 P.11 ADD Q54,R534 Level shift, and CPU_LDT_REQ#,ALLOW_LDTSTOP Pull high 300 to 1.8vs D

12/19 P.20 Change New Card CP_PE# to SB GPM5#

Change CRT_DET to SB GPM7#
Change EC_LID_OUT# to SB GPM4#
Del USB_OC#4

12/19 P.6 ADD R129,R538,R539

12/19 P.21 change R104 from 10K to 100K
12/19 P.34 Change R488,R483 to 75 ohm
12/19 P.37 Change R306 from 10K to 150K
12/19 P.6 POP R93

/
12/19 P.18 change D18 from RB411 to RB491

/x
12/19 P.19 Change Y2 location to X2 and p/n change to SJ132P7K220
C C
12/19 P.30 EC_SMB_CK1,EC_SMB_DA1 Pull high to +3VALW,EC_SMB_CK2,EC_SMB_CK2 pull high to +3VS
12/20 P.37 Reserve R541,R542,R543

su
12/20 P.33 Change R294,R288 P/N to SM010016720
12/20 P.31 ADD C655,C656,C657,C658,C659,C660,C661,C662 for EMI

p.
12/20 P.37 ADD Q57,R544
12/20 P.34 JMIC1.7,JMIC1.8,JLINE1.7,JLINE1.8 connect to AGND,

om
12/21 P.21 Change SATA HDD Port to U10 SATA port 1
12/24 P.21/P22. Change D7,D9 P/N to SC1B751V010
12/24 P.34 Change L73,L74,L67,L68,L71,L72 P/N to SM010015410
12/24 P.21 ADD SPI ROM Schematic for SB700

yc
12/24 P.34 JHP1.6,JHP1.10 connect to AGND
12/24 P.29 Add U17 .21 to gnd

m
B B
12/24 P.26 Change U5.18,U5.17,U5.5,U5.33 connect to +1.2_VDDCIO
12/26 P.34 Change R490 to 42.2K, R478,R479 to 1K,C621,C622 to 0.22u
//
12/26 P.35 Change R516 to 6.8K
1/22 P.15 Reversal MiniCard1 & MiniCard2 PCIE CLK Signal
1/22 P.37 Change R275 from 100K to 10K
p:

1/22 P.37 Change Q57.2 to VLDT_EN#

1/31 P.6 POP CPU internal themal sensor schematic
tt

1/31 P.11 change R64 to 133 ohm

1/31 P.14 Add AND GATE
h

1/31 P.15 Add C669

1/31 P.17 Change EC_DOCKIN#_S0 to Q50.2/Q49.2
1/31 P.18 Change EC_DOCKIN#_S0 to U7.1
A A
1/31 P.20 Change CRT_DET to U10.H7,add EC_DOCKIN# to U10.B9
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 49 of 50
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
1/31 P.21 Reserve AND gate form ACIN to U10.A4
1/31 P.28 Reserve MINI1_LED# Pull high 100K to +3VS
1/31 P.30 ADD R551,R552 (VR_ON pull down 100k,BT_ON# Pull 100k)
1/31 P.30 Del JP12
1/31 P.33 Change R257 from 200k to 330k
D D
1/31 P.33 ADD EC_DOCKIN#_S0 to R530.1
1/31 P.34 Change R459,R446,R475,R470 to 75ohm
1/31 P.34 Add R553,R554,R555,R556
1/31 P.38 Add C672
2/4 P.25 For EMI request,add C676
2/4 P.31 For EMI request,add C673,C674,C675
2/4 P.34 For EMI request,add D31
2/12 P.6 Change R361,R365 to 2.2k
2/12 P.30/31 ADD ESB_CLK/ESB/DATA (add R557,R558,R559,R560,R561,R562)

/
2/13 P.28 ADD R563
2/14 P.6/20 UPDATE cpu internal themal sensor schematic (add R564,R565,R566,R567,R568,R569,ADD CPU_SIC_SB,CPU_SID_SB)

/x
3/12 R493=>61.9K (SD034619280)
R516=>1K (SD028100180)
R517=>4.7K (SD028470180)
R518=>1.8K (SD028180180)

su
C C647=> 0.068u (SE026683K80) C

3/12 P.33 For EMI request,Change R440 to SD028100A80

p.
3/12 P.12 Change C109,C150,C130,C88,C92,C35,C34,C36,C38 to SE000000I10 (22U)
3/12 P.7 Change C77,C78,C79,C80 to SGA00002380

om
3/12 P.37 Change R186 to10K
3/17 P.11 ADD R570,R571, Un-pop Q28,Q56,R324,R534
3/26 P.6 Un-pop R351,C436,R360,R566,R568,Q31,Q30
3/26 P.19 Change C192,C22 to 22p

yc
3/26 P.34 Change R487,R480,R488,R483 to 56.2

m
4/16 P.8 Change C257 from 0.1U to 1UF
4/16 P.19 Change C192, C212 to 12P for RTC Timer issue //
4/16 P.28 Add L, C on SYSON# signal close to USB/B connector and TV/B connector
B B
4/16 P.30 Change the board ID back to R0.3 for BIOS identify issue
4/16 P.31 Add 100pF capacitor on +3VS close to MEDIA/B
p:

4/16 P.32 Change C373 to 0.22U_0603_X7R for VGA power sequence

4/16 P.32 Remove power on/off button SW3 for MP BOM
tt

4/16 P.37 Reserve voltage divider circuit on Power MOS

h

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JALB0 LA-4171P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 18, 2008 Sheet 50 of 50
5 4 3 2 1