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Datasheet: Integrated Gigabit Ethernet Controller For Pci Express™ Applications

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0% found this document useful (0 votes)
191 views

Datasheet: Integrated Gigabit Ethernet Controller For Pci Express™ Applications

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anh_sao_dem_92
Copyright
© © All Rights Reserved
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You are on page 1/ 29

www.DataSheet4U.

com

RTL8111

INTEGRATED GIGABIT ETHERNET CONTROLLER


FOR PCI EXPRESS™ APPLICATIONS

DataSheet4U.com e
DataShe

DATASHEET

Rev. 1.2
24 March 2005
Track ID: JATR-1076-21

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RTL8111
Datasheet

COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT


This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
et4U.com DataSheet4U.com e
DataShe
REVISION HISTORY
Revision Release Date Summary
1.0 2004/08/19 First release.
1.1 2004/11/05 Package changes. See section 8, Mechanical Dimensions, page 23, and
section 9, Ordering Information, page 24.
1.2 2005/03/24 Changed Table 8, Power & Ground, page 6.
Changed Table 6, Regulator & Reference, page 5.
Added lead (Pb)-free package identification information on page 3 and on
page 24.

Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.2

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RTL8111
Datasheet

Table of Contents
1. GENERAL DESCRIPTION...............................................................................................................1
2. FEATURES ..........................................................................................................................................2
3. SYSTEM APPLICATIONS................................................................................................................2
4. PIN ASSIGNMENTS ..........................................................................................................................3
4.1. LEAD (PB)-FREE PACKAGE IDENTIFICATION ..................................................................................3
5. PIN DESCRIPTIONS .........................................................................................................................4
5.1. POWER MANAGEMENT/ISOLATION .................................................................................................4
5.2. PCI EXPRESS INTERFACE................................................................................................................4
5.3. EEPROM .......................................................................................................................................4
5.4. TRANSCEIVER INTERFACE...............................................................................................................5
5.5. CLOCK ............................................................................................................................................5
5.6. REGULATOR & REFERENCE ............................................................................................................5
5.7. LEDS ..............................................................................................................................................6
5.8. POWER & GROUND .........................................................................................................................6
5.9. NC (NOT CONNECTED) PINS ..........................................................................................................6
6. FUNCTIONAL DESCRIPTION........................................................................................................7
6.1. PCI EXPRESS BUS INTERFACE ........................................................................................................7
6.1.1. PCI Express Transmitter .......................................................................................................7
et4U.com 6.1.2. PCI Express Receiver ............................................................................................................7
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6.2. LED FUNCTIONS ............................................................................................................................7
6.2.1. Link Monitor ..........................................................................................................................7
6.2.2. Rx LED...................................................................................................................................8
6.2.3. Tx LED...................................................................................................................................8
6.2.4. Tx/Rx LED .............................................................................................................................9
6.2.5. LINK/ACT LED ...................................................................................................................10
6.3. PHY TRANSCEIVER ......................................................................................................................11
6.3.1. PHY Transmitter..................................................................................................................11
6.3.2. PHY Receiver.......................................................................................................................11
6.4. NEXT PAGE ...................................................................................................................................12
6.5. EEPROM INTERFACE ..................................................................................................................12
6.6. POWER MANAGEMENT .................................................................................................................13
6.7. VITAL PRODUCT DATA (VPD)......................................................................................................15
7. CHARACTERISTICS ......................................................................................................................16
7.1. ABSOLUTE MAXIMUM RATINGS ...................................................................................................16
7.2. RECOMMENDED OPERATING CONDITIONS ....................................................................................16
7.3. CRYSTAL REQUIREMENTS.............................................................................................................16
7.4. THERMAL CHARACTERISTICS .......................................................................................................17
7.5. DC CHARACTERISTICS .................................................................................................................17
Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.2

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7.6. AC CHARACTERISTICS .................................................................................................................18


7.6.1. Serial EEPROM Interface Timing .......................................................................................18
7.7. PCI EXPRESS BUS PARAMETERS ..................................................................................................19
7.7.1. Differential Transmitter Parameters ...................................................................................19
7.7.2. Differential Receiver Parameters ........................................................................................20
7.7.3. REFCLK Parameters...........................................................................................................20
7.7.4. Auxiliary Signal Timing Parameters ...................................................................................22
8. MECHANICAL DIMENSIONS ......................................................................................................23
8.1. MECHANICAL DIMENSIONS NOTES ...............................................................................................24
9. ORDERING INFORMATION.........................................................................................................24

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Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.2

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Datasheet

List of Tables
Table 1. Power Management/Isolation......................................................................................................4
Table 2. PCI Express Interface..................................................................................................................4
Table 3. EEPROM.....................................................................................................................................4
Table 4. Transceiver Interface...................................................................................................................5
Table 5. Clock ...........................................................................................................................................5
Table 6. Regulator & Reference................................................................................................................5
Table 7. LEDs............................................................................................................................................6
Table 8. Power & Ground .........................................................................................................................6
Table 9. NC (Not Connected) Pins............................................................................................................6
Table 10. EEPROM Interface ...................................................................................................................12
Table 11. Absolute Maximum Ratings .....................................................................................................16
Table 12. Recommended Operating Conditions .......................................................................................16
Table 13. Crystal Requirements ................................................................................................................16
Table 14. Thermal Characteristics ............................................................................................................17
Table 15. DC Characteristics ....................................................................................................................17
Table 16. EEPROM Access Timing Parameters.......................................................................................18
Table 17. Differential Transmitter Parameters..........................................................................................19
Table 18. Differential Receiver Parameters ..............................................................................................20
Table 19. REFCLK Parameters.................................................................................................................20
Table 20. Auxiliary Signal Timing Parameters.........................................................................................22
Table 21. Ordering Information ................................................................................................................24

et4U.com DataSheet4U.com e
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List of Figures
Figure 1. Pin Assignments.........................................................................................................................3
Figure 2. Rx LED ......................................................................................................................................8
Figure 3. Tx LED ......................................................................................................................................8
Figure 4. Tx/Rx LED.................................................................................................................................9
Figure 5. LINK/ACT LED ......................................................................................................................10
Figure 6. Serial EEPROM Interface Timing ...........................................................................................18
Figure 7. REFCLK Single-Ended Measurement Points for Trise and Tfall ...............................................21
Figure 8. REFCLK Single-Ended Measurement Points for Vovs, Vuds, and Vrb ......................................21
Figure 9. REFCLK Differential Measurement Points for Tperiod, Duty Cycle, and Jitter........................21
Figure 10. REFCLK Vcross Range .............................................................................................................22
Figure 11. Auxiliary Signal Timing ..........................................................................................................22

Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.2

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RTL8111
Datasheet

1. General Description
The Realtek RTL8111 Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media
Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and
embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, they offer
high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as
Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation,
echo cancellation, timing recovery, and error correction are implemented to provide robust transmission
and reception capability at high speeds.

The device supports the PCI Express 1.0a bus interface for host communications with power management
and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab
specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will
auto-configure related bits of the PCI power management registers in PCI configuration space.

Advanced Configuration Power management Interface (ACPI)--power management for modern operating
systems that are capable of Operating System-directed Power Management (OSPM)—is also supported to
achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also
supported.

In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™, Re-LinkOk, and
Microsoft® Wake-up frame) is supported in both ACPI and APM (Advanced Power Management)
environments. To support WOL from a deep power down state (e.g., D3cold, i.e. main power is off and
et4U.com only auxiliary exists), the auxiliary power DataSheet4U.com
source must be able to provide the needed power for the DataShee
RTL8111.

The RTL8111 is fully compliant with Microsoft® NDIS5 (IP, TCP, UDP) Checksum and Segmentation
Task-offload features, and supports IEEE 802 IP Layer 2 priority encoding and 802.1Q Virtual bridged
Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially
benefiting performance when in operation on a network server.

The device features next-generation PCI Express interconnect technology. PCI Express is a
high-bandwidth, low pin count, serial, interconnect technology that offers significant improvements in
performance over conventional PCI and also maintains software compatibility with existing PCI
infrastructure.

The RTL8111 is suitable for multiple market segments and emerging applications, such as desktop, mobile,
workstation, server, communications platforms, and embedded applications.

Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.2

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2. Features
Integrated 10/100/1000 transceiver Supports IEEE 802.1P Layer 2 Priority
Auto-Negotiation with Next Page Encoding
capability Supports IEEE 802.1Q VLAN tagging
Supports PCI Express™ 1.0a Serial EEPROM
Supports pair swap/polarity/skew Transmit/Receive on-chip buffer
correction (8KB/16KB) support
Crossover Detection & Auto-Correction Supports power down/link down power
Wake-on-LAN and remote wake-up saving
support Supports PCI Message Signaled
Microsoft® NDIS5 Checksum Offload Interrupt (MSI)
(IP, TCP, UDP) and Largesend Offload 128-pin DHS-QFP package
support
Supports Full Duplex flow control
(IEEE 802.3x)
Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
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3. System Applications
PCI Express™ Gigabit Ethernet on Motherboard, Notebook, or Embedded system

Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.2

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4. Pin Assignments

CKXTAL2
CKXTAL1
AVDD33
GVDD21

VDD18

VDD33

VDD18
LED0
LED1
LED2
LED3
GND

GND
GND

GND
NC

NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VCTRL18 1 102 NC
GND 2 101 GND
RSET 3 100 EESK
GND 4 99 EEDI
MDIP0 5 98 VDD33
MDIN0 6 97 EEDO

AVDD25 7 96 EECS

GND 8 95 NC
MDIP1 9 94 VDD18
MDIN1 10 93 GND
AVDD25 11 92 GND
VCTRL25 12 91 NC

GND 13 90 NC

AVDD33 14 89 NC
VCTRL20 15 88 NC
GVDD21 16 87 VDD18
GND 17 86 NC
MDIP2 18 RTL8111 85 GND
MDIN2 19 84 NC
AVDD25 20 83 NC

GND 21 82 NC
MDIP3 22 81 NC
MDIN3 23 80 GND

et4U.com LLLLLLL TXXXV


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AVDD25 24 79
GND 25 78 NC

GND 26 77 NC
VDD18 27 76 NC
NC 28 75 NC
NC 29 74 VDD18
NC 30 73 VDD33
NC 31 72 GND
NC 32 71 ISOLATEB
VDD33 33 70 NC
NC 34 69 NC
NC 35 68 NC
LANWAKEB 36 67 NC
PERSTB 37 66 NC

GND 38 65 NC
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
EGND
GND
EVDD18

EVDD18
EVDD18
VDD18

VDD18
NC
NC
NC

NC
NC
NC

HSIP
HSIN

REFCLK_P
REFCLK_M

HSOP
HSON

NC

NC
NC
NC
NC
NC
EGND

Figure 1. Pin Assignments

4.1. Lead (Pb)-Free Package Identification


Lead (Pb)-free package is indicated by an “L” in the location marked “T” in Figure 1.

Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 Rev. 1.2

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5. Pin Descriptions
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin

5.1. Power Management/Isolation


Table 1. Power Management/Isolation
Symbol Type Pin No Description
Power Management Event: Open drain, active low.
LANWAKEB O/D 36
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
Isolate Pin: Active low.
Used to isolate the RTL8111 from the PCI Express bus. The RTL8111 will not drive
ISOLATEB I 71
its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI
Express input as long as the Isolate pin is asserted.

5.2. PCI Express Interface


Table 2. PCI Express Interface
Symbol Type Pin No Description
REFCLK_P I 50
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.
REFCLK_N I 51
et4U.com HSOP O 54 DataSheet4U.com e
PCI Express Transmit Differential Pair. DataShe
HSON O 55
HSIP I 47
PCI Express Receive Differential Pair.
HSIN I 48
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8111 returns to a
PERSTB I 37
pre-defined reset state and is ready for initialization and configuration after
the de-assertion of the PERSTB.

5.3. EEPROM
Table 3. EEPROM
Symbol Type Pin No Description
EESK O 75 Serial data clock.
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to EEPROM. To support wakeup from ACPI
EEDI/AUX O/I 74
D3cold or APM power-down, this pin must be pulled high to Aux. Power
via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111
assumes that no Aux. Power exists.
EEDO I 72 Input from serial data output pin of EEPROM.
EECS O 71 EECS: EEPROM chip select.

Integrated Gigabit Ethernet Controller for PCI Express 4 Track ID: JATR-1076-21 Rev. 1.2

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5.4. Transceiver Interface


Table 4. Transceiver Interface
Symbol Type Pin No Description
MDIP0 I/O 5 In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the
6 transmit pair in 10Base-T and 100Base-TX.
MDIN0 I/O In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair
in 10Base-T and 100Base-TX.
MDIP1 I/O 9 In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is
10 the transmit pair in 10Base-T and 100Base-TX.
MDIN1 I/O In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
MDIP2 I/O 18 In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
MDIN2 I/O 19 In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDIP3 I/O 22 In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
MDIN3 I/O 23 In MDI crossover mode, this pair acts as the BI_DC+/- pair.

5.5. Clock
Table 5. Clock
Symbol Type Pin No Description
CKXTAL1 I 125 Input of 25MHz clock reference.
CKXTAL2 O 126 Output of 25MHz clock reference.

et4U.com 5.6. Regulator & ReferenceDataSheet4U.com e


DataShe
Table 6. Regulator & Reference
Symbol Type Pin No Description
VCTRL25 O 12 Regulator Control. Voltage control to external 2.5V power transistor.
VCTRL20 O 15 Regulator Control. Voltage control to external 2.1V power transistor.
VCTRL18 O 1 Regulator Control. Voltage control to external 1.8V power transistor.
RSET I 3 Reference. External resistor reference.
Note: Refer to the most updated schematic circuit for correct configuration.

Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.2

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Datasheet

5.7. LEDs
Table 7. LEDs
Symbol Type Pin No Description
LED0 O 120 LEDS1-0 00 01 10 11
LED1 O 119 LINK10/1000/ LINK10/AC
LED0 Tx/Rx Tx
LED2 O 118 ACT T
LINK100/100 LINK100/
LED1 LINK100 LINK
0/ACT ACT
LED3 O 117 LED2 LINK10 FULL Rx FULL
LINK1000/
LED3 LINK1000 LINK1000 FULL
ACT
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the 93C46. If there is no 93C46, the default values = 1, 1.

5.8. Power & Ground


Table 8. Power & Ground
Symbol Type Pin No Description
VDD33 Power 33, 73, 98, 115 Digital 3.3V power supply.
27, 42, 59, 74, 87, 94,
VDD18 Power Digital 1.8V power supply.
110, 121
AVDD25 Power 7, 11, 20, 24 Analog 2.5V power supply.
GVDD21 Power 16, 128 Analog 2.1V power supply.
EVDD18 Power 46, 52, 53 Analog 1.8V power supply.
AVDD33 Power 14, 124 Analog 3.3V power supply.
et4U.com DataSheet4U.com e
2, 4, 8, 13, 17, 21, 25, Digital Ground. DataShe
26, 38, 57, 72, 80, 85,
GND Power
92, 93, 101, 109, 122,
123, 127
EGND Power 49, 56 Analog Ground.
Note: Refer to the most updated schematic circuit for correct configuration.

5.9. NC (Not Connected) Pins


Table 9. NC (Not Connected) Pins
Symbol Type Pin No Description
28, 29, 30, 31, 32, 34, 35, 39,
40, 41, 43, 44, 45, 58, 60, 61,
62, 63, 64, 65, 66, 67, 68, 69,
NC 70, 75, 76, 77, 78, 79, 81, 82, Not Connected.
83, 84, 86, 88, 89, 90, 91, 95,
102, 103, 104, 105, 106, 107,
108, 111, 112, 113, 114, 116

Integrated Gigabit Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.2

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6. Functional Description
6.1. PCI Express Bus Interface
The RTL8111 is compliant with PCI Express Base Specification Revision 1.0a, and runs at a 2.5GHz
signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8111
supports four types of PCI Express messages: interrupt messages, error messages, power management
messages, and hot-plug messages. The PCI Express lane polarity reversal and link reversal are also
supported to ease PCB layout constraints.

6.1.1. PCI Express Transmitter


The RTL8111’s PCI Express block receives digital data from the Ethernet interface and performs data
scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit code
groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and 8B/10B
coding technology is used to benefit embedded clocking, error detection, and DC balance by sacrificing a
25 percent overhead to the system through the addition of 2 extra bits. The data code groups are passed
through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB
trace to its upstream device via a differential driver.

6.1.2. PCI Express Receiver


The RTL8111’s PCI Express block receives 2.5Gbps serial data from its upstream device to generate
parallel data. The receiver’s PLL circuits are resynchronized to maintain bit and symbol lock. Through
et4U.com 8B/10B decoding technology and data descrambling,
DataSheet4U.com
the original digital data is recovered and passed to DataShee
the RTL8111’s internal Ethernet MAC to be transmitted onto the Ethernet media.

6.2. LED Functions


The RTL8111 supports 4 LED signals in 4 different configurable operation modes. The following sections
describe the various LED actions.

6.2.1. Link Monitor


The Link Monitor senses link integrity, such as LINK10, LINK100, LINK1000, LINK10/100/1000,
LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link
LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no
network connection exists.

Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.2

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6.2.2. Rx LED
In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring.

Power On

LED = High

Receiving No
Packet?

Yes

LED = High for 40 ms

LED = Low for 40 ms

Figure 2. Rx LED

6.2.3. Tx LED
et4U.com DataSheet4U.com
In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. e
DataShe

Power On

LED = High

Transmitting No
Packet?

Yes

LED = High for 40 ms

LED = Low for 40 ms

Figure 3. Tx LED
Integrated Gigabit Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.2

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6.2.4. Tx/Rx LED


In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is
occurring.

Power On

LED = High

No
Tx/Rx Packet?

Yes

LED = High for 40 ms

LED = Low for 40 ms

Figure 4. Tx/Rx LED


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6.2.5. LINK/ACT LED


In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8111 is linked and
operating properly. When this LED is high for extended periods, it indicates that a link problem exists.

Power On

LED = High

No
Link?

Yes

LED = Low

No Tx/Rx
Packet?

et4U.com Yes
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LED = High for 40 ms

LED = Low for 40 ms

Figure 5. LINK/ACT LED

Integrated Gigabit Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.2

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6.3. PHY Transceiver


6.3.1. PHY Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111
operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and CAT.3 UTP
cable (10Mbps).
GMII (1000Mbps) Mode
The RTL8111’s PCS layer receives data bytes from the MAC through the GMII interface and performs the
generation of continuous code-groups through 4D-PAM5 coding technology. These code groups are
passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair
CAT5 cable at 125MBaud/s through a D/A converter.
MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B
symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to
125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the
D/A converter and transmitted onto the media.
MII (10Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.

et4U.com 6.3.2. PHY Receiver DataSheet4U.com


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e
GMII (1000Mbps) Mode
Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received
signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of
125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the
Rx Buffer Manager.
MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.

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6.4. Next Page


If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and
Reg8 as defined in IEEE 802.3ab.

6.5. EEPROM Interface


The RTL8111 requires the attachment of an external EEPROM. The 93C46/93C56 is a 1K-bit/2K-bit
EEPROM. The EEPROM interface permits the RTL8111 to read from, and write data to, an external serial
EEPROM device.
Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be
overridden following a power-on or software EEPROM auto-load command. The RTL8111 will auto-load
values from the EEPROM. If the EEPROM is not present, the RTL8111 initialization uses default values
for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM
using bit-bang accesses via the 9346CR Register, or using PCI VPD (Vital Product Data). The interface
consists of EESK, EECS, EEDO, and EEDI.
Table 10. EEPROM Interface
EEPROM Description
EECS 93C46/93C56 chip select.
EESK EEPROM serial data clock.
Input data bus/Input pin to detect if Aux. Power exists on initial power-on.
This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM
EEDI/Aux
power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not
et4U.com pulled high to Aux. DataSheet4U.com
Power, the RTL8111 assumes that no Aux. Power exists. e
DataShe
EEDO Output data bus.

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6.6. Power Management


The RTL8111 is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI
Express Active State Power Management (ASPM), and Network Device Class Power Management
Reference Specification (V1.0a), such as to support an Operating System-directed Power Management
(OSPM) environment.
The RTL8111 can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify
the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin
when such a packet or event occurs. Then the system can be restored to a normal state to process incoming
jobs.

When the RTL8111 is in power down mode (D1 ~ D3):


• The Rx state machine is stopped. The RTL8111 monitors the network for wakeup events such as a
Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power
down mode, the RTL8111 will not reflect the status of any incoming packets in the ISR register and
will not receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before
entering power down mode are held by the RTL8111.
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8111 transmits data that was not moved into the Tx on-chip
buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
et4U.com DataSheet4U.com e
DataShe
The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI
configuration space depend on the existence of Aux power (bit15, PMC) = 1.
If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s.
Example:
If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above
4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76)
In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM
PMC be set to C2 F7 (Realtek EEPROM default value).
If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C2 77, then PCI PMC = C2 77)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above
4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76)

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In the above case, if wakeup support is not desired when main power is off, it is suggested that the
EEPROM PMC be set to 02 76.
Link Wakeup occurs only when the following conditions are met:
• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponded
wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.

Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111, e.g., a broadcast,
multicast, or unicast packet addressed to the current RTL8111 adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding
wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in
any part of a valid Ethernet packet.

A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8111, e.g., a broadcast,
multicast, or unicast address to the current RTL8111 adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRCA of the received WakeupDataSheet4U.com
Frame matches the 16-bit CRC of the sample Wakeup Frame
et4U.com ee
pattern given by the local machine’s OS. Or, the RTL8111 is configured to allow direct packet wakeup, DataSh
e.g., a broadcast, multicast, or unicast network packet.
Note: 16-bit CRC: The RTL8111 supports two normal wakeup frames (covering 64 mask bytes from
offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes
from offset 0 to 127 of any incoming network packet).

The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the
following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111 may assert the corresponding wake-up method (message, beacon, or LANWAKEB) in
the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the
PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8111 to stop asserting the corresponding wake-up method (message,
beacon, or LANWAKEB) (if enabled).

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When the RTL8111 is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8111 are
disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the original
power state was D3cold. There is almost no hardware delay at the device’s power state transition. When in
ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek
default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the
EEPROM, if required.

6.7. Vital Product Data (VPD)


Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8111’s PCI Configuration Space is
used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data
between the VPD data register and the 93C46/93C56 has completed or not.
1. Write VPD register: (write data to the 93C46/93C56)
Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM.
When the flag bit is reset to 0 by the RTL8111, the VPD data (4 bytes per VPD access) has been
transferred from the VPD data register to EEPROM.
2. Read VPD register: (read data from the 93C46/93C56)
Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from
EEPROM. When the flag bit is set to 1 by the RTL8111, the VPD data (4 bytes per VPD access)
has been transferred from EEPROM to the VPD data register.

Note 1: Refer to the PCI 2.2 Specifications for further information.


et4U.com Note 2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.2 Specifications.
DataSheet4U.com e
VPD data is always consecutive 4-byte data starting from the VPD address specified. DataShe

Note 3: Realtek reserves offset 40h to 7Fh in EEPROM mainly for VPD data to be stored.
Note 4: The VPD function of the RTL8111 is designed to be able to access the full range of the
93C46/93C56 EEPROM.

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7. Characteristics
7.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the
device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise
specified.
Table 11. Absolute Maximum Ratings
Symbol Description Minimum Maximum Unit
VDD3, HV1VDD Supply Voltage 3.3V -0.5 4 V
V0VDD Supply Voltage 2.5V -0.5 3 V
VDD1A, VDD20,
Supply Voltage V* V
LV2VDD
VDD1 Supply Voltage 1.8V -0.5 2.3 V
DCinput Input Voltage -0.5 Corresponding Supply Voltage + 0.5 V
DCoutput Output Voltage -0.5 Corresponding Supply Voltage + 0.5 V
Storage Temperature -55 125 °C
* Refer to the most updated schematic circuit for correct configuration.

7.2. Recommended Operating Conditions


Table 12. Recommended Operating Conditions
Description Pins Minimum Typical Maximum Unit
VDD3, HV1VDD 3.0 3.3 3.6 V
V0VDD 2. 25 2.5 2.75 V
et4U.com Supply Voltage VDD VDD1A, VDD20, DataSheet4U.com e
LV2VDD
* V DataShe
VDD1 1.71 1.8 1.89 V
Ambient Temperature TA 0 70 °C
Maximum Junction
125 °C
Temperature
* Refer to the most updated schematic circuit for correct configuration.

7.3. Crystal Requirements


Table 13. Crystal Requirements
Symbol Description/Condition Minimum Typical Maximum Unit
Parallel resonant crystal reference frequency,
Fref 25 MHz
fundamental mode, AT-cut type.
Parallel resonant crystal frequency stability,
Fref Stability -50 +50 ppm
fundamental mode, AT-cut type. Ta=25°C.
Parallel resonant crystal frequency tolerance,
Fref Tolerance fundamental mode, AT-cut type. -30 +30 ppm
Ta=-20°C ~+70°C.
Fref Duty Cycle Reference clock input duty cycle. 40 60 %
CL Load Capacitance. pF
ESR Equivalent Series Resistance. Ω
DL Drive Level. 0.5 mW

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7.4. Thermal Characteristics


Table 14. Thermal Characteristics
Parameter Minimum Maximum Units
Storage temperature -55 125 °C
Operating temperature 0 70 °C

7.5. DC Characteristics
Table 15. DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
VDD3,
3.3V Supply Voltage 3.0 3.3 3.6 V
LV1VDD
V0VDD 2.5V Supply Voltage 2.25 2.5 2.75 V
VDD1A,
LV2VDD, Supply Voltage* V
VDD20
VDD1 1.8V Supply Voltage 1.71 1.8 1.89 V
Minimum High Level
Voh Ioh = -8mA 0.9 * VDD3 VDD3 V
Output Voltage
Maximum Low Level
Vol Iol= 8mA 0.1 * VDD3 V
Output Voltage
Minimum High Level
Vih 0.5 * VDD3 VDD3+0.5 V
Input Voltage
Maximum Low Level
Vil -0.5 0.3 * VDD3 V
Input Voltage
et4U.com DataSheet4U.com
Vin = VDD3 or e
Iin Input Current -1.0 1.0 µA DataShe
GND
Average Operating At 1Gbps with
Icc33 Supply Current from heavy network 43 mA
3.3V traffic
Average Operating At 1Gbps with
Icc25 Supply Current from heavy network 193 mA
2.5V traffic
At 1Gbps with
Average Operating
Icc21 heavy network 287 mA
Supply Current
traffic
Average Operating At 1Gbps with
Icc18 Supply Current from heavy network 530 mA
1.8V traffic
* Refer to the most updated schematic circuit for correct configuration.

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7.6. AC Characteristics
7.6.1. Serial EEPROM Interface Timing
93C46(64*16)/93C56(128*16)

EESK

EECS tcs

EEDI (Read) 1 1 0 An A2 A1 A0
(Read)
EEDO High Impedance 0 Dn D1 D0

EESK

EECS tcs

EEDI (Write) 1 0 1 An ... A0 Dn ... D0


(Write)
EEDO High Impedance BUSY READY
twp

tsk
et4U.com EESK DataSheet4U.com e
tskh tskl tcsh DataShe
EECS tcss
tdis tdih
EEDI
tdos tdoh
EEDO (Read)
tsv
EEDO STATUS VALID
(Program)
Figure 6. Serial EEPROM Interface Timing

Table 16. EEPROM Access Timing Parameters


Symbol Parameter EEPROM Type Min. Max. Unit
tcs Minimum CS Low Time 9346 1000 ns
twp Write Cycle Time 9346 10 ms
tsk SK Clock Cycle Time 9346 4 µs
tskh SK High Time 9346 1000 ns
tskl SK Low Time 9346 1000 ns
tcss CS Setup Time 9346 200 ns
tcsh CS Hold Time 9346 0 ns
tdis DI Setup Time 9346 400 ns

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Symbol Parameter EEPROM Type Min. Max. Unit


tdih DI Hold Time 9346 400 ns
tdos DO Setup Time 9346 2000 ns
tdoh DO Hold Time 9346 2000 ns
tsv CS to Status Valid 9346 1000 ns

7.7. PCI Express Bus Parameters


7.7.1. Differential Transmitter Parameters
Table 17. Differential Transmitter Parameters
Symbol Parameter Min Typical Max Units
UI Unit Interval2 399.88 400 400.12 ps
VTX-DIFFp-p Differential Peak to Peak Output Voltage 0.800 1.2 V
VTX-DE-RATIO De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB
TTX-EYE Minimum Tx Eye Width 0.70 UI
TTX-EYE-MEDIAN- Maximum time between the jitter median and 0.15 UI
to-MAX-JITTER maximum deviation from the median
TTX-RISE, TTX-FALL D+/D- Tx Output Rise/Fall Time 0.125 UI
VTX-CM-ACp RMS AC Peak Common Mode Output Voltage 20 mV
VTX-CM-DCACTIVE- Absolute Delta of DC Common Mode Voltage During 0 100 mV
IDLEDELTA L0 and Electrical Idle
VTX-CM-DCLINE- Absolute Delta of DC Common Mode Voltage between 0 25 mV
DELTA D+ and D-
VTX-IDLE-DIFFp Electrical Idle Differential Peak Output Voltage 0 20 mV
et4U.com VTX-RCV-DETECT The amount of voltage changeDataSheet4U.com
allowed during Receiver 600 mV e
Detection DataShe
VTX-DC-CM The TX DC Common Mode Voltage 0 3.6 V
ITX-SHORT TX Short Circuit Current Limit 90 mA
TTX-IDLE-MIN Minimum time spent in Electrical Idle 50 UI
TTX-IDLE- SETTO-IDLE Maximum time to transition to a valid Electrical Idle 20 UI
after sending an Electrical Idle ordered set
TTX-IDLE-TOTO- Maximum time to transition to valid TX specifications 20 UI
DIFF-DATA after leaving an Electrical Idle condition
RLTX-DIFF Differential Return Loss 12 dB
RLTX-CM Common Mode Return Loss 6 dB
ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 Ω
ZTX-DC Transmitter DC Impedance 40 Ω
LTX-SKEW Lane-to-Lane Output Skew 500+2 ps
UI
CTX AC Coupling Capacitor 75 200 nF
Tcrosslink Crosslink Random Timeout 0 1 ms
Note 1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter.
Note 2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate
frequency, at a modulation rate in the range not exceeding 30 kHz – 33 kHz. The +/- 300 ppm requirement still holds,
which requires the two communicating ports be modulated such that they never exceed a total of 600 ppm difference.

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7.7.2. Differential Receiver Parameters


Table 18. Differential Receiver Parameters
Symbol Parameter Min. Typical Max. Units
UI Unit Interval 399.88 400 400.12 ps
VRX-DIFFp-p Differential Input Peak to Peak Voltage 0.175 1.200 V
TRX-EYE Minimum Receiver Eye Width 0.4 UI
TRX-EYE-MEDIAN-to- Maximum time between the jitter median and maximum 0.3 UI
MAX-JITTER deviation from the median
VRX-CM-ACp AC Peak Common Mode Input Voltage 150 mV
RLRX-DIFF Differential Return Loss 15 dB
RLRX-CM Common Mode Return Loss 6 dB
ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 Ω
ZRX--DC DC Input Impedance 40 50 60 Ω
ZRX-HIGH-IMP-DC Powered Down DC Input Impedance 200 k Ω
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold 65 175 mV
TRX-IDLE-DET- Unexpected Electrical Idle Enter Detect Threshold 10 ms
DIFFENTERTIME Integration Time
LRX-SKEW Total Skew 20 ns
Note: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter.

7.7.3. REFCLK Parameters


Table 19. REFCLK Parameters
Symbol Parameter 100MHz Input Units
Min Max
et4U.com Tabsmin Absolute min. DIF CLK Period
DataSheet4U.com 9.872 ns e
DataShe
Trise Rise Time 175 700 ps
Tfall Fall Time 175 700 ps
h∆ Trise Rise Time Variation 125 ps
∆ Tfall Fall Time Variation 125 ps
Rise/Fall Matching 20 %
Vhigh Voltage High (typical 0.71V) 660 850 mV
Vlow Voltage Low (typical 0.0V) -150 mV
Vcross absolute Absolute Crossing Point Voltages 250 550 mV
Vcross relative Relative Crossing Point Voltages Note2 Note2 V
Total ∆ Vcross Total Variation of Vcross over all edges 140 mV
Tccjitter Cycle to Cycle Jitter 125 ps
Duty Cycle 45 55 %
Vovs Maximum Voltage (Overshoot) Vhigh_avg + 0.3 V
Vuds Minimum Voltage (Undershoot) -0.3 V
Vrb Ringback Voltage 0.2 N/A V
Note 1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter.
Note 2: Vcross relative Min = 0.5(Vhigh_avg – 0.710) + 0.250, Vcross relative Max = 0.5(Vhigh_avg – 0.710) + 0.550. The crossing point
must meet the absolute and relative crossing point specifications simultaneously.
Note 3: The nominal single-ended swing for each clock is 0 to 0.7V with a nominal frequency of 100MHz ±300 PPM.
Note 4: The reference clocks may support spread spectrum clocking. The minimum clock period cannot be violated.

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Figure 7. REFCLK Single-Ended Measurement Points for Trise and Tfall

et4U.com DataSheet4U.com e
Figure 8. REFCLK Single-Ended Measurement Points for Vovs, Vuds, and Vrb DataShe

Figure 9. REFCLK Differential Measurement Points for Tperiod, Duty Cycle, and Jitter

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Figure 10. REFCLK Vcross Range

7.7.4. Auxiliary Signal Timing Parameters


Table 20. Auxiliary Signal Timing Parameters
Symbol Parameter Min Max Units
TPVPERL Power stable to PERSTB inactive 100 ms
TPERST-CLK REFCLK stable before PERSTB inactive 100 µs
TPERST PERSTB active time 100 µs
TFAIL Power level invalid to PWRGD inactive 500 ns
TWKRF LANWAKEB rise – fall time 100 ns

et4U.com DataSheet4U.com e
DataShe

3.3 Vaux
Power Stable Wakeup Event Power Stable
3.3/12V

PERSTB Clock not


Clock Stable Stable Clock Stable
REFCLK

PCI-E Link Inactive Active Inactive Active


T PVPERL T PERST
T PERST-CLK
T FAIL

Figure 11. Auxiliary Signal Timing

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8. Mechanical Dimensions
SEATING
PLANE

SEE DETAIL “F”


SEE DETAIL “A”

et4U.com DataSheet4U.com e
DataShe
DETAIL “F”

DETAIL “A”
GAGE PLANE

METAL
BASE

PLATING
WITH

See the Mechanical Dimensions notes on the next page.

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8.1. Mechanical Dimensions Notes


Symbol Dimensions in inches Dimensions in mm Notes:
Min Typical Max Min Typical Max 1. Dimensions D & E do not include interlead flash.
A - - 0.134 - - 3.40 2. Dimension b does not include dambar rotrusion/intrusion.
A1 0.004 0.010 0.036 0.10 0.25 0.91 3. Controlling dimension: Millimeter
A2 0.102 0.112 0.122 2.60 2.85 3.10 4. General appearance spec. Should be based on final visual
b 0.005 0.009 0.013 0.12 0.22 0.32 inspection.
c 0.002 0.006 0.010 0.05 0.15 0.25
D 0.541 0.551 0.561 13.75 14.00 14.25 TITLE: 128 DHS-QFP (14x20 mm) PACKAGE OUTLINE
E 0.778 0.787 0.797 19.75 20.00 20.25 -CU L/F, FOOTPRINT 3.2 mm
e 0.010 0.020 0.030 0.25 0.5 0.75 LEADFRAME MATERIAL:
HD 0.665 0.677 0.689 16.90 17.20 17.50 APPROVE DOC. NO.
HE 0.902 0.913 0.925 22.90 23.20 23.50 VERSION 1.2
L 0.027 0.035 0.043 0.68 0.88 1.08 PAGE
L1 0.053 0.063 0.073 1.35 1.60 1.85 CHECK DWG NO. Q128 - 1
y - - 0.004 - - 0.10 DATE 12 February 2003
θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP.

9. Ordering Information
Table 21. Ordering Information
et4U.com Part Number Package
DataSheet4U.com Status
RTL8111 128-pin DHS-QFP
RTL8111-LF 128-pin DHS-QFP Lead (Pb)-Free
Note: See page 3 for lead (Pb)-free package ID information.

Realtek Semiconductor Corp.


Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
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