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16 To 1 Multiplexer: Dataflow

This document describes a 16 to 1 multiplexer module that uses 4-to-1 multiplexers to select one of 16 input bits and output it based on a 4-bit selection value. It includes the module for the 16-to-1 multiplexer, a module for the 4-to-1 multiplexer building block, a testbench that iterates through all possible input and selection values, and a schematic.

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Alisha Vinod
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256 views3 pages

16 To 1 Multiplexer: Dataflow

This document describes a 16 to 1 multiplexer module that uses 4-to-1 multiplexers to select one of 16 input bits and output it based on a 4-bit selection value. It includes the module for the 16-to-1 multiplexer, a module for the 4-to-1 multiplexer building block, a testbench that iterates through all possible input and selection values, and a schematic.

Uploaded by

Alisha Vinod
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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16 TO 1 MULTIPLEXER

DATAFLOW
module s16to1mux(

input [15:0]a,

input [3:0]sel,

output o);

wire [3:0]b;

s4to1mux p(a[3:0], sel[1:0], b[0]);

s4to1mux q(a[7:4], sel[1:0], b[1]);

s4to1mux r(a[11:8], sel[1:0], b[2]);

s4to1mux s(a[15:12], sel[1:0], b[3]);

s4to1mux t(b[3:0], sel[3:2], o);

endmodule

module s4to1mux(input [3:0]i, [1:0]s, output out);

assign out=(!s[0]&!s[1]&i[0])|(!s[0]&s[1]&i[1])|(s[0]&!s[1]&i[2])|(s[0]&s[1]&i[3]);

endmodule

TESTBENCH
module testbench11(

);

wire o;

reg[15:0]a;

reg [3:0]sel;

integer i, j;

s16to1mux r1(a, sel, o);


initial

begin

for(i=0; i<256; i=i+1)

begin

assign a=i;

for(j=0; j<16; j=j+1)

begin

assign sel=j;

#10;

end

end

end

endmodule

SCHEMATIC
SIMULATION

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